1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2020, Red Hat Inc. All rights reserved.
4 * Copyright 2025 Arm Limited and/or its affiliates.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include "pauth_aarch64.hpp"
28 #include "register_aarch64.hpp"
29 #include "runtime/arguments.hpp"
30 #include "runtime/globals_extension.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.inline.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/formatBuffer.hpp"
35 #include "utilities/macros.hpp"
36
37 int VM_Version::_cpu;
38 int VM_Version::_model;
39 int VM_Version::_model2;
40 int VM_Version::_variant;
41 int VM_Version::_revision;
42 int VM_Version::_stepping;
43
44 int VM_Version::_zva_length;
45 int VM_Version::_dcache_line_size;
46 int VM_Version::_icache_line_size;
47 int VM_Version::_initial_sve_vector_length;
48 int VM_Version::_max_supported_sve_vector_length;
49 bool VM_Version::_rop_protection;
50 uintptr_t VM_Version::_pac_mask;
51
52 SpinWait VM_Version::_spin_wait;
53
54 static SpinWait get_spin_wait_desc() {
55 SpinWait spin_wait(OnSpinWaitInst, OnSpinWaitInstCount);
56 if (spin_wait.inst() == SpinWait::SB && !VM_Version::supports_sb()) {
57 vm_exit_during_initialization("OnSpinWaitInst is SB but current CPU does not support SB instruction");
58 }
59
60 return spin_wait;
61 }
62
63 void VM_Version::initialize() {
64 _supports_atomic_getset4 = true;
65 _supports_atomic_getadd4 = true;
66 _supports_atomic_getset8 = true;
67 _supports_atomic_getadd8 = true;
68
69 get_os_cpu_info();
70
71 int dcache_line = VM_Version::dcache_line_size();
72
73 // Limit AllocatePrefetchDistance so that it does not exceed the
74 // static constraint of 512 defined in runtime/globals.hpp.
75 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
76 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
77
78 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
79 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
80 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
81 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
82 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
83 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
84 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
85 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
86
87 if (PrefetchCopyIntervalInBytes != -1 &&
88 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
89 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
90 PrefetchCopyIntervalInBytes &= ~7;
91 if (PrefetchCopyIntervalInBytes >= 32768)
92 PrefetchCopyIntervalInBytes = 32760;
93 }
94
95 if (AllocatePrefetchDistance != -1 && (AllocatePrefetchDistance & 7)) {
96 warning("AllocatePrefetchDistance must be multiple of 8");
97 AllocatePrefetchDistance &= ~7;
98 }
99
100 if (AllocatePrefetchStepSize & 7) {
101 warning("AllocatePrefetchStepSize must be multiple of 8");
102 AllocatePrefetchStepSize &= ~7;
103 }
104
105 if (SoftwarePrefetchHintDistance != -1 &&
106 (SoftwarePrefetchHintDistance & 7)) {
107 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
108 SoftwarePrefetchHintDistance &= ~7;
109 }
110
111 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && (dcache_line > ContendedPaddingWidth)) {
112 ContendedPaddingWidth = dcache_line;
113 }
114
115 if (os::supports_map_sync()) {
116 // if dcpop is available publish data cache line flush size via
117 // generic field, otherwise let if default to zero thereby
118 // disabling writeback
119 if (VM_Version::supports_dcpop()) {
120 _data_cache_line_flush_size = dcache_line;
121 }
122 }
123
124 // Enable vendor specific features
125
126 // Ampere eMAG
127 if (_cpu == CPU_AMCC && (_model == CPU_MODEL_EMAG) && (_variant == 0x3)) {
128 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
129 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
130 }
131 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
132 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
133 }
134 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
135 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
136 }
137 }
138
139 // Ampere CPUs
140 if (_cpu == CPU_AMPERE && ((_model == CPU_MODEL_AMPERE_1) ||
141 (_model == CPU_MODEL_AMPERE_1A) ||
142 (_model == CPU_MODEL_AMPERE_1B))) {
143 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
144 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
145 }
146 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
147 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
148 }
149 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
150 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 2);
151 }
152 if (FLAG_IS_DEFAULT(CodeEntryAlignment) &&
153 (_model == CPU_MODEL_AMPERE_1A || _model == CPU_MODEL_AMPERE_1B)) {
154 FLAG_SET_DEFAULT(CodeEntryAlignment, 32);
155 }
156 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
157 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
158 }
159 }
160
161 // ThunderX
162 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
163 guarantee(_variant != 0, "Pre-release hardware no longer supported.");
164 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
165 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
166 }
167 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
168 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
169 }
170 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
171 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
172 }
173 }
174
175 // ThunderX2
176 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
177 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
178 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
179 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
180 }
181 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
182 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
183 }
184 }
185
186 // HiSilicon TSV110
187 if (_cpu == CPU_HISILICON && _model == 0xd01) {
188 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
189 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
190 }
191 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
192 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
193 }
194 }
195
196 // Cortex A53
197 if (_cpu == CPU_ARM && model_is(0xd03)) {
198 _features |= CPU_A53MAC;
199 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
200 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
201 }
202 }
203
204 // Cortex A73
205 if (_cpu == CPU_ARM && model_is(0xd09)) {
206 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
207 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
208 }
209 // A73 is faster with short-and-easy-for-speculative-execution-loop
210 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
211 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
212 }
213 }
214
215 // Neoverse
216 // N1: 0xd0c
217 // N2: 0xd49
218 // N3: 0xd8e
219 // V1: 0xd40
220 // V2: 0xd4f
221 // V3: 0xd84
222 if (_cpu == CPU_ARM && (model_is(0xd0c) || model_is(0xd49) ||
223 model_is(0xd40) || model_is(0xd4f) ||
224 model_is(0xd8e) || model_is(0xd84))) {
225 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
226 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
227 }
228
229 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
230 if (model_is(0xd4f) && VM_Version::supports_sb()) {
231 FLAG_SET_DEFAULT(OnSpinWaitInst, "sb");
232 } else {
233 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
234 }
235 }
236
237 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
238 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 1);
239 }
240 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
241 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
242 }
243 }
244
245 if (_features & (CPU_FP | CPU_ASIMD)) {
246 if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
247 FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
248 }
249 }
250
251 if (FLAG_IS_DEFAULT(UseCRC32)) {
252 UseCRC32 = VM_Version::supports_crc32();
253 }
254
255 if (UseCRC32 && !VM_Version::supports_crc32()) {
256 warning("UseCRC32 specified, but not supported on this CPU");
257 FLAG_SET_DEFAULT(UseCRC32, false);
258 }
259
260 // Neoverse
261 // V1: 0xd40
262 // V2: 0xd4f
263 // V3: 0xd84
264 if (_cpu == CPU_ARM &&
265 (model_is(0xd40) || model_is(0xd4f) || model_is(0xd84))) {
266 if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
267 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
268 }
269 if (FLAG_IS_DEFAULT(CodeEntryAlignment)) {
270 FLAG_SET_DEFAULT(CodeEntryAlignment, 32);
271 }
272 }
273
274 if (UseCryptoPmullForCRC32 && (!VM_Version::supports_pmull() || !VM_Version::supports_sha3() || !VM_Version::supports_crc32())) {
275 warning("UseCryptoPmullForCRC32 specified, but not supported on this CPU");
276 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, false);
277 }
278
279 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
280 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
281 }
282
283 if (UseVectorizedMismatchIntrinsic) {
284 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
285 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
286 }
287
288 if (VM_Version::supports_lse()) {
289 if (FLAG_IS_DEFAULT(UseLSE))
290 FLAG_SET_DEFAULT(UseLSE, true);
291 } else {
292 if (UseLSE) {
293 warning("UseLSE specified, but not supported on this CPU");
294 FLAG_SET_DEFAULT(UseLSE, false);
295 }
296 }
297
298 if (VM_Version::supports_aes()) {
299 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
300 UseAESIntrinsics =
301 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
302 if (UseAESIntrinsics && !UseAES) {
303 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
304 UseAES = true;
305 }
306 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
307 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
308 }
309 } else {
310 if (UseAES) {
311 warning("AES instructions are not available on this CPU");
312 FLAG_SET_DEFAULT(UseAES, false);
313 }
314 if (UseAESIntrinsics) {
315 warning("AES intrinsics are not available on this CPU");
316 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
317 }
318 if (UseAESCTRIntrinsics) {
319 warning("AES/CTR intrinsics are not available on this CPU");
320 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
321 }
322 }
323
324
325 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
326 UseCRC32Intrinsics = true;
327 }
328
329 if (VM_Version::supports_crc32()) {
330 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
331 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
332 }
333 } else if (UseCRC32CIntrinsics) {
334 warning("CRC32C is not available on the CPU");
335 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
336 }
337
338 if (FLAG_IS_DEFAULT(UseFMA)) {
339 FLAG_SET_DEFAULT(UseFMA, true);
340 }
341
342 if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
343 UseMD5Intrinsics = true;
344 }
345
346 if (VM_Version::supports_sha1() || VM_Version::supports_sha256() ||
347 VM_Version::supports_sha3() || VM_Version::supports_sha512()) {
348 if (FLAG_IS_DEFAULT(UseSHA)) {
349 FLAG_SET_DEFAULT(UseSHA, true);
350 }
351 } else if (UseSHA) {
352 warning("SHA instructions are not available on this CPU");
353 FLAG_SET_DEFAULT(UseSHA, false);
354 }
355
356 if (UseSHA && VM_Version::supports_sha1()) {
357 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
358 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
359 }
360 } else if (UseSHA1Intrinsics) {
361 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
362 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
363 }
364
365 if (UseSHA && VM_Version::supports_sha256()) {
366 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
367 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
368 }
369 } else if (UseSHA256Intrinsics) {
370 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
371 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
372 }
373
374 if (UseSHA && VM_Version::supports_sha3()) {
375 // Auto-enable UseSHA3Intrinsics on hardware with performance benefit.
376 // Note that the evaluation of UseSHA3Intrinsics shows better performance
377 // on Apple silicon but worse performance on Neoverse V1 and N2.
378 if (_cpu == CPU_APPLE) { // Apple silicon
379 if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
380 FLAG_SET_DEFAULT(UseSHA3Intrinsics, true);
381 }
382 }
383 } else if (UseSHA3Intrinsics && UseSIMDForSHA3Intrinsic) {
384 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
385 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
386 }
387
388 if (UseSHA && VM_Version::supports_sha512()) {
389 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
390 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
391 }
392 } else if (UseSHA512Intrinsics) {
393 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
394 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
395 }
396
397 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA3Intrinsics || UseSHA512Intrinsics)) {
398 FLAG_SET_DEFAULT(UseSHA, false);
399 }
400
401 if (VM_Version::supports_pmull()) {
402 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
403 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
404 }
405 } else if (UseGHASHIntrinsics) {
406 warning("GHASH intrinsics are not available on this CPU");
407 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
408 }
409
410 if (_features & CPU_ASIMD) {
411 if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
412 UseChaCha20Intrinsics = true;
413 }
414 } else if (UseChaCha20Intrinsics) {
415 if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
416 warning("ChaCha20 intrinsic requires ASIMD instructions");
417 }
418 FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
419 }
420
421 if (_features & CPU_ASIMD) {
422 if (FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
423 UseKyberIntrinsics = true;
424 }
425 } else if (UseKyberIntrinsics) {
426 if (!FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
427 warning("Kyber intrinsics require ASIMD instructions");
428 }
429 FLAG_SET_DEFAULT(UseKyberIntrinsics, false);
430 }
431
432 if (_features & CPU_ASIMD) {
433 if (FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
434 UseDilithiumIntrinsics = true;
435 }
436 } else if (UseDilithiumIntrinsics) {
437 if (!FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
438 warning("Dilithium intrinsics require ASIMD instructions");
439 }
440 FLAG_SET_DEFAULT(UseDilithiumIntrinsics, false);
441 }
442
443 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
444 UseBASE64Intrinsics = true;
445 }
446
447 if (is_zva_enabled()) {
448 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
449 FLAG_SET_DEFAULT(UseBlockZeroing, true);
450 }
451 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
452 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
453 }
454 } else if (UseBlockZeroing) {
455 warning("DC ZVA is not available on this CPU");
456 FLAG_SET_DEFAULT(UseBlockZeroing, false);
457 }
458
459 if (VM_Version::supports_sve2()) {
460 if (FLAG_IS_DEFAULT(UseSVE)) {
461 FLAG_SET_DEFAULT(UseSVE, 2);
462 }
463 } else if (VM_Version::supports_sve()) {
464 if (FLAG_IS_DEFAULT(UseSVE)) {
465 FLAG_SET_DEFAULT(UseSVE, 1);
466 } else if (UseSVE > 1) {
467 warning("SVE2 specified, but not supported on current CPU. Using SVE.");
468 FLAG_SET_DEFAULT(UseSVE, 1);
469 }
470 } else if (UseSVE > 0) {
471 warning("UseSVE specified, but not supported on current CPU. Disabling SVE.");
472 FLAG_SET_DEFAULT(UseSVE, 0);
473 }
474
475 if (UseSVE > 0) {
476 int vl = get_current_sve_vector_length();
477 if (vl < 0) {
478 warning("Unable to get SVE vector length on this system. "
479 "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.");
480 FLAG_SET_DEFAULT(UseSVE, 0);
481 } else if ((vl == 0) || ((vl % FloatRegister::sve_vl_min) != 0) || !is_power_of_2(vl)) {
482 warning("Detected SVE vector length (%d) should be a power of two and a multiple of %d. "
483 "Disabling SVE. Specify -XX:UseSVE=0 to shun this warning.",
484 vl, FloatRegister::sve_vl_min);
485 FLAG_SET_DEFAULT(UseSVE, 0);
486 } else {
487 _initial_sve_vector_length = vl;
488 }
489 }
490
491 // This machine allows unaligned memory accesses
492 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
493 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
494 }
495
496 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
497 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
498 }
499
500 if (!UsePopCountInstruction) {
501 warning("UsePopCountInstruction is always enabled on this CPU");
502 UsePopCountInstruction = true;
503 }
504
505 if (UseBranchProtection == nullptr || strcmp(UseBranchProtection, "none") == 0) {
506 _rop_protection = false;
507 } else if (strcmp(UseBranchProtection, "standard") == 0 ||
508 strcmp(UseBranchProtection, "pac-ret") == 0) {
509 _rop_protection = false;
510 // Enable ROP-protection if
511 // 1) this code has been built with branch-protection and
512 // 2) the CPU/OS supports it
513 #ifdef __ARM_FEATURE_PAC_DEFAULT
514 if (!VM_Version::supports_paca()) {
515 // Disable PAC to prevent illegal instruction crashes.
516 warning("ROP-protection specified, but not supported on this CPU. Disabling ROP-protection.");
517 } else {
518 _rop_protection = true;
519 }
520 #else
521 warning("ROP-protection specified, but this VM was built without ROP-protection support. Disabling ROP-protection.");
522 #endif
523 } else {
524 vm_exit_during_initialization(err_msg("Unsupported UseBranchProtection: %s", UseBranchProtection));
525 }
526
527 if (_rop_protection == true) {
528 // Determine the mask of address bits used for PAC. Clear bit 55 of
529 // the input to make it look like a user address.
530 _pac_mask = (uintptr_t)pauth_strip_pointer((address)~(UINT64_C(1) << 55));
531 }
532
533 #ifdef COMPILER2
534 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
535 UseMultiplyToLenIntrinsic = true;
536 }
537
538 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
539 UseSquareToLenIntrinsic = true;
540 }
541
542 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
543 UseMulAddIntrinsic = true;
544 }
545
546 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
547 UseMontgomeryMultiplyIntrinsic = true;
548 }
549 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
550 UseMontgomerySquareIntrinsic = true;
551 }
552
553 if (UseSVE > 0) {
554 if (FLAG_IS_DEFAULT(MaxVectorSize)) {
555 MaxVectorSize = _initial_sve_vector_length;
556 } else if (MaxVectorSize < FloatRegister::sve_vl_min) {
557 warning("SVE does not support vector length less than %d bytes. Disabling SVE.",
558 FloatRegister::sve_vl_min);
559 UseSVE = 0;
560 } else if (!((MaxVectorSize % FloatRegister::sve_vl_min) == 0 && is_power_of_2(MaxVectorSize))) {
561 vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
562 }
563
564 if (UseSVE > 0) {
565 // Acquire the largest supported vector length of this machine
566 _max_supported_sve_vector_length = set_and_get_current_sve_vector_length(FloatRegister::sve_vl_max);
567
568 if (MaxVectorSize != _max_supported_sve_vector_length) {
569 int new_vl = set_and_get_current_sve_vector_length(MaxVectorSize);
570 if (new_vl < 0) {
571 vm_exit_during_initialization(
572 err_msg("Current system does not support SVE vector length for MaxVectorSize: %d",
573 (int)MaxVectorSize));
574 } else if (new_vl != MaxVectorSize) {
575 warning("Current system only supports max SVE vector length %d. Set MaxVectorSize to %d",
576 new_vl, new_vl);
577 }
578 MaxVectorSize = new_vl;
579 }
580 _initial_sve_vector_length = MaxVectorSize;
581 }
582 }
583
584 if (UseSVE == 0) { // NEON
585 int min_vector_size = 8;
586 int max_vector_size = FloatRegister::neon_vl;
587 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
588 if (!is_power_of_2(MaxVectorSize)) {
589 vm_exit_during_initialization(err_msg("Unsupported MaxVectorSize: %d", (int)MaxVectorSize));
590 } else if (MaxVectorSize < min_vector_size) {
591 warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
592 FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
593 } else if (MaxVectorSize > max_vector_size) {
594 warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
595 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
596 }
597 } else {
598 FLAG_SET_DEFAULT(MaxVectorSize, FloatRegister::neon_vl);
599 }
600 }
601
602 int inline_size = (UseSVE > 0 && MaxVectorSize >= FloatRegister::sve_vl_min) ? MaxVectorSize : 0;
603 if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
604 FLAG_SET_DEFAULT(ArrayOperationPartialInlineSize, inline_size);
605 } else if (ArrayOperationPartialInlineSize != 0 && ArrayOperationPartialInlineSize != inline_size) {
606 warning("Setting ArrayOperationPartialInlineSize to %d", inline_size);
607 ArrayOperationPartialInlineSize = inline_size;
608 }
609
610 if (FLAG_IS_DEFAULT(OptoScheduling)) {
611 OptoScheduling = true;
612 }
613
614 if (FLAG_IS_DEFAULT(AlignVector)) {
615 AlignVector = AvoidUnalignedAccesses;
616 }
617
618 if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
619 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
620 }
621
622 if (FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic)) {
623 FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, true);
624 }
625 #endif
626
627 _spin_wait = get_spin_wait_desc();
628
629 check_virtualizations();
630
631 // Sync SVE related CPU features with flags
632 if (UseSVE < 2) {
633 _features &= ~CPU_SVE2;
634 _features &= ~CPU_SVEBITPERM;
635 }
636 if (UseSVE < 1) {
637 _features &= ~CPU_SVE;
638 }
639
640 // Construct the "features" string
641 char buf[512];
642 int buf_used_len = os::snprintf_checked(buf, sizeof(buf), "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
643 if (_model2) {
644 os::snprintf_checked(buf + buf_used_len, sizeof(buf) - buf_used_len, "(0x%03x)", _model2);
645 }
646 size_t features_offset = strnlen(buf, sizeof(buf));
647 #define ADD_FEATURE_IF_SUPPORTED(id, name, bit) \
648 do { \
649 if (VM_Version::supports_##name()) strcat(buf, ", " #name); \
650 } while(0);
651 CPU_FEATURE_FLAGS(ADD_FEATURE_IF_SUPPORTED)
652 #undef ADD_FEATURE_IF_SUPPORTED
653
654 _cpu_info_string = os::strdup(buf);
655
656 _features_string = extract_features_string(_cpu_info_string,
657 strnlen(_cpu_info_string, sizeof(buf)),
658 features_offset);
659 }
660
661 #if defined(LINUX)
662 static bool check_info_file(const char* fpath,
663 const char* virt1, VirtualizationType vt1,
664 const char* virt2, VirtualizationType vt2) {
665 char line[500];
666 FILE* fp = os::fopen(fpath, "r");
667 if (fp == nullptr) {
668 return false;
669 }
670 while (fgets(line, sizeof(line), fp) != nullptr) {
671 if (strcasestr(line, virt1) != nullptr) {
672 Abstract_VM_Version::_detected_virtualization = vt1;
673 fclose(fp);
674 return true;
675 }
676 if (virt2 != nullptr && strcasestr(line, virt2) != nullptr) {
677 Abstract_VM_Version::_detected_virtualization = vt2;
678 fclose(fp);
679 return true;
680 }
681 }
682 fclose(fp);
683 return false;
684 }
685 #endif
686
687 void VM_Version::check_virtualizations() {
688 #if defined(LINUX)
689 const char* pname_file = "/sys/devices/virtual/dmi/id/product_name";
690 const char* tname_file = "/sys/hypervisor/type";
691 if (check_info_file(pname_file, "KVM", KVM, "VMWare", VMWare)) {
692 return;
693 }
694 check_info_file(tname_file, "Xen", XenPVHVM, nullptr, NoDetectedVirtualization);
695 #endif
696 }
697
698 void VM_Version::print_platform_virtualization_info(outputStream* st) {
699 #if defined(LINUX)
700 VirtualizationType vrt = VM_Version::get_detected_virtualization();
701 if (vrt == KVM) {
702 st->print_cr("KVM virtualization detected");
703 } else if (vrt == VMWare) {
704 st->print_cr("VMWare virtualization detected");
705 } else if (vrt == XenPVHVM) {
706 st->print_cr("Xen virtualization detected");
707 }
708 #endif
709 }
710
711 void VM_Version::initialize_cpu_information(void) {
712 // do nothing if cpu info has been initialized
713 if (_initialized) {
714 return;
715 }
716
717 _no_of_cores = os::processor_count();
718 _no_of_threads = _no_of_cores;
719 _no_of_sockets = _no_of_cores;
720 snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64");
721
722 int desc_len = snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 ");
723 get_compatible_board(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len);
724 desc_len = (int)strlen(_cpu_desc);
725 snprintf(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len, " %s", _cpu_info_string);
726
727 _initialized = true;
728 }