75 // these four CPU features, e.g., "hw.optional.arm.FEAT_AES", but the
76 // corresponding string names are not available before xnu-8019 version.
77 // Hence, assertions are omitted considering backward compatibility.
78 _features |= CPU_AES | CPU_PMULL | CPU_SHA1 | CPU_SHA2;
79
80 if (cpu_has("hw.optional.armv8_crc32")) {
81 _features |= CPU_CRC32;
82 }
83 if (cpu_has("hw.optional.arm.FEAT_LSE") ||
84 cpu_has("hw.optional.armv8_1_atomics")) {
85 _features |= CPU_LSE;
86 }
87 if (cpu_has("hw.optional.arm.FEAT_SHA512") ||
88 cpu_has("hw.optional.armv8_2_sha512")) {
89 _features |= CPU_SHA512;
90 }
91 if (cpu_has("hw.optional.arm.FEAT_SHA3") ||
92 cpu_has("hw.optional.armv8_2_sha3")) {
93 _features |= CPU_SHA3;
94 }
95
96 int cache_line_size;
97 int hw_conf_cache_line[] = { CTL_HW, HW_CACHELINE };
98 sysctllen = sizeof(cache_line_size);
99 if (sysctl(hw_conf_cache_line, 2, &cache_line_size, &sysctllen, nullptr, 0)) {
100 cache_line_size = 16;
101 }
102 _icache_line_size = 16; // minimal line length CCSIDR_EL1 can hold
103 _dcache_line_size = cache_line_size;
104
105 uint64_t dczid_el0;
106 __asm__ (
107 "mrs %0, DCZID_EL0\n"
108 : "=r"(dczid_el0)
109 );
110 if (!(dczid_el0 & 0x10)) {
111 _zva_length = 4 << (dczid_el0 & 0xf);
112 }
113
114 int family;
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75 // these four CPU features, e.g., "hw.optional.arm.FEAT_AES", but the
76 // corresponding string names are not available before xnu-8019 version.
77 // Hence, assertions are omitted considering backward compatibility.
78 _features |= CPU_AES | CPU_PMULL | CPU_SHA1 | CPU_SHA2;
79
80 if (cpu_has("hw.optional.armv8_crc32")) {
81 _features |= CPU_CRC32;
82 }
83 if (cpu_has("hw.optional.arm.FEAT_LSE") ||
84 cpu_has("hw.optional.armv8_1_atomics")) {
85 _features |= CPU_LSE;
86 }
87 if (cpu_has("hw.optional.arm.FEAT_SHA512") ||
88 cpu_has("hw.optional.armv8_2_sha512")) {
89 _features |= CPU_SHA512;
90 }
91 if (cpu_has("hw.optional.arm.FEAT_SHA3") ||
92 cpu_has("hw.optional.armv8_2_sha3")) {
93 _features |= CPU_SHA3;
94 }
95 if (cpu_has("hw.optional.arm.FEAT_SB")) {
96 _features |= CPU_SB;
97 }
98
99 int cache_line_size;
100 int hw_conf_cache_line[] = { CTL_HW, HW_CACHELINE };
101 sysctllen = sizeof(cache_line_size);
102 if (sysctl(hw_conf_cache_line, 2, &cache_line_size, &sysctllen, nullptr, 0)) {
103 cache_line_size = 16;
104 }
105 _icache_line_size = 16; // minimal line length CCSIDR_EL1 can hold
106 _dcache_line_size = cache_line_size;
107
108 uint64_t dczid_el0;
109 __asm__ (
110 "mrs %0, DCZID_EL0\n"
111 : "=r"(dczid_el0)
112 );
113 if (!(dczid_el0 & 0x10)) {
114 _zva_length = 4 << (dczid_el0 & 0xf);
115 }
116
117 int family;
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