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src/hotspot/cpu/aarch64/aarch64.ad

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1945   if (Assembler::operand_valid_for_add_sub_immediate(offset)) {
1946     __ add(as_Register(reg), sp, offset);
1947   } else {
1948     ShouldNotReachHere();
1949   }
1950 }
1951 
1952 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1953   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1954   return 4;
1955 }
1956 
1957 //=============================================================================
1958 
1959 #ifndef PRODUCT
1960 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1961 {
1962   st->print_cr("# MachUEPNode");
1963   if (UseCompressedClassPointers) {
1964     st->print_cr("\tldrw rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1965     if (CompressedKlassPointers::shift() != 0) {
1966       st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1967     }
1968   } else {
1969    st->print_cr("\tldr rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1970   }
1971   st->print_cr("\tcmp r0, rscratch1\t # Inline cache check");
1972   st->print_cr("\tbne, SharedRuntime::_ic_miss_stub");
1973 }
1974 #endif
1975 
1976 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1977 {
1978   // This is the unverified entry point.
1979   MacroAssembler _masm(&cbuf);
1980 
1981   __ cmp_klass(j_rarg0, rscratch2, rscratch1);
1982   Label skip;
1983   // TODO
1984   // can we avoid this skip and still use a reloc?
1985   __ br(Assembler::EQ, skip);


2166 }
2167 
2168 // Does the CPU require late expand (see block.cpp for description of late expand)?
2169 const bool Matcher::require_postalloc_expand = false;
2170 
2171 // Do we need to mask the count passed to shift instructions or does
2172 // the cpu only look at the lower 5/6 bits anyway?
2173 const bool Matcher::need_masked_shift_count = false;
2174 
2175 // This affects two different things:
2176 //  - how Decode nodes are matched
2177 //  - how ImplicitNullCheck opportunities are recognized
2178 // If true, the matcher will try to remove all Decodes and match them
2179 // (as operands) into nodes. NullChecks are not prepared to deal with
2180 // Decodes by final_graph_reshaping().
2181 // If false, final_graph_reshaping() forces the decode behind the Cmp
2182 // for a NullCheck. The matcher matches the Decode node into a register.
2183 // Implicit_null_check optimization moves the Decode along with the
2184 // memory operation back up before the NullCheck.
2185 bool Matcher::narrow_oop_use_complex_address() {
2186   return CompressedOops::shift() == 0;
2187 }
2188 
2189 bool Matcher::narrow_klass_use_complex_address() {
2190 // TODO
2191 // decide whether we need to set this to true
2192   return false;
2193 }
2194 
2195 bool Matcher::const_oop_prefer_decode() {
2196   // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
2197   return CompressedOops::base() == NULL;
2198 }
2199 
2200 bool Matcher::const_klass_prefer_decode() {
2201   // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
2202   return CompressedKlassPointers::base() == NULL;
2203 }
2204 
2205 // Is it better to copy float constants, or load them directly from
2206 // memory?  Intel can load a float constant from a direct address,
2207 // requiring no extra registers.  Most RISCs will have to materialize
2208 // an address into a register first, so they would do better to copy
2209 // the constant from stack.
2210 const bool Matcher::rematerialize_float_constants = false;
2211 
2212 // If CPU can load and store mis-aligned doubles directly then no
2213 // fixup is needed.  Else we split the double into 2 integer pieces
2214 // and move it piece-by-piece.  Only happens when passing doubles into
2215 // C code as the Java calling convention forces doubles to be aligned.
2216 const bool Matcher::misaligned_doubles_ok = true;
2217 
2218 // No-op on amd64
2219 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2220   Unimplemented();
2221 }
2222 


3915   predicate(n->get_long() == 65535L);
3916   match(ConL);
3917 
3918   op_cost(0);
3919   format %{ %}
3920   interface(CONST_INTER);
3921 %}
3922 
3923 operand immL_4294967295()
3924 %{
3925   predicate(n->get_long() == 4294967295L);
3926   match(ConL);
3927 
3928   op_cost(0);
3929   format %{ %}
3930   interface(CONST_INTER);
3931 %}
3932 
3933 operand immL_bitmask()
3934 %{
3935   predicate((n->get_long() != 0)
3936             && ((n->get_long() & 0xc000000000000000l) == 0)
3937             && is_power_of_2(n->get_long() + 1));
3938   match(ConL);
3939 
3940   op_cost(0);
3941   format %{ %}
3942   interface(CONST_INTER);
3943 %}
3944 
3945 operand immI_bitmask()
3946 %{
3947   predicate((n->get_int() != 0)
3948             && ((n->get_int() & 0xc0000000) == 0)
3949             && is_power_of_2(n->get_int() + 1));
3950   match(ConI);
3951 
3952   op_cost(0);
3953   format %{ %}
3954   interface(CONST_INTER);
3955 %}
3956 
3957 // Scale values for scaled offset addressing modes (up to long but not quad)
3958 operand immIScale()
3959 %{
3960   predicate(0 <= n->get_int() && (n->get_int() <= 3));
3961   match(ConI);
3962 
3963   op_cost(0);
3964   format %{ %}
3965   interface(CONST_INTER);
3966 %}
3967 
3968 // 26 bit signed offset -- for pc-relative branches


5027     disp($off);
5028   %}
5029 %}
5030 
5031 operand indOffL16(iRegP reg, immLoffset16 off)
5032 %{
5033   constraint(ALLOC_IN_RC(ptr_reg));
5034   match(AddP reg off);
5035   op_cost(0);
5036   format %{ "[$reg, $off]" %}
5037   interface(MEMORY_INTER) %{
5038     base($reg);
5039     index(0xffffffff);
5040     scale(0x0);
5041     disp($off);
5042   %}
5043 %}
5044 
5045 operand indirectN(iRegN reg)
5046 %{
5047   predicate(CompressedOops::shift() == 0);
5048   constraint(ALLOC_IN_RC(ptr_reg));
5049   match(DecodeN reg);
5050   op_cost(0);
5051   format %{ "[$reg]\t# narrow" %}
5052   interface(MEMORY_INTER) %{
5053     base($reg);
5054     index(0xffffffff);
5055     scale(0x0);
5056     disp(0x0);
5057   %}
5058 %}
5059 
5060 operand indIndexScaledI2LN(iRegN reg, iRegI ireg, immIScale scale)
5061 %{
5062   predicate(CompressedOops::shift() == 0 && size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5063   constraint(ALLOC_IN_RC(ptr_reg));
5064   match(AddP (DecodeN reg) (LShiftL (ConvI2L ireg) scale));
5065   op_cost(0);
5066   format %{ "$reg, $ireg sxtw($scale), 0, I2L\t# narrow" %}
5067   interface(MEMORY_INTER) %{
5068     base($reg);
5069     index($ireg);
5070     scale($scale);
5071     disp(0x0);
5072   %}
5073 %}
5074 
5075 operand indIndexScaledN(iRegN reg, iRegL lreg, immIScale scale)
5076 %{
5077   predicate(CompressedOops::shift() == 0 && size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5078   constraint(ALLOC_IN_RC(ptr_reg));
5079   match(AddP (DecodeN reg) (LShiftL lreg scale));
5080   op_cost(0);
5081   format %{ "$reg, $lreg lsl($scale)\t# narrow" %}
5082   interface(MEMORY_INTER) %{
5083     base($reg);
5084     index($lreg);
5085     scale($scale);
5086     disp(0x0);
5087   %}
5088 %}
5089 
5090 operand indIndexI2LN(iRegN reg, iRegI ireg)
5091 %{
5092   predicate(CompressedOops::shift() == 0);
5093   constraint(ALLOC_IN_RC(ptr_reg));
5094   match(AddP (DecodeN reg) (ConvI2L ireg));
5095   op_cost(0);
5096   format %{ "$reg, $ireg, 0, I2L\t# narrow" %}
5097   interface(MEMORY_INTER) %{
5098     base($reg);
5099     index($ireg);
5100     scale(0x0);
5101     disp(0x0);
5102   %}
5103 %}
5104 
5105 operand indIndexN(iRegN reg, iRegL lreg)
5106 %{
5107   predicate(CompressedOops::shift() == 0);
5108   constraint(ALLOC_IN_RC(ptr_reg));
5109   match(AddP (DecodeN reg) lreg);
5110   op_cost(0);
5111   format %{ "$reg, $lreg\t# narrow" %}
5112   interface(MEMORY_INTER) %{
5113     base($reg);
5114     index($lreg);
5115     scale(0x0);
5116     disp(0x0);
5117   %}
5118 %}
5119 
5120 operand indOffIN(iRegN reg, immIOffset off)
5121 %{
5122   predicate(CompressedOops::shift() == 0);
5123   constraint(ALLOC_IN_RC(ptr_reg));
5124   match(AddP (DecodeN reg) off);
5125   op_cost(0);
5126   format %{ "[$reg, $off]\t# narrow" %}
5127   interface(MEMORY_INTER) %{
5128     base($reg);
5129     index(0xffffffff);
5130     scale(0x0);
5131     disp($off);
5132   %}
5133 %}
5134 
5135 operand indOffLN(iRegN reg, immLoffset off)
5136 %{
5137   predicate(CompressedOops::shift() == 0);
5138   constraint(ALLOC_IN_RC(ptr_reg));
5139   match(AddP (DecodeN reg) off);
5140   op_cost(0);
5141   format %{ "[$reg, $off]\t# narrow" %}
5142   interface(MEMORY_INTER) %{
5143     base($reg);
5144     index(0xffffffff);
5145     scale(0x0);
5146     disp($off);
5147   %}
5148 %}
5149 
5150 
5151 
5152 // AArch64 opto stubs need to write to the pc slot in the thread anchor
5153 operand thread_anchor_pc(thread_RegP reg, immL_pc_off off)
5154 %{
5155   constraint(ALLOC_IN_RC(ptr_reg));
5156   match(AddP reg off);
5157   op_cost(0);


7022   ins_pipe(istore_mem);
7023 %}
7024 
7025 // Store Compressed Pointer
7026 instruct storeN(iRegN src, memory mem)
7027 %{
7028   match(Set mem (StoreN mem src));
7029   predicate(!needs_releasing_store(n));
7030 
7031   ins_cost(INSN_COST);
7032   format %{ "strw  $src, $mem\t# compressed ptr" %}
7033 
7034   ins_encode(aarch64_enc_strw(src, mem));
7035 
7036   ins_pipe(istore_reg_mem);
7037 %}
7038 
7039 instruct storeImmN0(iRegIHeapbase heapbase, immN0 zero, memory mem)
7040 %{
7041   match(Set mem (StoreN mem zero));
7042   predicate(CompressedOops::base() == NULL &&
7043             CompressedKlassPointers::base() == NULL &&
7044             (!needs_releasing_store(n)));
7045 
7046   ins_cost(INSN_COST);
7047   format %{ "strw  rheapbase, $mem\t# compressed ptr (rheapbase==0)" %}
7048 
7049   ins_encode(aarch64_enc_strw(heapbase, mem));
7050 
7051   ins_pipe(istore_reg_mem);
7052 %}
7053 
7054 // Store Float
7055 instruct storeF(vRegF src, memory mem)
7056 %{
7057   match(Set mem (StoreF mem src));
7058   predicate(!needs_releasing_store(n));
7059 
7060   ins_cost(INSN_COST);
7061   format %{ "strs  $src, $mem\t# float" %}
7062 
7063   ins_encode( aarch64_enc_strs(src, mem) );


7805   ins_pipe(ialu_reg);
7806 %}
7807 
7808 // Convert oop into int for vectors alignment masking
7809 instruct convP2I(iRegINoSp dst, iRegP src) %{
7810   match(Set dst (ConvL2I (CastP2X src)));
7811 
7812   ins_cost(INSN_COST);
7813   format %{ "movw $dst, $src\t# ptr -> int" %}
7814   ins_encode %{
7815     __ movw($dst$$Register, $src$$Register);
7816   %}
7817 
7818   ins_pipe(ialu_reg);
7819 %}
7820 
7821 // Convert compressed oop into int for vectors alignment masking
7822 // in case of 32bit oops (heap < 4Gb).
7823 instruct convN2I(iRegINoSp dst, iRegN src)
7824 %{
7825   predicate(CompressedOops::shift() == 0);
7826   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
7827 
7828   ins_cost(INSN_COST);
7829   format %{ "mov dst, $src\t# compressed ptr -> int" %}
7830   ins_encode %{
7831     __ movw($dst$$Register, $src$$Register);
7832   %}
7833 
7834   ins_pipe(ialu_reg);
7835 %}
7836 
7837 
7838 // Convert oop pointer into compressed form
7839 instruct encodeHeapOop(iRegNNoSp dst, iRegP src, rFlagsReg cr) %{
7840   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
7841   match(Set dst (EncodeP src));
7842   effect(KILL cr);
7843   ins_cost(INSN_COST * 3);
7844   format %{ "encode_heap_oop $dst, $src" %}
7845   ins_encode %{


11326   format %{ "sub  $dst, $src1, $src2, LSL $src3" %}
11327 
11328   ins_encode %{
11329     __ sub(as_Register($dst$$reg),
11330               as_Register($src1$$reg),
11331               as_Register($src2$$reg),
11332               Assembler::LSL,
11333               $src3$$constant & 0x3f);
11334   %}
11335 
11336   ins_pipe(ialu_reg_reg_shift);
11337 %}
11338 
11339 
11340 
11341 // Shift Left followed by Shift Right.
11342 // This idiom is used by the compiler for the i2b bytecode etc.
11343 instruct sbfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
11344 %{
11345   match(Set dst (RShiftL (LShiftL src lshift_count) rshift_count));




11346   ins_cost(INSN_COST * 2);
11347   format %{ "sbfm  $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
11348   ins_encode %{
11349     int lshift = $lshift_count$$constant & 63;
11350     int rshift = $rshift_count$$constant & 63;
11351     int s = 63 - lshift;
11352     int r = (rshift - lshift) & 63;
11353     __ sbfm(as_Register($dst$$reg),
11354             as_Register($src$$reg),
11355             r, s);
11356   %}
11357 
11358   ins_pipe(ialu_reg_shift);
11359 %}
11360 
11361 // Shift Left followed by Shift Right.
11362 // This idiom is used by the compiler for the i2b bytecode etc.
11363 instruct sbfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
11364 %{
11365   match(Set dst (RShiftI (LShiftI src lshift_count) rshift_count));




11366   ins_cost(INSN_COST * 2);
11367   format %{ "sbfmw  $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
11368   ins_encode %{
11369     int lshift = $lshift_count$$constant & 31;
11370     int rshift = $rshift_count$$constant & 31;
11371     int s = 31 - lshift;
11372     int r = (rshift - lshift) & 31;
11373     __ sbfmw(as_Register($dst$$reg),
11374             as_Register($src$$reg),
11375             r, s);
11376   %}
11377 
11378   ins_pipe(ialu_reg_shift);
11379 %}
11380 
11381 // Shift Left followed by Shift Right.
11382 // This idiom is used by the compiler for the i2b bytecode etc.
11383 instruct ubfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
11384 %{
11385   match(Set dst (URShiftL (LShiftL src lshift_count) rshift_count));




11386   ins_cost(INSN_COST * 2);
11387   format %{ "ubfm  $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
11388   ins_encode %{
11389     int lshift = $lshift_count$$constant & 63;
11390     int rshift = $rshift_count$$constant & 63;
11391     int s = 63 - lshift;
11392     int r = (rshift - lshift) & 63;
11393     __ ubfm(as_Register($dst$$reg),
11394             as_Register($src$$reg),
11395             r, s);
11396   %}
11397 
11398   ins_pipe(ialu_reg_shift);
11399 %}
11400 
11401 // Shift Left followed by Shift Right.
11402 // This idiom is used by the compiler for the i2b bytecode etc.
11403 instruct ubfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
11404 %{
11405   match(Set dst (URShiftI (LShiftI src lshift_count) rshift_count));




11406   ins_cost(INSN_COST * 2);
11407   format %{ "ubfmw  $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
11408   ins_encode %{
11409     int lshift = $lshift_count$$constant & 31;
11410     int rshift = $rshift_count$$constant & 31;
11411     int s = 31 - lshift;
11412     int r = (rshift - lshift) & 31;
11413     __ ubfmw(as_Register($dst$$reg),
11414             as_Register($src$$reg),
11415             r, s);
11416   %}
11417 
11418   ins_pipe(ialu_reg_shift);
11419 %}
11420 // Bitfield extract with shift & mask
11421 
11422 instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
11423 %{
11424   match(Set dst (AndI (URShiftI src rshift) mask));
11425   // Make sure we are not going to exceed what ubfxw can do.
11426   predicate((exact_log2(n->in(2)->get_int() + 1) + (n->in(1)->in(2)->get_int() & 31)) <= (31 + 1));
11427 
11428   ins_cost(INSN_COST);
11429   format %{ "ubfxw $dst, $src, $rshift, $mask" %}
11430   ins_encode %{
11431     int rshift = $rshift$$constant & 31;
11432     long mask = $mask$$constant;
11433     int width = exact_log2(mask+1);
11434     __ ubfxw(as_Register($dst$$reg),
11435             as_Register($src$$reg), rshift, width);
11436   %}
11437   ins_pipe(ialu_reg_shift);
11438 %}
11439 instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
11440 %{
11441   match(Set dst (AndL (URShiftL src rshift) mask));
11442   // Make sure we are not going to exceed what ubfx can do.
11443   predicate((exact_log2_long(n->in(2)->get_long() + 1) + (n->in(1)->in(2)->get_int() & 63)) <= (63 + 1));
11444 
11445   ins_cost(INSN_COST);
11446   format %{ "ubfx $dst, $src, $rshift, $mask" %}
11447   ins_encode %{
11448     int rshift = $rshift$$constant & 63;
11449     long mask = $mask$$constant;
11450     int width = exact_log2_long(mask+1);
11451     __ ubfx(as_Register($dst$$reg),
11452             as_Register($src$$reg), rshift, width);
11453   %}
11454   ins_pipe(ialu_reg_shift);
11455 %}
11456 
11457 // We can use ubfx when extending an And with a mask when we know mask
11458 // is positive.  We know that because immI_bitmask guarantees it.
11459 instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
11460 %{
11461   match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));
11462   // Make sure we are not going to exceed what ubfxw can do.
11463   predicate((exact_log2(n->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(1)->in(2)->get_int() & 31)) <= (31 + 1));
11464 
11465   ins_cost(INSN_COST * 2);
11466   format %{ "ubfx $dst, $src, $rshift, $mask" %}
11467   ins_encode %{
11468     int rshift = $rshift$$constant & 31;
11469     long mask = $mask$$constant;
11470     int width = exact_log2(mask+1);
11471     __ ubfx(as_Register($dst$$reg),
11472             as_Register($src$$reg), rshift, width);
11473   %}
11474   ins_pipe(ialu_reg_shift);
11475 %}
11476 
11477 // We can use ubfiz when masking by a positive number and then left shifting the result.
11478 // We know that the mask is positive because immI_bitmask guarantees it.
11479 instruct ubfizwI(iRegINoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
11480 %{
11481   match(Set dst (LShiftI (AndI src mask) lshift));
11482   predicate((exact_log2(n->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 31)) <= (31 + 1));

11483 
11484   ins_cost(INSN_COST);
11485   format %{ "ubfizw $dst, $src, $lshift, $mask" %}
11486   ins_encode %{
11487     int lshift = $lshift$$constant & 31;
11488     long mask = $mask$$constant;
11489     int width = exact_log2(mask+1);
11490     __ ubfizw(as_Register($dst$$reg),
11491           as_Register($src$$reg), lshift, width);
11492   %}
11493   ins_pipe(ialu_reg_shift);
11494 %}
11495 // We can use ubfiz when masking by a positive number and then left shifting the result.
11496 // We know that the mask is positive because immL_bitmask guarantees it.
11497 instruct ubfizL(iRegLNoSp dst, iRegL src, immI lshift, immL_bitmask mask)
11498 %{
11499   match(Set dst (LShiftL (AndL src mask) lshift));
11500   predicate((exact_log2_long(n->in(1)->in(2)->get_long() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1));

11501 
11502   ins_cost(INSN_COST);
11503   format %{ "ubfiz $dst, $src, $lshift, $mask" %}
11504   ins_encode %{
11505     int lshift = $lshift$$constant & 63;
11506     long mask = $mask$$constant;
11507     int width = exact_log2_long(mask+1);
11508     __ ubfiz(as_Register($dst$$reg),
11509           as_Register($src$$reg), lshift, width);
11510   %}
11511   ins_pipe(ialu_reg_shift);
11512 %}
11513 
11514 // If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz
11515 instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
11516 %{
11517   match(Set dst (LShiftL (ConvI2L (AndI src mask)) lshift));
11518   predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1));

11519 
11520   ins_cost(INSN_COST);
11521   format %{ "ubfiz $dst, $src, $lshift, $mask" %}
11522   ins_encode %{
11523     int lshift = $lshift$$constant & 63;
11524     long mask = $mask$$constant;
11525     int width = exact_log2(mask+1);
11526     __ ubfiz(as_Register($dst$$reg),
11527              as_Register($src$$reg), lshift, width);
11528   %}
11529   ins_pipe(ialu_reg_shift);
11530 %}
11531 
11532 // Rotations
11533 
11534 instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
11535 %{
11536   match(Set dst (OrL (LShiftL src1 lshift) (URShiftL src2 rshift)));
11537   predicate(0 == (((n->in(1)->in(2)->get_int() & 63) + (n->in(2)->in(2)->get_int() & 63)) & 63));
11538 
11539   ins_cost(INSN_COST);
11540   format %{ "extr $dst, $src1, $src2, #$rshift" %}
11541 
11542   ins_encode %{
11543     __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
11544             $rshift$$constant & 63);
11545   %}
11546   ins_pipe(ialu_reg_reg_extr);
11547 %}
11548 
11549 instruct extrOrI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
11550 %{
11551   match(Set dst (OrI (LShiftI src1 lshift) (URShiftI src2 rshift)));
11552   predicate(0 == (((n->in(1)->in(2)->get_int() & 31) + (n->in(2)->in(2)->get_int() & 31)) & 31));
11553 
11554   ins_cost(INSN_COST);
11555   format %{ "extr $dst, $src1, $src2, #$rshift" %}
11556 
11557   ins_encode %{
11558     __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
11559             $rshift$$constant & 31);
11560   %}
11561   ins_pipe(ialu_reg_reg_extr);
11562 %}
11563 
11564 instruct extrAddL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
11565 %{
11566   match(Set dst (AddL (LShiftL src1 lshift) (URShiftL src2 rshift)));
11567   predicate(0 == (((n->in(1)->in(2)->get_int() & 63) + (n->in(2)->in(2)->get_int() & 63)) & 63));
11568 
11569   ins_cost(INSN_COST);
11570   format %{ "extr $dst, $src1, $src2, #$rshift" %}
11571 
11572   ins_encode %{
11573     __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
11574             $rshift$$constant & 63);
11575   %}
11576   ins_pipe(ialu_reg_reg_extr);
11577 %}
11578 
11579 instruct extrAddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
11580 %{
11581   match(Set dst (AddI (LShiftI src1 lshift) (URShiftI src2 rshift)));
11582   predicate(0 == (((n->in(1)->in(2)->get_int() & 31) + (n->in(2)->in(2)->get_int() & 31)) & 31));
11583 
11584   ins_cost(INSN_COST);
11585   format %{ "extr $dst, $src1, $src2, #$rshift" %}
11586 
11587   ins_encode %{
11588     __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
11589             $rshift$$constant & 31);
11590   %}
11591   ins_pipe(ialu_reg_reg_extr);
11592 %}
11593 
11594 
11595 // rol expander
11596 
11597 instruct rolL_rReg(iRegLNoSp dst, iRegL src, iRegI shift, rFlagsReg cr)
11598 %{
11599   effect(DEF dst, USE src, USE shift);
11600 
11601   format %{ "rol    $dst, $src, $shift" %}
11602   ins_cost(INSN_COST * 3);


14029 
14030 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr)
14031 %{
14032   match(Set dst (CmpLTMask src zero));
14033   effect(KILL cr);
14034 
14035   ins_cost(INSN_COST);
14036 
14037   format %{ "asrw $dst, $src, #31\t# cmpLTMask0" %}
14038 
14039   ins_encode %{
14040     __ asrw(as_Register($dst$$reg), as_Register($src$$reg), 31);
14041   %}
14042 
14043   ins_pipe(ialu_reg_shift);
14044 %}
14045 
14046 // ============================================================================
14047 // Max and Min
14048 
14049 instruct cmovI_reg_reg_lt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
14050 %{
14051   effect( DEF dst, USE src1, USE src2, USE cr );
14052 
14053   ins_cost(INSN_COST * 2);
14054   format %{ "cselw $dst, $src1, $src2 lt\t"  %}






14055 
14056   ins_encode %{


14057     __ cselw(as_Register($dst$$reg),
14058              as_Register($src1$$reg),
14059              as_Register($src2$$reg),
14060              Assembler::LT);
14061   %}
14062 
14063   ins_pipe(icond_reg_reg);
14064 %}
14065 
14066 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
14067 %{
14068   match(Set dst (MinI src1 src2));
14069   ins_cost(INSN_COST * 3);
14070 
14071   expand %{
14072     rFlagsReg cr;
14073     compI_reg_reg(cr, src1, src2);
14074     cmovI_reg_reg_lt(dst, src1, src2, cr);
14075   %}
14076 
14077 %}
14078 // FROM HERE
14079 
14080 instruct cmovI_reg_reg_gt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
14081 %{
14082   effect( DEF dst, USE src1, USE src2, USE cr );
14083 
14084   ins_cost(INSN_COST * 2);
14085   format %{ "cselw $dst, $src1, $src2 gt\t"  %}






14086 
14087   ins_encode %{


14088     __ cselw(as_Register($dst$$reg),
14089              as_Register($src1$$reg),
14090              as_Register($src2$$reg),
14091              Assembler::GT);
14092   %}
14093 
14094   ins_pipe(icond_reg_reg);
14095 %}
14096 
14097 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
14098 %{
14099   match(Set dst (MaxI src1 src2));
14100   ins_cost(INSN_COST * 3);
14101   expand %{
14102     rFlagsReg cr;
14103     compI_reg_reg(cr, src1, src2);
14104     cmovI_reg_reg_gt(dst, src1, src2, cr);
14105   %}
14106 %}
14107 
14108 // ============================================================================
14109 // Branch Instructions
14110 
14111 // Direct Branch.
14112 instruct branch(label lbl)
14113 %{
14114   match(Goto);
14115 
14116   effect(USE lbl);
14117 
14118   ins_cost(BRANCH_COST);
14119   format %{ "b  $lbl" %}
14120 
14121   ins_encode(aarch64_enc_b(lbl));
14122 
14123   ins_pipe(pipe_branch);
14124 %}
14125 




1945   if (Assembler::operand_valid_for_add_sub_immediate(offset)) {
1946     __ add(as_Register(reg), sp, offset);
1947   } else {
1948     ShouldNotReachHere();
1949   }
1950 }
1951 
1952 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1953   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1954   return 4;
1955 }
1956 
1957 //=============================================================================
1958 
1959 #ifndef PRODUCT
1960 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1961 {
1962   st->print_cr("# MachUEPNode");
1963   if (UseCompressedClassPointers) {
1964     st->print_cr("\tldrw rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1965     if (Universe::narrow_klass_shift() != 0) {
1966       st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1967     }
1968   } else {
1969    st->print_cr("\tldr rscratch1, j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1970   }
1971   st->print_cr("\tcmp r0, rscratch1\t # Inline cache check");
1972   st->print_cr("\tbne, SharedRuntime::_ic_miss_stub");
1973 }
1974 #endif
1975 
1976 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1977 {
1978   // This is the unverified entry point.
1979   MacroAssembler _masm(&cbuf);
1980 
1981   __ cmp_klass(j_rarg0, rscratch2, rscratch1);
1982   Label skip;
1983   // TODO
1984   // can we avoid this skip and still use a reloc?
1985   __ br(Assembler::EQ, skip);


2166 }
2167 
2168 // Does the CPU require late expand (see block.cpp for description of late expand)?
2169 const bool Matcher::require_postalloc_expand = false;
2170 
2171 // Do we need to mask the count passed to shift instructions or does
2172 // the cpu only look at the lower 5/6 bits anyway?
2173 const bool Matcher::need_masked_shift_count = false;
2174 
2175 // This affects two different things:
2176 //  - how Decode nodes are matched
2177 //  - how ImplicitNullCheck opportunities are recognized
2178 // If true, the matcher will try to remove all Decodes and match them
2179 // (as operands) into nodes. NullChecks are not prepared to deal with
2180 // Decodes by final_graph_reshaping().
2181 // If false, final_graph_reshaping() forces the decode behind the Cmp
2182 // for a NullCheck. The matcher matches the Decode node into a register.
2183 // Implicit_null_check optimization moves the Decode along with the
2184 // memory operation back up before the NullCheck.
2185 bool Matcher::narrow_oop_use_complex_address() {
2186   return Universe::narrow_oop_shift() == 0;
2187 }
2188 
2189 bool Matcher::narrow_klass_use_complex_address() {
2190 // TODO
2191 // decide whether we need to set this to true
2192   return false;
2193 }
2194 
2195 bool Matcher::const_oop_prefer_decode() {
2196   // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
2197   return Universe::narrow_oop_base() == NULL;
2198 }
2199 
2200 bool Matcher::const_klass_prefer_decode() {
2201   // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
2202   return Universe::narrow_klass_base() == NULL;
2203 }
2204 
2205 // Is it better to copy float constants, or load them directly from
2206 // memory?  Intel can load a float constant from a direct address,
2207 // requiring no extra registers.  Most RISCs will have to materialize
2208 // an address into a register first, so they would do better to copy
2209 // the constant from stack.
2210 const bool Matcher::rematerialize_float_constants = false;
2211 
2212 // If CPU can load and store mis-aligned doubles directly then no
2213 // fixup is needed.  Else we split the double into 2 integer pieces
2214 // and move it piece-by-piece.  Only happens when passing doubles into
2215 // C code as the Java calling convention forces doubles to be aligned.
2216 const bool Matcher::misaligned_doubles_ok = true;
2217 
2218 // No-op on amd64
2219 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2220   Unimplemented();
2221 }
2222 


3915   predicate(n->get_long() == 65535L);
3916   match(ConL);
3917 
3918   op_cost(0);
3919   format %{ %}
3920   interface(CONST_INTER);
3921 %}
3922 
3923 operand immL_4294967295()
3924 %{
3925   predicate(n->get_long() == 4294967295L);
3926   match(ConL);
3927 
3928   op_cost(0);
3929   format %{ %}
3930   interface(CONST_INTER);
3931 %}
3932 
3933 operand immL_bitmask()
3934 %{
3935   predicate(((n->get_long() & 0xc000000000000000l) == 0)

3936             && is_power_of_2(n->get_long() + 1));
3937   match(ConL);
3938 
3939   op_cost(0);
3940   format %{ %}
3941   interface(CONST_INTER);
3942 %}
3943 
3944 operand immI_bitmask()
3945 %{
3946   predicate(((n->get_int() & 0xc0000000) == 0)

3947             && is_power_of_2(n->get_int() + 1));
3948   match(ConI);
3949 
3950   op_cost(0);
3951   format %{ %}
3952   interface(CONST_INTER);
3953 %}
3954 
3955 // Scale values for scaled offset addressing modes (up to long but not quad)
3956 operand immIScale()
3957 %{
3958   predicate(0 <= n->get_int() && (n->get_int() <= 3));
3959   match(ConI);
3960 
3961   op_cost(0);
3962   format %{ %}
3963   interface(CONST_INTER);
3964 %}
3965 
3966 // 26 bit signed offset -- for pc-relative branches


5025     disp($off);
5026   %}
5027 %}
5028 
5029 operand indOffL16(iRegP reg, immLoffset16 off)
5030 %{
5031   constraint(ALLOC_IN_RC(ptr_reg));
5032   match(AddP reg off);
5033   op_cost(0);
5034   format %{ "[$reg, $off]" %}
5035   interface(MEMORY_INTER) %{
5036     base($reg);
5037     index(0xffffffff);
5038     scale(0x0);
5039     disp($off);
5040   %}
5041 %}
5042 
5043 operand indirectN(iRegN reg)
5044 %{
5045   predicate(Universe::narrow_oop_shift() == 0);
5046   constraint(ALLOC_IN_RC(ptr_reg));
5047   match(DecodeN reg);
5048   op_cost(0);
5049   format %{ "[$reg]\t# narrow" %}
5050   interface(MEMORY_INTER) %{
5051     base($reg);
5052     index(0xffffffff);
5053     scale(0x0);
5054     disp(0x0);
5055   %}
5056 %}
5057 
5058 operand indIndexScaledI2LN(iRegN reg, iRegI ireg, immIScale scale)
5059 %{
5060   predicate(Universe::narrow_oop_shift() == 0 && size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5061   constraint(ALLOC_IN_RC(ptr_reg));
5062   match(AddP (DecodeN reg) (LShiftL (ConvI2L ireg) scale));
5063   op_cost(0);
5064   format %{ "$reg, $ireg sxtw($scale), 0, I2L\t# narrow" %}
5065   interface(MEMORY_INTER) %{
5066     base($reg);
5067     index($ireg);
5068     scale($scale);
5069     disp(0x0);
5070   %}
5071 %}
5072 
5073 operand indIndexScaledN(iRegN reg, iRegL lreg, immIScale scale)
5074 %{
5075   predicate(Universe::narrow_oop_shift() == 0 && size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5076   constraint(ALLOC_IN_RC(ptr_reg));
5077   match(AddP (DecodeN reg) (LShiftL lreg scale));
5078   op_cost(0);
5079   format %{ "$reg, $lreg lsl($scale)\t# narrow" %}
5080   interface(MEMORY_INTER) %{
5081     base($reg);
5082     index($lreg);
5083     scale($scale);
5084     disp(0x0);
5085   %}
5086 %}
5087 
5088 operand indIndexI2LN(iRegN reg, iRegI ireg)
5089 %{
5090   predicate(Universe::narrow_oop_shift() == 0);
5091   constraint(ALLOC_IN_RC(ptr_reg));
5092   match(AddP (DecodeN reg) (ConvI2L ireg));
5093   op_cost(0);
5094   format %{ "$reg, $ireg, 0, I2L\t# narrow" %}
5095   interface(MEMORY_INTER) %{
5096     base($reg);
5097     index($ireg);
5098     scale(0x0);
5099     disp(0x0);
5100   %}
5101 %}
5102 
5103 operand indIndexN(iRegN reg, iRegL lreg)
5104 %{
5105   predicate(Universe::narrow_oop_shift() == 0);
5106   constraint(ALLOC_IN_RC(ptr_reg));
5107   match(AddP (DecodeN reg) lreg);
5108   op_cost(0);
5109   format %{ "$reg, $lreg\t# narrow" %}
5110   interface(MEMORY_INTER) %{
5111     base($reg);
5112     index($lreg);
5113     scale(0x0);
5114     disp(0x0);
5115   %}
5116 %}
5117 
5118 operand indOffIN(iRegN reg, immIOffset off)
5119 %{
5120   predicate(Universe::narrow_oop_shift() == 0);
5121   constraint(ALLOC_IN_RC(ptr_reg));
5122   match(AddP (DecodeN reg) off);
5123   op_cost(0);
5124   format %{ "[$reg, $off]\t# narrow" %}
5125   interface(MEMORY_INTER) %{
5126     base($reg);
5127     index(0xffffffff);
5128     scale(0x0);
5129     disp($off);
5130   %}
5131 %}
5132 
5133 operand indOffLN(iRegN reg, immLoffset off)
5134 %{
5135   predicate(Universe::narrow_oop_shift() == 0);
5136   constraint(ALLOC_IN_RC(ptr_reg));
5137   match(AddP (DecodeN reg) off);
5138   op_cost(0);
5139   format %{ "[$reg, $off]\t# narrow" %}
5140   interface(MEMORY_INTER) %{
5141     base($reg);
5142     index(0xffffffff);
5143     scale(0x0);
5144     disp($off);
5145   %}
5146 %}
5147 
5148 
5149 
5150 // AArch64 opto stubs need to write to the pc slot in the thread anchor
5151 operand thread_anchor_pc(thread_RegP reg, immL_pc_off off)
5152 %{
5153   constraint(ALLOC_IN_RC(ptr_reg));
5154   match(AddP reg off);
5155   op_cost(0);


7020   ins_pipe(istore_mem);
7021 %}
7022 
7023 // Store Compressed Pointer
7024 instruct storeN(iRegN src, memory mem)
7025 %{
7026   match(Set mem (StoreN mem src));
7027   predicate(!needs_releasing_store(n));
7028 
7029   ins_cost(INSN_COST);
7030   format %{ "strw  $src, $mem\t# compressed ptr" %}
7031 
7032   ins_encode(aarch64_enc_strw(src, mem));
7033 
7034   ins_pipe(istore_reg_mem);
7035 %}
7036 
7037 instruct storeImmN0(iRegIHeapbase heapbase, immN0 zero, memory mem)
7038 %{
7039   match(Set mem (StoreN mem zero));
7040   predicate(Universe::narrow_oop_base() == NULL &&
7041             Universe::narrow_klass_base() == NULL &&
7042             (!needs_releasing_store(n)));
7043 
7044   ins_cost(INSN_COST);
7045   format %{ "strw  rheapbase, $mem\t# compressed ptr (rheapbase==0)" %}
7046 
7047   ins_encode(aarch64_enc_strw(heapbase, mem));
7048 
7049   ins_pipe(istore_reg_mem);
7050 %}
7051 
7052 // Store Float
7053 instruct storeF(vRegF src, memory mem)
7054 %{
7055   match(Set mem (StoreF mem src));
7056   predicate(!needs_releasing_store(n));
7057 
7058   ins_cost(INSN_COST);
7059   format %{ "strs  $src, $mem\t# float" %}
7060 
7061   ins_encode( aarch64_enc_strs(src, mem) );


7803   ins_pipe(ialu_reg);
7804 %}
7805 
7806 // Convert oop into int for vectors alignment masking
7807 instruct convP2I(iRegINoSp dst, iRegP src) %{
7808   match(Set dst (ConvL2I (CastP2X src)));
7809 
7810   ins_cost(INSN_COST);
7811   format %{ "movw $dst, $src\t# ptr -> int" %}
7812   ins_encode %{
7813     __ movw($dst$$Register, $src$$Register);
7814   %}
7815 
7816   ins_pipe(ialu_reg);
7817 %}
7818 
7819 // Convert compressed oop into int for vectors alignment masking
7820 // in case of 32bit oops (heap < 4Gb).
7821 instruct convN2I(iRegINoSp dst, iRegN src)
7822 %{
7823   predicate(Universe::narrow_oop_shift() == 0);
7824   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
7825 
7826   ins_cost(INSN_COST);
7827   format %{ "mov dst, $src\t# compressed ptr -> int" %}
7828   ins_encode %{
7829     __ movw($dst$$Register, $src$$Register);
7830   %}
7831 
7832   ins_pipe(ialu_reg);
7833 %}
7834 
7835 
7836 // Convert oop pointer into compressed form
7837 instruct encodeHeapOop(iRegNNoSp dst, iRegP src, rFlagsReg cr) %{
7838   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
7839   match(Set dst (EncodeP src));
7840   effect(KILL cr);
7841   ins_cost(INSN_COST * 3);
7842   format %{ "encode_heap_oop $dst, $src" %}
7843   ins_encode %{


11324   format %{ "sub  $dst, $src1, $src2, LSL $src3" %}
11325 
11326   ins_encode %{
11327     __ sub(as_Register($dst$$reg),
11328               as_Register($src1$$reg),
11329               as_Register($src2$$reg),
11330               Assembler::LSL,
11331               $src3$$constant & 0x3f);
11332   %}
11333 
11334   ins_pipe(ialu_reg_reg_shift);
11335 %}
11336 
11337 
11338 
11339 // Shift Left followed by Shift Right.
11340 // This idiom is used by the compiler for the i2b bytecode etc.
11341 instruct sbfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
11342 %{
11343   match(Set dst (RShiftL (LShiftL src lshift_count) rshift_count));
11344   // Make sure we are not going to exceed what sbfm can do.
11345   predicate((unsigned int)n->in(2)->get_int() <= 63
11346             && (unsigned int)n->in(1)->in(2)->get_int() <= 63);
11347 
11348   ins_cost(INSN_COST * 2);
11349   format %{ "sbfm  $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
11350   ins_encode %{
11351     int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;

11352     int s = 63 - lshift;
11353     int r = (rshift - lshift) & 63;
11354     __ sbfm(as_Register($dst$$reg),
11355             as_Register($src$$reg),
11356             r, s);
11357   %}
11358 
11359   ins_pipe(ialu_reg_shift);
11360 %}
11361 
11362 // Shift Left followed by Shift Right.
11363 // This idiom is used by the compiler for the i2b bytecode etc.
11364 instruct sbfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
11365 %{
11366   match(Set dst (RShiftI (LShiftI src lshift_count) rshift_count));
11367   // Make sure we are not going to exceed what sbfmw can do.
11368   predicate((unsigned int)n->in(2)->get_int() <= 31
11369             && (unsigned int)n->in(1)->in(2)->get_int() <= 31);
11370 
11371   ins_cost(INSN_COST * 2);
11372   format %{ "sbfmw  $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
11373   ins_encode %{
11374     int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;

11375     int s = 31 - lshift;
11376     int r = (rshift - lshift) & 31;
11377     __ sbfmw(as_Register($dst$$reg),
11378             as_Register($src$$reg),
11379             r, s);
11380   %}
11381 
11382   ins_pipe(ialu_reg_shift);
11383 %}
11384 
11385 // Shift Left followed by Shift Right.
11386 // This idiom is used by the compiler for the i2b bytecode etc.
11387 instruct ubfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
11388 %{
11389   match(Set dst (URShiftL (LShiftL src lshift_count) rshift_count));
11390   // Make sure we are not going to exceed what ubfm can do.
11391   predicate((unsigned int)n->in(2)->get_int() <= 63
11392             && (unsigned int)n->in(1)->in(2)->get_int() <= 63);
11393 
11394   ins_cost(INSN_COST * 2);
11395   format %{ "ubfm  $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
11396   ins_encode %{
11397     int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;

11398     int s = 63 - lshift;
11399     int r = (rshift - lshift) & 63;
11400     __ ubfm(as_Register($dst$$reg),
11401             as_Register($src$$reg),
11402             r, s);
11403   %}
11404 
11405   ins_pipe(ialu_reg_shift);
11406 %}
11407 
11408 // Shift Left followed by Shift Right.
11409 // This idiom is used by the compiler for the i2b bytecode etc.
11410 instruct ubfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
11411 %{
11412   match(Set dst (URShiftI (LShiftI src lshift_count) rshift_count));
11413   // Make sure we are not going to exceed what ubfmw can do.
11414   predicate((unsigned int)n->in(2)->get_int() <= 31
11415             && (unsigned int)n->in(1)->in(2)->get_int() <= 31);
11416 
11417   ins_cost(INSN_COST * 2);
11418   format %{ "ubfmw  $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
11419   ins_encode %{
11420     int lshift = $lshift_count$$constant, rshift = $rshift_count$$constant;

11421     int s = 31 - lshift;
11422     int r = (rshift - lshift) & 31;
11423     __ ubfmw(as_Register($dst$$reg),
11424             as_Register($src$$reg),
11425             r, s);
11426   %}
11427 
11428   ins_pipe(ialu_reg_shift);
11429 %}
11430 // Bitfield extract with shift & mask
11431 
11432 instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
11433 %{
11434   match(Set dst (AndI (URShiftI src rshift) mask));


11435 
11436   ins_cost(INSN_COST);
11437   format %{ "ubfxw $dst, $src, $rshift, $mask" %}
11438   ins_encode %{
11439     int rshift = $rshift$$constant;
11440     long mask = $mask$$constant;
11441     int width = exact_log2(mask+1);
11442     __ ubfxw(as_Register($dst$$reg),
11443             as_Register($src$$reg), rshift, width);
11444   %}
11445   ins_pipe(ialu_reg_shift);
11446 %}
11447 instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
11448 %{
11449   match(Set dst (AndL (URShiftL src rshift) mask));


11450 
11451   ins_cost(INSN_COST);
11452   format %{ "ubfx $dst, $src, $rshift, $mask" %}
11453   ins_encode %{
11454     int rshift = $rshift$$constant;
11455     long mask = $mask$$constant;
11456     int width = exact_log2(mask+1);
11457     __ ubfx(as_Register($dst$$reg),
11458             as_Register($src$$reg), rshift, width);
11459   %}
11460   ins_pipe(ialu_reg_shift);
11461 %}
11462 
11463 // We can use ubfx when extending an And with a mask when we know mask
11464 // is positive.  We know that because immI_bitmask guarantees it.
11465 instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
11466 %{
11467   match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));


11468 
11469   ins_cost(INSN_COST * 2);
11470   format %{ "ubfx $dst, $src, $rshift, $mask" %}
11471   ins_encode %{
11472     int rshift = $rshift$$constant;
11473     long mask = $mask$$constant;
11474     int width = exact_log2(mask+1);
11475     __ ubfx(as_Register($dst$$reg),
11476             as_Register($src$$reg), rshift, width);
11477   %}
11478   ins_pipe(ialu_reg_shift);
11479 %}
11480 
11481 // We can use ubfiz when masking by a positive number and then left shifting the result.
11482 // We know that the mask is positive because immI_bitmask guarantees it.
11483 instruct ubfizwI(iRegINoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
11484 %{
11485   match(Set dst (LShiftI (AndI src mask) lshift));
11486   predicate((unsigned int)n->in(2)->get_int() <= 31 &&
11487     (exact_log2(n->in(1)->in(2)->get_int()+1) + (unsigned int)n->in(2)->get_int()) <= (31+1));
11488 
11489   ins_cost(INSN_COST);
11490   format %{ "ubfizw $dst, $src, $lshift, $mask" %}
11491   ins_encode %{
11492     int lshift = $lshift$$constant;
11493     long mask = $mask$$constant;
11494     int width = exact_log2(mask+1);
11495     __ ubfizw(as_Register($dst$$reg),
11496           as_Register($src$$reg), lshift, width);
11497   %}
11498   ins_pipe(ialu_reg_shift);
11499 %}
11500 // We can use ubfiz when masking by a positive number and then left shifting the result.
11501 // We know that the mask is positive because immL_bitmask guarantees it.
11502 instruct ubfizL(iRegLNoSp dst, iRegL src, immI lshift, immL_bitmask mask)
11503 %{
11504   match(Set dst (LShiftL (AndL src mask) lshift));
11505   predicate((unsigned int)n->in(2)->get_int() <= 63 &&
11506     (exact_log2_long(n->in(1)->in(2)->get_long()+1) + (unsigned int)n->in(2)->get_int()) <= (63+1));
11507 
11508   ins_cost(INSN_COST);
11509   format %{ "ubfiz $dst, $src, $lshift, $mask" %}
11510   ins_encode %{
11511     int lshift = $lshift$$constant;
11512     long mask = $mask$$constant;
11513     int width = exact_log2(mask+1);
11514     __ ubfiz(as_Register($dst$$reg),
11515           as_Register($src$$reg), lshift, width);
11516   %}
11517   ins_pipe(ialu_reg_shift);
11518 %}
11519 
11520 // If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz
11521 instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
11522 %{
11523   match(Set dst (LShiftL (ConvI2L(AndI src mask)) lshift));
11524   predicate((unsigned int)n->in(2)->get_int() <= 31 &&
11525     (exact_log2((unsigned int)n->in(1)->in(1)->in(2)->get_int()+1) + (unsigned int)n->in(2)->get_int()) <= 32);
11526 
11527   ins_cost(INSN_COST);
11528   format %{ "ubfiz $dst, $src, $lshift, $mask" %}
11529   ins_encode %{
11530     int lshift = $lshift$$constant;
11531     long mask = $mask$$constant;
11532     int width = exact_log2(mask+1);
11533     __ ubfiz(as_Register($dst$$reg),
11534              as_Register($src$$reg), lshift, width);
11535   %}
11536   ins_pipe(ialu_reg_shift);
11537 %}
11538 
11539 // Rotations
11540 
11541 instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
11542 %{
11543   match(Set dst (OrL (LShiftL src1 lshift) (URShiftL src2 rshift)));
11544   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 63));
11545 
11546   ins_cost(INSN_COST);
11547   format %{ "extr $dst, $src1, $src2, #$rshift" %}
11548 
11549   ins_encode %{
11550     __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
11551             $rshift$$constant & 63);
11552   %}
11553   ins_pipe(ialu_reg_reg_extr);
11554 %}
11555 
11556 instruct extrOrI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
11557 %{
11558   match(Set dst (OrI (LShiftI src1 lshift) (URShiftI src2 rshift)));
11559   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 31));
11560 
11561   ins_cost(INSN_COST);
11562   format %{ "extr $dst, $src1, $src2, #$rshift" %}
11563 
11564   ins_encode %{
11565     __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
11566             $rshift$$constant & 31);
11567   %}
11568   ins_pipe(ialu_reg_reg_extr);
11569 %}
11570 
11571 instruct extrAddL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
11572 %{
11573   match(Set dst (AddL (LShiftL src1 lshift) (URShiftL src2 rshift)));
11574   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 63));
11575 
11576   ins_cost(INSN_COST);
11577   format %{ "extr $dst, $src1, $src2, #$rshift" %}
11578 
11579   ins_encode %{
11580     __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
11581             $rshift$$constant & 63);
11582   %}
11583   ins_pipe(ialu_reg_reg_extr);
11584 %}
11585 
11586 instruct extrAddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
11587 %{
11588   match(Set dst (AddI (LShiftI src1 lshift) (URShiftI src2 rshift)));
11589   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 31));
11590 
11591   ins_cost(INSN_COST);
11592   format %{ "extr $dst, $src1, $src2, #$rshift" %}
11593 
11594   ins_encode %{
11595     __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
11596             $rshift$$constant & 31);
11597   %}
11598   ins_pipe(ialu_reg_reg_extr);
11599 %}
11600 
11601 
11602 // rol expander
11603 
11604 instruct rolL_rReg(iRegLNoSp dst, iRegL src, iRegI shift, rFlagsReg cr)
11605 %{
11606   effect(DEF dst, USE src, USE shift);
11607 
11608   format %{ "rol    $dst, $src, $shift" %}
11609   ins_cost(INSN_COST * 3);


14036 
14037 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr)
14038 %{
14039   match(Set dst (CmpLTMask src zero));
14040   effect(KILL cr);
14041 
14042   ins_cost(INSN_COST);
14043 
14044   format %{ "asrw $dst, $src, #31\t# cmpLTMask0" %}
14045 
14046   ins_encode %{
14047     __ asrw(as_Register($dst$$reg), as_Register($src$$reg), 31);
14048   %}
14049 
14050   ins_pipe(ialu_reg_shift);
14051 %}
14052 
14053 // ============================================================================
14054 // Max and Min
14055 
14056 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
14057 %{
14058   match(Set dst (MinI src1 src2));
14059 
14060   effect(DEF dst, USE src1, USE src2, KILL cr);
14061   size(8);
14062 
14063   ins_cost(INSN_COST * 3);
14064   format %{
14065     "cmpw $src1 $src2\t signed int\n\t"
14066     "cselw $dst, $src1, $src2 lt\t"
14067   %}
14068 
14069   ins_encode %{
14070     __ cmpw(as_Register($src1$$reg),
14071             as_Register($src2$$reg));
14072     __ cselw(as_Register($dst$$reg),
14073              as_Register($src1$$reg),
14074              as_Register($src2$$reg),
14075              Assembler::LT);
14076   %}
14077 
14078   ins_pipe(ialu_reg_reg);













14079 %}
14080 // FROM HERE
14081 
14082 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
14083 %{
14084   match(Set dst (MaxI src1 src2));
14085 
14086   effect(DEF dst, USE src1, USE src2, KILL cr);
14087   size(8);
14088 
14089   ins_cost(INSN_COST * 3);
14090   format %{
14091     "cmpw $src1 $src2\t signed int\n\t"
14092     "cselw $dst, $src1, $src2 gt\t"
14093   %}
14094 
14095   ins_encode %{
14096     __ cmpw(as_Register($src1$$reg),
14097             as_Register($src2$$reg));
14098     __ cselw(as_Register($dst$$reg),
14099              as_Register($src1$$reg),
14100              as_Register($src2$$reg),
14101              Assembler::GT);
14102   %}
14103 
14104   ins_pipe(ialu_reg_reg);











14105 %}
14106 
14107 // ============================================================================
14108 // Branch Instructions
14109 
14110 // Direct Branch.
14111 instruct branch(label lbl)
14112 %{
14113   match(Goto);
14114 
14115   effect(USE lbl);
14116 
14117   ins_cost(BRANCH_COST);
14118   format %{ "b  $lbl" %}
14119 
14120   ins_encode(aarch64_enc_b(lbl));
14121 
14122   ins_pipe(pipe_branch);
14123 %}
14124 


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