< prev index next >

src/hotspot/cpu/aarch64/assembler_aarch64.hpp

Print this page




 612 class Assembler : public AbstractAssembler {
 613 
 614 #ifndef PRODUCT
 615   static const unsigned long asm_bp;
 616 
 617   void emit_long(jint x) {
 618     if ((unsigned long)pc() == asm_bp)
 619       asm volatile ("nop");
 620     AbstractAssembler::emit_int32(x);
 621   }
 622 #else
 623   void emit_long(jint x) {
 624     AbstractAssembler::emit_int32(x);
 625   }
 626 #endif
 627 
 628 public:
 629 
 630   enum { instruction_size = 4 };
 631 
 632   //---<  calculate length of instruction  >---
 633   // We just use the values set above.
 634   // instruction must start at passed address
 635   static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
 636 
 637   //---<  longest instructions  >---
 638   static unsigned int instr_maxlen() { return instruction_size; }
 639 
 640   Address adjust(Register base, int offset, bool preIncrement) {
 641     if (preIncrement)
 642       return Address(Pre(base, offset));
 643     else
 644       return Address(Post(base, offset));
 645   }
 646 
 647   Address pre(Register base, int offset) {
 648     return adjust(base, offset, true);
 649   }
 650 
 651   Address post(Register base, int offset) {
 652     return adjust(base, offset, false);
 653   }
 654 
 655   Address post(Register base, Register idx) {
 656     return Address(Post(base, idx));
 657   }
 658 
 659   Instruction_aarch64* current;


1202   INSN2(ldaxr, xword, 0b010, 1);
1203   INSN_FOO(ldxp, xword, 0b011, 0);
1204   INSN_FOO(ldaxp, xword, 0b011, 1);
1205   INSN2(stlr, xword, 0b100, 1);
1206   INSN2(ldar, xword, 0b110, 1);
1207 
1208 #undef INSN2
1209 #undef INSN3
1210 #undef INSN4
1211 #undef INSN_FOO
1212 
1213   // 8.1 Compare and swap extensions
1214   void lse_cas(Register Rs, Register Rt, Register Rn,
1215                         enum operand_size sz, bool a, bool r, bool not_pair) {
1216     starti;
1217     if (! not_pair) { // Pair
1218       assert(sz == word || sz == xword, "invalid size");
1219       /* The size bit is in bit 30, not 31 */
1220       sz = (operand_size)(sz == word ? 0b00:0b01);
1221     }
1222     f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
1223     zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
1224   }
1225 
1226   // CAS
1227 #define INSN(NAME, a, r)                                                \
1228   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
1229     assert(Rs != Rn && Rs != Rt, "unpredictable instruction");          \
1230     lse_cas(Rs, Rt, Rn, sz, a, r, true);                                \
1231   }
1232   INSN(cas,    false, false)
1233   INSN(casa,   true,  false)
1234   INSN(casl,   false, true)
1235   INSN(casal,  true,  true)
1236 #undef INSN
1237 
1238   // CASP
1239 #define INSN(NAME, a, r)                                                \
1240   void NAME(operand_size sz, Register Rs, Register Rs1,                 \
1241             Register Rt, Register Rt1, Register Rn) {                   \
1242     assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 &&    \
1243            Rs->successor() == Rs1 && Rt->successor() == Rt1 &&          \




 612 class Assembler : public AbstractAssembler {
 613 
 614 #ifndef PRODUCT
 615   static const unsigned long asm_bp;
 616 
 617   void emit_long(jint x) {
 618     if ((unsigned long)pc() == asm_bp)
 619       asm volatile ("nop");
 620     AbstractAssembler::emit_int32(x);
 621   }
 622 #else
 623   void emit_long(jint x) {
 624     AbstractAssembler::emit_int32(x);
 625   }
 626 #endif
 627 
 628 public:
 629 
 630   enum { instruction_size = 4 };
 631 








 632   Address adjust(Register base, int offset, bool preIncrement) {
 633     if (preIncrement)
 634       return Address(Pre(base, offset));
 635     else
 636       return Address(Post(base, offset));
 637   }
 638 
 639   Address pre(Register base, int offset) {
 640     return adjust(base, offset, true);
 641   }
 642 
 643   Address post(Register base, int offset) {
 644     return adjust(base, offset, false);
 645   }
 646 
 647   Address post(Register base, Register idx) {
 648     return Address(Post(base, idx));
 649   }
 650 
 651   Instruction_aarch64* current;


1194   INSN2(ldaxr, xword, 0b010, 1);
1195   INSN_FOO(ldxp, xword, 0b011, 0);
1196   INSN_FOO(ldaxp, xword, 0b011, 1);
1197   INSN2(stlr, xword, 0b100, 1);
1198   INSN2(ldar, xword, 0b110, 1);
1199 
1200 #undef INSN2
1201 #undef INSN3
1202 #undef INSN4
1203 #undef INSN_FOO
1204 
1205   // 8.1 Compare and swap extensions
1206   void lse_cas(Register Rs, Register Rt, Register Rn,
1207                         enum operand_size sz, bool a, bool r, bool not_pair) {
1208     starti;
1209     if (! not_pair) { // Pair
1210       assert(sz == word || sz == xword, "invalid size");
1211       /* The size bit is in bit 30, not 31 */
1212       sz = (operand_size)(sz == word ? 0b00:0b01);
1213     }
1214     f(sz, 31, 30), f(0b001000, 29, 24), f(1, 23), f(a, 22), f(1, 21);
1215     rf(Rs, 16), f(r, 15), f(0b11111, 14, 10), rf(Rn, 5), rf(Rt, 0);
1216   }
1217 
1218   // CAS
1219 #define INSN(NAME, a, r)                                                \
1220   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
1221     assert(Rs != Rn && Rs != Rt, "unpredictable instruction");          \
1222     lse_cas(Rs, Rt, Rn, sz, a, r, true);                                \
1223   }
1224   INSN(cas,    false, false)
1225   INSN(casa,   true,  false)
1226   INSN(casl,   false, true)
1227   INSN(casal,  true,  true)
1228 #undef INSN
1229 
1230   // CASP
1231 #define INSN(NAME, a, r)                                                \
1232   void NAME(operand_size sz, Register Rs, Register Rs1,                 \
1233             Register Rt, Register Rt1, Register Rn) {                   \
1234     assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 &&    \
1235            Rs->successor() == Rs1 && Rt->successor() == Rt1 &&          \


< prev index next >