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src/hotspot/cpu/aarch64/assembler_aarch64.hpp

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@@ -627,18 +627,10 @@
 
 public:
 
   enum { instruction_size = 4 };
 
-  //---<  calculate length of instruction  >---
-  // We just use the values set above.
-  // instruction must start at passed address
-  static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
-
-  //---<  longest instructions  >---
-  static unsigned int instr_maxlen() { return instruction_size; }
-
   Address adjust(Register base, int offset, bool preIncrement) {
     if (preIncrement)
       return Address(Pre(base, offset));
     else
       return Address(Post(base, offset));

@@ -1217,12 +1209,12 @@
     if (! not_pair) { // Pair
       assert(sz == word || sz == xword, "invalid size");
       /* The size bit is in bit 30, not 31 */
       sz = (operand_size)(sz == word ? 0b00:0b01);
     }
-    f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
-    zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
+    f(sz, 31, 30), f(0b001000, 29, 24), f(1, 23), f(a, 22), f(1, 21);
+    rf(Rs, 16), f(r, 15), f(0b11111, 14, 10), rf(Rn, 5), rf(Rt, 0);
   }
 
   // CAS
 #define INSN(NAME, a, r)                                                \
   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
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