1 /*
   2  * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "asm/assembler.hpp"
  29 #include "c1/c1_CodeStubs.hpp"
  30 #include "c1/c1_Compilation.hpp"
  31 #include "c1/c1_LIRAssembler.hpp"
  32 #include "c1/c1_MacroAssembler.hpp"
  33 #include "c1/c1_Runtime1.hpp"
  34 #include "c1/c1_ValueStack.hpp"
  35 #include "ci/ciArrayKlass.hpp"
  36 #include "ci/ciInstance.hpp"
  37 #include "code/compiledIC.hpp"
  38 #include "gc/shared/barrierSet.hpp"
  39 #include "gc/shared/cardTableBarrierSet.hpp"
  40 #include "gc/shared/collectedHeap.hpp"
  41 #include "nativeInst_aarch64.hpp"
  42 #include "oops/objArrayKlass.hpp"
  43 #include "runtime/frame.inline.hpp"
  44 #include "runtime/sharedRuntime.hpp"
  45 #include "vmreg_aarch64.inline.hpp"
  46 
  47 
  48 
  49 #ifndef PRODUCT
  50 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  51 #else
  52 #define COMMENT(x)
  53 #endif
  54 
  55 NEEDS_CLEANUP // remove this definitions ?
  56 const Register IC_Klass    = rscratch2;   // where the IC klass is cached
  57 const Register SYNC_header = r0;   // synchronization header
  58 const Register SHIFT_count = r0;   // where count for shift operations must be
  59 
  60 #define __ _masm->
  61 
  62 
  63 static void select_different_registers(Register preserve,
  64                                        Register extra,
  65                                        Register &tmp1,
  66                                        Register &tmp2) {
  67   if (tmp1 == preserve) {
  68     assert_different_registers(tmp1, tmp2, extra);
  69     tmp1 = extra;
  70   } else if (tmp2 == preserve) {
  71     assert_different_registers(tmp1, tmp2, extra);
  72     tmp2 = extra;
  73   }
  74   assert_different_registers(preserve, tmp1, tmp2);
  75 }
  76 
  77 
  78 
  79 static void select_different_registers(Register preserve,
  80                                        Register extra,
  81                                        Register &tmp1,
  82                                        Register &tmp2,
  83                                        Register &tmp3) {
  84   if (tmp1 == preserve) {
  85     assert_different_registers(tmp1, tmp2, tmp3, extra);
  86     tmp1 = extra;
  87   } else if (tmp2 == preserve) {
  88     assert_different_registers(tmp1, tmp2, tmp3, extra);
  89     tmp2 = extra;
  90   } else if (tmp3 == preserve) {
  91     assert_different_registers(tmp1, tmp2, tmp3, extra);
  92     tmp3 = extra;
  93   }
  94   assert_different_registers(preserve, tmp1, tmp2, tmp3);
  95 }
  96 
  97 
  98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
  99 
 100 
 101 LIR_Opr LIR_Assembler::receiverOpr() {
 102   return FrameMap::receiver_opr;
 103 }
 104 
 105 LIR_Opr LIR_Assembler::osrBufferPointer() {
 106   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 107 }
 108 
 109 //--------------fpu register translations-----------------------
 110 
 111 
 112 address LIR_Assembler::float_constant(float f) {
 113   address const_addr = __ float_constant(f);
 114   if (const_addr == NULL) {
 115     bailout("const section overflow");
 116     return __ code()->consts()->start();
 117   } else {
 118     return const_addr;
 119   }
 120 }
 121 
 122 
 123 address LIR_Assembler::double_constant(double d) {
 124   address const_addr = __ double_constant(d);
 125   if (const_addr == NULL) {
 126     bailout("const section overflow");
 127     return __ code()->consts()->start();
 128   } else {
 129     return const_addr;
 130   }
 131 }
 132 
 133 address LIR_Assembler::int_constant(jlong n) {
 134   address const_addr = __ long_constant(n);
 135   if (const_addr == NULL) {
 136     bailout("const section overflow");
 137     return __ code()->consts()->start();
 138   } else {
 139     return const_addr;
 140   }
 141 }
 142 
 143 void LIR_Assembler::set_24bit_FPU() { Unimplemented(); }
 144 
 145 void LIR_Assembler::reset_FPU() { Unimplemented(); }
 146 
 147 void LIR_Assembler::fpop() { Unimplemented(); }
 148 
 149 void LIR_Assembler::fxch(int i) { Unimplemented(); }
 150 
 151 void LIR_Assembler::fld(int i) { Unimplemented(); }
 152 
 153 void LIR_Assembler::ffree(int i) { Unimplemented(); }
 154 
 155 void LIR_Assembler::breakpoint() { Unimplemented(); }
 156 
 157 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
 158 
 159 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
 160 
 161 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
 162 //-------------------------------------------
 163 
 164 static Register as_reg(LIR_Opr op) {
 165   return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
 166 }
 167 
 168 static jlong as_long(LIR_Opr data) {
 169   jlong result;
 170   switch (data->type()) {
 171   case T_INT:
 172     result = (data->as_jint());
 173     break;
 174   case T_LONG:
 175     result = (data->as_jlong());
 176     break;
 177   default:
 178     ShouldNotReachHere();
 179     result = 0;  // unreachable
 180   }
 181   return result;
 182 }
 183 
 184 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 185   Register base = addr->base()->as_pointer_register();
 186   LIR_Opr opr = addr->index();
 187   if (opr->is_cpu_register()) {
 188     Register index;
 189     if (opr->is_single_cpu())
 190       index = opr->as_register();
 191     else
 192       index = opr->as_register_lo();
 193     assert(addr->disp() == 0, "must be");
 194     switch(opr->type()) {
 195       case T_INT:
 196         return Address(base, index, Address::sxtw(addr->scale()));
 197       case T_LONG:
 198         return Address(base, index, Address::lsl(addr->scale()));
 199       default:
 200         ShouldNotReachHere();
 201       }
 202   } else  {
 203     intptr_t addr_offset = intptr_t(addr->disp());
 204     if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
 205       return Address(base, addr_offset, Address::lsl(addr->scale()));
 206     else {
 207       __ mov(tmp, addr_offset);
 208       return Address(base, tmp, Address::lsl(addr->scale()));
 209     }
 210   }
 211   return Address();
 212 }
 213 
 214 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 215   ShouldNotReachHere();
 216   return Address();
 217 }
 218 
 219 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 220   return as_Address(addr, rscratch1);
 221 }
 222 
 223 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 224   return as_Address(addr, rscratch1);  // Ouch
 225   // FIXME: This needs to be much more clever.  See x86.
 226 }
 227 
 228 
 229 void LIR_Assembler::osr_entry() {
 230   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 231   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 232   ValueStack* entry_state = osr_entry->state();
 233   int number_of_locks = entry_state->locks_size();
 234 
 235   // we jump here if osr happens with the interpreter
 236   // state set up to continue at the beginning of the
 237   // loop that triggered osr - in particular, we have
 238   // the following registers setup:
 239   //
 240   // r2: osr buffer
 241   //
 242 
 243   // build frame
 244   ciMethod* m = compilation()->method();
 245   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 246 
 247   // OSR buffer is
 248   //
 249   // locals[nlocals-1..0]
 250   // monitors[0..number_of_locks]
 251   //
 252   // locals is a direct copy of the interpreter frame so in the osr buffer
 253   // so first slot in the local array is the last local from the interpreter
 254   // and last slot is local[0] (receiver) from the interpreter
 255   //
 256   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 257   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 258   // in the interpreter frame (the method lock if a sync method)
 259 
 260   // Initialize monitors in the compiled activation.
 261   //   r2: pointer to osr buffer
 262   //
 263   // All other registers are dead at this point and the locals will be
 264   // copied into place by code emitted in the IR.
 265 
 266   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 267   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 268     int monitor_offset = BytesPerWord * method()->max_locals() +
 269       (2 * BytesPerWord) * (number_of_locks - 1);
 270     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 271     // the OSR buffer using 2 word entries: first the lock and then
 272     // the oop.
 273     for (int i = 0; i < number_of_locks; i++) {
 274       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 275 #ifdef ASSERT
 276       // verify the interpreter's monitor has a non-null object
 277       {
 278         Label L;
 279         __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 280         __ cbnz(rscratch1, L);
 281         __ stop("locked object is NULL");
 282         __ bind(L);
 283       }
 284 #endif
 285       __ ldr(r19, Address(OSR_buf, slot_offset + 0));
 286       __ str(r19, frame_map()->address_for_monitor_lock(i));
 287       __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 288       __ str(r19, frame_map()->address_for_monitor_object(i));
 289     }
 290   }
 291 }
 292 
 293 
 294 // inline cache check; done before the frame is built.
 295 int LIR_Assembler::check_icache() {
 296   Register receiver = FrameMap::receiver_opr->as_register();
 297   Register ic_klass = IC_Klass;
 298   int start_offset = __ offset();
 299   __ inline_cache_check(receiver, ic_klass);
 300 
 301   // if icache check fails, then jump to runtime routine
 302   // Note: RECEIVER must still contain the receiver!
 303   Label dont;
 304   __ br(Assembler::EQ, dont);
 305   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 306 
 307   // We align the verified entry point unless the method body
 308   // (including its inline cache check) will fit in a single 64-byte
 309   // icache line.
 310   if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
 311     // force alignment after the cache check.
 312     __ align(CodeEntryAlignment);
 313   }
 314 
 315   __ bind(dont);
 316   return start_offset;
 317 }
 318 
 319 
 320 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 321   if (o == NULL) {
 322     __ mov(reg, zr);
 323   } else {
 324     __ movoop(reg, o, /*immediate*/true);
 325   }
 326 }
 327 
 328 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
 329   address target = NULL;
 330   relocInfo::relocType reloc_type = relocInfo::none;
 331 
 332   switch (patching_id(info)) {
 333   case PatchingStub::access_field_id:
 334     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 335     reloc_type = relocInfo::section_word_type;
 336     break;
 337   case PatchingStub::load_klass_id:
 338     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 339     reloc_type = relocInfo::metadata_type;
 340     break;
 341   case PatchingStub::load_mirror_id:
 342     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 343     reloc_type = relocInfo::oop_type;
 344     break;
 345   case PatchingStub::load_appendix_id:
 346     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 347     reloc_type = relocInfo::oop_type;
 348     break;
 349   default: ShouldNotReachHere();
 350   }
 351 
 352   __ far_call(RuntimeAddress(target));
 353   add_call_info_here(info);
 354 }
 355 
 356 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 357   deoptimize_trap(info);
 358 }
 359 
 360 
 361 // This specifies the rsp decrement needed to build the frame
 362 int LIR_Assembler::initial_frame_size_in_bytes() const {
 363   // if rounding, must let FrameMap know!
 364 
 365   // The frame_map records size in slots (32bit word)
 366 
 367   // subtract two words to account for return address and link
 368   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 369 }
 370 
 371 
 372 int LIR_Assembler::emit_exception_handler() {
 373   // if the last instruction is a call (typically to do a throw which
 374   // is coming at the end after block reordering) the return address
 375   // must still point into the code area in order to avoid assertion
 376   // failures when searching for the corresponding bci => add a nop
 377   // (was bug 5/14/1999 - gri)
 378   __ nop();
 379 
 380   // generate code for exception handler
 381   address handler_base = __ start_a_stub(exception_handler_size());
 382   if (handler_base == NULL) {
 383     // not enough space left for the handler
 384     bailout("exception handler overflow");
 385     return -1;
 386   }
 387 
 388   int offset = code_offset();
 389 
 390   // the exception oop and pc are in r0, and r3
 391   // no other registers need to be preserved, so invalidate them
 392   __ invalidate_registers(false, true, true, false, true, true);
 393 
 394   // check that there is really an exception
 395   __ verify_not_null_oop(r0);
 396 
 397   // search an exception handler (r0: exception oop, r3: throwing pc)
 398   __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));  __ should_not_reach_here();
 399   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 400   __ end_a_stub();
 401 
 402   return offset;
 403 }
 404 
 405 
 406 // Emit the code to remove the frame from the stack in the exception
 407 // unwind path.
 408 int LIR_Assembler::emit_unwind_handler() {
 409 #ifndef PRODUCT
 410   if (CommentedAssembly) {
 411     _masm->block_comment("Unwind handler");
 412   }
 413 #endif
 414 
 415   int offset = code_offset();
 416 
 417   // Fetch the exception from TLS and clear out exception related thread state
 418   __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
 419   __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
 420   __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
 421 
 422   __ bind(_unwind_handler_entry);
 423   __ verify_not_null_oop(r0);
 424   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 425     __ mov(r19, r0);  // Preserve the exception
 426   }
 427 
 428   // Preform needed unlocking
 429   MonitorExitStub* stub = NULL;
 430   if (method()->is_synchronized()) {
 431     monitor_address(0, FrameMap::r0_opr);
 432     stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
 433     __ unlock_object(r5, r4, r0, *stub->entry());
 434     __ bind(*stub->continuation());
 435   }
 436 
 437   if (compilation()->env()->dtrace_method_probes()) {
 438     __ call_Unimplemented();
 439 #if 0
 440     __ movptr(Address(rsp, 0), rax);
 441     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
 442     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 443 #endif
 444   }
 445 
 446   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 447     __ mov(r0, r19);  // Restore the exception
 448   }
 449 
 450   // remove the activation and dispatch to the unwind handler
 451   __ block_comment("remove_frame and dispatch to the unwind handler");
 452   __ remove_frame(initial_frame_size_in_bytes());
 453   __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 454 
 455   // Emit the slow path assembly
 456   if (stub != NULL) {
 457     stub->emit_code(this);
 458   }
 459 
 460   return offset;
 461 }
 462 
 463 
 464 int LIR_Assembler::emit_deopt_handler() {
 465   // if the last instruction is a call (typically to do a throw which
 466   // is coming at the end after block reordering) the return address
 467   // must still point into the code area in order to avoid assertion
 468   // failures when searching for the corresponding bci => add a nop
 469   // (was bug 5/14/1999 - gri)
 470   __ nop();
 471 
 472   // generate code for exception handler
 473   address handler_base = __ start_a_stub(deopt_handler_size());
 474   if (handler_base == NULL) {
 475     // not enough space left for the handler
 476     bailout("deopt handler overflow");
 477     return -1;
 478   }
 479 
 480   int offset = code_offset();
 481 
 482   __ adr(lr, pc());
 483   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 484   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 485   __ end_a_stub();
 486 
 487   return offset;
 488 }
 489 
 490 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
 491   _masm->code_section()->relocate(adr, relocInfo::poll_type);
 492   int pc_offset = code_offset();
 493   flush_debug_info(pc_offset);
 494   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 495   if (info->exception_handlers() != NULL) {
 496     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
 497   }
 498 }
 499 
 500 void LIR_Assembler::return_op(LIR_Opr result) {
 501   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
 502 
 503   // Pop the stack before the safepoint code
 504   __ remove_frame(initial_frame_size_in_bytes());
 505 
 506   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 507     __ reserved_stack_check();
 508   }
 509 
 510   address polling_page(os::get_polling_page());
 511   __ read_polling_page(rscratch1, polling_page, relocInfo::poll_return_type);
 512   __ ret(lr);
 513 }
 514 
 515 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 516   address polling_page(os::get_polling_page());
 517   guarantee(info != NULL, "Shouldn't be NULL");
 518   assert(os::is_poll_address(polling_page), "should be");
 519   __ get_polling_page(rscratch1, polling_page, relocInfo::poll_type);
 520   add_debug_info_for_branch(info);  // This isn't just debug info:
 521                                     // it's the oop map
 522   __ read_polling_page(rscratch1, relocInfo::poll_type);
 523   return __ offset();
 524 }
 525 
 526 
 527 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 528   if (from_reg == r31_sp)
 529     from_reg = sp;
 530   if (to_reg == r31_sp)
 531     to_reg = sp;
 532   __ mov(to_reg, from_reg);
 533 }
 534 
 535 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
 536 
 537 
 538 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 539   assert(src->is_constant(), "should not call otherwise");
 540   assert(dest->is_register(), "should not call otherwise");
 541   LIR_Const* c = src->as_constant_ptr();
 542 
 543   switch (c->type()) {
 544     case T_INT: {
 545       assert(patch_code == lir_patch_none, "no patching handled here");
 546       __ movw(dest->as_register(), c->as_jint());
 547       break;
 548     }
 549 
 550     case T_ADDRESS: {
 551       assert(patch_code == lir_patch_none, "no patching handled here");
 552       __ mov(dest->as_register(), c->as_jint());
 553       break;
 554     }
 555 
 556     case T_LONG: {
 557       assert(patch_code == lir_patch_none, "no patching handled here");
 558       __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
 559       break;
 560     }
 561 
 562     case T_OBJECT: {
 563         if (patch_code == lir_patch_none) {
 564           jobject2reg(c->as_jobject(), dest->as_register());
 565         } else {
 566           jobject2reg_with_patching(dest->as_register(), info);
 567         }
 568       break;
 569     }
 570 
 571     case T_METADATA: {
 572       if (patch_code != lir_patch_none) {
 573         klass2reg_with_patching(dest->as_register(), info);
 574       } else {
 575         __ mov_metadata(dest->as_register(), c->as_metadata());
 576       }
 577       break;
 578     }
 579 
 580     case T_FLOAT: {
 581       if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
 582         __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
 583       } else {
 584         __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
 585         __ ldrs(dest->as_float_reg(), Address(rscratch1));
 586       }
 587       break;
 588     }
 589 
 590     case T_DOUBLE: {
 591       if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
 592         __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
 593       } else {
 594         __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
 595         __ ldrd(dest->as_double_reg(), Address(rscratch1));
 596       }
 597       break;
 598     }
 599 
 600     default:
 601       ShouldNotReachHere();
 602   }
 603 }
 604 
 605 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 606   LIR_Const* c = src->as_constant_ptr();
 607   switch (c->type()) {
 608   case T_OBJECT:
 609     {
 610       if (! c->as_jobject())
 611         __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 612       else {
 613         const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 614         reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 615       }
 616     }
 617     break;
 618   case T_ADDRESS:
 619     {
 620       const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 621       reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 622     }
 623   case T_INT:
 624   case T_FLOAT:
 625     {
 626       Register reg = zr;
 627       if (c->as_jint_bits() == 0)
 628         __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 629       else {
 630         __ movw(rscratch1, c->as_jint_bits());
 631         __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
 632       }
 633     }
 634     break;
 635   case T_LONG:
 636   case T_DOUBLE:
 637     {
 638       Register reg = zr;
 639       if (c->as_jlong_bits() == 0)
 640         __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
 641                                                  lo_word_offset_in_bytes));
 642       else {
 643         __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
 644         __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
 645                                                         lo_word_offset_in_bytes));
 646       }
 647     }
 648     break;
 649   default:
 650     ShouldNotReachHere();
 651   }
 652 }
 653 
 654 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 655   assert(src->is_constant(), "should not call otherwise");
 656   LIR_Const* c = src->as_constant_ptr();
 657   LIR_Address* to_addr = dest->as_address_ptr();
 658 
 659   void (Assembler::* insn)(Register Rt, const Address &adr);
 660 
 661   switch (type) {
 662   case T_ADDRESS:
 663     assert(c->as_jint() == 0, "should be");
 664     insn = &Assembler::str;
 665     break;
 666   case T_LONG:
 667     assert(c->as_jlong() == 0, "should be");
 668     insn = &Assembler::str;
 669     break;
 670   case T_INT:
 671     assert(c->as_jint() == 0, "should be");
 672     insn = &Assembler::strw;
 673     break;
 674   case T_OBJECT:
 675   case T_ARRAY:
 676     assert(c->as_jobject() == 0, "should be");
 677     if (UseCompressedOops && !wide) {
 678       insn = &Assembler::strw;
 679     } else {
 680       insn = &Assembler::str;
 681     }
 682     break;
 683   case T_CHAR:
 684   case T_SHORT:
 685     assert(c->as_jint() == 0, "should be");
 686     insn = &Assembler::strh;
 687     break;
 688   case T_BOOLEAN:
 689   case T_BYTE:
 690     assert(c->as_jint() == 0, "should be");
 691     insn = &Assembler::strb;
 692     break;
 693   default:
 694     ShouldNotReachHere();
 695     insn = &Assembler::str;  // unreachable
 696   }
 697 
 698   if (info) add_debug_info_for_null_check_here(info);
 699   (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
 700 }
 701 
 702 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 703   assert(src->is_register(), "should not call otherwise");
 704   assert(dest->is_register(), "should not call otherwise");
 705 
 706   // move between cpu-registers
 707   if (dest->is_single_cpu()) {
 708     if (src->type() == T_LONG) {
 709       // Can do LONG -> OBJECT
 710       move_regs(src->as_register_lo(), dest->as_register());
 711       return;
 712     }
 713     assert(src->is_single_cpu(), "must match");
 714     if (src->type() == T_OBJECT) {
 715       __ verify_oop(src->as_register());
 716     }
 717     move_regs(src->as_register(), dest->as_register());
 718 
 719   } else if (dest->is_double_cpu()) {
 720     if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
 721       // Surprising to me but we can see move of a long to t_object
 722       __ verify_oop(src->as_register());
 723       move_regs(src->as_register(), dest->as_register_lo());
 724       return;
 725     }
 726     assert(src->is_double_cpu(), "must match");
 727     Register f_lo = src->as_register_lo();
 728     Register f_hi = src->as_register_hi();
 729     Register t_lo = dest->as_register_lo();
 730     Register t_hi = dest->as_register_hi();
 731     assert(f_hi == f_lo, "must be same");
 732     assert(t_hi == t_lo, "must be same");
 733     move_regs(f_lo, t_lo);
 734 
 735   } else if (dest->is_single_fpu()) {
 736     __ fmovs(dest->as_float_reg(), src->as_float_reg());
 737 
 738   } else if (dest->is_double_fpu()) {
 739     __ fmovd(dest->as_double_reg(), src->as_double_reg());
 740 
 741   } else {
 742     ShouldNotReachHere();
 743   }
 744 }
 745 
 746 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 747   if (src->is_single_cpu()) {
 748     if (type == T_ARRAY || type == T_OBJECT) {
 749       __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
 750       __ verify_oop(src->as_register());
 751     } else if (type == T_METADATA || type == T_DOUBLE) {
 752       __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
 753     } else {
 754       __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
 755     }
 756 
 757   } else if (src->is_double_cpu()) {
 758     Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 759     __ str(src->as_register_lo(), dest_addr_LO);
 760 
 761   } else if (src->is_single_fpu()) {
 762     Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 763     __ strs(src->as_float_reg(), dest_addr);
 764 
 765   } else if (src->is_double_fpu()) {
 766     Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 767     __ strd(src->as_double_reg(), dest_addr);
 768 
 769   } else {
 770     ShouldNotReachHere();
 771   }
 772 
 773 }
 774 
 775 
 776 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
 777   LIR_Address* to_addr = dest->as_address_ptr();
 778   PatchingStub* patch = NULL;
 779   Register compressed_src = rscratch1;
 780 
 781   if (patch_code != lir_patch_none) {
 782     deoptimize_trap(info);
 783     return;
 784   }
 785 
 786   if (type == T_ARRAY || type == T_OBJECT) {
 787     __ verify_oop(src->as_register());
 788 
 789     if (UseCompressedOops && !wide) {
 790       __ encode_heap_oop(compressed_src, src->as_register());
 791     } else {
 792       compressed_src = src->as_register();
 793     }
 794   }
 795 
 796   int null_check_here = code_offset();
 797   switch (type) {
 798     case T_FLOAT: {
 799       __ strs(src->as_float_reg(), as_Address(to_addr));
 800       break;
 801     }
 802 
 803     case T_DOUBLE: {
 804       __ strd(src->as_double_reg(), as_Address(to_addr));
 805       break;
 806     }
 807 
 808     case T_ARRAY:   // fall through
 809     case T_OBJECT:  // fall through
 810       if (UseCompressedOops && !wide) {
 811         __ strw(compressed_src, as_Address(to_addr, rscratch2));
 812       } else {
 813          __ str(compressed_src, as_Address(to_addr));
 814       }
 815       break;
 816     case T_METADATA:
 817       // We get here to store a method pointer to the stack to pass to
 818       // a dtrace runtime call. This can't work on 64 bit with
 819       // compressed klass ptrs: T_METADATA can be a compressed klass
 820       // ptr or a 64 bit method pointer.
 821       ShouldNotReachHere();
 822       __ str(src->as_register(), as_Address(to_addr));
 823       break;
 824     case T_ADDRESS:
 825       __ str(src->as_register(), as_Address(to_addr));
 826       break;
 827     case T_INT:
 828       __ strw(src->as_register(), as_Address(to_addr));
 829       break;
 830 
 831     case T_LONG: {
 832       __ str(src->as_register_lo(), as_Address_lo(to_addr));
 833       break;
 834     }
 835 
 836     case T_BYTE:    // fall through
 837     case T_BOOLEAN: {
 838       __ strb(src->as_register(), as_Address(to_addr));
 839       break;
 840     }
 841 
 842     case T_CHAR:    // fall through
 843     case T_SHORT:
 844       __ strh(src->as_register(), as_Address(to_addr));
 845       break;
 846 
 847     default:
 848       ShouldNotReachHere();
 849   }
 850   if (info != NULL) {
 851     add_debug_info_for_null_check(null_check_here, info);
 852   }
 853 }
 854 
 855 
 856 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 857   assert(src->is_stack(), "should not call otherwise");
 858   assert(dest->is_register(), "should not call otherwise");
 859 
 860   if (dest->is_single_cpu()) {
 861     if (type == T_ARRAY || type == T_OBJECT) {
 862       __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
 863       __ verify_oop(dest->as_register());
 864     } else if (type == T_METADATA) {
 865       __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
 866     } else {
 867       __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
 868     }
 869 
 870   } else if (dest->is_double_cpu()) {
 871     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
 872     __ ldr(dest->as_register_lo(), src_addr_LO);
 873 
 874   } else if (dest->is_single_fpu()) {
 875     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
 876     __ ldrs(dest->as_float_reg(), src_addr);
 877 
 878   } else if (dest->is_double_fpu()) {
 879     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
 880     __ ldrd(dest->as_double_reg(), src_addr);
 881 
 882   } else {
 883     ShouldNotReachHere();
 884   }
 885 }
 886 
 887 
 888 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 889   address target = NULL;
 890   relocInfo::relocType reloc_type = relocInfo::none;
 891 
 892   switch (patching_id(info)) {
 893   case PatchingStub::access_field_id:
 894     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 895     reloc_type = relocInfo::section_word_type;
 896     break;
 897   case PatchingStub::load_klass_id:
 898     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 899     reloc_type = relocInfo::metadata_type;
 900     break;
 901   case PatchingStub::load_mirror_id:
 902     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 903     reloc_type = relocInfo::oop_type;
 904     break;
 905   case PatchingStub::load_appendix_id:
 906     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 907     reloc_type = relocInfo::oop_type;
 908     break;
 909   default: ShouldNotReachHere();
 910   }
 911 
 912   __ far_call(RuntimeAddress(target));
 913   add_call_info_here(info);
 914 }
 915 
 916 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 917 
 918   LIR_Opr temp;
 919   if (type == T_LONG || type == T_DOUBLE)
 920     temp = FrameMap::rscratch1_long_opr;
 921   else
 922     temp = FrameMap::rscratch1_opr;
 923 
 924   stack2reg(src, temp, src->type());
 925   reg2stack(temp, dest, dest->type(), false);
 926 }
 927 
 928 
 929 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
 930   LIR_Address* addr = src->as_address_ptr();
 931   LIR_Address* from_addr = src->as_address_ptr();
 932 
 933   if (addr->base()->type() == T_OBJECT) {
 934     __ verify_oop(addr->base()->as_pointer_register());
 935   }
 936 
 937   if (patch_code != lir_patch_none) {
 938     deoptimize_trap(info);
 939     return;
 940   }
 941 
 942   if (info != NULL) {
 943     add_debug_info_for_null_check_here(info);
 944   }
 945   int null_check_here = code_offset();
 946   switch (type) {
 947     case T_FLOAT: {
 948       __ ldrs(dest->as_float_reg(), as_Address(from_addr));
 949       break;
 950     }
 951 
 952     case T_DOUBLE: {
 953       __ ldrd(dest->as_double_reg(), as_Address(from_addr));
 954       break;
 955     }
 956 
 957     case T_ARRAY:   // fall through
 958     case T_OBJECT:  // fall through
 959       if (UseCompressedOops && !wide) {
 960         __ ldrw(dest->as_register(), as_Address(from_addr));
 961       } else {
 962          __ ldr(dest->as_register(), as_Address(from_addr));
 963       }
 964       break;
 965     case T_METADATA:
 966       // We get here to store a method pointer to the stack to pass to
 967       // a dtrace runtime call. This can't work on 64 bit with
 968       // compressed klass ptrs: T_METADATA can be a compressed klass
 969       // ptr or a 64 bit method pointer.
 970       ShouldNotReachHere();
 971       __ ldr(dest->as_register(), as_Address(from_addr));
 972       break;
 973     case T_ADDRESS:
 974       // FIXME: OMG this is a horrible kludge.  Any offset from an
 975       // address that matches klass_offset_in_bytes() will be loaded
 976       // as a word, not a long.
 977       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
 978         __ ldrw(dest->as_register(), as_Address(from_addr));
 979       } else {
 980         __ ldr(dest->as_register(), as_Address(from_addr));
 981       }
 982       break;
 983     case T_INT:
 984       __ ldrw(dest->as_register(), as_Address(from_addr));
 985       break;
 986 
 987     case T_LONG: {
 988       __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
 989       break;
 990     }
 991 
 992     case T_BYTE:
 993       __ ldrsb(dest->as_register(), as_Address(from_addr));
 994       break;
 995     case T_BOOLEAN: {
 996       __ ldrb(dest->as_register(), as_Address(from_addr));
 997       break;
 998     }
 999 
1000     case T_CHAR:
1001       __ ldrh(dest->as_register(), as_Address(from_addr));
1002       break;
1003     case T_SHORT:
1004       __ ldrsh(dest->as_register(), as_Address(from_addr));
1005       break;
1006 
1007     default:
1008       ShouldNotReachHere();
1009   }
1010 
1011   if (type == T_ARRAY || type == T_OBJECT) {
1012     if (UseCompressedOops && !wide) {
1013       __ decode_heap_oop(dest->as_register());
1014     }
1015     __ verify_oop(dest->as_register());
1016   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1017     if (UseCompressedClassPointers) {
1018       __ decode_klass_not_null(dest->as_register());
1019     }
1020   }
1021 }
1022 
1023 
1024 int LIR_Assembler::array_element_size(BasicType type) const {
1025   int elem_size = type2aelembytes(type);
1026   return exact_log2(elem_size);
1027 }
1028 
1029 
1030 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1031   switch (op->code()) {
1032   case lir_idiv:
1033   case lir_irem:
1034     arithmetic_idiv(op->code(),
1035                     op->in_opr1(),
1036                     op->in_opr2(),
1037                     op->in_opr3(),
1038                     op->result_opr(),
1039                     op->info());
1040     break;
1041   case lir_fmad:
1042     __ fmaddd(op->result_opr()->as_double_reg(),
1043               op->in_opr1()->as_double_reg(),
1044               op->in_opr2()->as_double_reg(),
1045               op->in_opr3()->as_double_reg());
1046     break;
1047   case lir_fmaf:
1048     __ fmadds(op->result_opr()->as_float_reg(),
1049               op->in_opr1()->as_float_reg(),
1050               op->in_opr2()->as_float_reg(),
1051               op->in_opr3()->as_float_reg());
1052     break;
1053   default:      ShouldNotReachHere(); break;
1054   }
1055 }
1056 
1057 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1058 #ifdef ASSERT
1059   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1060   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1061   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1062 #endif
1063 
1064   if (op->cond() == lir_cond_always) {
1065     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1066     __ b(*(op->label()));
1067   } else {
1068     Assembler::Condition acond;
1069     if (op->code() == lir_cond_float_branch) {
1070       bool is_unordered = (op->ublock() == op->block());
1071       // Assembler::EQ does not permit unordered branches, so we add
1072       // another branch here.  Likewise, Assembler::NE does not permit
1073       // ordered branches.
1074       if (is_unordered && op->cond() == lir_cond_equal
1075           || !is_unordered && op->cond() == lir_cond_notEqual)
1076         __ br(Assembler::VS, *(op->ublock()->label()));
1077       switch(op->cond()) {
1078       case lir_cond_equal:        acond = Assembler::EQ; break;
1079       case lir_cond_notEqual:     acond = Assembler::NE; break;
1080       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1081       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1082       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1083       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1084       default:                    ShouldNotReachHere();
1085         acond = Assembler::EQ;  // unreachable
1086       }
1087     } else {
1088       switch (op->cond()) {
1089         case lir_cond_equal:        acond = Assembler::EQ; break;
1090         case lir_cond_notEqual:     acond = Assembler::NE; break;
1091         case lir_cond_less:         acond = Assembler::LT; break;
1092         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1093         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1094         case lir_cond_greater:      acond = Assembler::GT; break;
1095         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1096         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1097         default:                    ShouldNotReachHere();
1098           acond = Assembler::EQ;  // unreachable
1099       }
1100     }
1101     __ br(acond,*(op->label()));
1102   }
1103 }
1104 
1105 
1106 
1107 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1108   LIR_Opr src  = op->in_opr();
1109   LIR_Opr dest = op->result_opr();
1110 
1111   switch (op->bytecode()) {
1112     case Bytecodes::_i2f:
1113       {
1114         __ scvtfws(dest->as_float_reg(), src->as_register());
1115         break;
1116       }
1117     case Bytecodes::_i2d:
1118       {
1119         __ scvtfwd(dest->as_double_reg(), src->as_register());
1120         break;
1121       }
1122     case Bytecodes::_l2d:
1123       {
1124         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1125         break;
1126       }
1127     case Bytecodes::_l2f:
1128       {
1129         __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1130         break;
1131       }
1132     case Bytecodes::_f2d:
1133       {
1134         __ fcvts(dest->as_double_reg(), src->as_float_reg());
1135         break;
1136       }
1137     case Bytecodes::_d2f:
1138       {
1139         __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1140         break;
1141       }
1142     case Bytecodes::_i2c:
1143       {
1144         __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1145         break;
1146       }
1147     case Bytecodes::_i2l:
1148       {
1149         __ sxtw(dest->as_register_lo(), src->as_register());
1150         break;
1151       }
1152     case Bytecodes::_i2s:
1153       {
1154         __ sxth(dest->as_register(), src->as_register());
1155         break;
1156       }
1157     case Bytecodes::_i2b:
1158       {
1159         __ sxtb(dest->as_register(), src->as_register());
1160         break;
1161       }
1162     case Bytecodes::_l2i:
1163       {
1164         _masm->block_comment("FIXME: This could be a no-op");
1165         __ uxtw(dest->as_register(), src->as_register_lo());
1166         break;
1167       }
1168     case Bytecodes::_d2l:
1169       {
1170         __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1171         break;
1172       }
1173     case Bytecodes::_f2i:
1174       {
1175         __ fcvtzsw(dest->as_register(), src->as_float_reg());
1176         break;
1177       }
1178     case Bytecodes::_f2l:
1179       {
1180         __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1181         break;
1182       }
1183     case Bytecodes::_d2i:
1184       {
1185         __ fcvtzdw(dest->as_register(), src->as_double_reg());
1186         break;
1187       }
1188     default: ShouldNotReachHere();
1189   }
1190 }
1191 
1192 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1193   if (op->init_check()) {
1194     __ ldrb(rscratch1, Address(op->klass()->as_register(),
1195                                InstanceKlass::init_state_offset()));
1196     __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1197     add_debug_info_for_null_check_here(op->stub()->info());
1198     __ br(Assembler::NE, *op->stub()->entry());
1199   }
1200   __ allocate_object(op->obj()->as_register(),
1201                      op->tmp1()->as_register(),
1202                      op->tmp2()->as_register(),
1203                      op->header_size(),
1204                      op->object_size(),
1205                      op->klass()->as_register(),
1206                      *op->stub()->entry());
1207   __ bind(*op->stub()->continuation());
1208 }
1209 
1210 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1211   Register len =  op->len()->as_register();
1212   __ uxtw(len, len);
1213 
1214   if (UseSlowPath ||
1215       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1216       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1217     __ b(*op->stub()->entry());
1218   } else {
1219     Register tmp1 = op->tmp1()->as_register();
1220     Register tmp2 = op->tmp2()->as_register();
1221     Register tmp3 = op->tmp3()->as_register();
1222     if (len == tmp1) {
1223       tmp1 = tmp3;
1224     } else if (len == tmp2) {
1225       tmp2 = tmp3;
1226     } else if (len == tmp3) {
1227       // everything is ok
1228     } else {
1229       __ mov(tmp3, len);
1230     }
1231     __ allocate_array(op->obj()->as_register(),
1232                       len,
1233                       tmp1,
1234                       tmp2,
1235                       arrayOopDesc::header_size(op->type()),
1236                       array_element_size(op->type()),
1237                       op->klass()->as_register(),
1238                       *op->stub()->entry());
1239   }
1240   __ bind(*op->stub()->continuation());
1241 }
1242 
1243 void LIR_Assembler::type_profile_helper(Register mdo,
1244                                         ciMethodData *md, ciProfileData *data,
1245                                         Register recv, Label* update_done) {
1246   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1247     Label next_test;
1248     // See if the receiver is receiver[n].
1249     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1250     __ ldr(rscratch1, Address(rscratch2));
1251     __ cmp(recv, rscratch1);
1252     __ br(Assembler::NE, next_test);
1253     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1254     __ addptr(data_addr, DataLayout::counter_increment);
1255     __ b(*update_done);
1256     __ bind(next_test);
1257   }
1258 
1259   // Didn't find receiver; find next empty slot and fill it in
1260   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1261     Label next_test;
1262     __ lea(rscratch2,
1263            Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1264     Address recv_addr(rscratch2);
1265     __ ldr(rscratch1, recv_addr);
1266     __ cbnz(rscratch1, next_test);
1267     __ str(recv, recv_addr);
1268     __ mov(rscratch1, DataLayout::counter_increment);
1269     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1270     __ str(rscratch1, Address(rscratch2));
1271     __ b(*update_done);
1272     __ bind(next_test);
1273   }
1274 }
1275 
1276 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1277   // we always need a stub for the failure case.
1278   CodeStub* stub = op->stub();
1279   Register obj = op->object()->as_register();
1280   Register k_RInfo = op->tmp1()->as_register();
1281   Register klass_RInfo = op->tmp2()->as_register();
1282   Register dst = op->result_opr()->as_register();
1283   ciKlass* k = op->klass();
1284   Register Rtmp1 = noreg;
1285 
1286   // check if it needs to be profiled
1287   ciMethodData* md;
1288   ciProfileData* data;
1289 
1290   const bool should_profile = op->should_profile();
1291 
1292   if (should_profile) {
1293     ciMethod* method = op->profiled_method();
1294     assert(method != NULL, "Should have method");
1295     int bci = op->profiled_bci();
1296     md = method->method_data_or_null();
1297     assert(md != NULL, "Sanity");
1298     data = md->bci_to_data(bci);
1299     assert(data != NULL,                "need data for type check");
1300     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1301   }
1302   Label profile_cast_success, profile_cast_failure;
1303   Label *success_target = should_profile ? &profile_cast_success : success;
1304   Label *failure_target = should_profile ? &profile_cast_failure : failure;
1305 
1306   if (obj == k_RInfo) {
1307     k_RInfo = dst;
1308   } else if (obj == klass_RInfo) {
1309     klass_RInfo = dst;
1310   }
1311   if (k->is_loaded() && !UseCompressedClassPointers) {
1312     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1313   } else {
1314     Rtmp1 = op->tmp3()->as_register();
1315     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1316   }
1317 
1318   assert_different_registers(obj, k_RInfo, klass_RInfo);
1319 
1320     if (should_profile) {
1321       Label not_null;
1322       __ cbnz(obj, not_null);
1323       // Object is null; update MDO and exit
1324       Register mdo  = klass_RInfo;
1325       __ mov_metadata(mdo, md->constant_encoding());
1326       Address data_addr
1327         = __ form_address(rscratch2, mdo,
1328                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1329                           0);
1330       __ ldrb(rscratch1, data_addr);
1331       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1332       __ strb(rscratch1, data_addr);
1333       __ b(*obj_is_null);
1334       __ bind(not_null);
1335     } else {
1336       __ cbz(obj, *obj_is_null);
1337     }
1338 
1339   if (!k->is_loaded()) {
1340     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1341   } else {
1342     __ mov_metadata(k_RInfo, k->constant_encoding());
1343   }
1344   __ verify_oop(obj);
1345 
1346   if (op->fast_check()) {
1347     // get object class
1348     // not a safepoint as obj null check happens earlier
1349     __ load_klass(rscratch1, obj);
1350     __ cmp( rscratch1, k_RInfo);
1351 
1352     __ br(Assembler::NE, *failure_target);
1353     // successful cast, fall through to profile or jump
1354   } else {
1355     // get object class
1356     // not a safepoint as obj null check happens earlier
1357     __ load_klass(klass_RInfo, obj);
1358     if (k->is_loaded()) {
1359       // See if we get an immediate positive hit
1360       __ ldr(rscratch1, Address(klass_RInfo, long(k->super_check_offset())));
1361       __ cmp(k_RInfo, rscratch1);
1362       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1363         __ br(Assembler::NE, *failure_target);
1364         // successful cast, fall through to profile or jump
1365       } else {
1366         // See if we get an immediate positive hit
1367         __ br(Assembler::EQ, *success_target);
1368         // check for self
1369         __ cmp(klass_RInfo, k_RInfo);
1370         __ br(Assembler::EQ, *success_target);
1371 
1372         __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1373         __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1374         __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1375         // result is a boolean
1376         __ cbzw(klass_RInfo, *failure_target);
1377         // successful cast, fall through to profile or jump
1378       }
1379     } else {
1380       // perform the fast part of the checking logic
1381       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1382       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1383       __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1384       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1385       __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1386       // result is a boolean
1387       __ cbz(k_RInfo, *failure_target);
1388       // successful cast, fall through to profile or jump
1389     }
1390   }
1391   if (should_profile) {
1392     Register mdo  = klass_RInfo, recv = k_RInfo;
1393     __ bind(profile_cast_success);
1394     __ mov_metadata(mdo, md->constant_encoding());
1395     __ load_klass(recv, obj);
1396     Label update_done;
1397     type_profile_helper(mdo, md, data, recv, success);
1398     __ b(*success);
1399 
1400     __ bind(profile_cast_failure);
1401     __ mov_metadata(mdo, md->constant_encoding());
1402     Address counter_addr
1403       = __ form_address(rscratch2, mdo,
1404                         md->byte_offset_of_slot(data, CounterData::count_offset()),
1405                         0);
1406     __ ldr(rscratch1, counter_addr);
1407     __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1408     __ str(rscratch1, counter_addr);
1409     __ b(*failure);
1410   }
1411   __ b(*success);
1412 }
1413 
1414 
1415 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1416   const bool should_profile = op->should_profile();
1417 
1418   LIR_Code code = op->code();
1419   if (code == lir_store_check) {
1420     Register value = op->object()->as_register();
1421     Register array = op->array()->as_register();
1422     Register k_RInfo = op->tmp1()->as_register();
1423     Register klass_RInfo = op->tmp2()->as_register();
1424     Register Rtmp1 = op->tmp3()->as_register();
1425 
1426     CodeStub* stub = op->stub();
1427 
1428     // check if it needs to be profiled
1429     ciMethodData* md;
1430     ciProfileData* data;
1431 
1432     if (should_profile) {
1433       ciMethod* method = op->profiled_method();
1434       assert(method != NULL, "Should have method");
1435       int bci = op->profiled_bci();
1436       md = method->method_data_or_null();
1437       assert(md != NULL, "Sanity");
1438       data = md->bci_to_data(bci);
1439       assert(data != NULL,                "need data for type check");
1440       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1441     }
1442     Label profile_cast_success, profile_cast_failure, done;
1443     Label *success_target = should_profile ? &profile_cast_success : &done;
1444     Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1445 
1446     if (should_profile) {
1447       Label not_null;
1448       __ cbnz(value, not_null);
1449       // Object is null; update MDO and exit
1450       Register mdo  = klass_RInfo;
1451       __ mov_metadata(mdo, md->constant_encoding());
1452       Address data_addr
1453         = __ form_address(rscratch2, mdo,
1454                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1455                           0);
1456       __ ldrb(rscratch1, data_addr);
1457       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1458       __ strb(rscratch1, data_addr);
1459       __ b(done);
1460       __ bind(not_null);
1461     } else {
1462       __ cbz(value, done);
1463     }
1464 
1465     add_debug_info_for_null_check_here(op->info_for_exception());
1466     __ load_klass(k_RInfo, array);
1467     __ load_klass(klass_RInfo, value);
1468 
1469     // get instance klass (it's already uncompressed)
1470     __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1471     // perform the fast part of the checking logic
1472     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1473     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1474     __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1475     __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1476     __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1477     // result is a boolean
1478     __ cbzw(k_RInfo, *failure_target);
1479     // fall through to the success case
1480 
1481     if (should_profile) {
1482       Register mdo  = klass_RInfo, recv = k_RInfo;
1483       __ bind(profile_cast_success);
1484       __ mov_metadata(mdo, md->constant_encoding());
1485       __ load_klass(recv, value);
1486       Label update_done;
1487       type_profile_helper(mdo, md, data, recv, &done);
1488       __ b(done);
1489 
1490       __ bind(profile_cast_failure);
1491       __ mov_metadata(mdo, md->constant_encoding());
1492       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1493       __ lea(rscratch2, counter_addr);
1494       __ ldr(rscratch1, Address(rscratch2));
1495       __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1496       __ str(rscratch1, Address(rscratch2));
1497       __ b(*stub->entry());
1498     }
1499 
1500     __ bind(done);
1501   } else if (code == lir_checkcast) {
1502     Register obj = op->object()->as_register();
1503     Register dst = op->result_opr()->as_register();
1504     Label success;
1505     emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1506     __ bind(success);
1507     if (dst != obj) {
1508       __ mov(dst, obj);
1509     }
1510   } else if (code == lir_instanceof) {
1511     Register obj = op->object()->as_register();
1512     Register dst = op->result_opr()->as_register();
1513     Label success, failure, done;
1514     emit_typecheck_helper(op, &success, &failure, &failure);
1515     __ bind(failure);
1516     __ mov(dst, zr);
1517     __ b(done);
1518     __ bind(success);
1519     __ mov(dst, 1);
1520     __ bind(done);
1521   } else {
1522     ShouldNotReachHere();
1523   }
1524 }
1525 
1526 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1527   __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1528   __ cset(rscratch1, Assembler::NE);
1529   __ membar(__ AnyAny);
1530 }
1531 
1532 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1533   __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1534   __ cset(rscratch1, Assembler::NE);
1535   __ membar(__ AnyAny);
1536 }
1537 
1538 
1539 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1540   assert(VM_Version::supports_cx8(), "wrong machine");
1541   Register addr;
1542   if (op->addr()->is_register()) {
1543     addr = as_reg(op->addr());
1544   } else {
1545     assert(op->addr()->is_address(), "what else?");
1546     LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1547     assert(addr_ptr->disp() == 0, "need 0 disp");
1548     assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1549     addr = as_reg(addr_ptr->base());
1550   }
1551   Register newval = as_reg(op->new_value());
1552   Register cmpval = as_reg(op->cmp_value());
1553 
1554   if (op->code() == lir_cas_obj) {
1555     if (UseCompressedOops) {
1556       Register t1 = op->tmp1()->as_register();
1557       assert(op->tmp1()->is_valid(), "must be");
1558       __ encode_heap_oop(t1, cmpval);
1559       cmpval = t1;
1560       __ encode_heap_oop(rscratch2, newval);
1561       newval = rscratch2;
1562       casw(addr, newval, cmpval);
1563     } else {
1564       casl(addr, newval, cmpval);
1565     }
1566   } else if (op->code() == lir_cas_int) {
1567     casw(addr, newval, cmpval);
1568   } else {
1569     casl(addr, newval, cmpval);
1570   }
1571 }
1572 
1573 
1574 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1575 
1576   Assembler::Condition acond, ncond;
1577   switch (condition) {
1578   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1579   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1580   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1581   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1582   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1583   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1584   case lir_cond_belowEqual:
1585   case lir_cond_aboveEqual:
1586   default:                    ShouldNotReachHere();
1587     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1588   }
1589 
1590   assert(result->is_single_cpu() || result->is_double_cpu(),
1591          "expect single register for result");
1592   if (opr1->is_constant() && opr2->is_constant()
1593       && opr1->type() == T_INT && opr2->type() == T_INT) {
1594     jint val1 = opr1->as_jint();
1595     jint val2 = opr2->as_jint();
1596     if (val1 == 0 && val2 == 1) {
1597       __ cset(result->as_register(), ncond);
1598       return;
1599     } else if (val1 == 1 && val2 == 0) {
1600       __ cset(result->as_register(), acond);
1601       return;
1602     }
1603   }
1604 
1605   if (opr1->is_constant() && opr2->is_constant()
1606       && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1607     jlong val1 = opr1->as_jlong();
1608     jlong val2 = opr2->as_jlong();
1609     if (val1 == 0 && val2 == 1) {
1610       __ cset(result->as_register_lo(), ncond);
1611       return;
1612     } else if (val1 == 1 && val2 == 0) {
1613       __ cset(result->as_register_lo(), acond);
1614       return;
1615     }
1616   }
1617 
1618   if (opr1->is_stack()) {
1619     stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1620     opr1 = FrameMap::rscratch1_opr;
1621   } else if (opr1->is_constant()) {
1622     LIR_Opr tmp
1623       = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1624     const2reg(opr1, tmp, lir_patch_none, NULL);
1625     opr1 = tmp;
1626   }
1627 
1628   if (opr2->is_stack()) {
1629     stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1630     opr2 = FrameMap::rscratch2_opr;
1631   } else if (opr2->is_constant()) {
1632     LIR_Opr tmp
1633       = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1634     const2reg(opr2, tmp, lir_patch_none, NULL);
1635     opr2 = tmp;
1636   }
1637 
1638   if (result->type() == T_LONG)
1639     __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1640   else
1641     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1642 }
1643 
1644 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1645   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1646 
1647   if (left->is_single_cpu()) {
1648     Register lreg = left->as_register();
1649     Register dreg = as_reg(dest);
1650 
1651     if (right->is_single_cpu()) {
1652       // cpu register - cpu register
1653 
1654       assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1655              "should be");
1656       Register rreg = right->as_register();
1657       switch (code) {
1658       case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1659       case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1660       case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1661       default:      ShouldNotReachHere();
1662       }
1663 
1664     } else if (right->is_double_cpu()) {
1665       Register rreg = right->as_register_lo();
1666       // single_cpu + double_cpu: can happen with obj+long
1667       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1668       switch (code) {
1669       case lir_add: __ add(dreg, lreg, rreg); break;
1670       case lir_sub: __ sub(dreg, lreg, rreg); break;
1671       default: ShouldNotReachHere();
1672       }
1673     } else if (right->is_constant()) {
1674       // cpu register - constant
1675       jlong c;
1676 
1677       // FIXME.  This is fugly: we really need to factor all this logic.
1678       switch(right->type()) {
1679       case T_LONG:
1680         c = right->as_constant_ptr()->as_jlong();
1681         break;
1682       case T_INT:
1683       case T_ADDRESS:
1684         c = right->as_constant_ptr()->as_jint();
1685         break;
1686       default:
1687         ShouldNotReachHere();
1688         c = 0;  // unreachable
1689         break;
1690       }
1691 
1692       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1693       if (c == 0 && dreg == lreg) {
1694         COMMENT("effective nop elided");
1695         return;
1696       }
1697       switch(left->type()) {
1698       case T_INT:
1699         switch (code) {
1700         case lir_add: __ addw(dreg, lreg, c); break;
1701         case lir_sub: __ subw(dreg, lreg, c); break;
1702         default: ShouldNotReachHere();
1703         }
1704         break;
1705       case T_OBJECT:
1706       case T_ADDRESS:
1707         switch (code) {
1708         case lir_add: __ add(dreg, lreg, c); break;
1709         case lir_sub: __ sub(dreg, lreg, c); break;
1710         default: ShouldNotReachHere();
1711         }
1712         break;
1713       default:
1714         ShouldNotReachHere();
1715       }
1716     } else {
1717       ShouldNotReachHere();
1718     }
1719 
1720   } else if (left->is_double_cpu()) {
1721     Register lreg_lo = left->as_register_lo();
1722 
1723     if (right->is_double_cpu()) {
1724       // cpu register - cpu register
1725       Register rreg_lo = right->as_register_lo();
1726       switch (code) {
1727       case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1728       case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1729       case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1730       case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1731       case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1732       default:
1733         ShouldNotReachHere();
1734       }
1735 
1736     } else if (right->is_constant()) {
1737       jlong c = right->as_constant_ptr()->as_jlong();
1738       Register dreg = as_reg(dest);
1739       switch (code) {
1740         case lir_add:
1741         case lir_sub:
1742           if (c == 0 && dreg == lreg_lo) {
1743             COMMENT("effective nop elided");
1744             return;
1745           }
1746           code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1747           break;
1748         case lir_div:
1749           assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1750           if (c == 1) {
1751             // move lreg_lo to dreg if divisor is 1
1752             __ mov(dreg, lreg_lo);
1753           } else {
1754             unsigned int shift = exact_log2_long(c);
1755             // use rscratch1 as intermediate result register
1756             __ asr(rscratch1, lreg_lo, 63);
1757             __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1758             __ asr(dreg, rscratch1, shift);
1759           }
1760           break;
1761         case lir_rem:
1762           assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1763           if (c == 1) {
1764             // move 0 to dreg if divisor is 1
1765             __ mov(dreg, zr);
1766           } else {
1767             // use rscratch1 as intermediate result register
1768             __ negs(rscratch1, lreg_lo);
1769             __ andr(dreg, lreg_lo, c - 1);
1770             __ andr(rscratch1, rscratch1, c - 1);
1771             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1772           }
1773           break;
1774         default:
1775           ShouldNotReachHere();
1776       }
1777     } else {
1778       ShouldNotReachHere();
1779     }
1780   } else if (left->is_single_fpu()) {
1781     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1782     switch (code) {
1783     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1784     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1785     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1786     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1787     default:
1788       ShouldNotReachHere();
1789     }
1790   } else if (left->is_double_fpu()) {
1791     if (right->is_double_fpu()) {
1792       // cpu register - cpu register
1793       switch (code) {
1794       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1795       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1796       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1797       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1798       default:
1799         ShouldNotReachHere();
1800       }
1801     } else {
1802       if (right->is_constant()) {
1803         ShouldNotReachHere();
1804       }
1805       ShouldNotReachHere();
1806     }
1807   } else if (left->is_single_stack() || left->is_address()) {
1808     assert(left == dest, "left and dest must be equal");
1809     ShouldNotReachHere();
1810   } else {
1811     ShouldNotReachHere();
1812   }
1813 }
1814 
1815 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1816 
1817 
1818 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1819   switch(code) {
1820   case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1821   case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1822   default      : ShouldNotReachHere();
1823   }
1824 }
1825 
1826 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1827 
1828   assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1829   Register Rleft = left->is_single_cpu() ? left->as_register() :
1830                                            left->as_register_lo();
1831    if (dst->is_single_cpu()) {
1832      Register Rdst = dst->as_register();
1833      if (right->is_constant()) {
1834        switch (code) {
1835          case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1836          case lir_logic_or:  __ orrw (Rdst, Rleft, right->as_jint()); break;
1837          case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1838          default: ShouldNotReachHere(); break;
1839        }
1840      } else {
1841        Register Rright = right->is_single_cpu() ? right->as_register() :
1842                                                   right->as_register_lo();
1843        switch (code) {
1844          case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1845          case lir_logic_or:  __ orrw (Rdst, Rleft, Rright); break;
1846          case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1847          default: ShouldNotReachHere(); break;
1848        }
1849      }
1850    } else {
1851      Register Rdst = dst->as_register_lo();
1852      if (right->is_constant()) {
1853        switch (code) {
1854          case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1855          case lir_logic_or:  __ orr (Rdst, Rleft, right->as_jlong()); break;
1856          case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1857          default: ShouldNotReachHere(); break;
1858        }
1859      } else {
1860        Register Rright = right->is_single_cpu() ? right->as_register() :
1861                                                   right->as_register_lo();
1862        switch (code) {
1863          case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1864          case lir_logic_or:  __ orr (Rdst, Rleft, Rright); break;
1865          case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1866          default: ShouldNotReachHere(); break;
1867        }
1868      }
1869    }
1870 }
1871 
1872 
1873 
1874 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1875 
1876   // opcode check
1877   assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1878   bool is_irem = (code == lir_irem);
1879 
1880   // operand check
1881   assert(left->is_single_cpu(),   "left must be register");
1882   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
1883   assert(result->is_single_cpu(), "result must be register");
1884   Register lreg = left->as_register();
1885   Register dreg = result->as_register();
1886 
1887   // power-of-2 constant check and codegen
1888   if (right->is_constant()) {
1889     int c = right->as_constant_ptr()->as_jint();
1890     assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1891     if (is_irem) {
1892       if (c == 1) {
1893         // move 0 to dreg if divisor is 1
1894         __ movw(dreg, zr);
1895       } else {
1896         // use rscratch1 as intermediate result register
1897         __ negsw(rscratch1, lreg);
1898         __ andw(dreg, lreg, c - 1);
1899         __ andw(rscratch1, rscratch1, c - 1);
1900         __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1901       }
1902     } else {
1903       if (c == 1) {
1904         // move lreg to dreg if divisor is 1
1905         __ movw(dreg, lreg);
1906       } else {
1907         unsigned int shift = exact_log2(c);
1908         // use rscratch1 as intermediate result register
1909         __ asrw(rscratch1, lreg, 31);
1910         __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1911         __ asrw(dreg, rscratch1, shift);
1912       }
1913     }
1914   } else {
1915     Register rreg = right->as_register();
1916     __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1917   }
1918 }
1919 
1920 
1921 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1922   if (opr1->is_constant() && opr2->is_single_cpu()) {
1923     // tableswitch
1924     Register reg = as_reg(opr2);
1925     struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1926     __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1927   } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1928     Register reg1 = as_reg(opr1);
1929     if (opr2->is_single_cpu()) {
1930       // cpu register - cpu register
1931       Register reg2 = opr2->as_register();
1932       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1933         __ cmpoop(reg1, reg2);
1934       } else {
1935         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
1936         __ cmpw(reg1, reg2);
1937       }
1938       return;
1939     }
1940     if (opr2->is_double_cpu()) {
1941       // cpu register - cpu register
1942       Register reg2 = opr2->as_register_lo();
1943       __ cmp(reg1, reg2);
1944       return;
1945     }
1946 
1947     if (opr2->is_constant()) {
1948       bool is_32bit = false; // width of register operand
1949       jlong imm;
1950 
1951       switch(opr2->type()) {
1952       case T_INT:
1953         imm = opr2->as_constant_ptr()->as_jint();
1954         is_32bit = true;
1955         break;
1956       case T_LONG:
1957         imm = opr2->as_constant_ptr()->as_jlong();
1958         break;
1959       case T_ADDRESS:
1960         imm = opr2->as_constant_ptr()->as_jint();
1961         break;
1962       case T_OBJECT:
1963       case T_ARRAY:
1964         jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1965         __ cmpoop(reg1, rscratch1);
1966         return;
1967       default:
1968         ShouldNotReachHere();
1969         imm = 0;  // unreachable
1970         break;
1971       }
1972 
1973       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1974         if (is_32bit)
1975           __ cmpw(reg1, imm);
1976         else
1977           __ subs(zr, reg1, imm);
1978         return;
1979       } else {
1980         __ mov(rscratch1, imm);
1981         if (is_32bit)
1982           __ cmpw(reg1, rscratch1);
1983         else
1984           __ cmp(reg1, rscratch1);
1985         return;
1986       }
1987     } else
1988       ShouldNotReachHere();
1989   } else if (opr1->is_single_fpu()) {
1990     FloatRegister reg1 = opr1->as_float_reg();
1991     assert(opr2->is_single_fpu(), "expect single float register");
1992     FloatRegister reg2 = opr2->as_float_reg();
1993     __ fcmps(reg1, reg2);
1994   } else if (opr1->is_double_fpu()) {
1995     FloatRegister reg1 = opr1->as_double_reg();
1996     assert(opr2->is_double_fpu(), "expect double float register");
1997     FloatRegister reg2 = opr2->as_double_reg();
1998     __ fcmpd(reg1, reg2);
1999   } else {
2000     ShouldNotReachHere();
2001   }
2002 }
2003 
2004 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2005   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2006     bool is_unordered_less = (code == lir_ucmp_fd2i);
2007     if (left->is_single_fpu()) {
2008       __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2009     } else if (left->is_double_fpu()) {
2010       __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2011     } else {
2012       ShouldNotReachHere();
2013     }
2014   } else if (code == lir_cmp_l2i) {
2015     Label done;
2016     __ cmp(left->as_register_lo(), right->as_register_lo());
2017     __ mov(dst->as_register(), (u_int64_t)-1L);
2018     __ br(Assembler::LT, done);
2019     __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2020     __ bind(done);
2021   } else {
2022     ShouldNotReachHere();
2023   }
2024 }
2025 
2026 
2027 void LIR_Assembler::align_call(LIR_Code code) {  }
2028 
2029 
2030 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2031   address call = __ trampoline_call(Address(op->addr(), rtype));
2032   if (call == NULL) {
2033     bailout("trampoline stub overflow");
2034     return;
2035   }
2036   add_call_info(code_offset(), op->info());
2037 }
2038 
2039 
2040 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2041   address call = __ ic_call(op->addr());
2042   if (call == NULL) {
2043     bailout("trampoline stub overflow");
2044     return;
2045   }
2046   add_call_info(code_offset(), op->info());
2047 }
2048 
2049 
2050 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2051 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2052   ShouldNotReachHere();
2053 }
2054 
2055 
2056 void LIR_Assembler::emit_static_call_stub() {
2057   address call_pc = __ pc();
2058   address stub = __ start_a_stub(call_stub_size());
2059   if (stub == NULL) {
2060     bailout("static call stub overflow");
2061     return;
2062   }
2063 
2064   int start = __ offset();
2065 
2066   __ relocate(static_stub_Relocation::spec(call_pc));
2067   __ emit_static_call_stub();
2068 
2069   assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2070         <= call_stub_size(), "stub too big");
2071   __ end_a_stub();
2072 }
2073 
2074 
2075 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2076   assert(exceptionOop->as_register() == r0, "must match");
2077   assert(exceptionPC->as_register() == r3, "must match");
2078 
2079   // exception object is not added to oop map by LinearScan
2080   // (LinearScan assumes that no oops are in fixed registers)
2081   info->add_register_oop(exceptionOop);
2082   Runtime1::StubID unwind_id;
2083 
2084   // get current pc information
2085   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2086   int pc_for_athrow_offset = __ offset();
2087   InternalAddress pc_for_athrow(__ pc());
2088   __ adr(exceptionPC->as_register(), pc_for_athrow);
2089   add_call_info(pc_for_athrow_offset, info); // for exception handler
2090 
2091   __ verify_not_null_oop(r0);
2092   // search an exception handler (r0: exception oop, r3: throwing pc)
2093   if (compilation()->has_fpu_code()) {
2094     unwind_id = Runtime1::handle_exception_id;
2095   } else {
2096     unwind_id = Runtime1::handle_exception_nofpu_id;
2097   }
2098   __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2099 
2100   // FIXME: enough room for two byte trap   ????
2101   __ nop();
2102 }
2103 
2104 
2105 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2106   assert(exceptionOop->as_register() == r0, "must match");
2107 
2108   __ b(_unwind_handler_entry);
2109 }
2110 
2111 
2112 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2113   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2114   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2115 
2116   switch (left->type()) {
2117     case T_INT: {
2118       switch (code) {
2119       case lir_shl:  __ lslvw (dreg, lreg, count->as_register()); break;
2120       case lir_shr:  __ asrvw (dreg, lreg, count->as_register()); break;
2121       case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2122       default:
2123         ShouldNotReachHere();
2124         break;
2125       }
2126       break;
2127     case T_LONG:
2128     case T_ADDRESS:
2129     case T_OBJECT:
2130       switch (code) {
2131       case lir_shl:  __ lslv (dreg, lreg, count->as_register()); break;
2132       case lir_shr:  __ asrv (dreg, lreg, count->as_register()); break;
2133       case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2134       default:
2135         ShouldNotReachHere();
2136         break;
2137       }
2138       break;
2139     default:
2140       ShouldNotReachHere();
2141       break;
2142     }
2143   }
2144 }
2145 
2146 
2147 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2148   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2149   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2150 
2151   switch (left->type()) {
2152     case T_INT: {
2153       switch (code) {
2154       case lir_shl:  __ lslw (dreg, lreg, count); break;
2155       case lir_shr:  __ asrw (dreg, lreg, count); break;
2156       case lir_ushr: __ lsrw (dreg, lreg, count); break;
2157       default:
2158         ShouldNotReachHere();
2159         break;
2160       }
2161       break;
2162     case T_LONG:
2163     case T_ADDRESS:
2164     case T_OBJECT:
2165       switch (code) {
2166       case lir_shl:  __ lsl (dreg, lreg, count); break;
2167       case lir_shr:  __ asr (dreg, lreg, count); break;
2168       case lir_ushr: __ lsr (dreg, lreg, count); break;
2169       default:
2170         ShouldNotReachHere();
2171         break;
2172       }
2173       break;
2174     default:
2175       ShouldNotReachHere();
2176       break;
2177     }
2178   }
2179 }
2180 
2181 
2182 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2183   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2184   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2185   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2186   __ str (r, Address(sp, offset_from_rsp_in_bytes));
2187 }
2188 
2189 
2190 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2191   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2192   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2193   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2194   __ mov (rscratch1, c);
2195   __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2196 }
2197 
2198 
2199 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2200   ShouldNotReachHere();
2201   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2202   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2203   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2204   __ lea(rscratch1, __ constant_oop_address(o));
2205   __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2206 }
2207 
2208 
2209 // This code replaces a call to arraycopy; no exception may
2210 // be thrown in this code, they must be thrown in the System.arraycopy
2211 // activation frame; we could save some checks if this would not be the case
2212 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2213   ciArrayKlass* default_type = op->expected_type();
2214   Register src = op->src()->as_register();
2215   Register dst = op->dst()->as_register();
2216   Register src_pos = op->src_pos()->as_register();
2217   Register dst_pos = op->dst_pos()->as_register();
2218   Register length  = op->length()->as_register();
2219   Register tmp = op->tmp()->as_register();
2220 
2221   __ resolve(ACCESS_READ, src);
2222   __ resolve(ACCESS_WRITE, dst);
2223 
2224   CodeStub* stub = op->stub();
2225   int flags = op->flags();
2226   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2227   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2228 
2229   // if we don't know anything, just go through the generic arraycopy
2230   if (default_type == NULL // || basic_type == T_OBJECT
2231       ) {
2232     Label done;
2233     assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2234 
2235     // Save the arguments in case the generic arraycopy fails and we
2236     // have to fall back to the JNI stub
2237     __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2238     __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2239     __ str(src,              Address(sp, 4*BytesPerWord));
2240 
2241     address copyfunc_addr = StubRoutines::generic_arraycopy();
2242     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2243 
2244     // The arguments are in java calling convention so we shift them
2245     // to C convention
2246     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2247     __ mov(c_rarg0, j_rarg0);
2248     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2249     __ mov(c_rarg1, j_rarg1);
2250     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2251     __ mov(c_rarg2, j_rarg2);
2252     assert_different_registers(c_rarg3, j_rarg4);
2253     __ mov(c_rarg3, j_rarg3);
2254     __ mov(c_rarg4, j_rarg4);
2255 #ifndef PRODUCT
2256     if (PrintC1Statistics) {
2257       __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2258     }
2259 #endif
2260     __ far_call(RuntimeAddress(copyfunc_addr));
2261 
2262     __ cbz(r0, *stub->continuation());
2263 
2264     // Reload values from the stack so they are where the stub
2265     // expects them.
2266     __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2267     __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2268     __ ldr(src,              Address(sp, 4*BytesPerWord));
2269 
2270     // r0 is -1^K where K == partial copied count
2271     __ eonw(rscratch1, r0, 0);
2272     // adjust length down and src/end pos up by partial copied count
2273     __ subw(length, length, rscratch1);
2274     __ addw(src_pos, src_pos, rscratch1);
2275     __ addw(dst_pos, dst_pos, rscratch1);
2276     __ b(*stub->entry());
2277 
2278     __ bind(*stub->continuation());
2279     return;
2280   }
2281 
2282   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2283 
2284   int elem_size = type2aelembytes(basic_type);
2285   int shift_amount;
2286   int scale = exact_log2(elem_size);
2287 
2288   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2289   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2290   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2291   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2292 
2293   // test for NULL
2294   if (flags & LIR_OpArrayCopy::src_null_check) {
2295     __ cbz(src, *stub->entry());
2296   }
2297   if (flags & LIR_OpArrayCopy::dst_null_check) {
2298     __ cbz(dst, *stub->entry());
2299   }
2300 
2301   // If the compiler was not able to prove that exact type of the source or the destination
2302   // of the arraycopy is an array type, check at runtime if the source or the destination is
2303   // an instance type.
2304   if (flags & LIR_OpArrayCopy::type_check) {
2305     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2306       __ load_klass(tmp, dst);
2307       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2308       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2309       __ br(Assembler::GE, *stub->entry());
2310     }
2311 
2312     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2313       __ load_klass(tmp, src);
2314       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2315       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2316       __ br(Assembler::GE, *stub->entry());
2317     }
2318   }
2319 
2320   // check if negative
2321   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2322     __ cmpw(src_pos, 0);
2323     __ br(Assembler::LT, *stub->entry());
2324   }
2325   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2326     __ cmpw(dst_pos, 0);
2327     __ br(Assembler::LT, *stub->entry());
2328   }
2329 
2330   if (flags & LIR_OpArrayCopy::length_positive_check) {
2331     __ cmpw(length, 0);
2332     __ br(Assembler::LT, *stub->entry());
2333   }
2334 
2335   if (flags & LIR_OpArrayCopy::src_range_check) {
2336     __ addw(tmp, src_pos, length);
2337     __ ldrw(rscratch1, src_length_addr);
2338     __ cmpw(tmp, rscratch1);
2339     __ br(Assembler::HI, *stub->entry());
2340   }
2341   if (flags & LIR_OpArrayCopy::dst_range_check) {
2342     __ addw(tmp, dst_pos, length);
2343     __ ldrw(rscratch1, dst_length_addr);
2344     __ cmpw(tmp, rscratch1);
2345     __ br(Assembler::HI, *stub->entry());
2346   }
2347 
2348   if (flags & LIR_OpArrayCopy::type_check) {
2349     // We don't know the array types are compatible
2350     if (basic_type != T_OBJECT) {
2351       // Simple test for basic type arrays
2352       if (UseCompressedClassPointers) {
2353         __ ldrw(tmp, src_klass_addr);
2354         __ ldrw(rscratch1, dst_klass_addr);
2355         __ cmpw(tmp, rscratch1);
2356       } else {
2357         __ ldr(tmp, src_klass_addr);
2358         __ ldr(rscratch1, dst_klass_addr);
2359         __ cmp(tmp, rscratch1);
2360       }
2361       __ br(Assembler::NE, *stub->entry());
2362     } else {
2363       // For object arrays, if src is a sub class of dst then we can
2364       // safely do the copy.
2365       Label cont, slow;
2366 
2367 #define PUSH(r1, r2)                                    \
2368       stp(r1, r2, __ pre(sp, -2 * wordSize));
2369 
2370 #define POP(r1, r2)                                     \
2371       ldp(r1, r2, __ post(sp, 2 * wordSize));
2372 
2373       __ PUSH(src, dst);
2374 
2375       __ load_klass(src, src);
2376       __ load_klass(dst, dst);
2377 
2378       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2379 
2380       __ PUSH(src, dst);
2381       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2382       __ POP(src, dst);
2383 
2384       __ cbnz(src, cont);
2385 
2386       __ bind(slow);
2387       __ POP(src, dst);
2388 
2389       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2390       if (copyfunc_addr != NULL) { // use stub if available
2391         // src is not a sub class of dst so we have to do a
2392         // per-element check.
2393 
2394         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2395         if ((flags & mask) != mask) {
2396           // Check that at least both of them object arrays.
2397           assert(flags & mask, "one of the two should be known to be an object array");
2398 
2399           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2400             __ load_klass(tmp, src);
2401           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2402             __ load_klass(tmp, dst);
2403           }
2404           int lh_offset = in_bytes(Klass::layout_helper_offset());
2405           Address klass_lh_addr(tmp, lh_offset);
2406           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2407           __ ldrw(rscratch1, klass_lh_addr);
2408           __ mov(rscratch2, objArray_lh);
2409           __ eorw(rscratch1, rscratch1, rscratch2);
2410           __ cbnzw(rscratch1, *stub->entry());
2411         }
2412 
2413        // Spill because stubs can use any register they like and it's
2414        // easier to restore just those that we care about.
2415         __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2416         __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2417         __ str(src,              Address(sp, 4*BytesPerWord));
2418 
2419         __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2420         __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2421         assert_different_registers(c_rarg0, dst, dst_pos, length);
2422         __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2423         __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2424         assert_different_registers(c_rarg1, dst, length);
2425         __ uxtw(c_rarg2, length);
2426         assert_different_registers(c_rarg2, dst);
2427 
2428         __ load_klass(c_rarg4, dst);
2429         __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2430         __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2431         __ far_call(RuntimeAddress(copyfunc_addr));
2432 
2433 #ifndef PRODUCT
2434         if (PrintC1Statistics) {
2435           Label failed;
2436           __ cbnz(r0, failed);
2437           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2438           __ bind(failed);
2439         }
2440 #endif
2441 
2442         __ cbz(r0, *stub->continuation());
2443 
2444 #ifndef PRODUCT
2445         if (PrintC1Statistics) {
2446           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2447         }
2448 #endif
2449         assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2450 
2451         // Restore previously spilled arguments
2452         __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2453         __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2454         __ ldr(src,              Address(sp, 4*BytesPerWord));
2455 
2456         // return value is -1^K where K is partial copied count
2457         __ eonw(rscratch1, r0, zr);
2458         // adjust length down and src/end pos up by partial copied count
2459         __ subw(length, length, rscratch1);
2460         __ addw(src_pos, src_pos, rscratch1);
2461         __ addw(dst_pos, dst_pos, rscratch1);
2462       }
2463 
2464       __ b(*stub->entry());
2465 
2466       __ bind(cont);
2467       __ POP(src, dst);
2468     }
2469   }
2470 
2471 #ifdef ASSERT
2472   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2473     // Sanity check the known type with the incoming class.  For the
2474     // primitive case the types must match exactly with src.klass and
2475     // dst.klass each exactly matching the default type.  For the
2476     // object array case, if no type check is needed then either the
2477     // dst type is exactly the expected type and the src type is a
2478     // subtype which we can't check or src is the same array as dst
2479     // but not necessarily exactly of type default_type.
2480     Label known_ok, halt;
2481     __ mov_metadata(tmp, default_type->constant_encoding());
2482     if (UseCompressedClassPointers) {
2483       __ encode_klass_not_null(tmp);
2484     }
2485 
2486     if (basic_type != T_OBJECT) {
2487 
2488       if (UseCompressedClassPointers) {
2489         __ ldrw(rscratch1, dst_klass_addr);
2490         __ cmpw(tmp, rscratch1);
2491       } else {
2492         __ ldr(rscratch1, dst_klass_addr);
2493         __ cmp(tmp, rscratch1);
2494       }
2495       __ br(Assembler::NE, halt);
2496       if (UseCompressedClassPointers) {
2497         __ ldrw(rscratch1, src_klass_addr);
2498         __ cmpw(tmp, rscratch1);
2499       } else {
2500         __ ldr(rscratch1, src_klass_addr);
2501         __ cmp(tmp, rscratch1);
2502       }
2503       __ br(Assembler::EQ, known_ok);
2504     } else {
2505       if (UseCompressedClassPointers) {
2506         __ ldrw(rscratch1, dst_klass_addr);
2507         __ cmpw(tmp, rscratch1);
2508       } else {
2509         __ ldr(rscratch1, dst_klass_addr);
2510         __ cmp(tmp, rscratch1);
2511       }
2512       __ br(Assembler::EQ, known_ok);
2513       __ cmp(src, dst);
2514       __ br(Assembler::EQ, known_ok);
2515     }
2516     __ bind(halt);
2517     __ stop("incorrect type information in arraycopy");
2518     __ bind(known_ok);
2519   }
2520 #endif
2521 
2522 #ifndef PRODUCT
2523   if (PrintC1Statistics) {
2524     __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2525   }
2526 #endif
2527 
2528   __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2529   __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2530   assert_different_registers(c_rarg0, dst, dst_pos, length);
2531   __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2532   __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2533   assert_different_registers(c_rarg1, dst, length);
2534   __ uxtw(c_rarg2, length);
2535   assert_different_registers(c_rarg2, dst);
2536 
2537   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2538   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2539   const char *name;
2540   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2541 
2542  CodeBlob *cb = CodeCache::find_blob(entry);
2543  if (cb) {
2544    __ far_call(RuntimeAddress(entry));
2545  } else {
2546    __ call_VM_leaf(entry, 3);
2547  }
2548 
2549   __ bind(*stub->continuation());
2550 }
2551 
2552 
2553 
2554 
2555 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2556   Register obj = op->obj_opr()->as_register();  // may not be an oop
2557   Register hdr = op->hdr_opr()->as_register();
2558   Register lock = op->lock_opr()->as_register();
2559   if (!UseFastLocking) {
2560     __ b(*op->stub()->entry());
2561   } else if (op->code() == lir_lock) {
2562     Register scratch = noreg;
2563     if (UseBiasedLocking) {
2564       scratch = op->scratch_opr()->as_register();
2565     }
2566     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2567     __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
2568     // add debug info for NullPointerException only if one is possible
2569     int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
2570     if (op->info() != NULL) {
2571       add_debug_info_for_null_check(null_check_offset, op->info());
2572     }
2573     // done
2574   } else if (op->code() == lir_unlock) {
2575     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2576     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2577   } else {
2578     Unimplemented();
2579   }
2580   __ bind(*op->stub()->continuation());
2581 }
2582 
2583 
2584 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2585   ciMethod* method = op->profiled_method();
2586   int bci          = op->profiled_bci();
2587   ciMethod* callee = op->profiled_callee();
2588 
2589   // Update counter for all call types
2590   ciMethodData* md = method->method_data_or_null();
2591   assert(md != NULL, "Sanity");
2592   ciProfileData* data = md->bci_to_data(bci);
2593   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2594   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2595   Register mdo  = op->mdo()->as_register();
2596   __ mov_metadata(mdo, md->constant_encoding());
2597   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2598   // Perform additional virtual call profiling for invokevirtual and
2599   // invokeinterface bytecodes
2600   if (op->should_profile_receiver_type()) {
2601     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2602     Register recv = op->recv()->as_register();
2603     assert_different_registers(mdo, recv);
2604     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2605     ciKlass* known_klass = op->known_holder();
2606     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2607       // We know the type that will be seen at this call site; we can
2608       // statically update the MethodData* rather than needing to do
2609       // dynamic tests on the receiver type
2610 
2611       // NOTE: we should probably put a lock around this search to
2612       // avoid collisions by concurrent compilations
2613       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2614       uint i;
2615       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2616         ciKlass* receiver = vc_data->receiver(i);
2617         if (known_klass->equals(receiver)) {
2618           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2619           __ addptr(data_addr, DataLayout::counter_increment);
2620           return;
2621         }
2622       }
2623 
2624       // Receiver type not found in profile data; select an empty slot
2625 
2626       // Note that this is less efficient than it should be because it
2627       // always does a write to the receiver part of the
2628       // VirtualCallData rather than just the first time
2629       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2630         ciKlass* receiver = vc_data->receiver(i);
2631         if (receiver == NULL) {
2632           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2633           __ mov_metadata(rscratch1, known_klass->constant_encoding());
2634           __ lea(rscratch2, recv_addr);
2635           __ str(rscratch1, Address(rscratch2));
2636           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2637           __ addptr(data_addr, DataLayout::counter_increment);
2638           return;
2639         }
2640       }
2641     } else {
2642       __ load_klass(recv, recv);
2643       Label update_done;
2644       type_profile_helper(mdo, md, data, recv, &update_done);
2645       // Receiver did not match any saved receiver and there is no empty row for it.
2646       // Increment total counter to indicate polymorphic case.
2647       __ addptr(counter_addr, DataLayout::counter_increment);
2648 
2649       __ bind(update_done);
2650     }
2651   } else {
2652     // Static call
2653     __ addptr(counter_addr, DataLayout::counter_increment);
2654   }
2655 }
2656 
2657 
2658 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2659   Unimplemented();
2660 }
2661 
2662 
2663 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2664   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2665 }
2666 
2667 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2668   assert(op->crc()->is_single_cpu(),  "crc must be register");
2669   assert(op->val()->is_single_cpu(),  "byte value must be register");
2670   assert(op->result_opr()->is_single_cpu(), "result must be register");
2671   Register crc = op->crc()->as_register();
2672   Register val = op->val()->as_register();
2673   Register res = op->result_opr()->as_register();
2674 
2675   assert_different_registers(val, crc, res);
2676   unsigned long offset;
2677   __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2678   if (offset) __ add(res, res, offset);
2679 
2680   __ mvnw(crc, crc); // ~crc
2681   __ update_byte_crc32(crc, val, res);
2682   __ mvnw(res, crc); // ~crc
2683 }
2684 
2685 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2686   COMMENT("emit_profile_type {");
2687   Register obj = op->obj()->as_register();
2688   Register tmp = op->tmp()->as_pointer_register();
2689   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2690   ciKlass* exact_klass = op->exact_klass();
2691   intptr_t current_klass = op->current_klass();
2692   bool not_null = op->not_null();
2693   bool no_conflict = op->no_conflict();
2694 
2695   Label update, next, none;
2696 
2697   bool do_null = !not_null;
2698   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2699   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2700 
2701   assert(do_null || do_update, "why are we here?");
2702   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2703   assert(mdo_addr.base() != rscratch1, "wrong register");
2704 
2705   __ verify_oop(obj);
2706 
2707   if (tmp != obj) {
2708     __ mov(tmp, obj);
2709   }
2710   if (do_null) {
2711     __ cbnz(tmp, update);
2712     if (!TypeEntries::was_null_seen(current_klass)) {
2713       __ ldr(rscratch2, mdo_addr);
2714       __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2715       __ str(rscratch2, mdo_addr);
2716     }
2717     if (do_update) {
2718 #ifndef ASSERT
2719       __ b(next);
2720     }
2721 #else
2722       __ b(next);
2723     }
2724   } else {
2725     __ cbnz(tmp, update);
2726     __ stop("unexpected null obj");
2727 #endif
2728   }
2729 
2730   __ bind(update);
2731 
2732   if (do_update) {
2733 #ifdef ASSERT
2734     if (exact_klass != NULL) {
2735       Label ok;
2736       __ load_klass(tmp, tmp);
2737       __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2738       __ eor(rscratch1, tmp, rscratch1);
2739       __ cbz(rscratch1, ok);
2740       __ stop("exact klass and actual klass differ");
2741       __ bind(ok);
2742     }
2743 #endif
2744     if (!no_conflict) {
2745       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2746         if (exact_klass != NULL) {
2747           __ mov_metadata(tmp, exact_klass->constant_encoding());
2748         } else {
2749           __ load_klass(tmp, tmp);
2750         }
2751 
2752         __ ldr(rscratch2, mdo_addr);
2753         __ eor(tmp, tmp, rscratch2);
2754         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2755         // klass seen before, nothing to do. The unknown bit may have been
2756         // set already but no need to check.
2757         __ cbz(rscratch1, next);
2758 
2759         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2760 
2761         if (TypeEntries::is_type_none(current_klass)) {
2762           __ cbz(rscratch2, none);
2763           __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2764           __ br(Assembler::EQ, none);
2765           // There is a chance that the checks above (re-reading profiling
2766           // data from memory) fail if another thread has just set the
2767           // profiling to this obj's klass
2768           __ dmb(Assembler::ISHLD);
2769           __ ldr(rscratch2, mdo_addr);
2770           __ eor(tmp, tmp, rscratch2);
2771           __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2772           __ cbz(rscratch1, next);
2773         }
2774       } else {
2775         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2776                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2777 
2778         __ ldr(tmp, mdo_addr);
2779         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2780       }
2781 
2782       // different than before. Cannot keep accurate profile.
2783       __ ldr(rscratch2, mdo_addr);
2784       __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2785       __ str(rscratch2, mdo_addr);
2786 
2787       if (TypeEntries::is_type_none(current_klass)) {
2788         __ b(next);
2789 
2790         __ bind(none);
2791         // first time here. Set profile type.
2792         __ str(tmp, mdo_addr);
2793       }
2794     } else {
2795       // There's a single possible klass at this profile point
2796       assert(exact_klass != NULL, "should be");
2797       if (TypeEntries::is_type_none(current_klass)) {
2798         __ mov_metadata(tmp, exact_klass->constant_encoding());
2799         __ ldr(rscratch2, mdo_addr);
2800         __ eor(tmp, tmp, rscratch2);
2801         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2802         __ cbz(rscratch1, next);
2803 #ifdef ASSERT
2804         {
2805           Label ok;
2806           __ ldr(rscratch1, mdo_addr);
2807           __ cbz(rscratch1, ok);
2808           __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2809           __ br(Assembler::EQ, ok);
2810           // may have been set by another thread
2811           __ dmb(Assembler::ISHLD);
2812           __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2813           __ ldr(rscratch2, mdo_addr);
2814           __ eor(rscratch2, rscratch1, rscratch2);
2815           __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2816           __ cbz(rscratch2, ok);
2817 
2818           __ stop("unexpected profiling mismatch");
2819           __ bind(ok);
2820         }
2821 #endif
2822         // first time here. Set profile type.
2823         __ ldr(tmp, mdo_addr);
2824       } else {
2825         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2826                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2827 
2828         __ ldr(tmp, mdo_addr);
2829         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2830 
2831         __ orr(tmp, tmp, TypeEntries::type_unknown);
2832         __ str(tmp, mdo_addr);
2833         // FIXME: Write barrier needed here?
2834       }
2835     }
2836 
2837     __ bind(next);
2838   }
2839   COMMENT("} emit_profile_type");
2840 }
2841 
2842 
2843 void LIR_Assembler::align_backward_branch_target() {
2844 }
2845 
2846 
2847 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2848   // tmp must be unused
2849   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2850 
2851   if (left->is_single_cpu()) {
2852     assert(dest->is_single_cpu(), "expect single result reg");
2853     __ negw(dest->as_register(), left->as_register());
2854   } else if (left->is_double_cpu()) {
2855     assert(dest->is_double_cpu(), "expect double result reg");
2856     __ neg(dest->as_register_lo(), left->as_register_lo());
2857   } else if (left->is_single_fpu()) {
2858     assert(dest->is_single_fpu(), "expect single float result reg");
2859     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2860   } else {
2861     assert(left->is_double_fpu(), "expect double float operand reg");
2862     assert(dest->is_double_fpu(), "expect double float result reg");
2863     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2864   }
2865 }
2866 
2867 
2868 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2869   assert(patch_code == lir_patch_none, "Patch code not supported");
2870   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2871 }
2872 
2873 
2874 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2875   assert(!tmp->is_valid(), "don't need temporary");
2876 
2877   CodeBlob *cb = CodeCache::find_blob(dest);
2878   if (cb) {
2879     __ far_call(RuntimeAddress(dest));
2880   } else {
2881     __ mov(rscratch1, RuntimeAddress(dest));
2882     int len = args->length();
2883     int type = 0;
2884     if (! result->is_illegal()) {
2885       switch (result->type()) {
2886       case T_VOID:
2887         type = 0;
2888         break;
2889       case T_INT:
2890       case T_LONG:
2891       case T_OBJECT:
2892         type = 1;
2893         break;
2894       case T_FLOAT:
2895         type = 2;
2896         break;
2897       case T_DOUBLE:
2898         type = 3;
2899         break;
2900       default:
2901         ShouldNotReachHere();
2902         break;
2903       }
2904     }
2905     int num_gpargs = 0;
2906     int num_fpargs = 0;
2907     for (int i = 0; i < args->length(); i++) {
2908       LIR_Opr arg = args->at(i);
2909       if (arg->type() == T_FLOAT || arg->type() == T_DOUBLE) {
2910         num_fpargs++;
2911       } else {
2912         num_gpargs++;
2913       }
2914     }
2915     __ blrt(rscratch1, num_gpargs, num_fpargs, type);
2916   }
2917 
2918   if (info != NULL) {
2919     add_call_info_here(info);
2920   }
2921   __ maybe_isb();
2922 }
2923 
2924 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2925   if (dest->is_address() || src->is_address()) {
2926     move_op(src, dest, type, lir_patch_none, info,
2927             /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false);
2928   } else {
2929     ShouldNotReachHere();
2930   }
2931 }
2932 
2933 #ifdef ASSERT
2934 // emit run-time assertion
2935 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2936   assert(op->code() == lir_assert, "must be");
2937 
2938   if (op->in_opr1()->is_valid()) {
2939     assert(op->in_opr2()->is_valid(), "both operands must be valid");
2940     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2941   } else {
2942     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2943     assert(op->condition() == lir_cond_always, "no other conditions allowed");
2944   }
2945 
2946   Label ok;
2947   if (op->condition() != lir_cond_always) {
2948     Assembler::Condition acond = Assembler::AL;
2949     switch (op->condition()) {
2950       case lir_cond_equal:        acond = Assembler::EQ;  break;
2951       case lir_cond_notEqual:     acond = Assembler::NE;  break;
2952       case lir_cond_less:         acond = Assembler::LT;  break;
2953       case lir_cond_lessEqual:    acond = Assembler::LE;  break;
2954       case lir_cond_greaterEqual: acond = Assembler::GE;  break;
2955       case lir_cond_greater:      acond = Assembler::GT;  break;
2956       case lir_cond_belowEqual:   acond = Assembler::LS;  break;
2957       case lir_cond_aboveEqual:   acond = Assembler::HS;  break;
2958       default:                    ShouldNotReachHere();
2959     }
2960     __ br(acond, ok);
2961   }
2962   if (op->halt()) {
2963     const char* str = __ code_string(op->msg());
2964     __ stop(str);
2965   } else {
2966     breakpoint();
2967   }
2968   __ bind(ok);
2969 }
2970 #endif
2971 
2972 #ifndef PRODUCT
2973 #define COMMENT(x)   do { __ block_comment(x); } while (0)
2974 #else
2975 #define COMMENT(x)
2976 #endif
2977 
2978 void LIR_Assembler::membar() {
2979   COMMENT("membar");
2980   __ membar(MacroAssembler::AnyAny);
2981 }
2982 
2983 void LIR_Assembler::membar_acquire() {
2984   __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2985 }
2986 
2987 void LIR_Assembler::membar_release() {
2988   __ membar(Assembler::LoadStore|Assembler::StoreStore);
2989 }
2990 
2991 void LIR_Assembler::membar_loadload() {
2992   __ membar(Assembler::LoadLoad);
2993 }
2994 
2995 void LIR_Assembler::membar_storestore() {
2996   __ membar(MacroAssembler::StoreStore);
2997 }
2998 
2999 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3000 
3001 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3002 
3003 void LIR_Assembler::on_spin_wait() {
3004   Unimplemented();
3005 }
3006 
3007 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3008   __ mov(result_reg->as_register(), rthread);
3009 }
3010 
3011 
3012 void LIR_Assembler::peephole(LIR_List *lir) {
3013 #if 0
3014   if (tableswitch_count >= max_tableswitches)
3015     return;
3016 
3017   /*
3018     This finite-state automaton recognizes sequences of compare-and-
3019     branch instructions.  We will turn them into a tableswitch.  You
3020     could argue that C1 really shouldn't be doing this sort of
3021     optimization, but without it the code is really horrible.
3022   */
3023 
3024   enum { start_s, cmp1_s, beq_s, cmp_s } state;
3025   int first_key, last_key = -2147483648;
3026   int next_key = 0;
3027   int start_insn = -1;
3028   int last_insn = -1;
3029   Register reg = noreg;
3030   LIR_Opr reg_opr;
3031   state = start_s;
3032 
3033   LIR_OpList* inst = lir->instructions_list();
3034   for (int i = 0; i < inst->length(); i++) {
3035     LIR_Op* op = inst->at(i);
3036     switch (state) {
3037     case start_s:
3038       first_key = -1;
3039       start_insn = i;
3040       switch (op->code()) {
3041       case lir_cmp:
3042         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3043         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3044         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3045             && opr2->is_constant()
3046             && opr2->type() == T_INT) {
3047           reg_opr = opr1;
3048           reg = opr1->as_register();
3049           first_key = opr2->as_constant_ptr()->as_jint();
3050           next_key = first_key + 1;
3051           state = cmp_s;
3052           goto next_state;
3053         }
3054         break;
3055       }
3056       break;
3057     case cmp_s:
3058       switch (op->code()) {
3059       case lir_branch:
3060         if (op->as_OpBranch()->cond() == lir_cond_equal) {
3061           state = beq_s;
3062           last_insn = i;
3063           goto next_state;
3064         }
3065       }
3066       state = start_s;
3067       break;
3068     case beq_s:
3069       switch (op->code()) {
3070       case lir_cmp: {
3071         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3072         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3073         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3074             && opr1->as_register() == reg
3075             && opr2->is_constant()
3076             && opr2->type() == T_INT
3077             && opr2->as_constant_ptr()->as_jint() == next_key) {
3078           last_key = next_key;
3079           next_key++;
3080           state = cmp_s;
3081           goto next_state;
3082         }
3083       }
3084       }
3085       last_key = next_key;
3086       state = start_s;
3087       break;
3088     default:
3089       assert(false, "impossible state");
3090     }
3091     if (state == start_s) {
3092       if (first_key < last_key - 5L && reg != noreg) {
3093         {
3094           // printf("found run register %d starting at insn %d low value %d high value %d\n",
3095           //        reg->encoding(),
3096           //        start_insn, first_key, last_key);
3097           //   for (int i = 0; i < inst->length(); i++) {
3098           //     inst->at(i)->print();
3099           //     tty->print("\n");
3100           //   }
3101           //   tty->print("\n");
3102         }
3103 
3104         struct tableswitch *sw = &switches[tableswitch_count];
3105         sw->_insn_index = start_insn, sw->_first_key = first_key,
3106           sw->_last_key = last_key, sw->_reg = reg;
3107         inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3108         {
3109           // Insert the new table of branches
3110           int offset = last_insn;
3111           for (int n = first_key; n < last_key; n++) {
3112             inst->insert_before
3113               (last_insn + 1,
3114                new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3115                                 inst->at(offset)->as_OpBranch()->label()));
3116             offset -= 2, i++;
3117           }
3118         }
3119         // Delete all the old compare-and-branch instructions
3120         for (int n = first_key; n < last_key; n++) {
3121           inst->remove_at(start_insn);
3122           inst->remove_at(start_insn);
3123         }
3124         // Insert the tableswitch instruction
3125         inst->insert_before(start_insn,
3126                             new LIR_Op2(lir_cmp, lir_cond_always,
3127                                         LIR_OprFact::intConst(tableswitch_count),
3128                                         reg_opr));
3129         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3130         tableswitch_count++;
3131       }
3132       reg = noreg;
3133       last_key = -2147483648;
3134     }
3135   next_state:
3136     ;
3137   }
3138 #endif
3139 }
3140 
3141 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3142   Address addr = as_Address(src->as_address_ptr());
3143   BasicType type = src->type();
3144   bool is_oop = type == T_OBJECT || type == T_ARRAY;
3145 
3146   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3147   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3148 
3149   switch(type) {
3150   case T_INT:
3151     xchg = &MacroAssembler::atomic_xchgalw;
3152     add = &MacroAssembler::atomic_addalw;
3153     break;
3154   case T_LONG:
3155     xchg = &MacroAssembler::atomic_xchgal;
3156     add = &MacroAssembler::atomic_addal;
3157     break;
3158   case T_OBJECT:
3159   case T_ARRAY:
3160     if (UseCompressedOops) {
3161       xchg = &MacroAssembler::atomic_xchgalw;
3162       add = &MacroAssembler::atomic_addalw;
3163     } else {
3164       xchg = &MacroAssembler::atomic_xchgal;
3165       add = &MacroAssembler::atomic_addal;
3166     }
3167     break;
3168   default:
3169     ShouldNotReachHere();
3170     xchg = &MacroAssembler::atomic_xchgal;
3171     add = &MacroAssembler::atomic_addal; // unreachable
3172   }
3173 
3174   switch (code) {
3175   case lir_xadd:
3176     {
3177       RegisterOrConstant inc;
3178       Register tmp = as_reg(tmp_op);
3179       Register dst = as_reg(dest);
3180       if (data->is_constant()) {
3181         inc = RegisterOrConstant(as_long(data));
3182         assert_different_registers(dst, addr.base(), tmp,
3183                                    rscratch1, rscratch2);
3184       } else {
3185         inc = RegisterOrConstant(as_reg(data));
3186         assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3187                                    rscratch1, rscratch2);
3188       }
3189       __ lea(tmp, addr);
3190       (_masm->*add)(dst, inc, tmp);
3191       break;
3192     }
3193   case lir_xchg:
3194     {
3195       Register tmp = tmp_op->as_register();
3196       Register obj = as_reg(data);
3197       Register dst = as_reg(dest);
3198       if (is_oop && UseCompressedOops) {
3199         __ encode_heap_oop(rscratch2, obj);
3200         obj = rscratch2;
3201       }
3202       assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3203       __ lea(tmp, addr);
3204       (_masm->*xchg)(dst, obj, tmp);
3205       if (is_oop && UseCompressedOops) {
3206         __ decode_heap_oop(dst);
3207       }
3208     }
3209     break;
3210   default:
3211     ShouldNotReachHere();
3212   }
3213   __ membar(__ AnyAny);
3214 }
3215 
3216 #undef __