1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2018, SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "jvm.h"
  28 #include "asm/assembler.inline.hpp"
  29 #include "asm/macroAssembler.inline.hpp"
  30 #include "compiler/disassembler.hpp"
  31 #include "memory/resourceArea.hpp"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "utilities/align.hpp"
  36 #include "utilities/defaultStream.hpp"
  37 #include "utilities/globalDefinitions.hpp"
  38 #include "vm_version_ppc.hpp"
  39 
  40 #include <sys/sysinfo.h>
  41 
  42 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
  43 #include <sys/auxv.h>
  44 
  45 #ifndef PPC_FEATURE2_HTM_NOSC
  46 #define PPC_FEATURE2_HTM_NOSC (1 << 24)
  47 #endif
  48 #endif
  49 
  50 bool VM_Version::_is_determine_features_test_running = false;
  51 uint64_t VM_Version::_dscr_val = 0;
  52 
  53 #define MSG(flag)   \
  54   if (flag && !FLAG_IS_DEFAULT(flag))                                  \
  55       jio_fprintf(defaultStream::error_stream(),                       \
  56                   "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
  57                   "         -XX:+" #flag " will be disabled!\n");
  58 
  59 void VM_Version::initialize() {
  60 
  61   // Test which instructions are supported and measure cache line size.
  62   determine_features();
  63 
  64   // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
  65   if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
  66     if (VM_Version::has_darn()) {
  67       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 9);
  68     } else if (VM_Version::has_lqarx()) {
  69       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
  70     } else if (VM_Version::has_popcntw()) {
  71       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
  72     } else if (VM_Version::has_cmpb()) {
  73       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
  74     } else if (VM_Version::has_popcntb()) {
  75       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
  76     } else {
  77       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
  78     }
  79   }
  80 
  81   bool PowerArchitecturePPC64_ok = false;
  82   switch (PowerArchitecturePPC64) {
  83     case 9: if (!VM_Version::has_darn()   ) break;
  84     case 8: if (!VM_Version::has_lqarx()  ) break;
  85     case 7: if (!VM_Version::has_popcntw()) break;
  86     case 6: if (!VM_Version::has_cmpb()   ) break;
  87     case 5: if (!VM_Version::has_popcntb()) break;
  88     case 0: PowerArchitecturePPC64_ok = true; break;
  89     default: break;
  90   }
  91   guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
  92             UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
  93 
  94   // Power 8: Configure Data Stream Control Register.
  95   if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
  96     config_dscr();
  97   }
  98 
  99   if (!UseSIGTRAP) {
 100     MSG(TrapBasedICMissChecks);
 101     MSG(TrapBasedNotEntrantChecks);
 102     MSG(TrapBasedNullChecks);
 103     FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
 104     FLAG_SET_ERGO(bool, TrapBasedNullChecks,       false);
 105     FLAG_SET_ERGO(bool, TrapBasedICMissChecks,     false);
 106   }
 107 
 108 #ifdef COMPILER2
 109   if (!UseSIGTRAP) {
 110     MSG(TrapBasedRangeChecks);
 111     FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
 112   }
 113 
 114   // On Power6 test for section size.
 115   if (PowerArchitecturePPC64 == 6) {
 116     determine_section_size();
 117   // TODO: PPC port } else {
 118   // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
 119   }
 120 
 121   if (PowerArchitecturePPC64 >= 8) {
 122     if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
 123       FLAG_SET_ERGO(bool, SuperwordUseVSX, true);
 124     }
 125   } else {
 126     if (SuperwordUseVSX) {
 127       warning("SuperwordUseVSX specified, but needs at least Power8.");
 128       FLAG_SET_DEFAULT(SuperwordUseVSX, false);
 129     }
 130   }
 131   MaxVectorSize = SuperwordUseVSX ? 16 : 8;
 132 
 133   if (PowerArchitecturePPC64 >= 9) {
 134     if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstructionsPPC64)) {
 135       FLAG_SET_ERGO(bool, UseCountTrailingZerosInstructionsPPC64, true);
 136     }
 137     if (FLAG_IS_DEFAULT(UseCharacterCompareIntrinsics)) {
 138       FLAG_SET_ERGO(bool, UseCharacterCompareIntrinsics, true);
 139     }
 140   } else {
 141     if (UseCountTrailingZerosInstructionsPPC64) {
 142       warning("UseCountTrailingZerosInstructionsPPC64 specified, but needs at least Power9.");
 143       FLAG_SET_DEFAULT(UseCountTrailingZerosInstructionsPPC64, false);
 144     }
 145     if (UseCharacterCompareIntrinsics) {
 146       warning("UseCharacterCompareIntrinsics specified, but needs at least Power9.");
 147       FLAG_SET_DEFAULT(UseCharacterCompareIntrinsics, false);
 148     }
 149   }
 150 #endif
 151 
 152   // Create and print feature-string.
 153   char buf[(num_features+1) * 16]; // Max 16 chars per feature.
 154   jio_snprintf(buf, sizeof(buf),
 155                "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 156                (has_fsqrt()   ? " fsqrt"   : ""),
 157                (has_isel()    ? " isel"    : ""),
 158                (has_lxarxeh() ? " lxarxeh" : ""),
 159                (has_cmpb()    ? " cmpb"    : ""),
 160                (has_popcntb() ? " popcntb" : ""),
 161                (has_popcntw() ? " popcntw" : ""),
 162                (has_fcfids()  ? " fcfids"  : ""),
 163                (has_vand()    ? " vand"    : ""),
 164                (has_lqarx()   ? " lqarx"   : ""),
 165                (has_vcipher() ? " aes"     : ""),
 166                (has_vpmsumb() ? " vpmsumb" : ""),
 167                (has_mfdscr()  ? " mfdscr"  : ""),
 168                (has_vsx()     ? " vsx"     : ""),
 169                (has_ldbrx()   ? " ldbrx"   : ""),
 170                (has_stdbrx()  ? " stdbrx"  : ""),
 171                (has_vshasig() ? " sha"     : ""),
 172                (has_tm()      ? " rtm"     : ""),
 173                (has_darn()    ? " darn"    : "")
 174                // Make sure number of %s matches num_features!
 175               );
 176   _features_string = os::strdup(buf);
 177   if (Verbose) {
 178     print_features();
 179   }
 180 
 181   // PPC64 supports 8-byte compare-exchange operations (see Atomic::cmpxchg)
 182   // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
 183   _supports_cx8 = true;
 184 
 185   // Used by C1.
 186   _supports_atomic_getset4 = true;
 187   _supports_atomic_getadd4 = true;
 188   _supports_atomic_getset8 = true;
 189   _supports_atomic_getadd8 = true;
 190 
 191   UseSSE = 0; // Only on x86 and x64
 192 
 193   intx cache_line_size = L1_data_cache_line_size();
 194 
 195   if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
 196 
 197   if (AllocatePrefetchStyle == 4) {
 198     AllocatePrefetchStepSize = cache_line_size; // Need exact value.
 199     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
 200     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
 201   } else {
 202     if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
 203     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
 204     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
 205   }
 206 
 207   assert(AllocatePrefetchLines > 0, "invalid value");
 208   if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
 209     AllocatePrefetchLines = 1; // Conservative value.
 210   }
 211 
 212   if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
 213     AllocatePrefetchStyle = 1; // Fall back if inappropriate.
 214   }
 215 
 216   assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
 217 
 218   // If running on Power8 or newer hardware, the implementation uses the available vector instructions.
 219   // In all other cases, the implementation uses only generally available instructions.
 220   if (!UseCRC32Intrinsics) {
 221     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 222       FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
 223     }
 224   }
 225 
 226   // Implementation does not use any of the vector instructions available with Power8.
 227   // Their exploitation is still pending (aka "work in progress").
 228   if (!UseCRC32CIntrinsics) {
 229     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 230       FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 231     }
 232   }
 233 
 234   // TODO: Provide implementation.
 235   if (UseAdler32Intrinsics) {
 236     warning("Adler32Intrinsics not available on this CPU.");
 237     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 238   }
 239 
 240   // The AES intrinsic stubs require AES instruction support.
 241   if (has_vcipher()) {
 242     if (FLAG_IS_DEFAULT(UseAES)) {
 243       UseAES = true;
 244     }
 245   } else if (UseAES) {
 246     if (!FLAG_IS_DEFAULT(UseAES))
 247       warning("AES instructions are not available on this CPU");
 248     FLAG_SET_DEFAULT(UseAES, false);
 249   }
 250 
 251   if (UseAES && has_vcipher()) {
 252     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 253       UseAESIntrinsics = true;
 254     }
 255   } else if (UseAESIntrinsics) {
 256     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 257       warning("AES intrinsics are not available on this CPU");
 258     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 259   }
 260 
 261   if (UseAESCTRIntrinsics) {
 262     warning("AES/CTR intrinsics are not available on this CPU");
 263     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 264   }
 265 
 266   if (UseGHASHIntrinsics) {
 267     warning("GHASH intrinsics are not available on this CPU");
 268     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 269   }
 270 
 271   if (FLAG_IS_DEFAULT(UseFMA)) {
 272     FLAG_SET_DEFAULT(UseFMA, true);
 273   }
 274 
 275   if (has_vshasig()) {
 276     if (FLAG_IS_DEFAULT(UseSHA)) {
 277       UseSHA = true;
 278     }
 279   } else if (UseSHA) {
 280     if (!FLAG_IS_DEFAULT(UseSHA))
 281       warning("SHA instructions are not available on this CPU");
 282     FLAG_SET_DEFAULT(UseSHA, false);
 283   }
 284 
 285   if (UseSHA1Intrinsics) {
 286     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 287     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 288   }
 289 
 290   if (UseSHA && has_vshasig()) {
 291     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 292       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 293     }
 294   } else if (UseSHA256Intrinsics) {
 295     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 296     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 297   }
 298 
 299   if (UseSHA && has_vshasig()) {
 300     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 301       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 302     }
 303   } else if (UseSHA512Intrinsics) {
 304     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 305     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 306   }
 307 
 308   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 309     FLAG_SET_DEFAULT(UseSHA, false);
 310   }
 311 
 312   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
 313     UseSquareToLenIntrinsic = true;
 314   }
 315   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
 316     UseMulAddIntrinsic = true;
 317   }
 318   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
 319     UseMultiplyToLenIntrinsic = true;
 320   }
 321   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
 322     UseMontgomeryMultiplyIntrinsic = true;
 323   }
 324   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
 325     UseMontgomerySquareIntrinsic = true;
 326   }
 327 
 328   if (UseVectorizedMismatchIntrinsic) {
 329     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
 330     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
 331   }
 332 
 333 
 334   // Adjust RTM (Restricted Transactional Memory) flags.
 335   if (UseRTMLocking) {
 336     // If CPU or OS do not support TM:
 337     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 338     // setting during arguments processing. See use_biased_locking().
 339     // VM_Version_init() is executed after UseBiasedLocking is used
 340     // in Thread::allocate().
 341     if (PowerArchitecturePPC64 < 8) {
 342       vm_exit_during_initialization("RTM instructions are not available on this CPU.");
 343     }
 344 
 345     if (!has_tm()) {
 346       vm_exit_during_initialization("RTM is not supported on this OS version.");
 347     }
 348   }
 349 
 350   if (UseRTMLocking) {
 351 #if INCLUDE_RTM_OPT
 352     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
 353       // RTM locking should be used only for applications with
 354       // high lock contention. For now we do not use it by default.
 355       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
 356     }
 357 #else
 358     // Only C2 does RTM locking optimization.
 359     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 360     // setting during arguments processing. See use_biased_locking().
 361     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 362 #endif
 363   } else { // !UseRTMLocking
 364     if (UseRTMForStackLocks) {
 365       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
 366         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
 367       }
 368       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
 369     }
 370     if (UseRTMDeopt) {
 371       FLAG_SET_DEFAULT(UseRTMDeopt, false);
 372     }
 373     if (PrintPreciseRTMLockingStatistics) {
 374       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
 375     }
 376   }
 377 
 378   // This machine allows unaligned memory accesses
 379   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
 380     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
 381   }
 382 }
 383 
 384 void VM_Version::print_platform_virtualization_info(outputStream* st) {
 385   const char* info_file = "/proc/ppc64/lparcfg";
 386   const char* kw[] = { "system_type=", // qemu indicates PowerKVM
 387                        "partition_entitled_capacity=", // entitled processor capacity percentage
 388                        "partition_max_entitled_capacity=",
 389                        "capacity_weight=", // partition CPU weight
 390                        "partition_active_processors=",
 391                        "partition_potential_processors=",
 392                        "entitled_proc_capacity_available=",
 393                        "capped=", // 0 - uncapped, 1 - vcpus capped at entitled processor capacity percentage
 394                        "shared_processor_mode=", // (non)dedicated partition
 395                        "system_potential_processors=",
 396                        "pool=", // CPU-pool number
 397                        "pool_capacity=",
 398                        "NumLpars=", // on non-KVM machines, NumLpars is not found for full partition mode machines
 399                        NULL };
 400   if (!print_matching_lines_from_file(info_file, st, kw)) {
 401     st->print_cr("  <%s Not Available>", info_file);
 402   }
 403 }
 404 
 405 bool VM_Version::use_biased_locking() {
 406 #if INCLUDE_RTM_OPT
 407   // RTM locking is most useful when there is high lock contention and
 408   // low data contention. With high lock contention the lock is usually
 409   // inflated and biased locking is not suitable for that case.
 410   // RTM locking code requires that biased locking is off.
 411   // Note: we can't switch off UseBiasedLocking in get_processor_features()
 412   // because it is used by Thread::allocate() which is called before
 413   // VM_Version::initialize().
 414   if (UseRTMLocking && UseBiasedLocking) {
 415     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
 416       FLAG_SET_DEFAULT(UseBiasedLocking, false);
 417     } else {
 418       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
 419       UseBiasedLocking = false;
 420     }
 421   }
 422 #endif
 423   return UseBiasedLocking;
 424 }
 425 
 426 void VM_Version::print_features() {
 427   tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
 428 }
 429 
 430 #ifdef COMPILER2
 431 // Determine section size on power6: If section size is 8 instructions,
 432 // there should be a difference between the two testloops of ~15 %. If
 433 // no difference is detected the section is assumed to be 32 instructions.
 434 void VM_Version::determine_section_size() {
 435 
 436   int unroll = 80;
 437 
 438   const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
 439 
 440   // Allocate space for the code.
 441   ResourceMark rm;
 442   CodeBuffer cb("detect_section_size", code_size, 0);
 443   MacroAssembler* a = new MacroAssembler(&cb);
 444 
 445   uint32_t *code = (uint32_t *)a->pc();
 446   // Emit code.
 447   void (*test1)() = (void(*)())(void *)a->function_entry();
 448 
 449   Label l1;
 450 
 451   a->li(R4, 1);
 452   a->sldi(R4, R4, 28);
 453   a->b(l1);
 454   a->align(CodeEntryAlignment);
 455 
 456   a->bind(l1);
 457 
 458   for (int i = 0; i < unroll; i++) {
 459     // Schleife 1
 460     // ------- sector 0 ------------
 461     // ;; 0
 462     a->nop();                   // 1
 463     a->fpnop0();                // 2
 464     a->fpnop1();                // 3
 465     a->addi(R4,R4, -1); // 4
 466 
 467     // ;;  1
 468     a->nop();                   // 5
 469     a->fmr(F6, F6);             // 6
 470     a->fmr(F7, F7);             // 7
 471     a->endgroup();              // 8
 472     // ------- sector 8 ------------
 473 
 474     // ;;  2
 475     a->nop();                   // 9
 476     a->nop();                   // 10
 477     a->fmr(F8, F8);             // 11
 478     a->fmr(F9, F9);             // 12
 479 
 480     // ;;  3
 481     a->nop();                   // 13
 482     a->fmr(F10, F10);           // 14
 483     a->fmr(F11, F11);           // 15
 484     a->endgroup();              // 16
 485     // -------- sector 16 -------------
 486 
 487     // ;;  4
 488     a->nop();                   // 17
 489     a->nop();                   // 18
 490     a->fmr(F15, F15);           // 19
 491     a->fmr(F16, F16);           // 20
 492 
 493     // ;;  5
 494     a->nop();                   // 21
 495     a->fmr(F17, F17);           // 22
 496     a->fmr(F18, F18);           // 23
 497     a->endgroup();              // 24
 498     // ------- sector 24  ------------
 499 
 500     // ;;  6
 501     a->nop();                   // 25
 502     a->nop();                   // 26
 503     a->fmr(F19, F19);           // 27
 504     a->fmr(F20, F20);           // 28
 505 
 506     // ;;  7
 507     a->nop();                   // 29
 508     a->fmr(F21, F21);           // 30
 509     a->fmr(F22, F22);           // 31
 510     a->brnop0();                // 32
 511 
 512     // ------- sector 32 ------------
 513   }
 514 
 515   // ;; 8
 516   a->cmpdi(CCR0, R4, unroll);   // 33
 517   a->bge(CCR0, l1);             // 34
 518   a->blr();
 519 
 520   // Emit code.
 521   void (*test2)() = (void(*)())(void *)a->function_entry();
 522   // uint32_t *code = (uint32_t *)a->pc();
 523 
 524   Label l2;
 525 
 526   a->li(R4, 1);
 527   a->sldi(R4, R4, 28);
 528   a->b(l2);
 529   a->align(CodeEntryAlignment);
 530 
 531   a->bind(l2);
 532 
 533   for (int i = 0; i < unroll; i++) {
 534     // Schleife 2
 535     // ------- sector 0 ------------
 536     // ;; 0
 537     a->brnop0();                  // 1
 538     a->nop();                     // 2
 539     //a->cmpdi(CCR0, R4, unroll);
 540     a->fpnop0();                  // 3
 541     a->fpnop1();                  // 4
 542     a->addi(R4,R4, -1);           // 5
 543 
 544     // ;; 1
 545 
 546     a->nop();                     // 6
 547     a->fmr(F6, F6);               // 7
 548     a->fmr(F7, F7);               // 8
 549     // ------- sector 8 ---------------
 550 
 551     // ;; 2
 552     a->endgroup();                // 9
 553 
 554     // ;; 3
 555     a->nop();                     // 10
 556     a->nop();                     // 11
 557     a->fmr(F8, F8);               // 12
 558 
 559     // ;; 4
 560     a->fmr(F9, F9);               // 13
 561     a->nop();                     // 14
 562     a->fmr(F10, F10);             // 15
 563 
 564     // ;; 5
 565     a->fmr(F11, F11);             // 16
 566     // -------- sector 16 -------------
 567 
 568     // ;; 6
 569     a->endgroup();                // 17
 570 
 571     // ;; 7
 572     a->nop();                     // 18
 573     a->nop();                     // 19
 574     a->fmr(F15, F15);             // 20
 575 
 576     // ;; 8
 577     a->fmr(F16, F16);             // 21
 578     a->nop();                     // 22
 579     a->fmr(F17, F17);             // 23
 580 
 581     // ;; 9
 582     a->fmr(F18, F18);             // 24
 583     // -------- sector 24 -------------
 584 
 585     // ;; 10
 586     a->endgroup();                // 25
 587 
 588     // ;; 11
 589     a->nop();                     // 26
 590     a->nop();                     // 27
 591     a->fmr(F19, F19);             // 28
 592 
 593     // ;; 12
 594     a->fmr(F20, F20);             // 29
 595     a->nop();                     // 30
 596     a->fmr(F21, F21);             // 31
 597 
 598     // ;; 13
 599     a->fmr(F22, F22);             // 32
 600   }
 601 
 602   // -------- sector 32 -------------
 603   // ;; 14
 604   a->cmpdi(CCR0, R4, unroll); // 33
 605   a->bge(CCR0, l2);           // 34
 606 
 607   a->blr();
 608   uint32_t *code_end = (uint32_t *)a->pc();
 609   a->flush();
 610 
 611   double loop1_seconds,loop2_seconds, rel_diff;
 612   uint64_t start1, stop1;
 613 
 614   start1 = os::current_thread_cpu_time(false);
 615   (*test1)();
 616   stop1 = os::current_thread_cpu_time(false);
 617   loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
 618 
 619 
 620   start1 = os::current_thread_cpu_time(false);
 621   (*test2)();
 622   stop1 = os::current_thread_cpu_time(false);
 623 
 624   loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
 625 
 626   rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
 627 
 628   if (PrintAssembly) {
 629     ttyLocker ttyl;
 630     tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
 631     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 632     tty->print_cr("Time loop1 :%f", loop1_seconds);
 633     tty->print_cr("Time loop2 :%f", loop2_seconds);
 634     tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
 635 
 636     if (rel_diff > 12.0) {
 637       tty->print_cr("Section Size 8 Instructions");
 638     } else{
 639       tty->print_cr("Section Size 32 Instructions or Power5");
 640     }
 641   }
 642 
 643 #if 0 // TODO: PPC port
 644   // Set sector size (if not set explicitly).
 645   if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
 646     if (rel_diff > 12.0) {
 647       PdScheduling::power6SectorSize = 0x20;
 648     } else {
 649       PdScheduling::power6SectorSize = 0x80;
 650     }
 651   } else if (Power6SectorSize128PPC64) {
 652     PdScheduling::power6SectorSize = 0x80;
 653   } else {
 654     PdScheduling::power6SectorSize = 0x20;
 655   }
 656 #endif
 657   if (UsePower6SchedulerPPC64) Unimplemented();
 658 }
 659 #endif // COMPILER2
 660 
 661 void VM_Version::determine_features() {
 662 #if defined(ABI_ELFv2)
 663   // 1 InstWord per call for the blr instruction.
 664   const int code_size = (num_features+1+2*1)*BytesPerInstWord;
 665 #else
 666   // 7 InstWords for each call (function descriptor + blr instruction).
 667   const int code_size = (num_features+1+2*7)*BytesPerInstWord;
 668 #endif
 669   int features = 0;
 670 
 671   // create test area
 672   enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
 673   char test_area[BUFFER_SIZE];
 674   char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
 675 
 676   // Allocate space for the code.
 677   ResourceMark rm;
 678   CodeBuffer cb("detect_cpu_features", code_size, 0);
 679   MacroAssembler* a = new MacroAssembler(&cb);
 680 
 681   // Must be set to true so we can generate the test code.
 682   _features = VM_Version::all_features_m;
 683 
 684   // Emit code.
 685   void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
 686   uint32_t *code = (uint32_t *)a->pc();
 687   // Don't use R0 in ldarx.
 688   // Keep R3_ARG1 unmodified, it contains &field (see below).
 689   // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
 690   a->fsqrt(F3, F4);                            // code[0]  -> fsqrt_m
 691   a->fsqrts(F3, F4);                           // code[1]  -> fsqrts_m
 692   a->isel(R7, R5, R6, 0);                      // code[2]  -> isel_m
 693   a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3]  -> lxarx_m
 694   a->cmpb(R7, R5, R6);                         // code[4]  -> cmpb
 695   a->popcntb(R7, R5);                          // code[5]  -> popcntb
 696   a->popcntw(R7, R5);                          // code[6]  -> popcntw
 697   a->fcfids(F3, F4);                           // code[7]  -> fcfids
 698   a->vand(VR0, VR0, VR0);                      // code[8]  -> vand
 699   // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
 700   a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9]  -> lqarx_m
 701   a->vcipher(VR0, VR1, VR2);                   // code[10] -> vcipher
 702   a->vpmsumb(VR0, VR1, VR2);                   // code[11] -> vpmsumb
 703   a->mfdscr(R0);                               // code[12] -> mfdscr
 704   a->lxvd2x(VSR0, R3_ARG1);                    // code[13] -> vsx
 705   a->ldbrx(R7, R3_ARG1, R4_ARG2);              // code[14] -> ldbrx
 706   a->stdbrx(R7, R3_ARG1, R4_ARG2);             // code[15] -> stdbrx
 707   a->vshasigmaw(VR0, VR1, 1, 0xF);             // code[16] -> vshasig
 708   // rtm is determined by OS
 709   a->darn(R7);                                 // code[17] -> darn
 710   a->blr();
 711 
 712   // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
 713   void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
 714   a->dcbz(R3_ARG1); // R3_ARG1 = addr
 715   a->blr();
 716 
 717   uint32_t *code_end = (uint32_t *)a->pc();
 718   a->flush();
 719   _features = VM_Version::unknown_m;
 720 
 721   // Print the detection code.
 722   if (PrintAssembly) {
 723     ttyLocker ttyl;
 724     tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
 725     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 726   }
 727 
 728   // Measure cache line size.
 729   memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
 730   (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
 731   int count = 0; // count zeroed bytes
 732   for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
 733   guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
 734   _L1_data_cache_line_size = count;
 735 
 736   // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
 737   VM_Version::_is_determine_features_test_running = true;
 738   // We must align the first argument to 16 bytes because of the lqarx check.
 739   (*test)(align_up((address)mid_of_test_area, 16), 0);
 740   VM_Version::_is_determine_features_test_running = false;
 741 
 742   // determine which instructions are legal.
 743   int feature_cntr = 0;
 744   if (code[feature_cntr++]) features |= fsqrt_m;
 745   if (code[feature_cntr++]) features |= fsqrts_m;
 746   if (code[feature_cntr++]) features |= isel_m;
 747   if (code[feature_cntr++]) features |= lxarxeh_m;
 748   if (code[feature_cntr++]) features |= cmpb_m;
 749   if (code[feature_cntr++]) features |= popcntb_m;
 750   if (code[feature_cntr++]) features |= popcntw_m;
 751   if (code[feature_cntr++]) features |= fcfids_m;
 752   if (code[feature_cntr++]) features |= vand_m;
 753   if (code[feature_cntr++]) features |= lqarx_m;
 754   if (code[feature_cntr++]) features |= vcipher_m;
 755   if (code[feature_cntr++]) features |= vpmsumb_m;
 756   if (code[feature_cntr++]) features |= mfdscr_m;
 757   if (code[feature_cntr++]) features |= vsx_m;
 758   if (code[feature_cntr++]) features |= ldbrx_m;
 759   if (code[feature_cntr++]) features |= stdbrx_m;
 760   if (code[feature_cntr++]) features |= vshasig_m;
 761   // feature rtm_m is determined by OS
 762   if (code[feature_cntr++]) features |= darn_m;
 763 
 764   // Print the detection code.
 765   if (PrintAssembly) {
 766     ttyLocker ttyl;
 767     tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
 768     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 769   }
 770 
 771   _features = features;
 772 
 773 #ifdef AIX
 774   // To enable it on AIX it's necessary POWER8 or above and at least AIX 7.2.
 775   // Actually, this is supported since AIX 7.1.. Unfortunately, this first
 776   // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
 777   // The Java property os.version, which is used in RTM tests to decide
 778   // whether the feature is available, only knows major and minor versions.
 779   // We don't want to change this property, as user code might depend on it.
 780   // So the tests can not check on subversion 3.30, and we only enable RTM
 781   // with AIX 7.2.
 782   if (has_lqarx()) { // POWER8 or above
 783     if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
 784       _features |= rtm_m;
 785     }
 786   }
 787 #endif
 788 #if defined(LINUX) && defined(VM_LITTLE_ENDIAN)
 789   unsigned long auxv = getauxval(AT_HWCAP2);
 790 
 791   if (auxv & PPC_FEATURE2_HTM_NOSC) {
 792     if (auxv & PPC_FEATURE2_HAS_HTM) {
 793       // TM on POWER8 and POWER9 in compat mode (VM) is supported by the JVM.
 794       // TM on POWER9 DD2.1 NV (baremetal) is not supported by the JVM (TM on
 795       // POWER9 DD2.1 NV has a few issues that need a couple of firmware
 796       // and kernel workarounds, so there is a new mode only supported
 797       // on non-virtualized P9 machines called HTM with no Suspend Mode).
 798       // TM on POWER9 D2.2+ NV is not supported at all by Linux.
 799       _features |= rtm_m;
 800     }
 801   }
 802 #endif
 803 }
 804 
 805 // Power 8: Configure Data Stream Control Register.
 806 void VM_Version::config_dscr() {
 807   // 7 InstWords for each call (function descriptor + blr instruction).
 808   const int code_size = (2+2*7)*BytesPerInstWord;
 809 
 810   // Allocate space for the code.
 811   ResourceMark rm;
 812   CodeBuffer cb("config_dscr", code_size, 0);
 813   MacroAssembler* a = new MacroAssembler(&cb);
 814 
 815   // Emit code.
 816   uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
 817   uint32_t *code = (uint32_t *)a->pc();
 818   a->mfdscr(R3);
 819   a->blr();
 820 
 821   void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
 822   a->mtdscr(R3);
 823   a->blr();
 824 
 825   uint32_t *code_end = (uint32_t *)a->pc();
 826   a->flush();
 827 
 828   // Print the detection code.
 829   if (PrintAssembly) {
 830     ttyLocker ttyl;
 831     tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
 832     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 833   }
 834 
 835   // Apply the configuration if needed.
 836   _dscr_val = (*get_dscr)();
 837   if (Verbose) {
 838     tty->print_cr("dscr value was 0x%lx" , _dscr_val);
 839   }
 840   bool change_requested = false;
 841   if (DSCR_PPC64 != (uintx)-1) {
 842     _dscr_val = DSCR_PPC64;
 843     change_requested = true;
 844   }
 845   if (DSCR_DPFD_PPC64 <= 7) {
 846     uint64_t mask = 0x7;
 847     if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
 848       _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
 849       change_requested = true;
 850     }
 851   }
 852   if (DSCR_URG_PPC64 <= 7) {
 853     uint64_t mask = 0x7 << 6;
 854     if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
 855       _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
 856       change_requested = true;
 857     }
 858   }
 859   if (change_requested) {
 860     (*set_dscr)(_dscr_val);
 861     if (Verbose) {
 862       tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
 863     }
 864   }
 865 }
 866 
 867 static uint64_t saved_features = 0;
 868 
 869 void VM_Version::allow_all() {
 870   saved_features = _features;
 871   _features      = all_features_m;
 872 }
 873 
 874 void VM_Version::revert() {
 875   _features = saved_features;
 876 }