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src/hotspot/cpu/s390/macroAssembler_s390.cpp

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1154 }
1155 
1156 // Load a 32bit constant into a 64bit register, sign-extend or zero-extend.
1157 // Patchable code sequence, but not atomically patchable.
1158 // Make sure to keep code size constant -> no value-dependent optimizations.
1159 // Do not kill condition code.
1160 void MacroAssembler::load_const_32to64(Register t, int64_t x, bool sign_extend) {
1161   if (sign_extend) { Assembler::z_lgfi(t, x); }
1162   else             { Assembler::z_llilf(t, x); }
1163 }
1164 
1165 // Load narrow oop constant, no decompression.
1166 void MacroAssembler::load_narrow_oop(Register t, narrowOop a) {
1167   assert(UseCompressedOops, "must be on to call this method");
1168   load_const_32to64(t, a, false /*sign_extend*/);
1169 }
1170 
1171 // Load narrow klass constant, compression required.
1172 void MacroAssembler::load_narrow_klass(Register t, Klass* k) {
1173   assert(UseCompressedClassPointers, "must be on to call this method");
1174   narrowKlass encoded_k = CompressedKlassPointers::encode(k);
1175   load_const_32to64(t, encoded_k, false /*sign_extend*/);
1176 }
1177 
1178 //------------------------------------------------------
1179 //  Compare (patchable) constant with register.
1180 //------------------------------------------------------
1181 
1182 // Compare narrow oop in reg with narrow oop constant, no decompression.
1183 void MacroAssembler::compare_immediate_narrow_oop(Register oop1, narrowOop oop2) {
1184   assert(UseCompressedOops, "must be on to call this method");
1185 
1186   Assembler::z_clfi(oop1, oop2);
1187 }
1188 
1189 // Compare narrow oop in reg with narrow oop constant, no decompression.
1190 void MacroAssembler::compare_immediate_narrow_klass(Register klass1, Klass* klass2) {
1191   assert(UseCompressedClassPointers, "must be on to call this method");
1192   narrowKlass encoded_k = CompressedKlassPointers::encode(klass2);
1193 
1194   Assembler::z_clfi(klass1, encoded_k);
1195 }
1196 
1197 //----------------------------------------------------------
1198 //  Check which kind of load_constant we have here.
1199 //----------------------------------------------------------
1200 
1201 // Detection of CPU version dependent load_const sequence.
1202 // The detection is valid only for code sequences generated by load_const,
1203 // not load_const_optimized.
1204 bool MacroAssembler::is_load_const(address a) {
1205   unsigned long inst1, inst2;
1206   unsigned int  len1,  len2;
1207 
1208   len1 = get_instruction(a, &inst1);
1209   len2 = get_instruction(a + len1, &inst2);
1210 
1211   return is_z_iihf(inst1) && is_z_iilf(inst2);
1212 }


1268   assert(is_compare_immediate32(pos), "not a compressed ptr compare");
1269 
1270   set_imm32(pos, np);
1271   return 6;
1272 }
1273 
1274 // Patching the immediate value of CPU version dependent load_narrow_oop sequence.
1275 // The passed ptr must NOT be in compressed format!
1276 int MacroAssembler::patch_load_narrow_oop(address pos, oop o) {
1277   assert(UseCompressedOops, "Can only patch compressed oops");
1278 
1279   narrowOop no = CompressedOops::encode(o);
1280   return patch_load_const_32to64(pos, no);
1281 }
1282 
1283 // Patching the immediate value of CPU version dependent load_narrow_klass sequence.
1284 // The passed ptr must NOT be in compressed format!
1285 int MacroAssembler::patch_load_narrow_klass(address pos, Klass* k) {
1286   assert(UseCompressedClassPointers, "Can only patch compressed klass pointers");
1287 
1288   narrowKlass nk = CompressedKlassPointers::encode(k);
1289   return patch_load_const_32to64(pos, nk);
1290 }
1291 
1292 // Patching the immediate value of CPU version dependent compare_immediate_narrow_oop sequence.
1293 // The passed ptr must NOT be in compressed format!
1294 int MacroAssembler::patch_compare_immediate_narrow_oop(address pos, oop o) {
1295   assert(UseCompressedOops, "Can only patch compressed oops");
1296 
1297   narrowOop no = CompressedOops::encode(o);
1298   return patch_compare_immediate_32(pos, no);
1299 }
1300 
1301 // Patching the immediate value of CPU version dependent compare_immediate_narrow_klass sequence.
1302 // The passed ptr must NOT be in compressed format!
1303 int MacroAssembler::patch_compare_immediate_narrow_klass(address pos, Klass* k) {
1304   assert(UseCompressedClassPointers, "Can only patch compressed klass pointers");
1305 
1306   narrowKlass nk = CompressedKlassPointers::encode(k);
1307   return patch_compare_immediate_32(pos, nk);
1308 }
1309 
1310 //------------------------------------------------------------------------
1311 //  Extract the constant from a load_constant instruction stream.
1312 //------------------------------------------------------------------------
1313 
1314 // Get constant from a load_const sequence.
1315 long MacroAssembler::get_const(address a) {
1316   assert(is_load_const(a), "not a load of a constant");
1317   unsigned long x;
1318   x =  (((unsigned long) (get_imm32(a,0) & 0xffffffff)) << 32);
1319   x |= (((unsigned long) (get_imm32(a,1) & 0xffffffff)));
1320   return (long) x;
1321 }
1322 
1323 //--------------------------------------
1324 //  Store a constant in memory.
1325 //--------------------------------------
1326 


3589     bind(ok);
3590   } else {
3591     if (needs_explicit_null_check((intptr_t)offset)) {
3592       // Provoke OS NULL exception if reg = NULL by
3593       // accessing M[reg] w/o changing any registers.
3594       z_lg(tmp, 0, reg);
3595     }
3596     // else
3597       // Nothing to do, (later) access of M[reg + offset]
3598       // will provoke OS NULL exception if reg = NULL.
3599   }
3600 }
3601 
3602 //-------------------------------------
3603 //  Compressed Klass Pointers
3604 //-------------------------------------
3605 
3606 // Klass oop manipulations if compressed.
3607 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3608   Register current = (src != noreg) ? src : dst; // Klass is in dst if no src provided. (dst == src) also possible.
3609   address  base    = CompressedKlassPointers::base();
3610   int      shift   = CompressedKlassPointers::shift();
3611   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3612 
3613   BLOCK_COMMENT("cKlass encoder {");
3614 
3615 #ifdef ASSERT
3616   Label ok;
3617   z_tmll(current, KlassAlignmentInBytes-1); // Check alignment.
3618   z_brc(Assembler::bcondAllZero, ok);
3619   // The plain disassembler does not recognize illtrap. It instead displays
3620   // a 32-bit value. Issueing two illtraps assures the disassembler finds
3621   // the proper beginning of the next instruction.
3622   z_illtrap(0xee);
3623   z_illtrap(0xee);
3624   bind(ok);
3625 #endif
3626 
3627   if (base != NULL) {
3628     unsigned int base_h = ((unsigned long)base)>>32;
3629     unsigned int base_l = (unsigned int)((unsigned long)base);
3630     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {


3638       lgr_if_needed(dst, current);
3639       z_sgr(dst, Z_R0);
3640     }
3641     current = dst;
3642   }
3643   if (shift != 0) {
3644     assert (LogKlassAlignmentInBytes == shift, "decode alg wrong");
3645     z_srlg(dst, current, shift);
3646     current = dst;
3647   }
3648   lgr_if_needed(dst, current); // Move may be required (if neither base nor shift != 0).
3649 
3650   BLOCK_COMMENT("} cKlass encoder");
3651 }
3652 
3653 // This function calculates the size of the code generated by
3654 //   decode_klass_not_null(register dst, Register src)
3655 // when (Universe::heap() != NULL). Hence, if the instructions
3656 // it generates change, then this method needs to be updated.
3657 int MacroAssembler::instr_size_for_decode_klass_not_null() {
3658   address  base    = CompressedKlassPointers::base();
3659   int shift_size   = CompressedKlassPointers::shift() == 0 ? 0 : 6; /* sllg */
3660   int addbase_size = 0;
3661   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3662 
3663   if (base != NULL) {
3664     unsigned int base_h = ((unsigned long)base)>>32;
3665     unsigned int base_l = (unsigned int)((unsigned long)base);
3666     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3667       addbase_size += 6; /* aih */
3668     } else if ((base_h == 0) && (base_l != 0)) {
3669       addbase_size += 6; /* algfi */
3670     } else {
3671       addbase_size += load_const_size();
3672       addbase_size += 4; /* algr */
3673     }
3674   }
3675 #ifdef ASSERT
3676   addbase_size += 10;
3677   addbase_size += 2; // Extra sigill.
3678 #endif
3679   return addbase_size + shift_size;
3680 }
3681 
3682 // !!! If the instructions that get generated here change
3683 //     then function instr_size_for_decode_klass_not_null()
3684 //     needs to get updated.
3685 // This variant of decode_klass_not_null() must generate predictable code!
3686 // The code must only depend on globally known parameters.
3687 void MacroAssembler::decode_klass_not_null(Register dst) {
3688   address  base    = CompressedKlassPointers::base();
3689   int      shift   = CompressedKlassPointers::shift();
3690   int      beg_off = offset();
3691   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3692 
3693   BLOCK_COMMENT("cKlass decoder (const size) {");
3694 
3695   if (shift != 0) { // Shift required?
3696     z_sllg(dst, dst, shift);
3697   }
3698   if (base != NULL) {
3699     unsigned int base_h = ((unsigned long)base)>>32;
3700     unsigned int base_l = (unsigned int)((unsigned long)base);
3701     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3702       z_aih(dst, base_h);     // Base has no set bits in lower half.
3703     } else if ((base_h == 0) && (base_l != 0)) {
3704       z_algfi(dst, base_l);   // Base has no set bits in upper half.
3705     } else {
3706       load_const(Z_R0, base); // Base has set bits everywhere.
3707       z_algr(dst, Z_R0);
3708     }
3709   }


3711 #ifdef ASSERT
3712   Label ok;
3713   z_tmll(dst, KlassAlignmentInBytes-1); // Check alignment.
3714   z_brc(Assembler::bcondAllZero, ok);
3715   // The plain disassembler does not recognize illtrap. It instead displays
3716   // a 32-bit value. Issueing two illtraps assures the disassembler finds
3717   // the proper beginning of the next instruction.
3718   z_illtrap(0xd1);
3719   z_illtrap(0xd1);
3720   bind(ok);
3721 #endif
3722   assert(offset() == beg_off + instr_size_for_decode_klass_not_null(), "Code gen mismatch.");
3723 
3724   BLOCK_COMMENT("} cKlass decoder (const size)");
3725 }
3726 
3727 // This variant of decode_klass_not_null() is for cases where
3728 //  1) the size of the generated instructions may vary
3729 //  2) the result is (potentially) stored in a register different from the source.
3730 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3731   address base  = CompressedKlassPointers::base();
3732   int     shift = CompressedKlassPointers::shift();
3733   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3734 
3735   BLOCK_COMMENT("cKlass decoder {");
3736 
3737   if (src == noreg) src = dst;
3738 
3739   if (shift != 0) { // Shift or at least move required?
3740     z_sllg(dst, src, shift);
3741   } else {
3742     lgr_if_needed(dst, src);
3743   }
3744 
3745   if (base != NULL) {
3746     unsigned int base_h = ((unsigned long)base)>>32;
3747     unsigned int base_l = (unsigned int)((unsigned long)base);
3748     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3749       z_aih(dst, base_h);     // Base has not set bits in lower half.
3750     } else if ((base_h == 0) && (base_l != 0)) {
3751       z_algfi(dst, base_l);   // Base has no set bits in upper half.
3752     } else {


3812     // Support s = noreg.
3813     if (s != noreg) {
3814       z_st(s, Address(d, oopDesc::klass_gap_offset_in_bytes()));
3815     } else {
3816       z_mvhi(Address(d, oopDesc::klass_gap_offset_in_bytes()), 0);
3817     }
3818   }
3819 }
3820 
3821 // Compare klass ptr in memory against klass ptr in register.
3822 //
3823 // Rop1            - klass in register, always uncompressed.
3824 // disp            - Offset of klass in memory, compressed/uncompressed, depending on runtime flag.
3825 // Rbase           - Base address of cKlass in memory.
3826 // maybeNULL       - True if Rop1 possibly is a NULL.
3827 void MacroAssembler::compare_klass_ptr(Register Rop1, int64_t disp, Register Rbase, bool maybeNULL) {
3828 
3829   BLOCK_COMMENT("compare klass ptr {");
3830 
3831   if (UseCompressedClassPointers) {
3832     const int shift = CompressedKlassPointers::shift();
3833     address   base  = CompressedKlassPointers::base();
3834 
3835     assert((shift == 0) || (shift == LogKlassAlignmentInBytes), "cKlass encoder detected bad shift");
3836     assert_different_registers(Rop1, Z_R0);
3837     assert_different_registers(Rop1, Rbase, Z_R1);
3838 
3839     // First encode register oop and then compare with cOop in memory.
3840     // This sequence saves an unnecessary cOop load and decode.
3841     if (base == NULL) {
3842       if (shift == 0) {
3843         z_cl(Rop1, disp, Rbase);     // Unscaled
3844       } else {
3845         z_srlg(Z_R0, Rop1, shift);   // ZeroBased
3846         z_cl(Z_R0, disp, Rbase);
3847       }
3848     } else {                         // HeapBased
3849 #ifdef ASSERT
3850       bool     used_R0 = true;
3851       bool     used_R1 = true;
3852 #endif
3853       Register current = Rop1;


3946   return pow2_offset;
3947 }
3948 
3949 int MacroAssembler::get_oop_base_complement(Register Rbase, uint64_t oop_base) {
3950   int offset = get_oop_base(Rbase, oop_base);
3951   z_lcgr(Rbase, Rbase);
3952   return -offset;
3953 }
3954 
3955 // Compare compressed oop in memory against oop in register.
3956 // Rop1            - Oop in register.
3957 // disp            - Offset of cOop in memory.
3958 // Rbase           - Base address of cOop in memory.
3959 // maybeNULL       - True if Rop1 possibly is a NULL.
3960 // maybeNULLtarget - Branch target for Rop1 == NULL, if flow control shall NOT continue with compare instruction.
3961 void MacroAssembler::compare_heap_oop(Register Rop1, Address mem, bool maybeNULL) {
3962   Register Rbase  = mem.baseOrR0();
3963   Register Rindex = mem.indexOrR0();
3964   int64_t  disp   = mem.disp();
3965 
3966   const int shift = CompressedOops::shift();
3967   address   base  = CompressedOops::base();
3968 
3969   assert(UseCompressedOops, "must be on to call this method");
3970   assert(Universe::heap() != NULL, "java heap must be initialized to call this method");
3971   assert((shift == 0) || (shift == LogMinObjAlignmentInBytes), "cOop encoder detected bad shift");
3972   assert_different_registers(Rop1, Z_R0);
3973   assert_different_registers(Rop1, Rbase, Z_R1);
3974   assert_different_registers(Rop1, Rindex, Z_R1);
3975 
3976   BLOCK_COMMENT("compare heap oop {");
3977 
3978   // First encode register oop and then compare with cOop in memory.
3979   // This sequence saves an unnecessary cOop load and decode.
3980   if (base == NULL) {
3981     if (shift == 0) {
3982       z_cl(Rop1, disp, Rindex, Rbase);  // Unscaled
3983     } else {
3984       z_srlg(Z_R0, Rop1, shift);        // ZeroBased
3985       z_cl(Z_R0, disp, Rindex, Rbase);
3986     }
3987   } else {                              // HeapBased


4058                                     Register tmp1, Register tmp2, Register tmp3,
4059                                     DecoratorSet decorators) {
4060   access_store_at(T_OBJECT, IN_HEAP | decorators, a, Roop, tmp1, tmp2, tmp3);
4061 }
4062 
4063 //-------------------------------------------------
4064 // Encode compressed oop. Generally usable encoder.
4065 //-------------------------------------------------
4066 // Rsrc - contains regular oop on entry. It remains unchanged.
4067 // Rdst - contains compressed oop on exit.
4068 // Rdst and Rsrc may indicate same register, in which case Rsrc does not remain unchanged.
4069 //
4070 // Rdst must not indicate scratch register Z_R1 (Z_R1_scratch) for functionality.
4071 // Rdst should not indicate scratch register Z_R0 (Z_R0_scratch) for performance.
4072 //
4073 // only32bitValid is set, if later code only uses the lower 32 bits. In this
4074 // case we must not fix the upper 32 bits.
4075 void MacroAssembler::oop_encoder(Register Rdst, Register Rsrc, bool maybeNULL,
4076                                  Register Rbase, int pow2_offset, bool only32bitValid) {
4077 
4078   const address oop_base  = CompressedOops::base();
4079   const int     oop_shift = CompressedOops::shift();
4080   const bool    disjoint  = CompressedOops::base_disjoint();
4081 
4082   assert(UseCompressedOops, "must be on to call this method");
4083   assert(Universe::heap() != NULL, "java heap must be initialized to call this encoder");
4084   assert((oop_shift == 0) || (oop_shift == LogMinObjAlignmentInBytes), "cOop encoder detected bad shift");
4085 
4086   if (disjoint || (oop_base == NULL)) {
4087     BLOCK_COMMENT("cOop encoder zeroBase {");
4088     if (oop_shift == 0) {
4089       if (oop_base != NULL && !only32bitValid) {
4090         z_llgfr(Rdst, Rsrc); // Clear upper bits in case the register will be decoded again.
4091       } else {
4092         lgr_if_needed(Rdst, Rsrc);
4093       }
4094     } else {
4095       z_srlg(Rdst, Rsrc, oop_shift);
4096       if (oop_base != NULL && !only32bitValid) {
4097         z_llgfr(Rdst, Rdst); // Clear upper bits in case the register will be decoded again.
4098       }
4099     }
4100     BLOCK_COMMENT("} cOop encoder zeroBase");


4193 #endif
4194   BLOCK_COMMENT("} cOop encoder general");
4195 }
4196 
4197 //-------------------------------------------------
4198 // decode compressed oop. Generally usable decoder.
4199 //-------------------------------------------------
4200 // Rsrc - contains compressed oop on entry.
4201 // Rdst - contains regular oop on exit.
4202 // Rdst and Rsrc may indicate same register.
4203 // Rdst must not be the same register as Rbase, if Rbase was preloaded (before call).
4204 // Rdst can be the same register as Rbase. Then, either Z_R0 or Z_R1 must be available as scratch.
4205 // Rbase - register to use for the base
4206 // pow2_offset - offset of base to nice value. If -1, base must be loaded.
4207 // For performance, it is good to
4208 //  - avoid Z_R0 for any of the argument registers.
4209 //  - keep Rdst and Rsrc distinct from Rbase. Rdst == Rsrc is ok for performance.
4210 //  - avoid Z_R1 for Rdst if Rdst == Rbase.
4211 void MacroAssembler::oop_decoder(Register Rdst, Register Rsrc, bool maybeNULL, Register Rbase, int pow2_offset) {
4212 
4213   const address oop_base  = CompressedOops::base();
4214   const int     oop_shift = CompressedOops::shift();
4215   const bool    disjoint  = CompressedOops::base_disjoint();
4216 
4217   assert(UseCompressedOops, "must be on to call this method");
4218   assert(Universe::heap() != NULL, "java heap must be initialized to call this decoder");
4219   assert((oop_shift == 0) || (oop_shift == LogMinObjAlignmentInBytes),
4220          "cOop encoder detected bad shift");
4221 
4222   // cOops are always loaded zero-extended from memory. No explicit zero-extension necessary.
4223 
4224   if (oop_base != NULL) {
4225     unsigned int oop_base_hl = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 32)) & 0xffff;
4226     unsigned int oop_base_hh = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 48)) & 0xffff;
4227     unsigned int oop_base_hf = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 32)) & 0xFFFFffff;
4228     if (disjoint && (oop_base_hl == 0 || oop_base_hh == 0)) {
4229       BLOCK_COMMENT("cOop decoder disjointBase {");
4230       // We do not need to load the base. Instead, we can install the upper bits
4231       // with an OR instead of an ADD.
4232       Label done;
4233 
4234       // Rsrc contains a narrow oop. Thus we are sure the leftmost <oop_shift> bits will never be set.
4235       if (maybeNULL) {  // NULL ptr must be preserved!


4338   // OopHandle::resolve is an indirection.
4339   z_lg(result, 0, result);
4340 }
4341 
4342 void MacroAssembler::load_mirror(Register mirror, Register method) {
4343   mem2reg_opt(mirror, Address(method, Method::const_offset()));
4344   mem2reg_opt(mirror, Address(mirror, ConstMethod::constants_offset()));
4345   mem2reg_opt(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
4346   mem2reg_opt(mirror, Address(mirror, Klass::java_mirror_offset()));
4347   resolve_oop_handle(mirror);
4348 }
4349 
4350 //---------------------------------------------------------------
4351 //---  Operations on arrays.
4352 //---------------------------------------------------------------
4353 
4354 // Compiler ensures base is doubleword aligned and cnt is #doublewords.
4355 // Emitter does not KILL cnt and base arguments, since they need to be copied to
4356 // work registers anyway.
4357 // Actually, only r0, r1, and r5 are killed.
4358 unsigned int MacroAssembler::Clear_Array(Register cnt_arg, Register base_pointer_arg, Register odd_tmp_reg) {


4359 
4360   int      block_start = offset();

4361   Register dst_len  = Z_R1;    // Holds dst len  for MVCLE.
4362   Register dst_addr = Z_R0;    // Holds dst addr for MVCLE.
4363 
4364   Label doXC, doMVCLE, done;
4365 
4366   BLOCK_COMMENT("Clear_Array {");
4367 
4368   // Check for zero len and convert to long.
4369   z_ltgfr(odd_tmp_reg, cnt_arg);
4370   z_bre(done);                    // Nothing to do if len == 0.
4371 
4372   // Prefetch data to be cleared.
4373   if (VM_Version::has_Prefetch()) {
4374     z_pfd(0x02,   0, Z_R0, base_pointer_arg);
4375     z_pfd(0x02, 256, Z_R0, base_pointer_arg);
4376   }
4377 
4378   z_sllg(dst_len, odd_tmp_reg, 3); // #bytes to clear.
4379   z_cghi(odd_tmp_reg, 32);         // Check for len <= 256 bytes (<=32 DW).
4380   z_brnh(doXC);                    // If so, use executed XC to clear.
4381 
4382   // MVCLE: initialize long arrays (general case).
4383   bind(doMVCLE);
4384   z_lgr(dst_addr, base_pointer_arg);
4385   // Pass 0 as source length to MVCLE: destination will be filled with padding byte 0.
4386   // The even register of the register pair is not killed.
4387   clear_reg(odd_tmp_reg, true, false);
4388   MacroAssembler::move_long_ext(dst_addr, as_Register(odd_tmp_reg->encoding()-1), 0);
4389   z_bru(done);
4390 
4391   // XC: initialize short arrays.
4392   Label XC_template; // Instr template, never exec directly!
4393     bind(XC_template);
4394     z_xc(0,0,base_pointer_arg,0,base_pointer_arg);
4395 
4396   bind(doXC);
4397     add2reg(dst_len, -1);               // Get #bytes-1 for EXECUTE.
4398     if (VM_Version::has_ExecuteExtensions()) {
4399       z_exrl(dst_len, XC_template);     // Execute XC with var. len.
4400     } else {
4401       z_larl(odd_tmp_reg, XC_template);
4402       z_ex(dst_len,0,Z_R0,odd_tmp_reg); // Execute XC with var. len.
4403     }
4404     // z_bru(done);      // fallthru
4405 
4406   bind(done);
4407 
4408   BLOCK_COMMENT("} Clear_Array");
4409 
4410   int block_end = offset();
4411   return block_end - block_start;
4412 }
4413 
4414 // Compiler ensures base is doubleword aligned and cnt is count of doublewords.
4415 // Emitter does not KILL any arguments nor work registers.
4416 // Emitter generates up to 16 XC instructions, depending on the array length.
4417 unsigned int MacroAssembler::Clear_Array_Const(long cnt, Register base) {
4418   int  block_start    = offset();
4419   int  off;
4420   int  lineSize_Bytes = AllocatePrefetchStepSize;
4421   int  lineSize_DW    = AllocatePrefetchStepSize>>LogBytesPerWord;
4422   bool doPrefetch     = VM_Version::has_Prefetch();


4444       z_xc(off*XC_maxlen, XC_maxlen-1, base, off*XC_maxlen, base);
4445 
4446       // Prefetch some cache lines in advance.
4447       if (doPrefetch && (off <= numXCInstr-AllocatePrefetchLines)) {
4448         z_pfd(0x02, (off+AllocatePrefetchLines)*lineSize_Bytes, Z_R0, base);
4449       }
4450     }
4451     if (off*XC_maxlen < cnt*BytesPerWord) {
4452       z_xc(off*XC_maxlen, (cnt*BytesPerWord-off*XC_maxlen)-1, base, off*XC_maxlen, base);
4453     }
4454   }
4455   BLOCK_COMMENT("} Clear_Array_Const");
4456 
4457   int block_end = offset();
4458   return block_end - block_start;
4459 }
4460 
4461 // Compiler ensures base is doubleword aligned and cnt is #doublewords.
4462 // Emitter does not KILL cnt and base arguments, since they need to be copied to
4463 // work registers anyway.
4464 // Actually, only r0, r1, (which are work registers) and odd_tmp_reg are killed.
4465 //
4466 // For very large arrays, exploit MVCLE H/W support.
4467 // MVCLE instruction automatically exploits H/W-optimized page mover.
4468 // - Bytes up to next page boundary are cleared with a series of XC to self.
4469 // - All full pages are cleared with the page mover H/W assist.
4470 // - Remaining bytes are again cleared by a series of XC to self.
4471 //
4472 unsigned int MacroAssembler::Clear_Array_Const_Big(long cnt, Register base_pointer_arg, Register odd_tmp_reg) {


4473 
4474   int      block_start = offset();
4475   Register dst_len  = Z_R1;      // Holds dst len  for MVCLE.
4476   Register dst_addr = Z_R0;      // Holds dst addr for MVCLE.
4477 
4478   BLOCK_COMMENT("Clear_Array_Const_Big {");
4479 
4480   // Get len to clear.
4481   load_const_optimized(dst_len, (long)cnt*8L);  // in Bytes = #DW*8
4482 
4483   // Prepare other args to MVCLE.
4484   z_lgr(dst_addr, base_pointer_arg);
4485   // Pass 0 as source length to MVCLE: destination will be filled with padding byte 0.
4486   // The even register of the register pair is not killed.
4487   (void) clear_reg(odd_tmp_reg, true, false);  // Src len of MVCLE is zero.
4488   MacroAssembler::move_long_ext(dst_addr, as_Register(odd_tmp_reg->encoding() - 1), 0);

4489   BLOCK_COMMENT("} Clear_Array_Const_Big");
4490 
4491   int block_end = offset();
4492   return block_end - block_start;
4493 }
4494 
4495 // Allocator.
4496 unsigned int MacroAssembler::CopyRawMemory_AlignedDisjoint(Register src_reg, Register dst_reg,
4497                                                            Register cnt_reg,
4498                                                            Register tmp1_reg, Register tmp2_reg) {
4499   // Tmp1 is oddReg.
4500   // Tmp2 is evenReg.
4501 
4502   int block_start = offset();
4503   Label doMVC, doMVCLE, done, MVC_template;
4504 
4505   BLOCK_COMMENT("CopyRawMemory_AlignedDisjoint {");
4506 
4507   // Check for zero len and convert to long.
4508   z_ltgfr(cnt_reg, cnt_reg);      // Remember casted value for doSTG case.




1154 }
1155 
1156 // Load a 32bit constant into a 64bit register, sign-extend or zero-extend.
1157 // Patchable code sequence, but not atomically patchable.
1158 // Make sure to keep code size constant -> no value-dependent optimizations.
1159 // Do not kill condition code.
1160 void MacroAssembler::load_const_32to64(Register t, int64_t x, bool sign_extend) {
1161   if (sign_extend) { Assembler::z_lgfi(t, x); }
1162   else             { Assembler::z_llilf(t, x); }
1163 }
1164 
1165 // Load narrow oop constant, no decompression.
1166 void MacroAssembler::load_narrow_oop(Register t, narrowOop a) {
1167   assert(UseCompressedOops, "must be on to call this method");
1168   load_const_32to64(t, a, false /*sign_extend*/);
1169 }
1170 
1171 // Load narrow klass constant, compression required.
1172 void MacroAssembler::load_narrow_klass(Register t, Klass* k) {
1173   assert(UseCompressedClassPointers, "must be on to call this method");
1174   narrowKlass encoded_k = Klass::encode_klass(k);
1175   load_const_32to64(t, encoded_k, false /*sign_extend*/);
1176 }
1177 
1178 //------------------------------------------------------
1179 //  Compare (patchable) constant with register.
1180 //------------------------------------------------------
1181 
1182 // Compare narrow oop in reg with narrow oop constant, no decompression.
1183 void MacroAssembler::compare_immediate_narrow_oop(Register oop1, narrowOop oop2) {
1184   assert(UseCompressedOops, "must be on to call this method");
1185 
1186   Assembler::z_clfi(oop1, oop2);
1187 }
1188 
1189 // Compare narrow oop in reg with narrow oop constant, no decompression.
1190 void MacroAssembler::compare_immediate_narrow_klass(Register klass1, Klass* klass2) {
1191   assert(UseCompressedClassPointers, "must be on to call this method");
1192   narrowKlass encoded_k = Klass::encode_klass(klass2);
1193 
1194   Assembler::z_clfi(klass1, encoded_k);
1195 }
1196 
1197 //----------------------------------------------------------
1198 //  Check which kind of load_constant we have here.
1199 //----------------------------------------------------------
1200 
1201 // Detection of CPU version dependent load_const sequence.
1202 // The detection is valid only for code sequences generated by load_const,
1203 // not load_const_optimized.
1204 bool MacroAssembler::is_load_const(address a) {
1205   unsigned long inst1, inst2;
1206   unsigned int  len1,  len2;
1207 
1208   len1 = get_instruction(a, &inst1);
1209   len2 = get_instruction(a + len1, &inst2);
1210 
1211   return is_z_iihf(inst1) && is_z_iilf(inst2);
1212 }


1268   assert(is_compare_immediate32(pos), "not a compressed ptr compare");
1269 
1270   set_imm32(pos, np);
1271   return 6;
1272 }
1273 
1274 // Patching the immediate value of CPU version dependent load_narrow_oop sequence.
1275 // The passed ptr must NOT be in compressed format!
1276 int MacroAssembler::patch_load_narrow_oop(address pos, oop o) {
1277   assert(UseCompressedOops, "Can only patch compressed oops");
1278 
1279   narrowOop no = CompressedOops::encode(o);
1280   return patch_load_const_32to64(pos, no);
1281 }
1282 
1283 // Patching the immediate value of CPU version dependent load_narrow_klass sequence.
1284 // The passed ptr must NOT be in compressed format!
1285 int MacroAssembler::patch_load_narrow_klass(address pos, Klass* k) {
1286   assert(UseCompressedClassPointers, "Can only patch compressed klass pointers");
1287 
1288   narrowKlass nk = Klass::encode_klass(k);
1289   return patch_load_const_32to64(pos, nk);
1290 }
1291 
1292 // Patching the immediate value of CPU version dependent compare_immediate_narrow_oop sequence.
1293 // The passed ptr must NOT be in compressed format!
1294 int MacroAssembler::patch_compare_immediate_narrow_oop(address pos, oop o) {
1295   assert(UseCompressedOops, "Can only patch compressed oops");
1296 
1297   narrowOop no = CompressedOops::encode(o);
1298   return patch_compare_immediate_32(pos, no);
1299 }
1300 
1301 // Patching the immediate value of CPU version dependent compare_immediate_narrow_klass sequence.
1302 // The passed ptr must NOT be in compressed format!
1303 int MacroAssembler::patch_compare_immediate_narrow_klass(address pos, Klass* k) {
1304   assert(UseCompressedClassPointers, "Can only patch compressed klass pointers");
1305 
1306   narrowKlass nk = Klass::encode_klass(k);
1307   return patch_compare_immediate_32(pos, nk);
1308 }
1309 
1310 //------------------------------------------------------------------------
1311 //  Extract the constant from a load_constant instruction stream.
1312 //------------------------------------------------------------------------
1313 
1314 // Get constant from a load_const sequence.
1315 long MacroAssembler::get_const(address a) {
1316   assert(is_load_const(a), "not a load of a constant");
1317   unsigned long x;
1318   x =  (((unsigned long) (get_imm32(a,0) & 0xffffffff)) << 32);
1319   x |= (((unsigned long) (get_imm32(a,1) & 0xffffffff)));
1320   return (long) x;
1321 }
1322 
1323 //--------------------------------------
1324 //  Store a constant in memory.
1325 //--------------------------------------
1326 


3589     bind(ok);
3590   } else {
3591     if (needs_explicit_null_check((intptr_t)offset)) {
3592       // Provoke OS NULL exception if reg = NULL by
3593       // accessing M[reg] w/o changing any registers.
3594       z_lg(tmp, 0, reg);
3595     }
3596     // else
3597       // Nothing to do, (later) access of M[reg + offset]
3598       // will provoke OS NULL exception if reg = NULL.
3599   }
3600 }
3601 
3602 //-------------------------------------
3603 //  Compressed Klass Pointers
3604 //-------------------------------------
3605 
3606 // Klass oop manipulations if compressed.
3607 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3608   Register current = (src != noreg) ? src : dst; // Klass is in dst if no src provided. (dst == src) also possible.
3609   address  base    = Universe::narrow_klass_base();
3610   int      shift   = Universe::narrow_klass_shift();
3611   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3612 
3613   BLOCK_COMMENT("cKlass encoder {");
3614 
3615 #ifdef ASSERT
3616   Label ok;
3617   z_tmll(current, KlassAlignmentInBytes-1); // Check alignment.
3618   z_brc(Assembler::bcondAllZero, ok);
3619   // The plain disassembler does not recognize illtrap. It instead displays
3620   // a 32-bit value. Issueing two illtraps assures the disassembler finds
3621   // the proper beginning of the next instruction.
3622   z_illtrap(0xee);
3623   z_illtrap(0xee);
3624   bind(ok);
3625 #endif
3626 
3627   if (base != NULL) {
3628     unsigned int base_h = ((unsigned long)base)>>32;
3629     unsigned int base_l = (unsigned int)((unsigned long)base);
3630     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {


3638       lgr_if_needed(dst, current);
3639       z_sgr(dst, Z_R0);
3640     }
3641     current = dst;
3642   }
3643   if (shift != 0) {
3644     assert (LogKlassAlignmentInBytes == shift, "decode alg wrong");
3645     z_srlg(dst, current, shift);
3646     current = dst;
3647   }
3648   lgr_if_needed(dst, current); // Move may be required (if neither base nor shift != 0).
3649 
3650   BLOCK_COMMENT("} cKlass encoder");
3651 }
3652 
3653 // This function calculates the size of the code generated by
3654 //   decode_klass_not_null(register dst, Register src)
3655 // when (Universe::heap() != NULL). Hence, if the instructions
3656 // it generates change, then this method needs to be updated.
3657 int MacroAssembler::instr_size_for_decode_klass_not_null() {
3658   address  base    = Universe::narrow_klass_base();
3659   int shift_size   = Universe::narrow_klass_shift() == 0 ? 0 : 6; /* sllg */
3660   int addbase_size = 0;
3661   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3662 
3663   if (base != NULL) {
3664     unsigned int base_h = ((unsigned long)base)>>32;
3665     unsigned int base_l = (unsigned int)((unsigned long)base);
3666     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3667       addbase_size += 6; /* aih */
3668     } else if ((base_h == 0) && (base_l != 0)) {
3669       addbase_size += 6; /* algfi */
3670     } else {
3671       addbase_size += load_const_size();
3672       addbase_size += 4; /* algr */
3673     }
3674   }
3675 #ifdef ASSERT
3676   addbase_size += 10;
3677   addbase_size += 2; // Extra sigill.
3678 #endif
3679   return addbase_size + shift_size;
3680 }
3681 
3682 // !!! If the instructions that get generated here change
3683 //     then function instr_size_for_decode_klass_not_null()
3684 //     needs to get updated.
3685 // This variant of decode_klass_not_null() must generate predictable code!
3686 // The code must only depend on globally known parameters.
3687 void MacroAssembler::decode_klass_not_null(Register dst) {
3688   address  base    = Universe::narrow_klass_base();
3689   int      shift   = Universe::narrow_klass_shift();
3690   int      beg_off = offset();
3691   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3692 
3693   BLOCK_COMMENT("cKlass decoder (const size) {");
3694 
3695   if (shift != 0) { // Shift required?
3696     z_sllg(dst, dst, shift);
3697   }
3698   if (base != NULL) {
3699     unsigned int base_h = ((unsigned long)base)>>32;
3700     unsigned int base_l = (unsigned int)((unsigned long)base);
3701     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3702       z_aih(dst, base_h);     // Base has no set bits in lower half.
3703     } else if ((base_h == 0) && (base_l != 0)) {
3704       z_algfi(dst, base_l);   // Base has no set bits in upper half.
3705     } else {
3706       load_const(Z_R0, base); // Base has set bits everywhere.
3707       z_algr(dst, Z_R0);
3708     }
3709   }


3711 #ifdef ASSERT
3712   Label ok;
3713   z_tmll(dst, KlassAlignmentInBytes-1); // Check alignment.
3714   z_brc(Assembler::bcondAllZero, ok);
3715   // The plain disassembler does not recognize illtrap. It instead displays
3716   // a 32-bit value. Issueing two illtraps assures the disassembler finds
3717   // the proper beginning of the next instruction.
3718   z_illtrap(0xd1);
3719   z_illtrap(0xd1);
3720   bind(ok);
3721 #endif
3722   assert(offset() == beg_off + instr_size_for_decode_klass_not_null(), "Code gen mismatch.");
3723 
3724   BLOCK_COMMENT("} cKlass decoder (const size)");
3725 }
3726 
3727 // This variant of decode_klass_not_null() is for cases where
3728 //  1) the size of the generated instructions may vary
3729 //  2) the result is (potentially) stored in a register different from the source.
3730 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3731   address base  = Universe::narrow_klass_base();
3732   int     shift = Universe::narrow_klass_shift();
3733   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3734 
3735   BLOCK_COMMENT("cKlass decoder {");
3736 
3737   if (src == noreg) src = dst;
3738 
3739   if (shift != 0) { // Shift or at least move required?
3740     z_sllg(dst, src, shift);
3741   } else {
3742     lgr_if_needed(dst, src);
3743   }
3744 
3745   if (base != NULL) {
3746     unsigned int base_h = ((unsigned long)base)>>32;
3747     unsigned int base_l = (unsigned int)((unsigned long)base);
3748     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3749       z_aih(dst, base_h);     // Base has not set bits in lower half.
3750     } else if ((base_h == 0) && (base_l != 0)) {
3751       z_algfi(dst, base_l);   // Base has no set bits in upper half.
3752     } else {


3812     // Support s = noreg.
3813     if (s != noreg) {
3814       z_st(s, Address(d, oopDesc::klass_gap_offset_in_bytes()));
3815     } else {
3816       z_mvhi(Address(d, oopDesc::klass_gap_offset_in_bytes()), 0);
3817     }
3818   }
3819 }
3820 
3821 // Compare klass ptr in memory against klass ptr in register.
3822 //
3823 // Rop1            - klass in register, always uncompressed.
3824 // disp            - Offset of klass in memory, compressed/uncompressed, depending on runtime flag.
3825 // Rbase           - Base address of cKlass in memory.
3826 // maybeNULL       - True if Rop1 possibly is a NULL.
3827 void MacroAssembler::compare_klass_ptr(Register Rop1, int64_t disp, Register Rbase, bool maybeNULL) {
3828 
3829   BLOCK_COMMENT("compare klass ptr {");
3830 
3831   if (UseCompressedClassPointers) {
3832     const int shift = Universe::narrow_klass_shift();
3833     address   base  = Universe::narrow_klass_base();
3834 
3835     assert((shift == 0) || (shift == LogKlassAlignmentInBytes), "cKlass encoder detected bad shift");
3836     assert_different_registers(Rop1, Z_R0);
3837     assert_different_registers(Rop1, Rbase, Z_R1);
3838 
3839     // First encode register oop and then compare with cOop in memory.
3840     // This sequence saves an unnecessary cOop load and decode.
3841     if (base == NULL) {
3842       if (shift == 0) {
3843         z_cl(Rop1, disp, Rbase);     // Unscaled
3844       } else {
3845         z_srlg(Z_R0, Rop1, shift);   // ZeroBased
3846         z_cl(Z_R0, disp, Rbase);
3847       }
3848     } else {                         // HeapBased
3849 #ifdef ASSERT
3850       bool     used_R0 = true;
3851       bool     used_R1 = true;
3852 #endif
3853       Register current = Rop1;


3946   return pow2_offset;
3947 }
3948 
3949 int MacroAssembler::get_oop_base_complement(Register Rbase, uint64_t oop_base) {
3950   int offset = get_oop_base(Rbase, oop_base);
3951   z_lcgr(Rbase, Rbase);
3952   return -offset;
3953 }
3954 
3955 // Compare compressed oop in memory against oop in register.
3956 // Rop1            - Oop in register.
3957 // disp            - Offset of cOop in memory.
3958 // Rbase           - Base address of cOop in memory.
3959 // maybeNULL       - True if Rop1 possibly is a NULL.
3960 // maybeNULLtarget - Branch target for Rop1 == NULL, if flow control shall NOT continue with compare instruction.
3961 void MacroAssembler::compare_heap_oop(Register Rop1, Address mem, bool maybeNULL) {
3962   Register Rbase  = mem.baseOrR0();
3963   Register Rindex = mem.indexOrR0();
3964   int64_t  disp   = mem.disp();
3965 
3966   const int shift = Universe::narrow_oop_shift();
3967   address   base  = Universe::narrow_oop_base();
3968 
3969   assert(UseCompressedOops, "must be on to call this method");
3970   assert(Universe::heap() != NULL, "java heap must be initialized to call this method");
3971   assert((shift == 0) || (shift == LogMinObjAlignmentInBytes), "cOop encoder detected bad shift");
3972   assert_different_registers(Rop1, Z_R0);
3973   assert_different_registers(Rop1, Rbase, Z_R1);
3974   assert_different_registers(Rop1, Rindex, Z_R1);
3975 
3976   BLOCK_COMMENT("compare heap oop {");
3977 
3978   // First encode register oop and then compare with cOop in memory.
3979   // This sequence saves an unnecessary cOop load and decode.
3980   if (base == NULL) {
3981     if (shift == 0) {
3982       z_cl(Rop1, disp, Rindex, Rbase);  // Unscaled
3983     } else {
3984       z_srlg(Z_R0, Rop1, shift);        // ZeroBased
3985       z_cl(Z_R0, disp, Rindex, Rbase);
3986     }
3987   } else {                              // HeapBased


4058                                     Register tmp1, Register tmp2, Register tmp3,
4059                                     DecoratorSet decorators) {
4060   access_store_at(T_OBJECT, IN_HEAP | decorators, a, Roop, tmp1, tmp2, tmp3);
4061 }
4062 
4063 //-------------------------------------------------
4064 // Encode compressed oop. Generally usable encoder.
4065 //-------------------------------------------------
4066 // Rsrc - contains regular oop on entry. It remains unchanged.
4067 // Rdst - contains compressed oop on exit.
4068 // Rdst and Rsrc may indicate same register, in which case Rsrc does not remain unchanged.
4069 //
4070 // Rdst must not indicate scratch register Z_R1 (Z_R1_scratch) for functionality.
4071 // Rdst should not indicate scratch register Z_R0 (Z_R0_scratch) for performance.
4072 //
4073 // only32bitValid is set, if later code only uses the lower 32 bits. In this
4074 // case we must not fix the upper 32 bits.
4075 void MacroAssembler::oop_encoder(Register Rdst, Register Rsrc, bool maybeNULL,
4076                                  Register Rbase, int pow2_offset, bool only32bitValid) {
4077 
4078   const address oop_base  = Universe::narrow_oop_base();
4079   const int     oop_shift = Universe::narrow_oop_shift();
4080   const bool    disjoint  = Universe::narrow_oop_base_disjoint();
4081 
4082   assert(UseCompressedOops, "must be on to call this method");
4083   assert(Universe::heap() != NULL, "java heap must be initialized to call this encoder");
4084   assert((oop_shift == 0) || (oop_shift == LogMinObjAlignmentInBytes), "cOop encoder detected bad shift");
4085 
4086   if (disjoint || (oop_base == NULL)) {
4087     BLOCK_COMMENT("cOop encoder zeroBase {");
4088     if (oop_shift == 0) {
4089       if (oop_base != NULL && !only32bitValid) {
4090         z_llgfr(Rdst, Rsrc); // Clear upper bits in case the register will be decoded again.
4091       } else {
4092         lgr_if_needed(Rdst, Rsrc);
4093       }
4094     } else {
4095       z_srlg(Rdst, Rsrc, oop_shift);
4096       if (oop_base != NULL && !only32bitValid) {
4097         z_llgfr(Rdst, Rdst); // Clear upper bits in case the register will be decoded again.
4098       }
4099     }
4100     BLOCK_COMMENT("} cOop encoder zeroBase");


4193 #endif
4194   BLOCK_COMMENT("} cOop encoder general");
4195 }
4196 
4197 //-------------------------------------------------
4198 // decode compressed oop. Generally usable decoder.
4199 //-------------------------------------------------
4200 // Rsrc - contains compressed oop on entry.
4201 // Rdst - contains regular oop on exit.
4202 // Rdst and Rsrc may indicate same register.
4203 // Rdst must not be the same register as Rbase, if Rbase was preloaded (before call).
4204 // Rdst can be the same register as Rbase. Then, either Z_R0 or Z_R1 must be available as scratch.
4205 // Rbase - register to use for the base
4206 // pow2_offset - offset of base to nice value. If -1, base must be loaded.
4207 // For performance, it is good to
4208 //  - avoid Z_R0 for any of the argument registers.
4209 //  - keep Rdst and Rsrc distinct from Rbase. Rdst == Rsrc is ok for performance.
4210 //  - avoid Z_R1 for Rdst if Rdst == Rbase.
4211 void MacroAssembler::oop_decoder(Register Rdst, Register Rsrc, bool maybeNULL, Register Rbase, int pow2_offset) {
4212 
4213   const address oop_base  = Universe::narrow_oop_base();
4214   const int     oop_shift = Universe::narrow_oop_shift();
4215   const bool    disjoint  = Universe::narrow_oop_base_disjoint();
4216 
4217   assert(UseCompressedOops, "must be on to call this method");
4218   assert(Universe::heap() != NULL, "java heap must be initialized to call this decoder");
4219   assert((oop_shift == 0) || (oop_shift == LogMinObjAlignmentInBytes),
4220          "cOop encoder detected bad shift");
4221 
4222   // cOops are always loaded zero-extended from memory. No explicit zero-extension necessary.
4223 
4224   if (oop_base != NULL) {
4225     unsigned int oop_base_hl = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 32)) & 0xffff;
4226     unsigned int oop_base_hh = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 48)) & 0xffff;
4227     unsigned int oop_base_hf = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 32)) & 0xFFFFffff;
4228     if (disjoint && (oop_base_hl == 0 || oop_base_hh == 0)) {
4229       BLOCK_COMMENT("cOop decoder disjointBase {");
4230       // We do not need to load the base. Instead, we can install the upper bits
4231       // with an OR instead of an ADD.
4232       Label done;
4233 
4234       // Rsrc contains a narrow oop. Thus we are sure the leftmost <oop_shift> bits will never be set.
4235       if (maybeNULL) {  // NULL ptr must be preserved!


4338   // OopHandle::resolve is an indirection.
4339   z_lg(result, 0, result);
4340 }
4341 
4342 void MacroAssembler::load_mirror(Register mirror, Register method) {
4343   mem2reg_opt(mirror, Address(method, Method::const_offset()));
4344   mem2reg_opt(mirror, Address(mirror, ConstMethod::constants_offset()));
4345   mem2reg_opt(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
4346   mem2reg_opt(mirror, Address(mirror, Klass::java_mirror_offset()));
4347   resolve_oop_handle(mirror);
4348 }
4349 
4350 //---------------------------------------------------------------
4351 //---  Operations on arrays.
4352 //---------------------------------------------------------------
4353 
4354 // Compiler ensures base is doubleword aligned and cnt is #doublewords.
4355 // Emitter does not KILL cnt and base arguments, since they need to be copied to
4356 // work registers anyway.
4357 // Actually, only r0, r1, and r5 are killed.
4358 unsigned int MacroAssembler::Clear_Array(Register cnt_arg, Register base_pointer_arg, Register src_addr, Register src_len) {
4359   // Src_addr is evenReg.
4360   // Src_len is odd_Reg.
4361 
4362   int      block_start = offset();
4363   Register tmp_reg  = src_len; // Holds target instr addr for EX.
4364   Register dst_len  = Z_R1;    // Holds dst len  for MVCLE.
4365   Register dst_addr = Z_R0;    // Holds dst addr for MVCLE.
4366 
4367   Label doXC, doMVCLE, done;
4368 
4369   BLOCK_COMMENT("Clear_Array {");
4370 
4371   // Check for zero len and convert to long.
4372   z_ltgfr(src_len, cnt_arg);      // Remember casted value for doSTG case.
4373   z_bre(done);                    // Nothing to do if len == 0.
4374 
4375   // Prefetch data to be cleared.
4376   if (VM_Version::has_Prefetch()) {
4377     z_pfd(0x02,   0, Z_R0, base_pointer_arg);
4378     z_pfd(0x02, 256, Z_R0, base_pointer_arg);
4379   }
4380 
4381   z_sllg(dst_len, src_len, 3);    // #bytes to clear.
4382   z_cghi(src_len, 32);            // Check for len <= 256 bytes (<=32 DW).
4383   z_brnh(doXC);                   // If so, use executed XC to clear.
4384 
4385   // MVCLE: initialize long arrays (general case).
4386   bind(doMVCLE);
4387   z_lgr(dst_addr, base_pointer_arg);
4388   clear_reg(src_len, true, false); // Src len of MVCLE is zero.
4389 
4390   MacroAssembler::move_long_ext(dst_addr, src_addr, 0);

4391   z_bru(done);
4392 
4393   // XC: initialize short arrays.
4394   Label XC_template; // Instr template, never exec directly!
4395     bind(XC_template);
4396     z_xc(0,0,base_pointer_arg,0,base_pointer_arg);
4397 
4398   bind(doXC);
4399     add2reg(dst_len, -1);             // Get #bytes-1 for EXECUTE.
4400     if (VM_Version::has_ExecuteExtensions()) {
4401       z_exrl(dst_len, XC_template);   // Execute XC with var. len.
4402     } else {
4403       z_larl(tmp_reg, XC_template);
4404       z_ex(dst_len,0,Z_R0,tmp_reg);   // Execute XC with var. len.
4405     }
4406     // z_bru(done);      // fallthru
4407 
4408   bind(done);
4409 
4410   BLOCK_COMMENT("} Clear_Array");
4411 
4412   int block_end = offset();
4413   return block_end - block_start;
4414 }
4415 
4416 // Compiler ensures base is doubleword aligned and cnt is count of doublewords.
4417 // Emitter does not KILL any arguments nor work registers.
4418 // Emitter generates up to 16 XC instructions, depending on the array length.
4419 unsigned int MacroAssembler::Clear_Array_Const(long cnt, Register base) {
4420   int  block_start    = offset();
4421   int  off;
4422   int  lineSize_Bytes = AllocatePrefetchStepSize;
4423   int  lineSize_DW    = AllocatePrefetchStepSize>>LogBytesPerWord;
4424   bool doPrefetch     = VM_Version::has_Prefetch();


4446       z_xc(off*XC_maxlen, XC_maxlen-1, base, off*XC_maxlen, base);
4447 
4448       // Prefetch some cache lines in advance.
4449       if (doPrefetch && (off <= numXCInstr-AllocatePrefetchLines)) {
4450         z_pfd(0x02, (off+AllocatePrefetchLines)*lineSize_Bytes, Z_R0, base);
4451       }
4452     }
4453     if (off*XC_maxlen < cnt*BytesPerWord) {
4454       z_xc(off*XC_maxlen, (cnt*BytesPerWord-off*XC_maxlen)-1, base, off*XC_maxlen, base);
4455     }
4456   }
4457   BLOCK_COMMENT("} Clear_Array_Const");
4458 
4459   int block_end = offset();
4460   return block_end - block_start;
4461 }
4462 
4463 // Compiler ensures base is doubleword aligned and cnt is #doublewords.
4464 // Emitter does not KILL cnt and base arguments, since they need to be copied to
4465 // work registers anyway.
4466 // Actually, only r0, r1, r4, and r5 (which are work registers) are killed.
4467 //
4468 // For very large arrays, exploit MVCLE H/W support.
4469 // MVCLE instruction automatically exploits H/W-optimized page mover.
4470 // - Bytes up to next page boundary are cleared with a series of XC to self.
4471 // - All full pages are cleared with the page mover H/W assist.
4472 // - Remaining bytes are again cleared by a series of XC to self.
4473 //
4474 unsigned int MacroAssembler::Clear_Array_Const_Big(long cnt, Register base_pointer_arg, Register src_addr, Register src_len) {
4475   // Src_addr is evenReg.
4476   // Src_len is odd_Reg.
4477 
4478   int      block_start = offset();
4479   Register dst_len  = Z_R1;      // Holds dst len  for MVCLE.
4480   Register dst_addr = Z_R0;      // Holds dst addr for MVCLE.
4481 
4482   BLOCK_COMMENT("Clear_Array_Const_Big {");
4483 
4484   // Get len to clear.
4485   load_const_optimized(dst_len, (long)cnt*8L);  // in Bytes = #DW*8
4486 
4487   // Prepare other args to MVCLE.
4488   z_lgr(dst_addr, base_pointer_arg);
4489   // Indicate unused result.
4490   (void) clear_reg(src_len, true, false);  // Src len of MVCLE is zero.
4491 
4492   // Clear.
4493   MacroAssembler::move_long_ext(dst_addr, src_addr, 0);
4494   BLOCK_COMMENT("} Clear_Array_Const_Big");
4495 
4496   int block_end = offset();
4497   return block_end - block_start;
4498 }
4499 
4500 // Allocator.
4501 unsigned int MacroAssembler::CopyRawMemory_AlignedDisjoint(Register src_reg, Register dst_reg,
4502                                                            Register cnt_reg,
4503                                                            Register tmp1_reg, Register tmp2_reg) {
4504   // Tmp1 is oddReg.
4505   // Tmp2 is evenReg.
4506 
4507   int block_start = offset();
4508   Label doMVC, doMVCLE, done, MVC_template;
4509 
4510   BLOCK_COMMENT("CopyRawMemory_AlignedDisjoint {");
4511 
4512   // Check for zero len and convert to long.
4513   z_ltgfr(cnt_reg, cnt_reg);      // Remember casted value for doSTG case.


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