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src/hotspot/cpu/s390/s390.ad

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*** 1,8 **** // ! // Copyright (c) 2017, 2019, Oracle and/or its affiliates. All rights reserved. ! // Copyright (c) 2017, 2019 SAP SE. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License version 2 only, as // published by the Free Software Foundation. --- 1,8 ---- // ! // Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved. ! // Copyright (c) 2017, SAP SE. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License version 2 only, as // published by the Free Software Foundation.
*** 472,494 **** Z_R13_H,Z_R13 /*Z_R14_H,Z_R14,*/ // return_pc /*Z_R15_H,Z_R15*/ // SP ); - // z_long_reg without even registers - reg_class z_long_odd_reg( - /*Z_R0_H,Z_R0*/ // R0 - /*Z_R1_H,Z_R1*/ - Z_R3_H,Z_R3, - Z_R5_H,Z_R5, - Z_R7_H,Z_R7, - Z_R9_H,Z_R9, - Z_R11_H,Z_R11, - Z_R13_H,Z_R13 - /*Z_R14_H,Z_R14,*/ // return_pc - /*Z_R15_H,Z_R15*/ // SP - ); // Special Class for Condition Code Flags Register reg_class z_condition_reg( Z_CR --- 472,481 ----
*** 1386,1395 **** --- 1373,1383 ---- // ic_miss_stub to find the proper method. __ load_const_optimized(R1_ic_miss_stub_addr, icmiss); __ z_br(R1_ic_miss_stub_addr); __ bind(valid); } + } uint MachUEPNode::size(PhaseRegAlloc *ra_) const { // Determine size dynamically. return MachNode::size(ra_);
*** 1641,1651 **** // Constant shift counts are handled in Ideal phase. const bool Matcher::need_masked_shift_count = false; // Set this as clone_shift_expressions. bool Matcher::narrow_oop_use_complex_address() { ! if (CompressedOops::base() == NULL && CompressedOops::shift() == 0) return true; return false; } bool Matcher::narrow_klass_use_complex_address() { NOT_LP64(ShouldNotCallThis()); --- 1629,1639 ---- // Constant shift counts are handled in Ideal phase. const bool Matcher::need_masked_shift_count = false; // Set this as clone_shift_expressions. bool Matcher::narrow_oop_use_complex_address() { ! if (Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0) return true; return false; } bool Matcher::narrow_klass_use_complex_address() { NOT_LP64(ShouldNotCallThis());
*** 1654,1669 **** return false; } bool Matcher::const_oop_prefer_decode() { // Prefer ConN+DecodeN over ConP in simple compressed oops mode. ! return CompressedOops::base() == NULL; } bool Matcher::const_klass_prefer_decode() { // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. ! return CompressedKlassPointers::base() == NULL; } // Is it better to copy float constants, or load them directly from memory? // Most RISCs will have to materialize an address into a // register first, so they would do better to copy the constant from stack. --- 1642,1657 ---- return false; } bool Matcher::const_oop_prefer_decode() { // Prefer ConN+DecodeN over ConP in simple compressed oops mode. ! return Universe::narrow_oop_base() == NULL; } bool Matcher::const_klass_prefer_decode() { // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. ! return Universe::narrow_klass_base() == NULL; } // Is it better to copy float constants, or load them directly from memory? // Most RISCs will have to materialize an address into a // register first, so they would do better to copy the constant from stack.
*** 3388,3398 **** operand iRegL() %{ constraint(ALLOC_IN_RC(z_long_reg)); match(RegL); match(revenRegL); match(roddRegL); - match(allRoddRegL); match(rarg1RegL); match(rarg5RegL); format %{ %} interface(REG_INTER); %} --- 3376,3385 ----
*** 3411,3428 **** match(iRegL); format %{ %} interface(REG_INTER); %} - // available odd registers for iRegL - operand allRoddRegL() %{ - constraint(ALLOC_IN_RC(z_long_odd_reg)); - match(iRegL); - format %{ %} - interface(REG_INTER); - %} - operand rarg1RegL() %{ constraint(ALLOC_IN_RC(z_rarg1_long_reg)); match(iRegL); format %{ %} interface(REG_INTER); --- 3398,3407 ----
*** 3504,3522 **** %} // Operands to remove register moves in unscaled mode. // Match read/write registers with an EncodeP node if neither shift nor add are required. operand iRegP2N(iRegP reg) %{ ! predicate(CompressedOops::shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL); constraint(ALLOC_IN_RC(z_memory_ptr_reg)); match(EncodeP reg); format %{ "$reg" %} interface(REG_INTER) %} operand iRegN2P(iRegN reg) %{ ! predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0 && _leaf->as_DecodeN()->in(0) == NULL); constraint(ALLOC_IN_RC(z_memory_ptr_reg)); match(DecodeN reg); format %{ "$reg" %} interface(REG_INTER) --- 3483,3501 ---- %} // Operands to remove register moves in unscaled mode. // Match read/write registers with an EncodeP node if neither shift nor add are required. operand iRegP2N(iRegP reg) %{ ! predicate(Universe::narrow_oop_shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL); constraint(ALLOC_IN_RC(z_memory_ptr_reg)); match(EncodeP reg); format %{ "$reg" %} interface(REG_INTER) %} operand iRegN2P(iRegN reg) %{ ! predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0 && _leaf->as_DecodeN()->in(0) == NULL); constraint(ALLOC_IN_RC(z_memory_ptr_reg)); match(DecodeN reg); format %{ "$reg" %} interface(REG_INTER)
*** 4315,4334 **** instruct loadConI(iRegI dst, immI src) %{ match(Set dst src); ins_cost(DEFAULT_COST); size(6); ! format %{ "LGFI $dst,$src\t # (int)" %} ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. ins_pipe(pipe_class_dummy); %} instruct loadConI16(iRegI dst, immI16 src) %{ match(Set dst src); ins_cost(DEFAULT_COST_LOW); size(4); ! format %{ "LGHI $dst,$src\t # (int)" %} ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. ins_pipe(pipe_class_dummy); %} instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{ --- 4294,4313 ---- instruct loadConI(iRegI dst, immI src) %{ match(Set dst src); ins_cost(DEFAULT_COST); size(6); ! format %{ "LGFI $dst,$src\t # (int)" %} ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. ins_pipe(pipe_class_dummy); %} instruct loadConI16(iRegI dst, immI16 src) %{ match(Set dst src); ins_cost(DEFAULT_COST_LOW); size(4); ! format %{ "LGHI $dst,$src\t # (int)" %} ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %} // Sign-extend to 64 bit, it's at no cost. ins_pipe(pipe_class_dummy); %} instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
*** 4720,4741 **** // Load narrow oop instruct loadN(iRegN dst, memory mem) %{ match(Set dst (LoadN mem)); ins_cost(MEMORY_REF_COST); size(Z_DISP3_SIZE); ! format %{ "LoadN $dst,$mem\t # (cOop)" %} opcode(LLGF_ZOPC, LLGF_ZOPC); ins_encode(z_form_rt_mem_opt(dst, mem)); ins_pipe(pipe_class_dummy); %} // Load narrow Klass Pointer instruct loadNKlass(iRegN dst, memory mem) %{ match(Set dst (LoadNKlass mem)); ins_cost(MEMORY_REF_COST); size(Z_DISP3_SIZE); ! format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %} opcode(LLGF_ZOPC, LLGF_ZOPC); ins_encode(z_form_rt_mem_opt(dst, mem)); ins_pipe(pipe_class_dummy); %} --- 4699,4720 ---- // Load narrow oop instruct loadN(iRegN dst, memory mem) %{ match(Set dst (LoadN mem)); ins_cost(MEMORY_REF_COST); size(Z_DISP3_SIZE); ! format %{ "LoadN $dst,$mem\t# (cOop)" %} opcode(LLGF_ZOPC, LLGF_ZOPC); ins_encode(z_form_rt_mem_opt(dst, mem)); ins_pipe(pipe_class_dummy); %} // Load narrow Klass Pointer instruct loadNKlass(iRegN dst, memory mem) %{ match(Set dst (LoadNKlass mem)); ins_cost(MEMORY_REF_COST); size(Z_DISP3_SIZE); ! format %{ "LoadNKlass $dst,$mem\t# (klass cOop)" %} opcode(LLGF_ZOPC, LLGF_ZOPC); ins_encode(z_form_rt_mem_opt(dst, mem)); ins_pipe(pipe_class_dummy); %}
*** 4781,4805 **** // Load and Decode Compressed Pointer // optimized variants for Unscaled cOops instruct decodeLoadN(iRegP dst, memory mem) %{ match(Set dst (DecodeN (LoadN mem))); ! predicate(false && (CompressedOops::base()==NULL)&&(CompressedOops::shift()==0)); ins_cost(MEMORY_REF_COST); size(Z_DISP3_SIZE); ! format %{ "DecodeLoadN $dst,$mem\t # (cOop Load+Decode)" %} opcode(LLGF_ZOPC, LLGF_ZOPC); ins_encode(z_form_rt_mem_opt(dst, mem)); ins_pipe(pipe_class_dummy); %} instruct decodeLoadNKlass(iRegP dst, memory mem) %{ match(Set dst (DecodeNKlass (LoadNKlass mem))); ! predicate(false && (CompressedKlassPointers::base()==NULL)&&(CompressedKlassPointers::shift()==0)); ins_cost(MEMORY_REF_COST); size(Z_DISP3_SIZE); ! format %{ "DecodeLoadNKlass $dst,$mem\t # (load/decode NKlass)" %} opcode(LLGF_ZOPC, LLGF_ZOPC); ins_encode(z_form_rt_mem_opt(dst, mem)); ins_pipe(pipe_class_dummy); %} --- 4760,4784 ---- // Load and Decode Compressed Pointer // optimized variants for Unscaled cOops instruct decodeLoadN(iRegP dst, memory mem) %{ match(Set dst (DecodeN (LoadN mem))); ! predicate(false && (Universe::narrow_oop_base()==NULL)&&(Universe::narrow_oop_shift()==0)); ins_cost(MEMORY_REF_COST); size(Z_DISP3_SIZE); ! format %{ "DecodeLoadN $dst,$mem\t# (cOop Load+Decode)" %} opcode(LLGF_ZOPC, LLGF_ZOPC); ins_encode(z_form_rt_mem_opt(dst, mem)); ins_pipe(pipe_class_dummy); %} instruct decodeLoadNKlass(iRegP dst, memory mem) %{ match(Set dst (DecodeNKlass (LoadNKlass mem))); ! predicate(false && (Universe::narrow_klass_base()==NULL)&&(Universe::narrow_klass_shift()==0)); ins_cost(MEMORY_REF_COST); size(Z_DISP3_SIZE); ! format %{ "DecodeLoadNKlass $dst,$mem\t# (load/decode NKlass)" %} opcode(LLGF_ZOPC, LLGF_ZOPC); ins_encode(z_form_rt_mem_opt(dst, mem)); ins_pipe(pipe_class_dummy); %}
*** 4820,4833 **** // General decoder instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{ match(Set dst (DecodeN src)); effect(KILL cr); ! predicate(CompressedOops::base() == NULL || !ExpandLoadingBaseDecode); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "decodeN $dst,$src\t # (decode cOop)" %} ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %} ins_pipe(pipe_class_dummy); %} // General Klass decoder --- 4799,4812 ---- // General decoder instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{ match(Set dst (DecodeN src)); effect(KILL cr); ! predicate(Universe::narrow_oop_base() == NULL || !ExpandLoadingBaseDecode); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "decodeN $dst,$src\t# (decode cOop)" %} ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true); %} ins_pipe(pipe_class_dummy); %} // General Klass decoder
*** 4844,4857 **** instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{ match(Set dst (DecodeN src)); effect(KILL cr); predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && ! (CompressedOops::base()== NULL || !ExpandLoadingBaseDecode_NN)); ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "decodeN $dst,$src\t # (decode cOop NN)" %} ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %} ins_pipe(pipe_class_dummy); %} instruct loadBase(iRegL dst, immL baseImm) %{ --- 4823,4836 ---- instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{ match(Set dst (DecodeN src)); effect(KILL cr); predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && ! (Universe::narrow_oop_base()== NULL || !ExpandLoadingBaseDecode_NN)); ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "decodeN $dst,$src\t# (decode cOop NN)" %} ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %} ins_pipe(pipe_class_dummy); %} instruct loadBase(iRegL dst, immL baseImm) %{
*** 4870,4909 **** // generate wrong code. Oop_decoder generates additional lgr when // dst==base. effect(KILL cr); predicate(false); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %} ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register, ! (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base())); %} ins_pipe(pipe_class_dummy); %} // Decoder for heapbased mode peeling off loading the base. instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{ match(Set dst (DecodeN src base)); effect(KILL cr); predicate(false); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %} ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register, ! (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base())); %} ins_pipe(pipe_class_dummy); %} // Decoder for heapbased mode peeling off loading the base. instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ match(Set dst (DecodeN src)); ! predicate(CompressedOops::base() != NULL && ExpandLoadingBaseDecode); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); // TODO: s390 port size(VARIABLE_SIZE); expand %{ ! immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %} iRegL base; loadBase(base, baseImm); decodeN_base(dst, src, base, cr); %} %} --- 4849,4888 ---- // generate wrong code. Oop_decoder generates additional lgr when // dst==base. effect(KILL cr); predicate(false); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "decodeN $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t# (decode cOop)" %} ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register, ! (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base())); %} ins_pipe(pipe_class_dummy); %} // Decoder for heapbased mode peeling off loading the base. instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{ match(Set dst (DecodeN src base)); effect(KILL cr); predicate(false); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "decodeN $dst = ($src << 3) + $base + pow2_offset\t# (decode cOop)" %} ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register, ! (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)Universe::narrow_oop_base())); %} ins_pipe(pipe_class_dummy); %} // Decoder for heapbased mode peeling off loading the base. instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ match(Set dst (DecodeN src)); ! predicate(Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST); // TODO: s390 port size(VARIABLE_SIZE); expand %{ ! immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %} iRegL base; loadBase(base, baseImm); decodeN_base(dst, src, base, cr); %} %}
*** 4911,4925 **** // Decoder for heapbased mode peeling off loading the base. instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ match(Set dst (DecodeN src)); predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && ! CompressedOops::base() != NULL && ExpandLoadingBaseDecode_NN); ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); expand %{ ! immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %} iRegL base; loadBase(base, baseImm); decodeN_NN_base(dst, src, base, cr); %} %} --- 4890,4904 ---- // Decoder for heapbased mode peeling off loading the base. instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{ match(Set dst (DecodeN src)); predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull || n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && ! Universe::narrow_oop_base() != NULL && ExpandLoadingBaseDecode_NN); ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); expand %{ ! immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %} iRegL base; loadBase(base, baseImm); decodeN_NN_base(dst, src, base, cr); %} %}
*** 4929,4944 **** // General encoder instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{ match(Set dst (EncodeP src)); effect(KILL cr); predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && ! (CompressedOops::base() == 0 || ! CompressedOops::base_disjoint() || !ExpandLoadingBaseEncode)); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "encodeP $dst,$src\t # (encode cOop)" %} ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} ins_pipe(pipe_class_dummy); %} // General class encoder --- 4908,4923 ---- // General encoder instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{ match(Set dst (EncodeP src)); effect(KILL cr); predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && ! (Universe::narrow_oop_base() == 0 || ! Universe::narrow_oop_base_disjoint() || !ExpandLoadingBaseEncode)); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "encodeP $dst,$src\t# (encode cOop)" %} ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} ins_pipe(pipe_class_dummy); %} // General class encoder
*** 4952,4967 **** instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{ match(Set dst (EncodeP src)); effect(KILL cr); predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && ! (CompressedOops::base() == 0 || ! CompressedOops::base_disjoint() || !ExpandLoadingBaseEncode_NN)); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "encodeP $dst,$src\t # (encode cOop)" %} ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} ins_pipe(pipe_class_dummy); %} // Encoder for heapbased mode peeling off loading the base. --- 4931,4946 ---- instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{ match(Set dst (EncodeP src)); effect(KILL cr); predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && ! (Universe::narrow_oop_base() == 0 || ! Universe::narrow_oop_base_disjoint() || !ExpandLoadingBaseEncode_NN)); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "encodeP $dst,$src\t# (encode cOop)" %} ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %} ins_pipe(pipe_class_dummy); %} // Encoder for heapbased mode peeling off loading the base.
*** 4969,4982 **** match(Set dst (EncodeP src (Binary base dst))); effect(TEMP_DEF dst); predicate(false); ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %} ins_encode %{ jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset ! (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift()); __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset); %} ins_pipe(pipe_class_dummy); %} --- 4948,4961 ---- match(Set dst (EncodeP src (Binary base dst))); effect(TEMP_DEF dst); predicate(false); ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "encodeP $dst = ($src>>3) +$base + pow2_offset\t# (encode cOop)" %} ins_encode %{ jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset ! (((uint64_t)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift()); __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset); %} ins_pipe(pipe_class_dummy); %}
*** 4985,5009 **** match(Set dst (EncodeP src base)); effect(USE pow2_offset); predicate(false); ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %} ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %} ins_pipe(pipe_class_dummy); %} // Encoder for heapbased mode peeling off loading the base. instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{ match(Set dst (EncodeP src)); effect(KILL cr); predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && ! (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode)); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); expand %{ ! immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %} immL_0 zero %{ (0) %} flagsReg ccr; iRegL base; iRegL negBase; loadBase(base, baseImm); --- 4964,4988 ---- match(Set dst (EncodeP src base)); effect(USE pow2_offset); predicate(false); ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); ! format %{ "encodeP $dst = ($src>>3) +$base + $pow2_offset\t# (encode cOop)" %} ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %} ins_pipe(pipe_class_dummy); %} // Encoder for heapbased mode peeling off loading the base. instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{ match(Set dst (EncodeP src)); effect(KILL cr); predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) && ! (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode)); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); expand %{ ! immL baseImm %{ ((jlong)(intptr_t)Universe::narrow_oop_base()) >> Universe::narrow_oop_shift() %} immL_0 zero %{ (0) %} flagsReg ccr; iRegL base; iRegL negBase; loadBase(base, baseImm);
*** 5015,5030 **** // Encoder for heapbased mode peeling off loading the base. instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{ match(Set dst (EncodeP src)); effect(KILL cr); predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && ! (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN)); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); expand %{ ! immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %} ! immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %} immL_0 zero %{ 0 %} flagsReg ccr; iRegL base; iRegL negBase; loadBase(base, baseImm); --- 4994,5009 ---- // Encoder for heapbased mode peeling off loading the base. instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{ match(Set dst (EncodeP src)); effect(KILL cr); predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) && ! (Universe::narrow_oop_base_overlaps() && ExpandLoadingBaseEncode_NN)); ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST); // TODO: s390 port size(VARIABLE_SIZE); expand %{ ! immL baseImm %{ (jlong)(intptr_t)Universe::narrow_oop_base() %} ! immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)Universe::narrow_oop_base())) %} immL_0 zero %{ 0 %} flagsReg ccr; iRegL base; iRegL negBase; loadBase(base, baseImm);
*** 5038,5059 **** // Store Compressed Pointer instruct storeN(memory mem, iRegN_P2N src) %{ match(Set mem (StoreN mem src)); ins_cost(MEMORY_REF_COST); size(Z_DISP_SIZE); ! format %{ "ST $src,$mem\t # (cOop)" %} opcode(STY_ZOPC, ST_ZOPC); ins_encode(z_form_rt_mem_opt(src, mem)); ins_pipe(pipe_class_dummy); %} // Store Compressed Klass pointer instruct storeNKlass(memory mem, iRegN src) %{ match(Set mem (StoreNKlass mem src)); ins_cost(MEMORY_REF_COST); size(Z_DISP_SIZE); ! format %{ "ST $src,$mem\t # (cKlass)" %} opcode(STY_ZOPC, ST_ZOPC); ins_encode(z_form_rt_mem_opt(src, mem)); ins_pipe(pipe_class_dummy); %} --- 5017,5038 ---- // Store Compressed Pointer instruct storeN(memory mem, iRegN_P2N src) %{ match(Set mem (StoreN mem src)); ins_cost(MEMORY_REF_COST); size(Z_DISP_SIZE); ! format %{ "ST $src,$mem\t# (cOop)" %} opcode(STY_ZOPC, ST_ZOPC); ins_encode(z_form_rt_mem_opt(src, mem)); ins_pipe(pipe_class_dummy); %} // Store Compressed Klass pointer instruct storeNKlass(memory mem, iRegN src) %{ match(Set mem (StoreNKlass mem src)); ins_cost(MEMORY_REF_COST); size(Z_DISP_SIZE); ! format %{ "ST $src,$mem\t# (cKlass)" %} opcode(STY_ZOPC, ST_ZOPC); ins_encode(z_form_rt_mem_opt(src, mem)); ins_pipe(pipe_class_dummy); %}
*** 5061,5081 **** instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{ match(Set cr (CmpN src1 src2)); ins_cost(DEFAULT_COST); size(2); ! format %{ "CLR $src1,$src2\t # (cOop)" %} opcode(CLR_ZOPC); ins_encode(z_rrform(src1, src2)); ins_pipe(pipe_class_dummy); %} instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{ match(Set cr (CmpN src1 src2)); ins_cost(DEFAULT_COST); size(6); ! format %{ "CLFI $src1,$src2\t # (cOop) compare immediate narrow" %} ins_encode %{ AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant); __ relocate(cOop.rspec(), 1); __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value()); %} --- 5040,5060 ---- instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{ match(Set cr (CmpN src1 src2)); ins_cost(DEFAULT_COST); size(2); ! format %{ "CLR $src1,$src2\t# (cOop)" %} opcode(CLR_ZOPC); ins_encode(z_rrform(src1, src2)); ins_pipe(pipe_class_dummy); %} instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{ match(Set cr (CmpN src1 src2)); ins_cost(DEFAULT_COST); size(6); ! format %{ "CLFI $src1,$src2\t# (cOop) compare immediate narrow" %} ins_encode %{ AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant); __ relocate(cOop.rspec(), 1); __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value()); %}
*** 5084,5094 **** instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{ match(Set cr (CmpN src1 src2)); ins_cost(DEFAULT_COST); size(6); ! format %{ "CLFI $src1,$src2\t # (NKlass) compare immediate narrow" %} ins_encode %{ AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant); __ relocate(NKlass.rspec(), 1); __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value()); %} --- 5063,5073 ---- instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{ match(Set cr (CmpN src1 src2)); ins_cost(DEFAULT_COST); size(6); ! format %{ "CLFI $src1,$src2\t# (NKlass) compare immediate narrow" %} ins_encode %{ AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant); __ relocate(NKlass.rspec(), 1); __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value()); %}
*** 5097,5107 **** instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{ match(Set cr (CmpN src1 src2)); ins_cost(DEFAULT_COST); size(2); ! format %{ "LTR $src1,$src2\t # (cOop) LTR because comparing against zero" %} opcode(LTR_ZOPC); ins_encode(z_rrform(src1, src1)); ins_pipe(pipe_class_dummy); %} --- 5076,5086 ---- instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{ match(Set cr (CmpN src1 src2)); ins_cost(DEFAULT_COST); size(2); ! format %{ "LTR $src1,$src2\t# (cOop) LTR because comparing against zero" %} opcode(LTR_ZOPC); ins_encode(z_rrform(src1, src1)); ins_pipe(pipe_class_dummy); %}
*** 6206,6216 **** ins_pipe(pipe_class_dummy); %} instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{ match(Set dst (AddP (AddP src1 src2) con)); ! predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0); ins_cost(DEFAULT_COST_LOW); size(4); format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %} opcode(LA_ZOPC); ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2)); --- 6185,6195 ---- ins_pipe(pipe_class_dummy); %} instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{ match(Set dst (AddP (AddP src1 src2) con)); ! predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); ins_cost(DEFAULT_COST_LOW); size(4); format %{ "LA $dst,$con($src1,$src2)\t # ptr d12(x,b)" %} opcode(LA_ZOPC); ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
*** 6228,6238 **** ins_pipe(pipe_class_dummy); %} instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{ match(Set dst (AddP (AddP src1 src2) con)); ! predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0); ins_cost(DEFAULT_COST); // TODO: s390 port size(FIXED_SIZE); format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %} opcode(LAY_ZOPC); ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2)); --- 6207,6217 ---- ins_pipe(pipe_class_dummy); %} instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{ match(Set dst (AddP (AddP src1 src2) con)); ! predicate( PreferLAoverADD && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); ins_cost(DEFAULT_COST); // TODO: s390 port size(FIXED_SIZE); format %{ "LAY $dst,$con($src1,$src2)\t # ptr d20(x,b)" %} opcode(LAY_ZOPC); ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
*** 6792,6802 **** instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{ match(Set dst (LShiftI src nbits)); effect(KILL cr); // R1 is killed, too. ins_cost(3 * DEFAULT_COST); size(14); ! format %{ "SLL $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %} ins_encode %{ __ z_lgr(Z_R1_scratch, $nbits$$Register); __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch); %} --- 6771,6781 ---- instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{ match(Set dst (LShiftI src nbits)); effect(KILL cr); // R1 is killed, too. ins_cost(3 * DEFAULT_COST); size(14); ! format %{ "SLL $dst,$src,[$nbits] & 31\t# use RISC-like SLLG also for int" %} ins_encode %{ __ z_lgr(Z_R1_scratch, $nbits$$Register); __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1); __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch); %}
*** 6806,6816 **** // Register Shift Left Immediate // Constant shift count is masked in ideal graph already. instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{ match(Set dst (LShiftI src nbits)); size(6); ! format %{ "SLL $dst,$src,$nbits\t # use RISC-like SLLG also for int" %} ins_encode %{ int Nbit = $nbits$$constant; assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); %} --- 6785,6795 ---- // Register Shift Left Immediate // Constant shift count is masked in ideal graph already. instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{ match(Set dst (LShiftI src nbits)); size(6); ! format %{ "SLL $dst,$src,$nbits\t# use RISC-like SLLG also for int" %} ins_encode %{ int Nbit = $nbits$$constant; assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph"); __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0); %}
*** 7122,7143 **** %} instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{ match(Set cr (OverflowSubI zero op2)); effect(DEF cr, USE op2); ! format %{ "NEG $op2\t # overflow check int" %} ins_encode %{ __ clear_reg(Z_R0_scratch, false, false); __ z_sr(Z_R0_scratch, $op2$$Register); %} ins_pipe(pipe_class_dummy); %} instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{ match(Set cr (OverflowSubL zero op2)); effect(DEF cr, USE op2); ! format %{ "NEGG $op2\t # overflow check long" %} ins_encode %{ __ clear_reg(Z_R0_scratch, true, false); __ z_sgr(Z_R0_scratch, $op2$$Register); %} ins_pipe(pipe_class_dummy); --- 7101,7122 ---- %} instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{ match(Set cr (OverflowSubI zero op2)); effect(DEF cr, USE op2); ! format %{ "NEG $op2\t# overflow check int" %} ins_encode %{ __ clear_reg(Z_R0_scratch, false, false); __ z_sr(Z_R0_scratch, $op2$$Register); %} ins_pipe(pipe_class_dummy); %} instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{ match(Set cr (OverflowSubL zero op2)); effect(DEF cr, USE op2); ! format %{ "NEGG $op2\t# overflow check long" %} ins_encode %{ __ clear_reg(Z_R0_scratch, true, false); __ z_sgr(Z_R0_scratch, $op2$$Register); %} ins_pipe(pipe_class_dummy);
*** 8552,8562 **** %} // Don't use LTGFR which performs sign extend. instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{ match(Set cr (CmpP (DecodeN op1) op2)); ! predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0); ins_cost(DEFAULT_COST_LOW); size(2); format %{ "LTR $op1, $op1\t # ptr" %} opcode(LTR_ZOPC); ins_encode(z_rrform(op1, op1)); --- 8531,8541 ---- %} // Don't use LTGFR which performs sign extend. instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{ match(Set cr (CmpP (DecodeN op1) op2)); ! predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0); ins_cost(DEFAULT_COST_LOW); size(2); format %{ "LTR $op1, $op1\t # ptr" %} opcode(LTR_ZOPC); ins_encode(z_rrform(op1, op1));
*** 9188,9198 **** // Same match rule as `branchConFar'. match(If cmp cr); effect(USE lbl); ins_cost(BRANCH_COST); size(4); ! format %{ "branch_con_short,$cmp $lbl" %} ins_encode(z_enc_branch_con_short(cmp, lbl)); ins_pipe(pipe_class_dummy); // If set to 1 this indicates that the current instruction is a // short variant of a long branch. This avoids using this // instruction in first-pass matching. It will then only be used in --- 9167,9177 ---- // Same match rule as `branchConFar'. match(If cmp cr); effect(USE lbl); ins_cost(BRANCH_COST); size(4); ! format %{ "branch_con_short,$cmp $cr, $lbl" %} ins_encode(z_enc_branch_con_short(cmp, lbl)); ins_pipe(pipe_class_dummy); // If set to 1 this indicates that the current instruction is a // short variant of a long branch. This avoids using this // instruction in first-pass matching. It will then only be used in
*** 9210,9220 **** match(If cmp cr); effect(USE cr, USE lbl); // Make more expensive to prefer compare_and_branch over separate instructions. ins_cost(2 * BRANCH_COST); size(6); ! format %{ "branch_con_far,$cmp $lbl" %} ins_encode(z_enc_branch_con_far(cmp, lbl)); ins_pipe(pipe_class_dummy); // This is not a short variant of a branch, but the long variant.. ins_short_branch(0); %} --- 9189,9199 ---- match(If cmp cr); effect(USE cr, USE lbl); // Make more expensive to prefer compare_and_branch over separate instructions. ins_cost(2 * BRANCH_COST); size(6); ! format %{ "branch_con_far,$cmp $cr, $lbl" %} ins_encode(z_enc_branch_con_far(cmp, lbl)); ins_pipe(pipe_class_dummy); // This is not a short variant of a branch, but the long variant.. ins_short_branch(0); %}
*** 9779,9789 **** // TailJump below removes the return address. instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{ match(TailCall jump_target method_oop); ins_cost(CALL_COST); size(2); ! format %{ "Jmp $jump_target\t # $method_oop holds method oop" %} ins_encode %{ __ z_br($jump_target$$Register); %} ins_pipe(pipe_class_dummy); %} // Return Instruction --- 9758,9768 ---- // TailJump below removes the return address. instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{ match(TailCall jump_target method_oop); ins_cost(CALL_COST); size(2); ! format %{ "Jmp $jump_target\t# $method_oop holds method oop" %} ins_encode %{ __ z_br($jump_target$$Register); %} ins_pipe(pipe_class_dummy); %} // Return Instruction
*** 9918,9944 **** format %{ "ClearArrayConst $cnt,$base" %} ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %} ins_pipe(pipe_class_dummy); %} ! instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{ match(Set dummy (ClearArray cnt base)); ! effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too. ins_cost(200); // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader. format %{ "ClearArrayConstBig $cnt,$base" %} ! ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %} ins_pipe(pipe_class_dummy); %} ! instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{ match(Set dummy (ClearArray cnt base)); ! effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too. ins_cost(300); // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off. format %{ "ClearArrayVar $cnt,$base" %} ! ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %} ins_pipe(pipe_class_dummy); %} // ============================================================================ // CompactStrings --- 9897,9923 ---- format %{ "ClearArrayConst $cnt,$base" %} ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %} ins_pipe(pipe_class_dummy); %} ! instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{ match(Set dummy (ClearArray cnt base)); ! effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too. ins_cost(200); // TODO: s390 port size(VARIABLE_SIZE); // Variable in size due to optimized constant loader. format %{ "ClearArrayConstBig $cnt,$base" %} ! ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $srcA$$Register, $srcL$$Register); %} ins_pipe(pipe_class_dummy); %} ! instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, revenRegL srcA, roddRegL srcL, flagsReg cr) %{ match(Set dummy (ClearArray cnt base)); ! effect(TEMP srcA, TEMP srcL, KILL cr); // R0, R1 are killed, too. ins_cost(300); // TODO: s390 port size(FIXED_SIZE); // z/Architecture: emitted code depends on PreferLAoverADD being on/off. format %{ "ClearArrayVar $cnt,$base" %} ! ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $srcA$$Register, $srcL$$Register); %} ins_pipe(pipe_class_dummy); %} // ============================================================================ // CompactStrings
*** 10787,10808 **** instruct bytes_reverse_int(iRegI dst, iRegI src) %{ match(Set dst (ReverseBytesI src)); predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported ins_cost(DEFAULT_COST); size(4); ! format %{ "LRVR $dst,$src\t # byte reverse int" %} opcode(LRVR_ZOPC); ins_encode(z_rreform(dst, src)); ins_pipe(pipe_class_dummy); %} instruct bytes_reverse_long(iRegL dst, iRegL src) %{ match(Set dst (ReverseBytesL src)); predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported ins_cost(DEFAULT_COST); // TODO: s390 port size(FIXED_SIZE); ! format %{ "LRVGR $dst,$src\t # byte reverse long" %} opcode(LRVGR_ZOPC); ins_encode(z_rreform(dst, src)); ins_pipe(pipe_class_dummy); %} --- 10766,10787 ---- instruct bytes_reverse_int(iRegI dst, iRegI src) %{ match(Set dst (ReverseBytesI src)); predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported ins_cost(DEFAULT_COST); size(4); ! format %{ "LRVR $dst,$src\t# byte reverse int" %} opcode(LRVR_ZOPC); ins_encode(z_rreform(dst, src)); ins_pipe(pipe_class_dummy); %} instruct bytes_reverse_long(iRegL dst, iRegL src) %{ match(Set dst (ReverseBytesL src)); predicate(UseByteReverseInstruction); // See Matcher::match_rule_supported ins_cost(DEFAULT_COST); // TODO: s390 port size(FIXED_SIZE); ! format %{ "LRVGR $dst,$src\t# byte reverse long" %} opcode(LRVGR_ZOPC); ins_encode(z_rreform(dst, src)); ins_pipe(pipe_class_dummy); %}
*** 10818,10829 **** instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ match(Set dst (CountLeadingZerosI src)); effect(KILL tmp, KILL cr); ins_cost(3 * DEFAULT_COST); size(14); ! format %{ "SLLG $dst,$src,32\t # no need to always count 32 zeroes first\n\t" ! "IILH $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t" "FLOGR $dst,$dst" %} ins_encode %{ // Performance experiments indicate that "FLOGR" is using some kind of // iteration to find the leftmost "1" bit. --- 10797,10808 ---- instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ match(Set dst (CountLeadingZerosI src)); effect(KILL tmp, KILL cr); ins_cost(3 * DEFAULT_COST); size(14); ! format %{ "SLLG $dst,$src,32\t# no need to always count 32 zeroes first\n\t" ! "IILH $dst,0x8000 \t# insert \"stop bit\" to force result 32 for zero src.\n\t" "FLOGR $dst,$dst" %} ins_encode %{ // Performance experiments indicate that "FLOGR" is using some kind of // iteration to find the leftmost "1" bit.
*** 10856,10866 **** instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{ match(Set dst (CountLeadingZerosL src)); effect(KILL tmp, KILL cr); ins_cost(DEFAULT_COST); size(4); ! format %{ "FLOGR $dst,$src \t # count leading zeros (long)\n\t" %} ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %} ins_pipe(pipe_class_dummy); %} // trailing zeroes --- 10835,10845 ---- instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{ match(Set dst (CountLeadingZerosL src)); effect(KILL tmp, KILL cr); ins_cost(DEFAULT_COST); size(4); ! format %{ "FLOGR $dst,$src \t# count leading zeros (long)\n\t" %} ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %} ins_pipe(pipe_class_dummy); %} // trailing zeroes
*** 10881,10898 **** instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ match(Set dst (CountTrailingZerosI src)); effect(TEMP_DEF dst, TEMP tmp, KILL cr); ins_cost(8 * DEFAULT_COST); // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. ! format %{ "LLGFR $dst,$src \t # clear upper 32 bits (we are dealing with int)\n\t" ! "LCGFR $tmp,$src \t # load 2's complement (32->64 bit)\n\t" ! "AGHI $dst,-1 \t # tmp1 = src-1\n\t" ! "AGHI $tmp,-1 \t # tmp2 = -src-1 = ~src\n\t" ! "NGR $dst,$tmp \t # tmp3 = tmp1&tmp2\n\t" ! "FLOGR $dst,$dst \t # count trailing zeros (int)\n\t" ! "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t" ! "LCR $dst,$dst \t # res = -tmp4" %} ins_encode %{ Register Rdst = $dst$$Register; Register Rsrc = $src$$Register; // Rtmp only needed for for zero-argument shortcut. With kill effect in --- 10860,10877 ---- instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{ match(Set dst (CountTrailingZerosI src)); effect(TEMP_DEF dst, TEMP tmp, KILL cr); ins_cost(8 * DEFAULT_COST); // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. ! format %{ "LLGFR $dst,$src \t# clear upper 32 bits (we are dealing with int)\n\t" ! "LCGFR $tmp,$src \t# load 2's complement (32->64 bit)\n\t" ! "AGHI $dst,-1 \t# tmp1 = src-1\n\t" ! "AGHI $tmp,-1 \t# tmp2 = -src-1 = ~src\n\t" ! "NGR $dst,$tmp \t# tmp3 = tmp1&tmp2\n\t" ! "FLOGR $dst,$dst \t# count trailing zeros (int)\n\t" ! "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t" ! "LCR $dst,$dst \t# res = -tmp4" %} ins_encode %{ Register Rdst = $dst$$Register; Register Rsrc = $src$$Register; // Rtmp only needed for for zero-argument shortcut. With kill effect in
*** 10934,10949 **** instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{ match(Set dst (CountTrailingZerosL src)); effect(TEMP_DEF dst, KILL tmp, KILL cr); ins_cost(8 * DEFAULT_COST); // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. ! format %{ "LCGR $dst,$src \t # preserve src\n\t" ! "NGR $dst,$src \t #\n\t" ! "AGHI $dst,-1 \t # tmp1 = src-1\n\t" ! "FLOGR $dst,$dst \t # count trailing zeros (long), kill $tmp\n\t" ! "AHI $dst,-64 \t # tmp4 = 64-(trailing zeroes)-64\n\t" ! "LCR $dst,$dst \t #" %} ins_encode %{ Register Rdst = $dst$$Register; Register Rsrc = $src$$Register; assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed. --- 10913,10928 ---- instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{ match(Set dst (CountTrailingZerosL src)); effect(TEMP_DEF dst, KILL tmp, KILL cr); ins_cost(8 * DEFAULT_COST); // TODO: s390 port size(FIXED_SIZE); // Emitted code depends on PreferLAoverADD being on/off. ! format %{ "LCGR $dst,$src \t# preserve src\n\t" ! "NGR $dst,$src \t#" ! "AGHI $dst,-1 \t# tmp1 = src-1\n\t" ! "FLOGR $dst,$dst \t# count trailing zeros (long), kill $tmp\n\t" ! "AHI $dst,-64 \t# tmp4 = 64-(trailing zeroes)-64\n\t" ! "LCR $dst,$dst \t#" %} ins_encode %{ Register Rdst = $dst$$Register; Register Rsrc = $src$$Register; assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
*** 10966,10976 **** match(Set dst (PopCountI src)); effect(TEMP_DEF dst, TEMP tmp, KILL cr); predicate(UsePopCountInstruction && VM_Version::has_PopCount()); ins_cost(DEFAULT_COST); size(24); ! format %{ "POPCNT $dst,$src\t # pop count int" %} ins_encode %{ Register Rdst = $dst$$Register; Register Rsrc = $src$$Register; Register Rtmp = $tmp$$Register; --- 10945,10955 ---- match(Set dst (PopCountI src)); effect(TEMP_DEF dst, TEMP tmp, KILL cr); predicate(UsePopCountInstruction && VM_Version::has_PopCount()); ins_cost(DEFAULT_COST); size(24); ! format %{ "POPCNT $dst,$src\t# pop count int" %} ins_encode %{ Register Rdst = $dst$$Register; Register Rsrc = $src$$Register; Register Rtmp = $tmp$$Register;
*** 10993,11003 **** match(Set dst (PopCountL src)); effect(TEMP_DEF dst, TEMP tmp, KILL cr); predicate(UsePopCountInstruction && VM_Version::has_PopCount()); ins_cost(DEFAULT_COST); // TODO: s390 port size(FIXED_SIZE); ! format %{ "POPCNT $dst,$src\t # pop count long" %} ins_encode %{ Register Rdst = $dst$$Register; Register Rsrc = $src$$Register; Register Rtmp = $tmp$$Register; --- 10972,10982 ---- match(Set dst (PopCountL src)); effect(TEMP_DEF dst, TEMP tmp, KILL cr); predicate(UsePopCountInstruction && VM_Version::has_PopCount()); ins_cost(DEFAULT_COST); // TODO: s390 port size(FIXED_SIZE); ! format %{ "POPCNT $dst,$src\t# pop count long" %} ins_encode %{ Register Rdst = $dst$$Register; Register Rsrc = $src$$Register; Register Rtmp = $tmp$$Register;
*** 11021,11025 **** --- 11000,11005 ---- // These must follow all instruction definitions as they use the names // defined in the instructions definitions. // ============================================================================ // TYPE PROFILING RULES +
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