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src/hotspot/cpu/x86/vm_version_x86.cpp

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*** 1,7 **** /* ! * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. --- 1,7 ---- /* ! * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation.
*** 678,688 **** if (logical_processors_per_package() == 1) { // HT processor could be installed on a system which doesn't support HT. _features &= ~CPU_HT; } ! if (is_intel()) { // Intel cpus specific settings if (is_knights_family()) { _features &= ~CPU_VZEROUPPER; } } --- 678,688 ---- if (logical_processors_per_package() == 1) { // HT processor could be installed on a system which doesn't support HT. _features &= ~CPU_HT; } ! if( is_intel() ) { // Intel cpus specific settings if (is_knights_family()) { _features &= ~CPU_VZEROUPPER; } }
*** 779,789 **** if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled."); FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); } } else { ! if (supports_sse4_1()) { if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true); } } else { // The AES-CTR intrinsic stubs require AES instruction support (of course) --- 779,789 ---- if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled."); FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); } } else { ! if(supports_sse4_1()) { if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true); } } else { // The AES-CTR intrinsic stubs require AES instruction support (of course)
*** 999,1009 **** // 16 byte vectors (in XMM) are supported with SSE2+ max_vector_size = 16; } else if (UseAVX == 1 || UseAVX == 2) { // 32 bytes vectors (in YMM) are only supported with AVX+ max_vector_size = 32; ! } else if (UseAVX > 2) { // 64 bytes vectors (in ZMM) are only supported with AVX 3 max_vector_size = 64; } #ifdef _LP64 --- 999,1009 ---- // 16 byte vectors (in XMM) are supported with SSE2+ max_vector_size = 16; } else if (UseAVX == 1 || UseAVX == 2) { // 32 bytes vectors (in YMM) are only supported with AVX+ max_vector_size = 32; ! } else if (UseAVX > 2 ) { // 64 bytes vectors (in ZMM) are only supported with AVX 3 max_vector_size = 64; } #ifdef _LP64
*** 1163,1204 **** if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3); } } ! if (is_amd_family()) { // AMD cpus specific settings ! if (supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop)) { // Use it on new AMD cpus starting from Opteron. UseAddressNop = true; } ! if (supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift)) { // Use it on new AMD cpus starting from Opteron. UseNewLongLShift = true; } ! if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) { if (supports_sse4a()) { UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron } else { UseXmmLoadAndClearUpper = false; } } ! if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) { ! if (supports_sse4a()) { UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' } else { UseXmmRegToRegMoveAll = false; } } ! if (FLAG_IS_DEFAULT(UseXmmI2F)) { ! if (supports_sse4a()) { UseXmmI2F = true; } else { UseXmmI2F = false; } } ! if (FLAG_IS_DEFAULT(UseXmmI2D)) { ! if (supports_sse4a()) { UseXmmI2D = true; } else { UseXmmI2D = false; } } --- 1163,1204 ---- if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3); } } ! if( is_amd() ) { // AMD cpus specific settings ! if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { // Use it on new AMD cpus starting from Opteron. UseAddressNop = true; } ! if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { // Use it on new AMD cpus starting from Opteron. UseNewLongLShift = true; } ! if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { if (supports_sse4a()) { UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron } else { UseXmmLoadAndClearUpper = false; } } ! if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { ! if( supports_sse4a() ) { UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' } else { UseXmmRegToRegMoveAll = false; } } ! if( FLAG_IS_DEFAULT(UseXmmI2F) ) { ! if( supports_sse4a() ) { UseXmmI2F = true; } else { UseXmmI2F = false; } } ! if( FLAG_IS_DEFAULT(UseXmmI2D) ) { ! if( supports_sse4a() ) { UseXmmI2D = true; } else { UseXmmI2D = false; } }
*** 1212,1222 **** } FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); } // some defaults for AMD family 15h ! if (cpu_family() == 0x15) { // On family 15h processors default is no sw prefetch if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0); } // Also, if some other prefetch style is specified, default instruction type is PREFETCHW --- 1212,1222 ---- } FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); } // some defaults for AMD family 15h ! if ( cpu_family() == 0x15 ) { // On family 15h processors default is no sw prefetch if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0); } // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
*** 1237,1248 **** // Limit vectors size to 16 bytes on AMD cpus < 17h. FLAG_SET_DEFAULT(MaxVectorSize, 16); } #endif // COMPILER2 ! // Some defaults for AMD family 17h || Hygon family 18h ! if (cpu_family() == 0x17 || cpu_family() == 0x18) { // On family 17h processors use XMM and UnalignedLoadStores for Array Copy if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { FLAG_SET_DEFAULT(UseXMMForArrayCopy, true); } if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { --- 1237,1248 ---- // Limit vectors size to 16 bytes on AMD cpus < 17h. FLAG_SET_DEFAULT(MaxVectorSize, 16); } #endif // COMPILER2 ! // Some defaults for AMD family 17h ! if ( cpu_family() == 0x17 ) { // On family 17h processors use XMM and UnalignedLoadStores for Array Copy if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { FLAG_SET_DEFAULT(UseXMMForArrayCopy, true); } if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
*** 1254,1286 **** } #endif } } ! if (is_intel()) { // Intel cpus specific settings ! if (FLAG_IS_DEFAULT(UseStoreImmI16)) { UseStoreImmI16 = false; // don't use it on Intel cpus } ! if (cpu_family() == 6 || cpu_family() == 15) { ! if (FLAG_IS_DEFAULT(UseAddressNop)) { // Use it on all Intel cpus starting from PentiumPro UseAddressNop = true; } } ! if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) { UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus } ! if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) { ! if (supports_sse3()) { UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus } else { UseXmmRegToRegMoveAll = false; } } ! if (cpu_family() == 6 && supports_sse3()) { // New Intel cpus #ifdef COMPILER2 ! if (FLAG_IS_DEFAULT(MaxLoopPad)) { // For new Intel cpus do the next optimization: // don't align the beginning of a loop if there are enough instructions // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) // in current fetch line (OptoLoopAlignment) or the padding // is big (> MaxLoopPad). --- 1254,1286 ---- } #endif } } ! if( is_intel() ) { // Intel cpus specific settings ! if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { UseStoreImmI16 = false; // don't use it on Intel cpus } ! if( cpu_family() == 6 || cpu_family() == 15 ) { ! if( FLAG_IS_DEFAULT(UseAddressNop) ) { // Use it on all Intel cpus starting from PentiumPro UseAddressNop = true; } } ! if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus } ! if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { ! if( supports_sse3() ) { UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus } else { UseXmmRegToRegMoveAll = false; } } ! if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus #ifdef COMPILER2 ! if( FLAG_IS_DEFAULT(MaxLoopPad) ) { // For new Intel cpus do the next optimization: // don't align the beginning of a loop if there are enough instructions // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) // in current fetch line (OptoLoopAlignment) or the padding // is big (> MaxLoopPad).
*** 1322,1332 **** } if (FLAG_IS_DEFAULT(UseIncDec)) { FLAG_SET_DEFAULT(UseIncDec, false); } } ! if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3); } } #ifdef _LP64 --- 1322,1332 ---- } if (FLAG_IS_DEFAULT(UseIncDec)) { FLAG_SET_DEFAULT(UseIncDec, false); } } ! if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3); } } #ifdef _LP64
*** 1571,1639 **** } } #endif // !PRODUCT } - void VM_Version::print_platform_virtualization_info(outputStream* st) { - VirtualizationType vrt = VM_Version::get_detected_virtualization(); - if (vrt == XenHVM) { - st->print_cr("Xen hardware-assisted virtualization detected"); - } else if (vrt == KVM) { - st->print_cr("KVM virtualization detected"); - } else if (vrt == VMWare) { - st->print_cr("VMWare virtualization detected"); - } else if (vrt == HyperV) { - st->print_cr("HyperV virtualization detected"); - } - } - - void VM_Version::check_virt_cpuid(uint32_t idx, uint32_t *regs) { - // TODO support 32 bit - #if defined(_LP64) - #if defined(_MSC_VER) - // Allocate space for the code - const int code_size = 100; - ResourceMark rm; - CodeBuffer cb("detect_virt", code_size, 0); - MacroAssembler* a = new MacroAssembler(&cb); - address code = a->pc(); - void (*test)(uint32_t idx, uint32_t *regs) = (void(*)(uint32_t idx, uint32_t *regs))code; - - a->movq(r9, rbx); // save nonvolatile register - - // next line would not work on 32-bit - a->movq(rax, c_rarg0 /* rcx */); - a->movq(r8, c_rarg1 /* rdx */); - a->cpuid(); - a->movl(Address(r8, 0), rax); - a->movl(Address(r8, 4), rbx); - a->movl(Address(r8, 8), rcx); - a->movl(Address(r8, 12), rdx); - - a->movq(rbx, r9); // restore nonvolatile register - a->ret(0); - - uint32_t *code_end = (uint32_t *)a->pc(); - a->flush(); - - // execute code - (*test)(idx, regs); - #elif defined(__GNUC__) - __asm__ volatile ( - " cpuid;" - " mov %%eax,(%1);" - " mov %%ebx,4(%1);" - " mov %%ecx,8(%1);" - " mov %%edx,12(%1);" - : "+a" (idx) - : "S" (regs) - : "ebx", "ecx", "edx", "memory" ); - #endif - #endif - } - - bool VM_Version::use_biased_locking() { #if INCLUDE_RTM_OPT // RTM locking is most useful when there is high lock contention and // low data contention. With high lock contention the lock is usually // inflated and biased locking is not suitable for that case. --- 1571,1580 ----
*** 1651,1708 **** } #endif return UseBiasedLocking; } - // On Xen, the cpuid instruction returns - // eax / registers[0]: Version of Xen - // ebx / registers[1]: chars 'XenV' - // ecx / registers[2]: chars 'MMXe' - // edx / registers[3]: chars 'nVMM' - // - // On KVM / VMWare / MS Hyper-V, the cpuid instruction returns - // ebx / registers[1]: chars 'KVMK' / 'VMwa' / 'Micr' - // ecx / registers[2]: chars 'VMKV' / 'reVM' / 'osof' - // edx / registers[3]: chars 'M' / 'ware' / 't Hv' - // - // more information : - // https://kb.vmware.com/s/article/1009458 - // - void VM_Version::check_virtualizations() { - #if defined(_LP64) - uint32_t registers[4]; - char signature[13]; - uint32_t base; - signature[12] = '\0'; - memset((void*)registers, 0, 4*sizeof(uint32_t)); - - for (base = 0x40000000; base < 0x40010000; base += 0x100) { - check_virt_cpuid(base, registers); - - *(uint32_t *)(signature + 0) = registers[1]; - *(uint32_t *)(signature + 4) = registers[2]; - *(uint32_t *)(signature + 8) = registers[3]; - - if (strncmp("VMwareVMware", signature, 12) == 0) { - Abstract_VM_Version::_detected_virtualization = VMWare; - } - - if (strncmp("Microsoft Hv", signature, 12) == 0) { - Abstract_VM_Version::_detected_virtualization = HyperV; - } - - if (strncmp("KVMKVMKVM", signature, 9) == 0) { - Abstract_VM_Version::_detected_virtualization = KVM; - } - - if (strncmp("XenVMMXenVMM", signature, 12) == 0) { - Abstract_VM_Version::_detected_virtualization = XenHVM; - } - } - #endif - } - void VM_Version::initialize() { ResourceMark rm; // Making this stub must be FIRST use of assembler stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); --- 1592,1601 ----
*** 1713,1721 **** VM_Version_StubGenerator g(&c); get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, g.generate_get_cpu_info()); get_processor_features(); - if (cpu_family() > 4) { // it supports CPUID - check_virtualizations(); - } } --- 1606,1611 ----
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