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src/hotspot/cpu/x86/vm_version_x86.cpp

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   1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "logging/log.hpp"
  30 #include "logging/logStream.hpp"
  31 #include "memory/resourceArea.hpp"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "utilities/virtualizationSupport.hpp"
  36 #include "vm_version_x86.hpp"
  37 
  38 
  39 int VM_Version::_cpu;
  40 int VM_Version::_model;
  41 int VM_Version::_stepping;
  42 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
  43 
  44 // Address of instruction which causes SEGV
  45 address VM_Version::_cpuinfo_segv_addr = 0;
  46 // Address of instruction after the one which causes SEGV
  47 address VM_Version::_cpuinfo_cont_addr = 0;
  48 
  49 static BufferBlob* stub_blob;
  50 static const int stub_size = 1100;
  51 
  52 extern "C" {
  53   typedef void (*get_cpu_info_stub_t)(void*);
  54 }
  55 static get_cpu_info_stub_t get_cpu_info_stub = NULL;


 664     _features &= ~CPU_AVX512BW;
 665     _features &= ~CPU_AVX512VL;
 666     _features &= ~CPU_AVX512_VPOPCNTDQ;
 667     _features &= ~CPU_VPCLMULQDQ;
 668     _features &= ~CPU_VAES;
 669   }
 670 
 671   if (UseAVX < 2)
 672     _features &= ~CPU_AVX2;
 673 
 674   if (UseAVX < 1) {
 675     _features &= ~CPU_AVX;
 676     _features &= ~CPU_VZEROUPPER;
 677   }
 678 
 679   if (logical_processors_per_package() == 1) {
 680     // HT processor could be installed on a system which doesn't support HT.
 681     _features &= ~CPU_HT;
 682   }
 683 
 684   if (is_intel()) { // Intel cpus specific settings
 685     if (is_knights_family()) {
 686       _features &= ~CPU_VZEROUPPER;
 687     }
 688   }
 689 
 690   char buf[256];
 691   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 692                cores_per_cpu(), threads_per_core(),
 693                cpu_family(), _model, _stepping,
 694                (supports_cmov() ? ", cmov" : ""),
 695                (supports_cmpxchg8() ? ", cx8" : ""),
 696                (supports_fxsr() ? ", fxsr" : ""),
 697                (supports_mmx()  ? ", mmx"  : ""),
 698                (supports_sse()  ? ", sse"  : ""),
 699                (supports_sse2() ? ", sse2" : ""),
 700                (supports_sse3() ? ", sse3" : ""),
 701                (supports_ssse3()? ", ssse3": ""),
 702                (supports_sse4_1() ? ", sse4.1" : ""),
 703                (supports_sse4_2() ? ", sse4.2" : ""),
 704                (supports_popcnt() ? ", popcnt" : ""),


 765       if (UseSSE > 2) {
 766         if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 767           FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 768         }
 769       } else {
 770         // The AES intrinsic stubs require AES instruction support (of course)
 771         // but also require sse3 mode or higher for instructions it use.
 772         if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 773           warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
 774         }
 775         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 776       }
 777 
 778       // --AES-CTR begins--
 779       if (!UseAESIntrinsics) {
 780         if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 781           warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
 782           FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 783         }
 784       } else {
 785         if (supports_sse4_1()) {
 786           if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 787             FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
 788           }
 789         } else {
 790            // The AES-CTR intrinsic stubs require AES instruction support (of course)
 791            // but also require sse4.1 mode or higher for instructions it use.
 792           if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 793              warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
 794            }
 795            FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 796         }
 797       }
 798       // --AES-CTR ends--
 799     }
 800   } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
 801     if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
 802       warning("AES instructions are not available on this CPU");
 803       FLAG_SET_DEFAULT(UseAES, false);
 804     }
 805     if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {


 985   if (UseFPUForSpilling) {
 986     if (UseSSE < 2) {
 987       // Only supported with SSE2+
 988       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 989     }
 990   }
 991 #endif
 992 
 993 #if COMPILER2_OR_JVMCI
 994   int max_vector_size = 0;
 995   if (UseSSE < 2) {
 996     // Vectors (in XMM) are only supported with SSE2+
 997     // SSE is always 2 on x64.
 998     max_vector_size = 0;
 999   } else if (UseAVX == 0 || !os_supports_avx_vectors()) {
1000     // 16 byte vectors (in XMM) are supported with SSE2+
1001     max_vector_size = 16;
1002   } else if (UseAVX == 1 || UseAVX == 2) {
1003     // 32 bytes vectors (in YMM) are only supported with AVX+
1004     max_vector_size = 32;
1005   } else if (UseAVX > 2) {
1006     // 64 bytes vectors (in ZMM) are only supported with AVX 3
1007     max_vector_size = 64;
1008   }
1009 
1010 #ifdef _LP64
1011   int min_vector_size = 4; // We require MaxVectorSize to be at least 4 on 64bit
1012 #else
1013   int min_vector_size = 0;
1014 #endif
1015 
1016   if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
1017     if (MaxVectorSize < min_vector_size) {
1018       warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
1019       FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
1020     }
1021     if (MaxVectorSize > max_vector_size) {
1022       warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
1023       FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1024     }
1025     if (!is_power_of_2(MaxVectorSize)) {


1149           UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
1150         }
1151       }
1152       if (supports_sse4_2()) {
1153         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1154           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1155         }
1156       } else {
1157         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1158           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1159         }
1160         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1161       }
1162     }
1163 
1164     if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1165       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1166     }
1167   }
1168 
1169   if (is_amd_family()) { // AMD cpus specific settings
1170     if (supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop)) {
1171       // Use it on new AMD cpus starting from Opteron.
1172       UseAddressNop = true;
1173     }
1174     if (supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift)) {
1175       // Use it on new AMD cpus starting from Opteron.
1176       UseNewLongLShift = true;
1177     }
1178     if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1179       if (supports_sse4a()) {
1180         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1181       } else {
1182         UseXmmLoadAndClearUpper = false;
1183       }
1184     }
1185     if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1186       if (supports_sse4a()) {
1187         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1188       } else {
1189         UseXmmRegToRegMoveAll = false;
1190       }
1191     }
1192     if (FLAG_IS_DEFAULT(UseXmmI2F)) {
1193       if (supports_sse4a()) {
1194         UseXmmI2F = true;
1195       } else {
1196         UseXmmI2F = false;
1197       }
1198     }
1199     if (FLAG_IS_DEFAULT(UseXmmI2D)) {
1200       if (supports_sse4a()) {
1201         UseXmmI2D = true;
1202       } else {
1203         UseXmmI2D = false;
1204       }
1205     }
1206     if (supports_sse4_2()) {
1207       if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1208         FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1209       }
1210     } else {
1211       if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1212         warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1213       }
1214       FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1215     }
1216 
1217     // some defaults for AMD family 15h
1218     if (cpu_family() == 0x15) {
1219       // On family 15h processors default is no sw prefetch
1220       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1221         FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1222       }
1223       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1224       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1225         FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1226       }
1227       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1228       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1229         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1230       }
1231       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1232         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1233       }
1234     }
1235 
1236 #ifdef COMPILER2
1237     if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1238       // Limit vectors size to 16 bytes on AMD cpus < 17h.
1239       FLAG_SET_DEFAULT(MaxVectorSize, 16);
1240     }
1241 #endif // COMPILER2
1242 
1243     // Some defaults for AMD family 17h || Hygon family 18h
1244     if (cpu_family() == 0x17 || cpu_family() == 0x18) {
1245       // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1246       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1247         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1248       }
1249       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1250         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1251       }
1252 #ifdef COMPILER2
1253       if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1254         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1255       }
1256 #endif
1257     }
1258   }
1259 
1260   if (is_intel()) { // Intel cpus specific settings
1261     if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1262       UseStoreImmI16 = false; // don't use it on Intel cpus
1263     }
1264     if (cpu_family() == 6 || cpu_family() == 15) {
1265       if (FLAG_IS_DEFAULT(UseAddressNop)) {
1266         // Use it on all Intel cpus starting from PentiumPro
1267         UseAddressNop = true;
1268       }
1269     }
1270     if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1271       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1272     }
1273     if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1274       if (supports_sse3()) {
1275         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1276       } else {
1277         UseXmmRegToRegMoveAll = false;
1278       }
1279     }
1280     if (cpu_family() == 6 && supports_sse3()) { // New Intel cpus
1281 #ifdef COMPILER2
1282       if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1283         // For new Intel cpus do the next optimization:
1284         // don't align the beginning of a loop if there are enough instructions
1285         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1286         // in current fetch line (OptoLoopAlignment) or the padding
1287         // is big (> MaxLoopPad).
1288         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1289         // generated NOP instructions. 11 is the largest size of one
1290         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1291         MaxLoopPad = 11;
1292       }
1293 #endif // COMPILER2
1294       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1295         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1296       }
1297       if ((supports_sse4_2() && supports_ht()) || supports_avx()) { // Newest Intel cpus
1298         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1299           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1300         }
1301       }
1302       if (supports_sse4_2()) {


1308           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1309         }
1310         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1311       }
1312     }
1313     if (is_atom_family() || is_knights_family()) {
1314 #ifdef COMPILER2
1315       if (FLAG_IS_DEFAULT(OptoScheduling)) {
1316         OptoScheduling = true;
1317       }
1318 #endif
1319       if (supports_sse4_2()) { // Silvermont
1320         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1321           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1322         }
1323       }
1324       if (FLAG_IS_DEFAULT(UseIncDec)) {
1325         FLAG_SET_DEFAULT(UseIncDec, false);
1326       }
1327     }
1328     if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1329       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1330     }
1331   }
1332 
1333 #ifdef _LP64
1334   if (UseSSE42Intrinsics) {
1335     if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1336       UseVectorizedMismatchIntrinsic = true;
1337     }
1338   } else if (UseVectorizedMismatchIntrinsic) {
1339     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1340       warning("vectorizedMismatch intrinsics are not available on this CPU");
1341     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1342   }
1343 #else
1344   if (UseVectorizedMismatchIntrinsic) {
1345     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1346       warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1347     }
1348     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);


1557         log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1558       }
1559     }
1560 
1561     if (PrefetchCopyIntervalInBytes > 0) {
1562       log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1563     }
1564     if (PrefetchScanIntervalInBytes > 0) {
1565       log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1566     }
1567     if (PrefetchFieldsAhead > 0) {
1568       log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1569     }
1570     if (ContendedPaddingWidth > 0) {
1571       log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1572     }
1573   }
1574 #endif // !PRODUCT
1575 }
1576 
1577 void VM_Version::print_platform_virtualization_info(outputStream* st) {
1578   VirtualizationType vrt = VM_Version::get_detected_virtualization();
1579   if (vrt == XenHVM) {
1580     st->print_cr("Xen hardware-assisted virtualization detected");
1581   } else if (vrt == KVM) {
1582     st->print_cr("KVM virtualization detected");
1583   } else if (vrt == VMWare) {
1584     st->print_cr("VMWare virtualization detected");
1585     VirtualizationSupport::print_virtualization_info(st);
1586   } else if (vrt == HyperV) {
1587     st->print_cr("HyperV virtualization detected");
1588   }
1589 }
1590 
1591 void VM_Version::check_virt_cpuid(uint32_t idx, uint32_t *regs) {
1592 // TODO support 32 bit
1593 #if defined(_LP64)
1594 #if defined(_MSC_VER)
1595   // Allocate space for the code
1596   const int code_size = 100;
1597   ResourceMark rm;
1598   CodeBuffer cb("detect_virt", code_size, 0);
1599   MacroAssembler* a = new MacroAssembler(&cb);
1600   address code = a->pc();
1601   void (*test)(uint32_t idx, uint32_t *regs) = (void(*)(uint32_t idx, uint32_t *regs))code;
1602 
1603   a->movq(r9, rbx); // save nonvolatile register
1604 
1605   // next line would not work on 32-bit
1606   a->movq(rax, c_rarg0 /* rcx */);
1607   a->movq(r8, c_rarg1 /* rdx */);
1608   a->cpuid();
1609   a->movl(Address(r8,  0), rax);
1610   a->movl(Address(r8,  4), rbx);
1611   a->movl(Address(r8,  8), rcx);
1612   a->movl(Address(r8, 12), rdx);
1613 
1614   a->movq(rbx, r9); // restore nonvolatile register
1615   a->ret(0);
1616 
1617   uint32_t *code_end = (uint32_t *)a->pc();
1618   a->flush();
1619 
1620   // execute code
1621   (*test)(idx, regs);
1622 #elif defined(__GNUC__)
1623   __asm__ volatile (
1624      "        cpuid;"
1625      "        mov %%eax,(%1);"
1626      "        mov %%ebx,4(%1);"
1627      "        mov %%ecx,8(%1);"
1628      "        mov %%edx,12(%1);"
1629      : "+a" (idx)
1630      : "S" (regs)
1631      : "ebx", "ecx", "edx", "memory" );
1632 #endif
1633 #endif
1634 }
1635 
1636 
1637 bool VM_Version::use_biased_locking() {
1638 #if INCLUDE_RTM_OPT
1639   // RTM locking is most useful when there is high lock contention and
1640   // low data contention.  With high lock contention the lock is usually
1641   // inflated and biased locking is not suitable for that case.
1642   // RTM locking code requires that biased locking is off.
1643   // Note: we can't switch off UseBiasedLocking in get_processor_features()
1644   // because it is used by Thread::allocate() which is called before
1645   // VM_Version::initialize().
1646   if (UseRTMLocking && UseBiasedLocking) {
1647     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1648       FLAG_SET_DEFAULT(UseBiasedLocking, false);
1649     } else {
1650       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1651       UseBiasedLocking = false;
1652     }
1653   }
1654 #endif
1655   return UseBiasedLocking;
1656 }
1657 
1658 // On Xen, the cpuid instruction returns
1659 //  eax / registers[0]: Version of Xen
1660 //  ebx / registers[1]: chars 'XenV'
1661 //  ecx / registers[2]: chars 'MMXe'
1662 //  edx / registers[3]: chars 'nVMM'
1663 //
1664 // On KVM / VMWare / MS Hyper-V, the cpuid instruction returns
1665 //  ebx / registers[1]: chars 'KVMK' / 'VMwa' / 'Micr'
1666 //  ecx / registers[2]: chars 'VMKV' / 'reVM' / 'osof'
1667 //  edx / registers[3]: chars 'M'    / 'ware' / 't Hv'
1668 //
1669 // more information :
1670 // https://kb.vmware.com/s/article/1009458
1671 //
1672 void VM_Version::check_virtualizations() {
1673 #if defined(_LP64)
1674   uint32_t registers[4];
1675   char signature[13];
1676   uint32_t base;
1677   signature[12] = '\0';
1678   memset((void*)registers, 0, 4*sizeof(uint32_t));
1679 
1680   for (base = 0x40000000; base < 0x40010000; base += 0x100) {
1681     check_virt_cpuid(base, registers);
1682 
1683     *(uint32_t *)(signature + 0) = registers[1];
1684     *(uint32_t *)(signature + 4) = registers[2];
1685     *(uint32_t *)(signature + 8) = registers[3];
1686 
1687     if (strncmp("VMwareVMware", signature, 12) == 0) {
1688       Abstract_VM_Version::_detected_virtualization = VMWare;
1689       // check for extended metrics from guestlib
1690       VirtualizationSupport::initialize();
1691     }
1692 
1693     if (strncmp("Microsoft Hv", signature, 12) == 0) {
1694       Abstract_VM_Version::_detected_virtualization = HyperV;
1695     }
1696 
1697     if (strncmp("KVMKVMKVM", signature, 9) == 0) {
1698       Abstract_VM_Version::_detected_virtualization = KVM;
1699     }
1700 
1701     if (strncmp("XenVMMXenVMM", signature, 12) == 0) {
1702       Abstract_VM_Version::_detected_virtualization = XenHVM;
1703     }
1704   }
1705 #endif
1706 }
1707 
1708 void VM_Version::initialize() {
1709   ResourceMark rm;
1710   // Making this stub must be FIRST use of assembler
1711 
1712   stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1713   if (stub_blob == NULL) {
1714     vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1715   }
1716   CodeBuffer c(stub_blob);
1717   VM_Version_StubGenerator g(&c);
1718   get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1719                                      g.generate_get_cpu_info());
1720 
1721   get_processor_features();
1722   if (cpu_family() > 4) { // it supports CPUID
1723     check_virtualizations();
1724   }
1725 }
   1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "logging/log.hpp"
  30 #include "logging/logStream.hpp"
  31 #include "memory/resourceArea.hpp"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"

  35 #include "vm_version_x86.hpp"
  36 
  37 
  38 int VM_Version::_cpu;
  39 int VM_Version::_model;
  40 int VM_Version::_stepping;
  41 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
  42 
  43 // Address of instruction which causes SEGV
  44 address VM_Version::_cpuinfo_segv_addr = 0;
  45 // Address of instruction after the one which causes SEGV
  46 address VM_Version::_cpuinfo_cont_addr = 0;
  47 
  48 static BufferBlob* stub_blob;
  49 static const int stub_size = 1100;
  50 
  51 extern "C" {
  52   typedef void (*get_cpu_info_stub_t)(void*);
  53 }
  54 static get_cpu_info_stub_t get_cpu_info_stub = NULL;


 663     _features &= ~CPU_AVX512BW;
 664     _features &= ~CPU_AVX512VL;
 665     _features &= ~CPU_AVX512_VPOPCNTDQ;
 666     _features &= ~CPU_VPCLMULQDQ;
 667     _features &= ~CPU_VAES;
 668   }
 669 
 670   if (UseAVX < 2)
 671     _features &= ~CPU_AVX2;
 672 
 673   if (UseAVX < 1) {
 674     _features &= ~CPU_AVX;
 675     _features &= ~CPU_VZEROUPPER;
 676   }
 677 
 678   if (logical_processors_per_package() == 1) {
 679     // HT processor could be installed on a system which doesn't support HT.
 680     _features &= ~CPU_HT;
 681   }
 682 
 683   if( is_intel() ) { // Intel cpus specific settings
 684     if (is_knights_family()) {
 685       _features &= ~CPU_VZEROUPPER;
 686     }
 687   }
 688 
 689   char buf[256];
 690   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 691                cores_per_cpu(), threads_per_core(),
 692                cpu_family(), _model, _stepping,
 693                (supports_cmov() ? ", cmov" : ""),
 694                (supports_cmpxchg8() ? ", cx8" : ""),
 695                (supports_fxsr() ? ", fxsr" : ""),
 696                (supports_mmx()  ? ", mmx"  : ""),
 697                (supports_sse()  ? ", sse"  : ""),
 698                (supports_sse2() ? ", sse2" : ""),
 699                (supports_sse3() ? ", sse3" : ""),
 700                (supports_ssse3()? ", ssse3": ""),
 701                (supports_sse4_1() ? ", sse4.1" : ""),
 702                (supports_sse4_2() ? ", sse4.2" : ""),
 703                (supports_popcnt() ? ", popcnt" : ""),


 764       if (UseSSE > 2) {
 765         if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 766           FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 767         }
 768       } else {
 769         // The AES intrinsic stubs require AES instruction support (of course)
 770         // but also require sse3 mode or higher for instructions it use.
 771         if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 772           warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
 773         }
 774         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 775       }
 776 
 777       // --AES-CTR begins--
 778       if (!UseAESIntrinsics) {
 779         if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 780           warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
 781           FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 782         }
 783       } else {
 784         if(supports_sse4_1()) {
 785           if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 786             FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
 787           }
 788         } else {
 789            // The AES-CTR intrinsic stubs require AES instruction support (of course)
 790            // but also require sse4.1 mode or higher for instructions it use.
 791           if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 792              warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
 793            }
 794            FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 795         }
 796       }
 797       // --AES-CTR ends--
 798     }
 799   } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
 800     if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
 801       warning("AES instructions are not available on this CPU");
 802       FLAG_SET_DEFAULT(UseAES, false);
 803     }
 804     if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {


 984   if (UseFPUForSpilling) {
 985     if (UseSSE < 2) {
 986       // Only supported with SSE2+
 987       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 988     }
 989   }
 990 #endif
 991 
 992 #if COMPILER2_OR_JVMCI
 993   int max_vector_size = 0;
 994   if (UseSSE < 2) {
 995     // Vectors (in XMM) are only supported with SSE2+
 996     // SSE is always 2 on x64.
 997     max_vector_size = 0;
 998   } else if (UseAVX == 0 || !os_supports_avx_vectors()) {
 999     // 16 byte vectors (in XMM) are supported with SSE2+
1000     max_vector_size = 16;
1001   } else if (UseAVX == 1 || UseAVX == 2) {
1002     // 32 bytes vectors (in YMM) are only supported with AVX+
1003     max_vector_size = 32;
1004   } else if (UseAVX > 2 ) {
1005     // 64 bytes vectors (in ZMM) are only supported with AVX 3
1006     max_vector_size = 64;
1007   }
1008 
1009 #ifdef _LP64
1010   int min_vector_size = 4; // We require MaxVectorSize to be at least 4 on 64bit
1011 #else
1012   int min_vector_size = 0;
1013 #endif
1014 
1015   if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
1016     if (MaxVectorSize < min_vector_size) {
1017       warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
1018       FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
1019     }
1020     if (MaxVectorSize > max_vector_size) {
1021       warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
1022       FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1023     }
1024     if (!is_power_of_2(MaxVectorSize)) {


1148           UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
1149         }
1150       }
1151       if (supports_sse4_2()) {
1152         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1153           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1154         }
1155       } else {
1156         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1157           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1158         }
1159         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1160       }
1161     }
1162 
1163     if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1164       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1165     }
1166   }
1167 
1168   if( is_amd() ) { // AMD cpus specific settings
1169     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1170       // Use it on new AMD cpus starting from Opteron.
1171       UseAddressNop = true;
1172     }
1173     if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1174       // Use it on new AMD cpus starting from Opteron.
1175       UseNewLongLShift = true;
1176     }
1177     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1178       if (supports_sse4a()) {
1179         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1180       } else {
1181         UseXmmLoadAndClearUpper = false;
1182       }
1183     }
1184     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1185       if( supports_sse4a() ) {
1186         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1187       } else {
1188         UseXmmRegToRegMoveAll = false;
1189       }
1190     }
1191     if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1192       if( supports_sse4a() ) {
1193         UseXmmI2F = true;
1194       } else {
1195         UseXmmI2F = false;
1196       }
1197     }
1198     if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1199       if( supports_sse4a() ) {
1200         UseXmmI2D = true;
1201       } else {
1202         UseXmmI2D = false;
1203       }
1204     }
1205     if (supports_sse4_2()) {
1206       if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1207         FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1208       }
1209     } else {
1210       if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1211         warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1212       }
1213       FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1214     }
1215 
1216     // some defaults for AMD family 15h
1217     if ( cpu_family() == 0x15 ) {
1218       // On family 15h processors default is no sw prefetch
1219       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1220         FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1221       }
1222       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1223       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1224         FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1225       }
1226       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1227       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1228         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1229       }
1230       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1231         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1232       }
1233     }
1234 
1235 #ifdef COMPILER2
1236     if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1237       // Limit vectors size to 16 bytes on AMD cpus < 17h.
1238       FLAG_SET_DEFAULT(MaxVectorSize, 16);
1239     }
1240 #endif // COMPILER2
1241 
1242     // Some defaults for AMD family 17h
1243     if ( cpu_family() == 0x17 ) {
1244       // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1245       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1246         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1247       }
1248       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1249         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1250       }
1251 #ifdef COMPILER2
1252       if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1253         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1254       }
1255 #endif
1256     }
1257   }
1258 
1259   if( is_intel() ) { // Intel cpus specific settings
1260     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1261       UseStoreImmI16 = false; // don't use it on Intel cpus
1262     }
1263     if( cpu_family() == 6 || cpu_family() == 15 ) {
1264       if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1265         // Use it on all Intel cpus starting from PentiumPro
1266         UseAddressNop = true;
1267       }
1268     }
1269     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1270       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1271     }
1272     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1273       if( supports_sse3() ) {
1274         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1275       } else {
1276         UseXmmRegToRegMoveAll = false;
1277       }
1278     }
1279     if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1280 #ifdef COMPILER2
1281       if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1282         // For new Intel cpus do the next optimization:
1283         // don't align the beginning of a loop if there are enough instructions
1284         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1285         // in current fetch line (OptoLoopAlignment) or the padding
1286         // is big (> MaxLoopPad).
1287         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1288         // generated NOP instructions. 11 is the largest size of one
1289         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1290         MaxLoopPad = 11;
1291       }
1292 #endif // COMPILER2
1293       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1294         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1295       }
1296       if ((supports_sse4_2() && supports_ht()) || supports_avx()) { // Newest Intel cpus
1297         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1298           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1299         }
1300       }
1301       if (supports_sse4_2()) {


1307           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1308         }
1309         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1310       }
1311     }
1312     if (is_atom_family() || is_knights_family()) {
1313 #ifdef COMPILER2
1314       if (FLAG_IS_DEFAULT(OptoScheduling)) {
1315         OptoScheduling = true;
1316       }
1317 #endif
1318       if (supports_sse4_2()) { // Silvermont
1319         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1320           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1321         }
1322       }
1323       if (FLAG_IS_DEFAULT(UseIncDec)) {
1324         FLAG_SET_DEFAULT(UseIncDec, false);
1325       }
1326     }
1327     if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1328       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1329     }
1330   }
1331 
1332 #ifdef _LP64
1333   if (UseSSE42Intrinsics) {
1334     if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1335       UseVectorizedMismatchIntrinsic = true;
1336     }
1337   } else if (UseVectorizedMismatchIntrinsic) {
1338     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1339       warning("vectorizedMismatch intrinsics are not available on this CPU");
1340     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1341   }
1342 #else
1343   if (UseVectorizedMismatchIntrinsic) {
1344     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1345       warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1346     }
1347     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);


1556         log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1557       }
1558     }
1559 
1560     if (PrefetchCopyIntervalInBytes > 0) {
1561       log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1562     }
1563     if (PrefetchScanIntervalInBytes > 0) {
1564       log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1565     }
1566     if (PrefetchFieldsAhead > 0) {
1567       log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1568     }
1569     if (ContendedPaddingWidth > 0) {
1570       log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1571     }
1572   }
1573 #endif // !PRODUCT
1574 }
1575 




























































1576 bool VM_Version::use_biased_locking() {
1577 #if INCLUDE_RTM_OPT
1578   // RTM locking is most useful when there is high lock contention and
1579   // low data contention.  With high lock contention the lock is usually
1580   // inflated and biased locking is not suitable for that case.
1581   // RTM locking code requires that biased locking is off.
1582   // Note: we can't switch off UseBiasedLocking in get_processor_features()
1583   // because it is used by Thread::allocate() which is called before
1584   // VM_Version::initialize().
1585   if (UseRTMLocking && UseBiasedLocking) {
1586     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1587       FLAG_SET_DEFAULT(UseBiasedLocking, false);
1588     } else {
1589       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1590       UseBiasedLocking = false;
1591     }
1592   }
1593 #endif
1594   return UseBiasedLocking;
1595 }
1596 


















































1597 void VM_Version::initialize() {
1598   ResourceMark rm;
1599   // Making this stub must be FIRST use of assembler
1600 
1601   stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1602   if (stub_blob == NULL) {
1603     vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1604   }
1605   CodeBuffer c(stub_blob);
1606   VM_Version_StubGenerator g(&c);
1607   get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1608                                      g.generate_get_cpu_info());
1609 
1610   get_processor_features();



1611 }
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