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src/hotspot/cpu/x86/vm_version_x86.hpp

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*** 493,509 **** uint64_t result = 0; if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) result |= CPU_CX8; if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) result |= CPU_CMOV; ! if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd_family() && _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) result |= CPU_FXSR; // HT flag is set for multi-core processors also. if (threads_per_core() > 1) result |= CPU_HT; ! if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd_family() && _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) result |= CPU_MMX; if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) result |= CPU_SSE; if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) --- 493,509 ---- uint64_t result = 0; if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) result |= CPU_CX8; if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) result |= CPU_CMOV; ! if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) result |= CPU_FXSR; // HT flag is set for multi-core processors also. if (threads_per_core() > 1) result |= CPU_HT; ! if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) result |= CPU_MMX; if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) result |= CPU_SSE; if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
*** 551,561 **** result |= CPU_VAES; if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0) result |= CPU_VNNI; } } ! if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) result |= CPU_BMI1; if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) result |= CPU_TSC; if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) result |= CPU_TSCINV; --- 551,561 ---- result |= CPU_VAES; if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0) result |= CPU_VNNI; } } ! if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) result |= CPU_BMI1; if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) result |= CPU_TSC; if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) result |= CPU_TSCINV;
*** 565,596 **** result |= CPU_ERMS; if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) result |= CPU_CLMUL; if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) result |= CPU_RTM; ! if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0) result |= CPU_ADX; ! if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) result |= CPU_BMI2; if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0) result |= CPU_SHA; if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0) result |= CPU_FMA; ! // AMD|Hygon features. ! if (is_amd_family()) { if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) result |= CPU_3DNOW_PREFETCH; if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) result |= CPU_LZCNT; if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) result |= CPU_SSE4A; } // Intel features. ! if (is_intel()) { ! if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) result |= CPU_LZCNT; // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { result |= CPU_3DNOW_PREFETCH; } --- 565,596 ---- result |= CPU_ERMS; if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) result |= CPU_CLMUL; if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) result |= CPU_RTM; ! if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0) result |= CPU_ADX; ! if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) result |= CPU_BMI2; if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0) result |= CPU_SHA; if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0) result |= CPU_FMA; ! // AMD features. ! if (is_amd()) { if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) result |= CPU_3DNOW_PREFETCH; if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) result |= CPU_LZCNT; if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) result |= CPU_SSE4A; } // Intel features. ! if(is_intel()) { ! if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) result |= CPU_LZCNT; // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) { result |= CPU_3DNOW_PREFETCH; }
*** 684,696 **** // Initialization static void initialize(); // Override Abstract_VM_Version implementation - static void print_platform_virtualization_info(outputStream*); - - // Override Abstract_VM_Version implementation static bool use_biased_locking(); // Asserts static void assert_is_initialized() { assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); --- 684,693 ----
*** 712,723 **** // determine whether a particular instruction is supported. // static int cpu_family() { return _cpu;} static bool is_P6() { return cpu_family() >= 6; } static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' - static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH' - static bool is_amd_family() { return is_amd() || is_hygon(); } static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS ' static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton static bool is_knights_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi --- 709,718 ----
*** 737,747 **** _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; } if (!supports_topology || result == 0) { result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); } ! } else if (is_amd_family()) { result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); } else if (is_zx()) { bool supports_topology = supports_processor_topology(); if (supports_topology) { result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / --- 732,742 ---- _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; } if (!supports_topology || result == 0) { result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); } ! } else if (is_amd()) { result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); } else if (is_zx()) { bool supports_topology = supports_processor_topology(); if (supports_topology) { result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
*** 773,783 **** static intx L1_line_size() { intx result = 0; if (is_intel()) { result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); ! } else if (is_amd_family()) { result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; } else if (is_zx()) { result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); } if (result < 32) // not defined ? --- 768,778 ---- static intx L1_line_size() { intx result = 0; if (is_intel()) { result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); ! } else if (is_amd()) { result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; } else if (is_zx()) { result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); } if (result < 32) // not defined ?
*** 860,870 **** return false; } // AMD features static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; } ! static bool supports_mmx_ext() { return is_amd_family() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; } static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; } static bool is_amd_Barcelona() { return is_amd() && extended_cpu_family() == CPU_FAMILY_AMD_11H; } --- 855,865 ---- return false; } // AMD features static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; } ! static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; } static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; } static bool is_amd_Barcelona() { return is_amd() && extended_cpu_family() == CPU_FAMILY_AMD_11H; }
*** 873,884 **** static bool supports_tscinv_bit() { return (_features & CPU_TSCINV) != 0; } static bool supports_tscinv() { return supports_tscinv_bit() && ! ((is_amd_family() && !is_amd_Barcelona()) || ! is_intel_tsc_synched_at_init()); } // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && supports_sse3() && _model != 0x1C; } --- 868,879 ---- static bool supports_tscinv_bit() { return (_features & CPU_TSCINV) != 0; } static bool supports_tscinv() { return supports_tscinv_bit() && ! ( (is_amd() && !is_amd_Barcelona()) || ! is_intel_tsc_synched_at_init() ); } // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && supports_sse3() && _model != 0x1C; }
*** 899,909 **** // Athlon - 128 / prefetchnta // Opteron - 256 / prefetchnta // Core - 256 / prefetchnta // It will be used only when AllocatePrefetchStyle > 0 ! if (is_amd_family()) { // AMD | Hygon if (supports_sse2()) { return 256; // Opteron } else { return 128; // Athlon } --- 894,904 ---- // Athlon - 128 / prefetchnta // Opteron - 256 / prefetchnta // Core - 256 / prefetchnta // It will be used only when AllocatePrefetchStyle > 0 ! if (is_amd()) { // AMD if (supports_sse2()) { return 256; // Opteron } else { return 128; // Athlon }
*** 933,945 **** // SSE2 and later processors implement a 'pause' instruction // that can be used for efficient implementation of // the intrinsic for java.lang.Thread.onSpinWait() static bool supports_on_spin_wait() { return supports_sse2(); } - - // support functions for virtualization detection - private: - static void check_virt_cpuid(uint32_t idx, uint32_t *regs); - static void check_virtualizations(); }; #endif // CPU_X86_VM_VERSION_X86_HPP --- 928,935 ----
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