< prev index next >

src/hotspot/cpu/x86/vm_version_x86.hpp

Print this page




 478     result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
 479     return result;
 480   }
 481 
 482   static uint32_t cpu_stepping() {
 483     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
 484     return result;
 485   }
 486 
 487   static uint logical_processor_count() {
 488     uint result = threads_per_core();
 489     return result;
 490   }
 491 
 492   static uint64_t feature_flags() {
 493     uint64_t result = 0;
 494     if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
 495       result |= CPU_CX8;
 496     if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
 497       result |= CPU_CMOV;
 498     if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd_family() &&
 499         _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
 500       result |= CPU_FXSR;
 501     // HT flag is set for multi-core processors also.
 502     if (threads_per_core() > 1)
 503       result |= CPU_HT;
 504     if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd_family() &&
 505         _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
 506       result |= CPU_MMX;
 507     if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
 508       result |= CPU_SSE;
 509     if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
 510       result |= CPU_SSE2;
 511     if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
 512       result |= CPU_SSE3;
 513     if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
 514       result |= CPU_SSSE3;
 515     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
 516       result |= CPU_SSE4_1;
 517     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
 518       result |= CPU_SSE4_2;
 519     if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
 520       result |= CPU_POPCNT;
 521     if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
 522         _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
 523         _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
 524         _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {


 536         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
 537           result |= CPU_AVX512DQ;
 538         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
 539           result |= CPU_AVX512PF;
 540         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
 541           result |= CPU_AVX512ER;
 542         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
 543           result |= CPU_AVX512BW;
 544         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
 545           result |= CPU_AVX512VL;
 546         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0)
 547           result |= CPU_AVX512_VPOPCNTDQ;
 548         if (_cpuid_info.sef_cpuid7_ecx.bits.vpclmulqdq != 0)
 549           result |= CPU_VPCLMULQDQ;
 550         if (_cpuid_info.sef_cpuid7_ecx.bits.vaes != 0)
 551           result |= CPU_VAES;
 552         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0)
 553           result |= CPU_VNNI;
 554       }
 555     }
 556     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
 557       result |= CPU_BMI1;
 558     if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
 559       result |= CPU_TSC;
 560     if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
 561       result |= CPU_TSCINV;
 562     if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
 563       result |= CPU_AES;
 564     if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
 565       result |= CPU_ERMS;
 566     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
 567       result |= CPU_CLMUL;
 568     if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
 569       result |= CPU_RTM;
 570     if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
 571        result |= CPU_ADX;
 572     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
 573       result |= CPU_BMI2;
 574     if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
 575       result |= CPU_SHA;
 576     if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
 577       result |= CPU_FMA;
 578 
 579     // AMD|Hygon features.
 580     if (is_amd_family()) {
 581       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
 582           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
 583         result |= CPU_3DNOW_PREFETCH;
 584       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
 585         result |= CPU_LZCNT;
 586       if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
 587         result |= CPU_SSE4A;
 588     }
 589     // Intel features.
 590     if (is_intel()) {
 591       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 592         result |= CPU_LZCNT;
 593       // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 594       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 595         result |= CPU_3DNOW_PREFETCH;
 596       }
 597     }
 598 
 599     // ZX features.
 600     if (is_zx()) {
 601       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 602         result |= CPU_LZCNT;
 603       // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 604       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 605         result |= CPU_3DNOW_PREFETCH;
 606       }
 607     }
 608 
 609     return result;
 610   }
 611 


 669   static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
 670 
 671   // The value used to check ymm register after signal handle
 672   static int ymm_test_value()    { return 0xCAFEBABE; }
 673 
 674   static void get_cpu_info_wrapper();
 675   static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
 676   static bool  is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
 677   static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
 678   static address  cpuinfo_cont_addr()           { return _cpuinfo_cont_addr; }
 679 
 680   static void clean_cpuFeatures()   { _features = 0; }
 681   static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); }
 682   static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); }
 683 
 684 
 685   // Initialization
 686   static void initialize();
 687 
 688   // Override Abstract_VM_Version implementation
 689   static void print_platform_virtualization_info(outputStream*);
 690 
 691   // Override Abstract_VM_Version implementation
 692   static bool use_biased_locking();
 693 
 694   // Asserts
 695   static void assert_is_initialized() {
 696     assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
 697   }
 698 
 699   //
 700   // Processor family:
 701   //       3   -  386
 702   //       4   -  486
 703   //       5   -  Pentium
 704   //       6   -  PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
 705   //              Pentium M, Core Solo, Core Duo, Core2 Duo
 706   //    family 6 model:   9,        13,       14,        15
 707   //    0x0f   -  Pentium 4, Opteron
 708   //
 709   // Note: The cpu family should be used to select between
 710   //       instruction sequences which are valid on all Intel
 711   //       processors.  Use the feature test functions below to
 712   //       determine whether a particular instruction is supported.
 713   //
 714   static int  cpu_family()        { return _cpu;}
 715   static bool is_P6()             { return cpu_family() >= 6; }
 716   static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
 717   static bool is_hygon()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
 718   static bool is_amd_family()     { return is_amd() || is_hygon(); }
 719   static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
 720   static bool is_zx()             { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS  '
 721   static bool is_atom_family()    { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
 722   static bool is_knights_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
 723 
 724   static bool supports_processor_topology() {
 725     return (_cpuid_info.std_max_function >= 0xB) &&
 726            // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
 727            // Some cpus have max cpuid >= 0xB but do not support processor topology.
 728            (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
 729   }
 730 
 731   static uint cores_per_cpu()  {
 732     uint result = 1;
 733     if (is_intel()) {
 734       bool supports_topology = supports_processor_topology();
 735       if (supports_topology) {
 736         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 737                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 738       }
 739       if (!supports_topology || result == 0) {
 740         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 741       }
 742     } else if (is_amd_family()) {
 743       result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
 744     } else if (is_zx()) {
 745       bool supports_topology = supports_processor_topology();
 746       if (supports_topology) {
 747         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 748                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 749       }
 750       if (!supports_topology || result == 0) {
 751         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 752       }
 753     }
 754     return result;
 755   }
 756 
 757   static uint threads_per_core()  {
 758     uint result = 1;
 759     if (is_intel() && supports_processor_topology()) {
 760       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 761     } else if (is_zx() && supports_processor_topology()) {
 762       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 763     } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
 764       if (cpu_family() >= 0x17) {
 765         result = _cpuid_info.ext_cpuid1E_ebx.bits.threads_per_core + 1;
 766       } else {
 767         result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
 768                  cores_per_cpu();
 769       }
 770     }
 771     return (result == 0 ? 1 : result);
 772   }
 773 
 774   static intx L1_line_size()  {
 775     intx result = 0;
 776     if (is_intel()) {
 777       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 778     } else if (is_amd_family()) {
 779       result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
 780     } else if (is_zx()) {
 781       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 782     }
 783     if (result < 32) // not defined ?
 784       result = 32;   // 32 bytes by default on x86 and other x64
 785     return result;
 786   }
 787 
 788   static intx prefetch_data_size()  {
 789     return L1_line_size();
 790   }
 791 
 792   //
 793   // Feature identification
 794   //
 795   static bool supports_cpuid()    { return _features  != 0; }
 796   static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; }
 797   static bool supports_cmov()     { return (_features & CPU_CMOV) != 0; }
 798   static bool supports_fxsr()     { return (_features & CPU_FXSR) != 0; }


 845   static bool is_intel_tsc_synched_at_init()  {
 846     if (is_intel_family_core()) {
 847       uint32_t ext_model = extended_cpu_model();
 848       if (ext_model == CPU_MODEL_NEHALEM_EP     ||
 849           ext_model == CPU_MODEL_WESTMERE_EP    ||
 850           ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
 851           ext_model == CPU_MODEL_IVYBRIDGE_EP) {
 852         // <= 2-socket invariant tsc support. EX versions are usually used
 853         // in > 2-socket systems and likely don't synchronize tscs at
 854         // initialization.
 855         // Code that uses tsc values must be prepared for them to arbitrarily
 856         // jump forward or backward.
 857         return true;
 858       }
 859     }
 860     return false;
 861   }
 862 
 863   // AMD features
 864   static bool supports_3dnow_prefetch()    { return (_features & CPU_3DNOW_PREFETCH) != 0; }
 865   static bool supports_mmx_ext()  { return is_amd_family() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
 866   static bool supports_lzcnt()    { return (_features & CPU_LZCNT) != 0; }
 867   static bool supports_sse4a()    { return (_features & CPU_SSE4A) != 0; }
 868 
 869   static bool is_amd_Barcelona()  { return is_amd() &&
 870                                            extended_cpu_family() == CPU_FAMILY_AMD_11H; }
 871 
 872   // Intel and AMD newer cores support fast timestamps well
 873   static bool supports_tscinv_bit() {
 874     return (_features & CPU_TSCINV) != 0;
 875   }
 876   static bool supports_tscinv() {
 877     return supports_tscinv_bit() &&
 878       ((is_amd_family() && !is_amd_Barcelona()) ||
 879         is_intel_tsc_synched_at_init());
 880   }
 881 
 882   // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
 883   static bool has_fast_idiv()     { return is_intel() && cpu_family() == 6 &&
 884                                            supports_sse3() && _model != 0x1C; }
 885 
 886   static bool supports_compare_and_exchange() { return true; }
 887 
 888   static intx allocate_prefetch_distance(bool use_watermark_prefetch) {
 889     // Hardware prefetching (distance/size in bytes):
 890     // Pentium 3 -  64 /  32
 891     // Pentium 4 - 256 / 128
 892     // Athlon    -  64 /  32 ????
 893     // Opteron   - 128 /  64 only when 2 sequential cache lines accessed
 894     // Core      - 128 /  64
 895     //
 896     // Software prefetching (distance in bytes / instruction with best score):
 897     // Pentium 3 - 128 / prefetchnta
 898     // Pentium 4 - 512 / prefetchnta
 899     // Athlon    - 128 / prefetchnta
 900     // Opteron   - 256 / prefetchnta
 901     // Core      - 256 / prefetchnta
 902     // It will be used only when AllocatePrefetchStyle > 0
 903 
 904     if (is_amd_family()) { // AMD | Hygon
 905       if (supports_sse2()) {
 906         return 256; // Opteron
 907       } else {
 908         return 128; // Athlon
 909       }
 910     } else { // Intel
 911       if (supports_sse3() && cpu_family() == 6) {
 912         if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
 913           return 192;
 914         } else if (use_watermark_prefetch) { // watermark prefetching on Core
 915 #ifdef _LP64
 916           return 384;
 917 #else
 918           return 320;
 919 #endif
 920         }
 921       }
 922       if (supports_sse2()) {
 923         if (cpu_family() == 6) {
 924           return 256; // Pentium M, Core, Core2
 925         } else {
 926           return 512; // Pentium 4
 927         }
 928       } else {
 929         return 128; // Pentium 3 (and all other old CPUs)
 930       }
 931     }
 932   }
 933 
 934   // SSE2 and later processors implement a 'pause' instruction
 935   // that can be used for efficient implementation of
 936   // the intrinsic for java.lang.Thread.onSpinWait()
 937   static bool supports_on_spin_wait() { return supports_sse2(); }
 938 
 939   // support functions for virtualization detection
 940  private:
 941   static void check_virt_cpuid(uint32_t idx, uint32_t *regs);
 942   static void check_virtualizations();
 943 };
 944 
 945 #endif // CPU_X86_VM_VERSION_X86_HPP


 478     result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
 479     return result;
 480   }
 481 
 482   static uint32_t cpu_stepping() {
 483     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
 484     return result;
 485   }
 486 
 487   static uint logical_processor_count() {
 488     uint result = threads_per_core();
 489     return result;
 490   }
 491 
 492   static uint64_t feature_flags() {
 493     uint64_t result = 0;
 494     if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
 495       result |= CPU_CX8;
 496     if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
 497       result |= CPU_CMOV;
 498     if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
 499         _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
 500       result |= CPU_FXSR;
 501     // HT flag is set for multi-core processors also.
 502     if (threads_per_core() > 1)
 503       result |= CPU_HT;
 504     if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
 505         _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
 506       result |= CPU_MMX;
 507     if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
 508       result |= CPU_SSE;
 509     if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
 510       result |= CPU_SSE2;
 511     if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
 512       result |= CPU_SSE3;
 513     if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
 514       result |= CPU_SSSE3;
 515     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
 516       result |= CPU_SSE4_1;
 517     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
 518       result |= CPU_SSE4_2;
 519     if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
 520       result |= CPU_POPCNT;
 521     if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
 522         _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
 523         _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
 524         _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {


 536         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
 537           result |= CPU_AVX512DQ;
 538         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
 539           result |= CPU_AVX512PF;
 540         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
 541           result |= CPU_AVX512ER;
 542         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
 543           result |= CPU_AVX512BW;
 544         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
 545           result |= CPU_AVX512VL;
 546         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0)
 547           result |= CPU_AVX512_VPOPCNTDQ;
 548         if (_cpuid_info.sef_cpuid7_ecx.bits.vpclmulqdq != 0)
 549           result |= CPU_VPCLMULQDQ;
 550         if (_cpuid_info.sef_cpuid7_ecx.bits.vaes != 0)
 551           result |= CPU_VAES;
 552         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0)
 553           result |= CPU_VNNI;
 554       }
 555     }
 556     if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
 557       result |= CPU_BMI1;
 558     if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
 559       result |= CPU_TSC;
 560     if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
 561       result |= CPU_TSCINV;
 562     if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
 563       result |= CPU_AES;
 564     if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
 565       result |= CPU_ERMS;
 566     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
 567       result |= CPU_CLMUL;
 568     if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
 569       result |= CPU_RTM;
 570     if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
 571        result |= CPU_ADX;
 572     if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
 573       result |= CPU_BMI2;
 574     if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
 575       result |= CPU_SHA;
 576     if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
 577       result |= CPU_FMA;
 578 
 579     // AMD features.
 580     if (is_amd()) {
 581       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
 582           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
 583         result |= CPU_3DNOW_PREFETCH;
 584       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
 585         result |= CPU_LZCNT;
 586       if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
 587         result |= CPU_SSE4A;
 588     }
 589     // Intel features.
 590     if(is_intel()) {
 591       if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 592         result |= CPU_LZCNT;
 593       // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 594       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 595         result |= CPU_3DNOW_PREFETCH;
 596       }
 597     }
 598 
 599     // ZX features.
 600     if (is_zx()) {
 601       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 602         result |= CPU_LZCNT;
 603       // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 604       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 605         result |= CPU_3DNOW_PREFETCH;
 606       }
 607     }
 608 
 609     return result;
 610   }
 611 


 669   static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
 670 
 671   // The value used to check ymm register after signal handle
 672   static int ymm_test_value()    { return 0xCAFEBABE; }
 673 
 674   static void get_cpu_info_wrapper();
 675   static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
 676   static bool  is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
 677   static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
 678   static address  cpuinfo_cont_addr()           { return _cpuinfo_cont_addr; }
 679 
 680   static void clean_cpuFeatures()   { _features = 0; }
 681   static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); }
 682   static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); }
 683 
 684 
 685   // Initialization
 686   static void initialize();
 687 
 688   // Override Abstract_VM_Version implementation



 689   static bool use_biased_locking();
 690 
 691   // Asserts
 692   static void assert_is_initialized() {
 693     assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
 694   }
 695 
 696   //
 697   // Processor family:
 698   //       3   -  386
 699   //       4   -  486
 700   //       5   -  Pentium
 701   //       6   -  PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
 702   //              Pentium M, Core Solo, Core Duo, Core2 Duo
 703   //    family 6 model:   9,        13,       14,        15
 704   //    0x0f   -  Pentium 4, Opteron
 705   //
 706   // Note: The cpu family should be used to select between
 707   //       instruction sequences which are valid on all Intel
 708   //       processors.  Use the feature test functions below to
 709   //       determine whether a particular instruction is supported.
 710   //
 711   static int  cpu_family()        { return _cpu;}
 712   static bool is_P6()             { return cpu_family() >= 6; }
 713   static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'


 714   static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
 715   static bool is_zx()             { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS  '
 716   static bool is_atom_family()    { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
 717   static bool is_knights_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
 718 
 719   static bool supports_processor_topology() {
 720     return (_cpuid_info.std_max_function >= 0xB) &&
 721            // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
 722            // Some cpus have max cpuid >= 0xB but do not support processor topology.
 723            (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
 724   }
 725 
 726   static uint cores_per_cpu()  {
 727     uint result = 1;
 728     if (is_intel()) {
 729       bool supports_topology = supports_processor_topology();
 730       if (supports_topology) {
 731         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 732                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 733       }
 734       if (!supports_topology || result == 0) {
 735         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 736       }
 737     } else if (is_amd()) {
 738       result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
 739     } else if (is_zx()) {
 740       bool supports_topology = supports_processor_topology();
 741       if (supports_topology) {
 742         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 743                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 744       }
 745       if (!supports_topology || result == 0) {
 746         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 747       }
 748     }
 749     return result;
 750   }
 751 
 752   static uint threads_per_core()  {
 753     uint result = 1;
 754     if (is_intel() && supports_processor_topology()) {
 755       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 756     } else if (is_zx() && supports_processor_topology()) {
 757       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 758     } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
 759       if (cpu_family() >= 0x17) {
 760         result = _cpuid_info.ext_cpuid1E_ebx.bits.threads_per_core + 1;
 761       } else {
 762         result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
 763                  cores_per_cpu();
 764       }
 765     }
 766     return (result == 0 ? 1 : result);
 767   }
 768 
 769   static intx L1_line_size()  {
 770     intx result = 0;
 771     if (is_intel()) {
 772       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 773     } else if (is_amd()) {
 774       result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
 775     } else if (is_zx()) {
 776       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 777     }
 778     if (result < 32) // not defined ?
 779       result = 32;   // 32 bytes by default on x86 and other x64
 780     return result;
 781   }
 782 
 783   static intx prefetch_data_size()  {
 784     return L1_line_size();
 785   }
 786 
 787   //
 788   // Feature identification
 789   //
 790   static bool supports_cpuid()    { return _features  != 0; }
 791   static bool supports_cmpxchg8() { return (_features & CPU_CX8) != 0; }
 792   static bool supports_cmov()     { return (_features & CPU_CMOV) != 0; }
 793   static bool supports_fxsr()     { return (_features & CPU_FXSR) != 0; }


 840   static bool is_intel_tsc_synched_at_init()  {
 841     if (is_intel_family_core()) {
 842       uint32_t ext_model = extended_cpu_model();
 843       if (ext_model == CPU_MODEL_NEHALEM_EP     ||
 844           ext_model == CPU_MODEL_WESTMERE_EP    ||
 845           ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
 846           ext_model == CPU_MODEL_IVYBRIDGE_EP) {
 847         // <= 2-socket invariant tsc support. EX versions are usually used
 848         // in > 2-socket systems and likely don't synchronize tscs at
 849         // initialization.
 850         // Code that uses tsc values must be prepared for them to arbitrarily
 851         // jump forward or backward.
 852         return true;
 853       }
 854     }
 855     return false;
 856   }
 857 
 858   // AMD features
 859   static bool supports_3dnow_prefetch()    { return (_features & CPU_3DNOW_PREFETCH) != 0; }
 860   static bool supports_mmx_ext()  { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
 861   static bool supports_lzcnt()    { return (_features & CPU_LZCNT) != 0; }
 862   static bool supports_sse4a()    { return (_features & CPU_SSE4A) != 0; }
 863 
 864   static bool is_amd_Barcelona()  { return is_amd() &&
 865                                            extended_cpu_family() == CPU_FAMILY_AMD_11H; }
 866 
 867   // Intel and AMD newer cores support fast timestamps well
 868   static bool supports_tscinv_bit() {
 869     return (_features & CPU_TSCINV) != 0;
 870   }
 871   static bool supports_tscinv() {
 872     return supports_tscinv_bit() &&
 873            ( (is_amd() && !is_amd_Barcelona()) ||
 874              is_intel_tsc_synched_at_init() );
 875   }
 876 
 877   // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
 878   static bool has_fast_idiv()     { return is_intel() && cpu_family() == 6 &&
 879                                            supports_sse3() && _model != 0x1C; }
 880 
 881   static bool supports_compare_and_exchange() { return true; }
 882 
 883   static intx allocate_prefetch_distance(bool use_watermark_prefetch) {
 884     // Hardware prefetching (distance/size in bytes):
 885     // Pentium 3 -  64 /  32
 886     // Pentium 4 - 256 / 128
 887     // Athlon    -  64 /  32 ????
 888     // Opteron   - 128 /  64 only when 2 sequential cache lines accessed
 889     // Core      - 128 /  64
 890     //
 891     // Software prefetching (distance in bytes / instruction with best score):
 892     // Pentium 3 - 128 / prefetchnta
 893     // Pentium 4 - 512 / prefetchnta
 894     // Athlon    - 128 / prefetchnta
 895     // Opteron   - 256 / prefetchnta
 896     // Core      - 256 / prefetchnta
 897     // It will be used only when AllocatePrefetchStyle > 0
 898 
 899     if (is_amd()) { // AMD
 900       if (supports_sse2()) {
 901         return 256; // Opteron
 902       } else {
 903         return 128; // Athlon
 904       }
 905     } else { // Intel
 906       if (supports_sse3() && cpu_family() == 6) {
 907         if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
 908           return 192;
 909         } else if (use_watermark_prefetch) { // watermark prefetching on Core
 910 #ifdef _LP64
 911           return 384;
 912 #else
 913           return 320;
 914 #endif
 915         }
 916       }
 917       if (supports_sse2()) {
 918         if (cpu_family() == 6) {
 919           return 256; // Pentium M, Core, Core2
 920         } else {
 921           return 512; // Pentium 4
 922         }
 923       } else {
 924         return 128; // Pentium 3 (and all other old CPUs)
 925       }
 926     }
 927   }
 928 
 929   // SSE2 and later processors implement a 'pause' instruction
 930   // that can be used for efficient implementation of
 931   // the intrinsic for java.lang.Thread.onSpinWait()
 932   static bool supports_on_spin_wait() { return supports_sse2(); }





 933 };
 934 
 935 #endif // CPU_X86_VM_VERSION_X86_HPP
< prev index next >