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src/hotspot/cpu/aarch64/aarch64.ad

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 940 // Class for 128 bit register v0
 941 reg_class v0_reg(
 942     V0, V0_H
 943 );
 944 
 945 // Class for 128 bit register v1
 946 reg_class v1_reg(
 947     V1, V1_H
 948 );
 949 
 950 // Class for 128 bit register v2
 951 reg_class v2_reg(
 952     V2, V2_H
 953 );
 954 
 955 // Class for 128 bit register v3
 956 reg_class v3_reg(
 957     V3, V3_H
 958 );
 959 
 960 // Class for 128 bit register v4
 961 reg_class v4_reg(
 962     V4, V4_H
 963 );
 964 
 965 // Class for 128 bit register v5
 966 reg_class v5_reg(
 967     V5, V5_H
 968 );
 969 
 970 // Class for 128 bit register v6
 971 reg_class v6_reg(
 972     V6, V6_H
 973 );
 974 
 975 // Class for 128 bit register v7
 976 reg_class v7_reg(
 977     V7, V7_H
 978 );
 979 
 980 // Class for 128 bit register v8
 981 reg_class v8_reg(
 982     V8, V8_H
 983 );
 984 
 985 // Class for 128 bit register v9
 986 reg_class v9_reg(
 987     V9, V9_H
 988 );
 989 
 990 // Class for 128 bit register v10
 991 reg_class v10_reg(
 992     V10, V10_H
 993 );
 994 
 995 // Class for 128 bit register v11
 996 reg_class v11_reg(
 997     V11, V11_H
 998 );
 999 
1000 // Class for 128 bit register v12
1001 reg_class v12_reg(
1002     V12, V12_H
1003 );
1004 
1005 // Class for 128 bit register v13
1006 reg_class v13_reg(
1007     V13, V13_H
1008 );
1009 
1010 // Class for 128 bit register v14
1011 reg_class v14_reg(
1012     V14, V14_H
1013 );
1014 
1015 // Class for 128 bit register v15
1016 reg_class v15_reg(
1017     V15, V15_H
1018 );
1019 
1020 // Class for 128 bit register v16
1021 reg_class v16_reg(
1022     V16, V16_H
1023 );
1024 
1025 // Class for 128 bit register v17
1026 reg_class v17_reg(
1027     V17, V17_H
1028 );
1029 
1030 // Class for 128 bit register v18
1031 reg_class v18_reg(
1032     V18, V18_H
1033 );
1034 
1035 // Class for 128 bit register v19
1036 reg_class v19_reg(
1037     V19, V19_H
1038 );
1039 
1040 // Class for 128 bit register v20
1041 reg_class v20_reg(
1042     V20, V20_H
1043 );
1044 
1045 // Class for 128 bit register v21
1046 reg_class v21_reg(
1047     V21, V21_H
1048 );
1049 
1050 // Class for 128 bit register v22
1051 reg_class v22_reg(
1052     V22, V22_H
1053 );
1054 
1055 // Class for 128 bit register v23
1056 reg_class v23_reg(
1057     V23, V23_H
1058 );
1059 
1060 // Class for 128 bit register v24
1061 reg_class v24_reg(
1062     V24, V24_H
1063 );
1064 
1065 // Class for 128 bit register v25
1066 reg_class v25_reg(
1067     V25, V25_H
1068 );
1069 
1070 // Class for 128 bit register v26
1071 reg_class v26_reg(
1072     V26, V26_H
1073 );
1074 
1075 // Class for 128 bit register v27
1076 reg_class v27_reg(
1077     V27, V27_H
1078 );
1079 
1080 // Class for 128 bit register v28
1081 reg_class v28_reg(
1082     V28, V28_H
1083 );
1084 
1085 // Class for 128 bit register v29
1086 reg_class v29_reg(
1087     V29, V29_H
1088 );
1089 
1090 // Class for 128 bit register v30
1091 reg_class v30_reg(
1092     V30, V30_H
1093 );
1094 
1095 // Class for 128 bit register v31
1096 reg_class v31_reg(
1097     V31, V31_H
1098 );
1099 
1100 // Singleton class for condition codes
1101 reg_class int_flags(RFLAGS);
1102 
1103 %}
1104 
1105 //----------DEFINITION BLOCK---------------------------------------------------
1106 // Define name --> value mappings to inform the ADLC of an integer valued name
1107 // Current support includes integer values in the range [0, 0x7FFFFFFF]
1108 // Format:
1109 //        int_def  <name>         ( <int_value>, <expression>);
1110 // Generated Code in ad_<arch>.hpp
1111 //        #define  <name>   (<expression>)
1112 //        // value == <int_value>
1113 // Generated code in ad_<arch>.cpp adlc_verification()
1114 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
1115 //
1116 
1117 // we follow the ppc-aix port in using a simple cost model which ranks
1118 // register operations as cheap, memory ops as more expensive and
1119 // branches as most expensive. the first two have a low as well as a


4897 %}
4898 
4899 operand vRegD_V2()
4900 %{
4901   constraint(ALLOC_IN_RC(v2_reg));
4902   match(RegD);
4903   op_cost(0);
4904   format %{ %}
4905   interface(REG_INTER);
4906 %}
4907 
4908 operand vRegD_V3()
4909 %{
4910   constraint(ALLOC_IN_RC(v3_reg));
4911   match(RegD);
4912   op_cost(0);
4913   format %{ %}
4914   interface(REG_INTER);
4915 %}
4916 
4917 operand vRegD_V4()
4918 %{
4919   constraint(ALLOC_IN_RC(v4_reg));
4920   match(RegD);
4921   op_cost(0);
4922   format %{ %}
4923   interface(REG_INTER);
4924 %}
4925 
4926 operand vRegD_V5()
4927 %{
4928   constraint(ALLOC_IN_RC(v5_reg));
4929   match(RegD);
4930   op_cost(0);
4931   format %{ %}
4932   interface(REG_INTER);
4933 %}
4934 
4935 operand vRegD_V6()
4936 %{
4937   constraint(ALLOC_IN_RC(v6_reg));
4938   match(RegD);
4939   op_cost(0);
4940   format %{ %}
4941   interface(REG_INTER);
4942 %}
4943 
4944 operand vRegD_V7()
4945 %{
4946   constraint(ALLOC_IN_RC(v7_reg));
4947   match(RegD);
4948   op_cost(0);
4949   format %{ %}
4950   interface(REG_INTER);
4951 %}
4952 
4953 operand vRegD_V8()
4954 %{
4955   constraint(ALLOC_IN_RC(v8_reg));
4956   match(RegD);
4957   op_cost(0);
4958   format %{ %}
4959   interface(REG_INTER);
4960 %}
4961 
4962 operand vRegD_V9()
4963 %{
4964   constraint(ALLOC_IN_RC(v9_reg));
4965   match(RegD);
4966   op_cost(0);
4967   format %{ %}
4968   interface(REG_INTER);
4969 %}
4970 
4971 operand vRegD_V10()
4972 %{
4973   constraint(ALLOC_IN_RC(v10_reg));
4974   match(RegD);
4975   op_cost(0);
4976   format %{ %}
4977   interface(REG_INTER);
4978 %}
4979 
4980 operand vRegD_V11()
4981 %{
4982   constraint(ALLOC_IN_RC(v11_reg));
4983   match(RegD);
4984   op_cost(0);
4985   format %{ %}
4986   interface(REG_INTER);
4987 %}
4988 
4989 operand vRegD_V12()
4990 %{
4991   constraint(ALLOC_IN_RC(v12_reg));
4992   match(RegD);
4993   op_cost(0);
4994   format %{ %}
4995   interface(REG_INTER);
4996 %}
4997 
4998 operand vRegD_V13()
4999 %{
5000   constraint(ALLOC_IN_RC(v13_reg));
5001   match(RegD);
5002   op_cost(0);
5003   format %{ %}
5004   interface(REG_INTER);
5005 %}
5006 
5007 operand vRegD_V14()
5008 %{
5009   constraint(ALLOC_IN_RC(v14_reg));
5010   match(RegD);
5011   op_cost(0);
5012   format %{ %}
5013   interface(REG_INTER);
5014 %}
5015 
5016 operand vRegD_V15()
5017 %{
5018   constraint(ALLOC_IN_RC(v15_reg));
5019   match(RegD);
5020   op_cost(0);
5021   format %{ %}
5022   interface(REG_INTER);
5023 %}
5024 
5025 operand vRegD_V16()
5026 %{
5027   constraint(ALLOC_IN_RC(v16_reg));
5028   match(RegD);
5029   op_cost(0);
5030   format %{ %}
5031   interface(REG_INTER);
5032 %}
5033 
5034 operand vRegD_V17()
5035 %{
5036   constraint(ALLOC_IN_RC(v17_reg));
5037   match(RegD);
5038   op_cost(0);
5039   format %{ %}
5040   interface(REG_INTER);
5041 %}
5042 
5043 operand vRegD_V18()
5044 %{
5045   constraint(ALLOC_IN_RC(v18_reg));
5046   match(RegD);
5047   op_cost(0);
5048   format %{ %}
5049   interface(REG_INTER);
5050 %}
5051 
5052 operand vRegD_V19()
5053 %{
5054   constraint(ALLOC_IN_RC(v19_reg));
5055   match(RegD);
5056   op_cost(0);
5057   format %{ %}
5058   interface(REG_INTER);
5059 %}
5060 
5061 operand vRegD_V20()
5062 %{
5063   constraint(ALLOC_IN_RC(v20_reg));
5064   match(RegD);
5065   op_cost(0);
5066   format %{ %}
5067   interface(REG_INTER);
5068 %}
5069 
5070 operand vRegD_V21()
5071 %{
5072   constraint(ALLOC_IN_RC(v21_reg));
5073   match(RegD);
5074   op_cost(0);
5075   format %{ %}
5076   interface(REG_INTER);
5077 %}
5078 
5079 operand vRegD_V22()
5080 %{
5081   constraint(ALLOC_IN_RC(v22_reg));
5082   match(RegD);
5083   op_cost(0);
5084   format %{ %}
5085   interface(REG_INTER);
5086 %}
5087 
5088 operand vRegD_V23()
5089 %{
5090   constraint(ALLOC_IN_RC(v23_reg));
5091   match(RegD);
5092   op_cost(0);
5093   format %{ %}
5094   interface(REG_INTER);
5095 %}
5096 
5097 operand vRegD_V24()
5098 %{
5099   constraint(ALLOC_IN_RC(v24_reg));
5100   match(RegD);
5101   op_cost(0);
5102   format %{ %}
5103   interface(REG_INTER);
5104 %}
5105 
5106 operand vRegD_V25()
5107 %{
5108   constraint(ALLOC_IN_RC(v25_reg));
5109   match(RegD);
5110   op_cost(0);
5111   format %{ %}
5112   interface(REG_INTER);
5113 %}
5114 
5115 operand vRegD_V26()
5116 %{
5117   constraint(ALLOC_IN_RC(v26_reg));
5118   match(RegD);
5119   op_cost(0);
5120   format %{ %}
5121   interface(REG_INTER);
5122 %}
5123 
5124 operand vRegD_V27()
5125 %{
5126   constraint(ALLOC_IN_RC(v27_reg));
5127   match(RegD);
5128   op_cost(0);
5129   format %{ %}
5130   interface(REG_INTER);
5131 %}
5132 
5133 operand vRegD_V28()
5134 %{
5135   constraint(ALLOC_IN_RC(v28_reg));
5136   match(RegD);
5137   op_cost(0);
5138   format %{ %}
5139   interface(REG_INTER);
5140 %}
5141 
5142 operand vRegD_V29()
5143 %{
5144   constraint(ALLOC_IN_RC(v29_reg));
5145   match(RegD);
5146   op_cost(0);
5147   format %{ %}
5148   interface(REG_INTER);
5149 %}
5150 
5151 operand vRegD_V30()
5152 %{
5153   constraint(ALLOC_IN_RC(v30_reg));
5154   match(RegD);
5155   op_cost(0);
5156   format %{ %}
5157   interface(REG_INTER);
5158 %}
5159 
5160 operand vRegD_V31()
5161 %{
5162   constraint(ALLOC_IN_RC(v31_reg));
5163   match(RegD);
5164   op_cost(0);
5165   format %{ %}
5166   interface(REG_INTER);
5167 %}
5168 
5169 // Flags register, used as output of signed compare instructions
5170 
5171 // note that on AArch64 we also use this register as the output for
5172 // for floating point compare instructions (CmpF CmpD). this ensures
5173 // that ordered inequality tests use GT, GE, LT or LE none of which
5174 // pass through cases where the result is unordered i.e. one or both
5175 // inputs to the compare is a NaN. this means that the ideal code can
5176 // replace e.g. a GT with an LE and not end up capturing the NaN case
5177 // (where the comparison should always fail). EQ and NE tests are
5178 // always generated in ideal code so that unordered folds into the NE
5179 // case, matching the behaviour of AArch64 NE.
5180 //
5181 // This differs from x86 where the outputs of FP compares use a
5182 // special FP flags registers and where compares based on this
5183 // register are distinguished into ordered inequalities (cmpOpUCF) and
5184 // EQ/NEQ tests (cmpOpUCF2). x86 has to special case the latter tests
5185 // to explicitly handle the unordered case in branches. x86 also has
5186 // to include extra CMoveX rules to accept a cmpOpUCF input.
5187 
5188 operand rFlagsReg()


14238   match(Set cr (CmpF src1 src2));
14239 
14240   ins_cost(3 * INSN_COST);
14241   format %{ "fcmps $src1, $src2" %}
14242 
14243   ins_encode %{
14244     __ fcmps(as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
14245   %}
14246 
14247   ins_pipe(pipe_class_compare);
14248 %}
14249 
14250 instruct compF_reg_zero(rFlagsReg cr, vRegF src1, immF0 src2)
14251 %{
14252   match(Set cr (CmpF src1 src2));
14253 
14254   ins_cost(3 * INSN_COST);
14255   format %{ "fcmps $src1, 0.0" %}
14256 
14257   ins_encode %{
14258     __ fcmps(as_FloatRegister($src1$$reg), 0.0);
14259   %}
14260 
14261   ins_pipe(pipe_class_compare);
14262 %}
14263 // FROM HERE
14264 
14265 instruct compD_reg_reg(rFlagsReg cr, vRegD src1, vRegD src2)
14266 %{
14267   match(Set cr (CmpD src1 src2));
14268 
14269   ins_cost(3 * INSN_COST);
14270   format %{ "fcmpd $src1, $src2" %}
14271 
14272   ins_encode %{
14273     __ fcmpd(as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
14274   %}
14275 
14276   ins_pipe(pipe_class_compare);
14277 %}
14278 
14279 instruct compD_reg_zero(rFlagsReg cr, vRegD src1, immD0 src2)
14280 %{
14281   match(Set cr (CmpD src1 src2));
14282 
14283   ins_cost(3 * INSN_COST);
14284   format %{ "fcmpd $src1, 0.0" %}
14285 
14286   ins_encode %{
14287     __ fcmpd(as_FloatRegister($src1$$reg), 0.0);
14288   %}
14289 
14290   ins_pipe(pipe_class_compare);
14291 %}
14292 
14293 instruct compF3_reg_reg(iRegINoSp dst, vRegF src1, vRegF src2, rFlagsReg cr)
14294 %{
14295   match(Set dst (CmpF3 src1 src2));
14296   effect(KILL cr);
14297 
14298   ins_cost(5 * INSN_COST);
14299   format %{ "fcmps $src1, $src2\n\t"
14300             "csinvw($dst, zr, zr, eq\n\t"
14301             "csnegw($dst, $dst, $dst, lt)"
14302   %}
14303 
14304   ins_encode %{
14305     Label done;
14306     FloatRegister s1 = as_FloatRegister($src1$$reg);
14307     FloatRegister s2 = as_FloatRegister($src2$$reg);


14343   %}
14344   ins_pipe(pipe_class_default);
14345 
14346 %}
14347 
14348 instruct compF3_reg_immF0(iRegINoSp dst, vRegF src1, immF0 zero, rFlagsReg cr)
14349 %{
14350   match(Set dst (CmpF3 src1 zero));
14351   effect(KILL cr);
14352 
14353   ins_cost(5 * INSN_COST);
14354   format %{ "fcmps $src1, 0.0\n\t"
14355             "csinvw($dst, zr, zr, eq\n\t"
14356             "csnegw($dst, $dst, $dst, lt)"
14357   %}
14358 
14359   ins_encode %{
14360     Label done;
14361     FloatRegister s1 = as_FloatRegister($src1$$reg);
14362     Register d = as_Register($dst$$reg);
14363     __ fcmps(s1, 0.0);
14364     // installs 0 if EQ else -1
14365     __ csinvw(d, zr, zr, Assembler::EQ);
14366     // keeps -1 if less or unordered else installs 1
14367     __ csnegw(d, d, d, Assembler::LT);
14368     __ bind(done);
14369   %}
14370 
14371   ins_pipe(pipe_class_default);
14372 
14373 %}
14374 
14375 instruct compD3_reg_immD0(iRegINoSp dst, vRegD src1, immD0 zero, rFlagsReg cr)
14376 %{
14377   match(Set dst (CmpD3 src1 zero));
14378   effect(KILL cr);
14379 
14380   ins_cost(5 * INSN_COST);
14381   format %{ "fcmpd $src1, 0.0\n\t"
14382             "csinvw($dst, zr, zr, eq\n\t"
14383             "csnegw($dst, $dst, $dst, lt)"
14384   %}
14385 
14386   ins_encode %{
14387     Label done;
14388     FloatRegister s1 = as_FloatRegister($src1$$reg);
14389     Register d = as_Register($dst$$reg);
14390     __ fcmpd(s1, 0.0);
14391     // installs 0 if EQ else -1
14392     __ csinvw(d, zr, zr, Assembler::EQ);
14393     // keeps -1 if less or unordered else installs 1
14394     __ csnegw(d, d, d, Assembler::LT);
14395     __ bind(done);
14396   %}
14397   ins_pipe(pipe_class_default);
14398 
14399 %}
14400 
14401 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegIorL2I p, iRegIorL2I q, rFlagsReg cr)
14402 %{
14403   match(Set dst (CmpLTMask p q));
14404   effect(KILL cr);
14405 
14406   ins_cost(3 * INSN_COST);
14407 
14408   format %{ "cmpw $p, $q\t# cmpLTMask\n\t"
14409             "csetw $dst, lt\n\t"
14410             "subw $dst, zr, $dst"


14926 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2)
14927 %{
14928   match(Set cr (FastUnlock object box));
14929   effect(TEMP tmp, TEMP tmp2);
14930 
14931   ins_cost(5 * INSN_COST);
14932   format %{ "fastunlock $object,$box\t! kills $tmp, $tmp2" %}
14933 
14934   ins_encode(aarch64_enc_fast_unlock(object, box, tmp, tmp2));
14935 
14936   ins_pipe(pipe_serial);
14937 %}
14938 
14939 
14940 // ============================================================================
14941 // Safepoint Instructions
14942 
14943 // TODO
14944 // provide a near and far version of this code
14945 
14946 instruct safePoint(rFlagsReg cr, iRegP poll)
14947 %{
14948   match(SafePoint poll);
14949   effect(KILL cr);
14950 
14951   format %{
14952     "ldrw zr, [$poll]\t# Safepoint: poll for GC"
14953   %}
14954   ins_encode %{
14955     __ read_polling_page(as_Register($poll$$reg), relocInfo::poll_type);
14956   %}
14957   ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
14958 %}
14959 
14960 
14961 // ============================================================================
14962 // Procedure Call/Return Instructions
14963 
14964 // Call Java Static Instruction
14965 
14966 instruct CallStaticJavaDirect(method meth)
14967 %{
14968   match(CallStaticJava);
14969 




 940 // Class for 128 bit register v0
 941 reg_class v0_reg(
 942     V0, V0_H
 943 );
 944 
 945 // Class for 128 bit register v1
 946 reg_class v1_reg(
 947     V1, V1_H
 948 );
 949 
 950 // Class for 128 bit register v2
 951 reg_class v2_reg(
 952     V2, V2_H
 953 );
 954 
 955 // Class for 128 bit register v3
 956 reg_class v3_reg(
 957     V3, V3_H
 958 );
 959 












































































































































 960 // Singleton class for condition codes
 961 reg_class int_flags(RFLAGS);
 962 
 963 %}
 964 
 965 //----------DEFINITION BLOCK---------------------------------------------------
 966 // Define name --> value mappings to inform the ADLC of an integer valued name
 967 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 968 // Format:
 969 //        int_def  <name>         ( <int_value>, <expression>);
 970 // Generated Code in ad_<arch>.hpp
 971 //        #define  <name>   (<expression>)
 972 //        // value == <int_value>
 973 // Generated code in ad_<arch>.cpp adlc_verification()
 974 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 975 //
 976 
 977 // we follow the ppc-aix port in using a simple cost model which ranks
 978 // register operations as cheap, memory ops as more expensive and
 979 // branches as most expensive. the first two have a low as well as a


4757 %}
4758 
4759 operand vRegD_V2()
4760 %{
4761   constraint(ALLOC_IN_RC(v2_reg));
4762   match(RegD);
4763   op_cost(0);
4764   format %{ %}
4765   interface(REG_INTER);
4766 %}
4767 
4768 operand vRegD_V3()
4769 %{
4770   constraint(ALLOC_IN_RC(v3_reg));
4771   match(RegD);
4772   op_cost(0);
4773   format %{ %}
4774   interface(REG_INTER);
4775 %}
4776 




























































































































































































































































4777 // Flags register, used as output of signed compare instructions
4778 
4779 // note that on AArch64 we also use this register as the output for
4780 // for floating point compare instructions (CmpF CmpD). this ensures
4781 // that ordered inequality tests use GT, GE, LT or LE none of which
4782 // pass through cases where the result is unordered i.e. one or both
4783 // inputs to the compare is a NaN. this means that the ideal code can
4784 // replace e.g. a GT with an LE and not end up capturing the NaN case
4785 // (where the comparison should always fail). EQ and NE tests are
4786 // always generated in ideal code so that unordered folds into the NE
4787 // case, matching the behaviour of AArch64 NE.
4788 //
4789 // This differs from x86 where the outputs of FP compares use a
4790 // special FP flags registers and where compares based on this
4791 // register are distinguished into ordered inequalities (cmpOpUCF) and
4792 // EQ/NEQ tests (cmpOpUCF2). x86 has to special case the latter tests
4793 // to explicitly handle the unordered case in branches. x86 also has
4794 // to include extra CMoveX rules to accept a cmpOpUCF input.
4795 
4796 operand rFlagsReg()


13846   match(Set cr (CmpF src1 src2));
13847 
13848   ins_cost(3 * INSN_COST);
13849   format %{ "fcmps $src1, $src2" %}
13850 
13851   ins_encode %{
13852     __ fcmps(as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
13853   %}
13854 
13855   ins_pipe(pipe_class_compare);
13856 %}
13857 
13858 instruct compF_reg_zero(rFlagsReg cr, vRegF src1, immF0 src2)
13859 %{
13860   match(Set cr (CmpF src1 src2));
13861 
13862   ins_cost(3 * INSN_COST);
13863   format %{ "fcmps $src1, 0.0" %}
13864 
13865   ins_encode %{
13866     __ fcmps(as_FloatRegister($src1$$reg), 0.0D);
13867   %}
13868 
13869   ins_pipe(pipe_class_compare);
13870 %}
13871 // FROM HERE
13872 
13873 instruct compD_reg_reg(rFlagsReg cr, vRegD src1, vRegD src2)
13874 %{
13875   match(Set cr (CmpD src1 src2));
13876 
13877   ins_cost(3 * INSN_COST);
13878   format %{ "fcmpd $src1, $src2" %}
13879 
13880   ins_encode %{
13881     __ fcmpd(as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
13882   %}
13883 
13884   ins_pipe(pipe_class_compare);
13885 %}
13886 
13887 instruct compD_reg_zero(rFlagsReg cr, vRegD src1, immD0 src2)
13888 %{
13889   match(Set cr (CmpD src1 src2));
13890 
13891   ins_cost(3 * INSN_COST);
13892   format %{ "fcmpd $src1, 0.0" %}
13893 
13894   ins_encode %{
13895     __ fcmpd(as_FloatRegister($src1$$reg), 0.0D);
13896   %}
13897 
13898   ins_pipe(pipe_class_compare);
13899 %}
13900 
13901 instruct compF3_reg_reg(iRegINoSp dst, vRegF src1, vRegF src2, rFlagsReg cr)
13902 %{
13903   match(Set dst (CmpF3 src1 src2));
13904   effect(KILL cr);
13905 
13906   ins_cost(5 * INSN_COST);
13907   format %{ "fcmps $src1, $src2\n\t"
13908             "csinvw($dst, zr, zr, eq\n\t"
13909             "csnegw($dst, $dst, $dst, lt)"
13910   %}
13911 
13912   ins_encode %{
13913     Label done;
13914     FloatRegister s1 = as_FloatRegister($src1$$reg);
13915     FloatRegister s2 = as_FloatRegister($src2$$reg);


13951   %}
13952   ins_pipe(pipe_class_default);
13953 
13954 %}
13955 
13956 instruct compF3_reg_immF0(iRegINoSp dst, vRegF src1, immF0 zero, rFlagsReg cr)
13957 %{
13958   match(Set dst (CmpF3 src1 zero));
13959   effect(KILL cr);
13960 
13961   ins_cost(5 * INSN_COST);
13962   format %{ "fcmps $src1, 0.0\n\t"
13963             "csinvw($dst, zr, zr, eq\n\t"
13964             "csnegw($dst, $dst, $dst, lt)"
13965   %}
13966 
13967   ins_encode %{
13968     Label done;
13969     FloatRegister s1 = as_FloatRegister($src1$$reg);
13970     Register d = as_Register($dst$$reg);
13971     __ fcmps(s1, 0.0D);
13972     // installs 0 if EQ else -1
13973     __ csinvw(d, zr, zr, Assembler::EQ);
13974     // keeps -1 if less or unordered else installs 1
13975     __ csnegw(d, d, d, Assembler::LT);
13976     __ bind(done);
13977   %}
13978 
13979   ins_pipe(pipe_class_default);
13980 
13981 %}
13982 
13983 instruct compD3_reg_immD0(iRegINoSp dst, vRegD src1, immD0 zero, rFlagsReg cr)
13984 %{
13985   match(Set dst (CmpD3 src1 zero));
13986   effect(KILL cr);
13987 
13988   ins_cost(5 * INSN_COST);
13989   format %{ "fcmpd $src1, 0.0\n\t"
13990             "csinvw($dst, zr, zr, eq\n\t"
13991             "csnegw($dst, $dst, $dst, lt)"
13992   %}
13993 
13994   ins_encode %{
13995     Label done;
13996     FloatRegister s1 = as_FloatRegister($src1$$reg);
13997     Register d = as_Register($dst$$reg);
13998     __ fcmpd(s1, 0.0D);
13999     // installs 0 if EQ else -1
14000     __ csinvw(d, zr, zr, Assembler::EQ);
14001     // keeps -1 if less or unordered else installs 1
14002     __ csnegw(d, d, d, Assembler::LT);
14003     __ bind(done);
14004   %}
14005   ins_pipe(pipe_class_default);
14006 
14007 %}
14008 
14009 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegIorL2I p, iRegIorL2I q, rFlagsReg cr)
14010 %{
14011   match(Set dst (CmpLTMask p q));
14012   effect(KILL cr);
14013 
14014   ins_cost(3 * INSN_COST);
14015 
14016   format %{ "cmpw $p, $q\t# cmpLTMask\n\t"
14017             "csetw $dst, lt\n\t"
14018             "subw $dst, zr, $dst"


14534 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2)
14535 %{
14536   match(Set cr (FastUnlock object box));
14537   effect(TEMP tmp, TEMP tmp2);
14538 
14539   ins_cost(5 * INSN_COST);
14540   format %{ "fastunlock $object,$box\t! kills $tmp, $tmp2" %}
14541 
14542   ins_encode(aarch64_enc_fast_unlock(object, box, tmp, tmp2));
14543 
14544   ins_pipe(pipe_serial);
14545 %}
14546 
14547 
14548 // ============================================================================
14549 // Safepoint Instructions
14550 
14551 // TODO
14552 // provide a near and far version of this code
14553 
14554 instruct safePoint(iRegP poll)
14555 %{
14556   match(SafePoint poll);

14557 
14558   format %{
14559     "ldrw zr, [$poll]\t# Safepoint: poll for GC"
14560   %}
14561   ins_encode %{
14562     __ read_polling_page(as_Register($poll$$reg), relocInfo::poll_type);
14563   %}
14564   ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
14565 %}
14566 
14567 
14568 // ============================================================================
14569 // Procedure Call/Return Instructions
14570 
14571 // Call Java Static Instruction
14572 
14573 instruct CallStaticJavaDirect(method meth)
14574 %{
14575   match(CallStaticJava);
14576 


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