1 /*
   2  * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  */
  24 
  25 #include <stdio.h>
  26 #include <sys/types.h>
  27 
  28 #include "precompiled.hpp"
  29 #include "asm/assembler.hpp"
  30 #include "asm/assembler.inline.hpp"
  31 #include "interpreter/interpreter.hpp"
  32 
  33 #ifndef PRODUCT
  34 const unsigned long Assembler::asm_bp = 0x00007fffee09ac88;
  35 #endif
  36 
  37 #include "compiler/disassembler.hpp"
  38 #include "memory/resourceArea.hpp"
  39 #include "runtime/interfaceSupport.inline.hpp"
  40 #include "runtime/sharedRuntime.hpp"
  41 
  42 // for the moment we reuse the logical/floating point immediate encode
  43 // and decode functiosn provided by the simulator. when we move to
  44 // real hardware we will need to pull taht code into here
  45 
  46 #include "immediate_aarch64.hpp"
  47 
  48 extern "C" void entry(CodeBuffer *cb);
  49 
  50 #define __ _masm.
  51 #ifdef PRODUCT
  52 #define BLOCK_COMMENT(str) /* nothing */
  53 #else
  54 #define BLOCK_COMMENT(str) block_comment(str)
  55 #endif
  56 
  57 #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
  58 
  59 static float unpack(unsigned value);
  60 
  61 short Assembler::SIMD_Size_in_bytes[] = {
  62   // T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
  63        8,   16,   8,  16,   8,  16,   8,  16,  16
  64 };
  65 
  66 #ifdef ASSERT
  67 static void asm_check(const unsigned int *insns, const unsigned int *insns1, size_t len) {
  68     bool ok = true;
  69     for (unsigned int i = 0; i < len; i++) {
  70       if (insns[i] != insns1[i]) {
  71         ok = false;
  72         printf("Ours:\n");
  73         Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
  74         printf("Theirs:\n");
  75         Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
  76         printf("\n");
  77       }
  78     }
  79     assert(ok, "Assembler smoke test failed");
  80   }
  81 #endif // ASSERT
  82 
  83 void entry(CodeBuffer *cb) {
  84 
  85   // {
  86   //   for (int i = 0; i < 256; i+=16)
  87   //     {
  88   //    printf("\"%20.20g\", ", unpack(i));
  89   //    printf("\"%20.20g\", ", unpack(i+1));
  90   //     }
  91   //   printf("\n");
  92   // }
  93 
  94   Assembler _masm(cb);
  95   address entry = __ pc();
  96 
  97   // Smoke test for assembler
  98 
  99 #ifdef ASSERT
 100 // BEGIN  Generated code -- do not edit
 101 // Generated by aarch64-asmtest.py
 102     Label back, forth;
 103     __ bind(back);
 104 
 105 // ArithOp
 106     __ add(r15, r12, r16, Assembler::LSR, 30);         //        add        x15, x12, x16, LSR #30
 107     __ sub(r1, r15, r3, Assembler::LSR, 32);           //        sub        x1, x15, x3, LSR #32
 108     __ adds(r13, r25, r5, Assembler::LSL, 13);         //        adds        x13, x25, x5, LSL #13
 109     __ subs(r22, r28, r6, Assembler::ASR, 17);         //        subs        x22, x28, x6, ASR #17
 110     __ addw(r0, r9, r22, Assembler::ASR, 6);           //        add        w0, w9, w22, ASR #6
 111     __ subw(r19, r3, r25, Assembler::LSL, 21);         //        sub        w19, w3, w25, LSL #21
 112     __ addsw(r4, r19, r11, Assembler::LSL, 20);        //        adds        w4, w19, w11, LSL #20
 113     __ subsw(r24, r7, r19, Assembler::ASR, 0);         //        subs        w24, w7, w19, ASR #0
 114     __ andr(r30, r7, r11, Assembler::LSL, 48);         //        and        x30, x7, x11, LSL #48
 115     __ orr(r24, r8, r15, Assembler::LSL, 12);          //        orr        x24, x8, x15, LSL #12
 116     __ eor(r17, r9, r23, Assembler::LSL, 1);           //        eor        x17, x9, x23, LSL #1
 117     __ ands(r14, r11, r4, Assembler::LSR, 55);         //        ands        x14, x11, x4, LSR #55
 118     __ andw(r19, r7, r12, Assembler::LSR, 17);         //        and        w19, w7, w12, LSR #17
 119     __ orrw(r19, r27, r11, Assembler::ASR, 28);        //        orr        w19, w27, w11, ASR #28
 120     __ eorw(r30, r3, r22, Assembler::LSR, 31);         //        eor        w30, w3, w22, LSR #31
 121     __ andsw(r19, r26, r28, Assembler::ASR, 0);        //        ands        w19, w26, w28, ASR #0
 122     __ bic(r29, r6, r26, Assembler::LSL, 51);          //        bic        x29, x6, x26, LSL #51
 123     __ orn(r26, r27, r17, Assembler::LSL, 35);         //        orn        x26, x27, x17, LSL #35
 124     __ eon(r21, r4, r14, Assembler::LSL, 5);           //        eon        x21, x4, x14, LSL #5
 125     __ bics(r2, r15, r0, Assembler::ASR, 5);           //        bics        x2, x15, x0, ASR #5
 126     __ bicw(r2, r7, r2, Assembler::LSL, 29);           //        bic        w2, w7, w2, LSL #29
 127     __ ornw(r24, r12, r21, Assembler::LSR, 5);         //        orn        w24, w12, w21, LSR #5
 128     __ eonw(r30, r15, r19, Assembler::LSL, 2);         //        eon        w30, w15, w19, LSL #2
 129     __ bicsw(r30, r23, r17, Assembler::ASR, 28);       //        bics        w30, w23, w17, ASR #28
 130 
 131 // AddSubImmOp
 132     __ addw(r4, r20, 660u);                            //        add        w4, w20, #660
 133     __ addsw(r2, r10, 710u);                           //        adds        w2, w10, #710
 134     __ subw(r19, r26, 244u);                           //        sub        w19, w26, #244
 135     __ subsw(r28, r13, 73u);                           //        subs        w28, w13, #73
 136     __ add(r2, r30, 862u);                             //        add        x2, x30, #862
 137     __ adds(r27, r16, 574u);                           //        adds        x27, x16, #574
 138     __ sub(r22, r9, 589u);                             //        sub        x22, x9, #589
 139     __ subs(r4, r1, 698u);                             //        subs        x4, x1, #698
 140 
 141 // LogicalImmOp
 142     __ andw(r28, r19, 4294709247ul);                   //        and        w28, w19, #0xfffc0fff
 143     __ orrw(r27, r5, 536870910ul);                     //        orr        w27, w5, #0x1ffffffe
 144     __ eorw(r30, r20, 4294840319ul);                   //        eor        w30, w20, #0xfffe0fff
 145     __ andsw(r22, r26, 4294959615ul);                  //        ands        w22, w26, #0xffffe1ff
 146     __ andr(r5, r7, 4194300ul);                        //        and        x5, x7, #0x3ffffc
 147     __ orr(r13, r7, 18014398509481728ul);              //        orr        x13, x7, #0x3fffffffffff00
 148     __ eor(r7, r9, 18442240474082197503ul);            //        eor        x7, x9, #0xfff0000000003fff
 149     __ ands(r3, r0, 18374686479671656447ul);           //        ands        x3, x0, #0xff00000000007fff
 150 
 151 // AbsOp
 152     __ b(__ pc());                                     //        b        .
 153     __ b(back);                                        //        b        back
 154     __ b(forth);                                       //        b        forth
 155     __ bl(__ pc());                                    //        bl        .
 156     __ bl(back);                                       //        bl        back
 157     __ bl(forth);                                      //        bl        forth
 158 
 159 // RegAndAbsOp
 160     __ cbzw(r16, __ pc());                             //        cbz        w16, .
 161     __ cbzw(r16, back);                                //        cbz        w16, back
 162     __ cbzw(r16, forth);                               //        cbz        w16, forth
 163     __ cbnzw(r19, __ pc());                            //        cbnz        w19, .
 164     __ cbnzw(r19, back);                               //        cbnz        w19, back
 165     __ cbnzw(r19, forth);                              //        cbnz        w19, forth
 166     __ cbz(r5, __ pc());                               //        cbz        x5, .
 167     __ cbz(r5, back);                                  //        cbz        x5, back
 168     __ cbz(r5, forth);                                 //        cbz        x5, forth
 169     __ cbnz(r4, __ pc());                              //        cbnz        x4, .
 170     __ cbnz(r4, back);                                 //        cbnz        x4, back
 171     __ cbnz(r4, forth);                                //        cbnz        x4, forth
 172     __ adr(r27, __ pc());                              //        adr        x27, .
 173     __ adr(r27, back);                                 //        adr        x27, back
 174     __ adr(r27, forth);                                //        adr        x27, forth
 175     __ _adrp(r16, __ pc());                            //        adrp        x16, .
 176 
 177 // RegImmAbsOp
 178     __ tbz(r28, 8, __ pc());                           //        tbz        x28, #8, .
 179     __ tbz(r28, 8, back);                              //        tbz        x28, #8, back
 180     __ tbz(r28, 8, forth);                             //        tbz        x28, #8, forth
 181     __ tbnz(r1, 1, __ pc());                           //        tbnz        x1, #1, .
 182     __ tbnz(r1, 1, back);                              //        tbnz        x1, #1, back
 183     __ tbnz(r1, 1, forth);                             //        tbnz        x1, #1, forth
 184 
 185 // MoveWideImmOp
 186     __ movnw(r20, 8639, 16);                           //        movn        w20, #8639, lsl 16
 187     __ movzw(r7, 25835, 0);                            //        movz        w7, #25835, lsl 0
 188     __ movkw(r17, 7261, 0);                            //        movk        w17, #7261, lsl 0
 189     __ movn(r14, 2097, 32);                            //        movn        x14, #2097, lsl 32
 190     __ movz(r9, 16082, 0);                             //        movz        x9, #16082, lsl 0
 191     __ movk(r19, 13962, 16);                           //        movk        x19, #13962, lsl 16
 192 
 193 // BitfieldOp
 194     __ sbfm(r9, r22, 6, 22);                           //        sbfm        x9, x22, #6, #22
 195     __ bfmw(r19, r0, 11, 0);                           //        bfm        w19, w0, #11, #0
 196     __ ubfmw(r10, r19, 11, 19);                        //        ubfm        w10, w19, #11, #19
 197     __ sbfm(r4, r15, 5, 17);                           //        sbfm        x4, x15, #5, #17
 198     __ bfm(r3, r5, 19, 28);                            //        bfm        x3, x5, #19, #28
 199     __ ubfm(r12, r28, 17, 2);                          //        ubfm        x12, x28, #17, #2
 200 
 201 // ExtractOp
 202     __ extrw(r15, r0, r22, 3);                         //        extr        w15, w0, w22, #3
 203     __ extr(r6, r14, r14, 55);                         //        extr        x6, x14, x14, #55
 204 
 205 // CondBranchOp
 206     __ br(Assembler::EQ, __ pc());                     //        b.EQ        .
 207     __ br(Assembler::EQ, back);                        //        b.EQ        back
 208     __ br(Assembler::EQ, forth);                       //        b.EQ        forth
 209     __ br(Assembler::NE, __ pc());                     //        b.NE        .
 210     __ br(Assembler::NE, back);                        //        b.NE        back
 211     __ br(Assembler::NE, forth);                       //        b.NE        forth
 212     __ br(Assembler::HS, __ pc());                     //        b.HS        .
 213     __ br(Assembler::HS, back);                        //        b.HS        back
 214     __ br(Assembler::HS, forth);                       //        b.HS        forth
 215     __ br(Assembler::CS, __ pc());                     //        b.CS        .
 216     __ br(Assembler::CS, back);                        //        b.CS        back
 217     __ br(Assembler::CS, forth);                       //        b.CS        forth
 218     __ br(Assembler::LO, __ pc());                     //        b.LO        .
 219     __ br(Assembler::LO, back);                        //        b.LO        back
 220     __ br(Assembler::LO, forth);                       //        b.LO        forth
 221     __ br(Assembler::CC, __ pc());                     //        b.CC        .
 222     __ br(Assembler::CC, back);                        //        b.CC        back
 223     __ br(Assembler::CC, forth);                       //        b.CC        forth
 224     __ br(Assembler::MI, __ pc());                     //        b.MI        .
 225     __ br(Assembler::MI, back);                        //        b.MI        back
 226     __ br(Assembler::MI, forth);                       //        b.MI        forth
 227     __ br(Assembler::PL, __ pc());                     //        b.PL        .
 228     __ br(Assembler::PL, back);                        //        b.PL        back
 229     __ br(Assembler::PL, forth);                       //        b.PL        forth
 230     __ br(Assembler::VS, __ pc());                     //        b.VS        .
 231     __ br(Assembler::VS, back);                        //        b.VS        back
 232     __ br(Assembler::VS, forth);                       //        b.VS        forth
 233     __ br(Assembler::VC, __ pc());                     //        b.VC        .
 234     __ br(Assembler::VC, back);                        //        b.VC        back
 235     __ br(Assembler::VC, forth);                       //        b.VC        forth
 236     __ br(Assembler::HI, __ pc());                     //        b.HI        .
 237     __ br(Assembler::HI, back);                        //        b.HI        back
 238     __ br(Assembler::HI, forth);                       //        b.HI        forth
 239     __ br(Assembler::LS, __ pc());                     //        b.LS        .
 240     __ br(Assembler::LS, back);                        //        b.LS        back
 241     __ br(Assembler::LS, forth);                       //        b.LS        forth
 242     __ br(Assembler::GE, __ pc());                     //        b.GE        .
 243     __ br(Assembler::GE, back);                        //        b.GE        back
 244     __ br(Assembler::GE, forth);                       //        b.GE        forth
 245     __ br(Assembler::LT, __ pc());                     //        b.LT        .
 246     __ br(Assembler::LT, back);                        //        b.LT        back
 247     __ br(Assembler::LT, forth);                       //        b.LT        forth
 248     __ br(Assembler::GT, __ pc());                     //        b.GT        .
 249     __ br(Assembler::GT, back);                        //        b.GT        back
 250     __ br(Assembler::GT, forth);                       //        b.GT        forth
 251     __ br(Assembler::LE, __ pc());                     //        b.LE        .
 252     __ br(Assembler::LE, back);                        //        b.LE        back
 253     __ br(Assembler::LE, forth);                       //        b.LE        forth
 254     __ br(Assembler::AL, __ pc());                     //        b.AL        .
 255     __ br(Assembler::AL, back);                        //        b.AL        back
 256     __ br(Assembler::AL, forth);                       //        b.AL        forth
 257     __ br(Assembler::NV, __ pc());                     //        b.NV        .
 258     __ br(Assembler::NV, back);                        //        b.NV        back
 259     __ br(Assembler::NV, forth);                       //        b.NV        forth
 260 
 261 // ImmOp
 262     __ svc(22064);                                     //        svc        #22064
 263     __ hvc(533);                                       //        hvc        #533
 264     __ smc(9942);                                      //        smc        #9942
 265     __ brk(4714);                                      //        brk        #4714
 266     __ hlt(4302);                                      //        hlt        #4302
 267 
 268 // Op
 269     __ nop();                                          //        nop
 270     __ eret();                                         //        eret
 271     __ drps();                                         //        drps
 272     __ isb();                                          //        isb
 273 
 274 // SystemOp
 275     __ dsb(Assembler::OSH);                            //        dsb        OSH
 276     __ dmb(Assembler::NSHLD);                          //        dmb        NSHLD
 277 
 278 // OneRegOp
 279     __ br(r20);                                        //        br        x20
 280     __ blr(r2);                                        //        blr        x2
 281 
 282 // LoadStoreExclusiveOp
 283     __ stxr(r18, r23, r0);                             //        stxr        w18, x23, [x0]
 284     __ stlxr(r30, r5, r22);                            //        stlxr        w30, x5, [x22]
 285     __ ldxr(r5, r8);                                   //        ldxr        x5, [x8]
 286     __ ldaxr(r20, r16);                                //        ldaxr        x20, [x16]
 287     __ stlr(r6, r11);                                  //        stlr        x6, [x11]
 288     __ ldar(r6, r27);                                  //        ldar        x6, [x27]
 289 
 290 // LoadStoreExclusiveOp
 291     __ stxrw(r10, r17, r5);                            //        stxr        w10, w17, [x5]
 292     __ stlxrw(r22, r9, r12);                           //        stlxr        w22, w9, [x12]
 293     __ ldxrw(r27, r8);                                 //        ldxr        w27, [x8]
 294     __ ldaxrw(r23, r2);                                //        ldaxr        w23, [x2]
 295     __ stlrw(r26, r29);                                //        stlr        w26, [x29]
 296     __ ldarw(r13, r10);                                //        ldar        w13, [x10]
 297 
 298 // LoadStoreExclusiveOp
 299     __ stxrh(r25, r28, r27);                           //        stxrh        w25, w28, [x27]
 300     __ stlxrh(r29, r22, r12);                          //        stlxrh        w29, w22, [x12]
 301     __ ldxrh(r22, r28);                                //        ldxrh        w22, [x28]
 302     __ ldaxrh(r3, r30);                                //        ldaxrh        w3, [x30]
 303     __ stlrh(r24, r15);                                //        stlrh        w24, [x15]
 304     __ ldarh(r27, r26);                                //        ldarh        w27, [x26]
 305 
 306 // LoadStoreExclusiveOp
 307     __ stxrb(r11, r10, r19);                           //        stxrb        w11, w10, [x19]
 308     __ stlxrb(r23, r27, r22);                          //        stlxrb        w23, w27, [x22]
 309     __ ldxrb(r24, r16);                                //        ldxrb        w24, [x16]
 310     __ ldaxrb(r24, r1);                                //        ldaxrb        w24, [x1]
 311     __ stlrb(r5, r29);                                 //        stlrb        w5, [x29]
 312     __ ldarb(r24, r16);                                //        ldarb        w24, [x16]
 313 
 314 // LoadStoreExclusiveOp
 315     __ ldxp(r25, r24, r17);                            //        ldxp        x25, x24, [x17]
 316     __ ldaxp(r22, r12, r19);                           //        ldaxp        x22, x12, [x19]
 317     __ stxp(r0, r26, r21, r25);                        //        stxp        w0, x26, x21, [x25]
 318     __ stlxp(r1, r6, r11, r5);                         //        stlxp        w1, x6, x11, [x5]
 319 
 320 // LoadStoreExclusiveOp
 321     __ ldxpw(r13, r14, r4);                            //        ldxp        w13, w14, [x4]
 322     __ ldaxpw(r17, r2, r6);                            //        ldaxp        w17, w2, [x6]
 323     __ stxpw(r15, r3, r9, r18);                        //        stxp        w15, w3, w9, [x18]
 324     __ stlxpw(r18, r17, r4, r9);                       //        stlxp        w18, w17, w4, [x9]
 325 
 326 // base_plus_unscaled_offset
 327 // LoadStoreOp
 328     __ str(r23, Address(r21, -49));                    //        str        x23, [x21, -49]
 329     __ strw(r21, Address(r2, 63));                     //        str        w21, [x2, 63]
 330     __ strb(r27, Address(r28, 11));                    //        strb        w27, [x28, 11]
 331     __ strh(r29, Address(r15, -13));                   //        strh        w29, [x15, -13]
 332     __ ldr(r14, Address(r30, -45));                    //        ldr        x14, [x30, -45]
 333     __ ldrw(r29, Address(r28, 53));                    //        ldr        w29, [x28, 53]
 334     __ ldrb(r20, Address(r26, 7));                     //        ldrb        w20, [x26, 7]
 335     __ ldrh(r25, Address(r2, -50));                    //        ldrh        w25, [x2, -50]
 336     __ ldrsb(r3, Address(r10, -15));                   //        ldrsb        x3, [x10, -15]
 337     __ ldrsh(r14, Address(r15, 19));                   //        ldrsh        x14, [x15, 19]
 338     __ ldrshw(r29, Address(r11, -5));                  //        ldrsh        w29, [x11, -5]
 339     __ ldrsw(r15, Address(r5, -71));                   //        ldrsw        x15, [x5, -71]
 340     __ ldrd(v19, Address(r12, 3));                     //        ldr        d19, [x12, 3]
 341     __ ldrs(v12, Address(r27, 42));                    //        ldr        s12, [x27, 42]
 342     __ strd(v22, Address(r28, 125));                   //        str        d22, [x28, 125]
 343     __ strs(v24, Address(r15, -20));                   //        str        s24, [x15, -20]
 344 
 345 // pre
 346 // LoadStoreOp
 347     __ str(r8, Address(__ pre(r28, -24)));             //        str        x8, [x28, -24]!
 348     __ strw(r6, Address(__ pre(r15, 37)));             //        str        w6, [x15, 37]!
 349     __ strb(r7, Address(__ pre(r1, 7)));               //        strb        w7, [x1, 7]!
 350     __ strh(r0, Address(__ pre(r17, 30)));             //        strh        w0, [x17, 30]!
 351     __ ldr(r25, Address(__ pre(r29, 84)));             //        ldr        x25, [x29, 84]!
 352     __ ldrw(r26, Address(__ pre(r20, -52)));           //        ldr        w26, [x20, -52]!
 353     __ ldrb(r26, Address(__ pre(r29, -25)));           //        ldrb        w26, [x29, -25]!
 354     __ ldrh(r4, Address(__ pre(r25, 26)));             //        ldrh        w4, [x25, 26]!
 355     __ ldrsb(r28, Address(__ pre(r8, -21)));           //        ldrsb        x28, [x8, -21]!
 356     __ ldrsh(r17, Address(__ pre(r14, -6)));           //        ldrsh        x17, [x14, -6]!
 357     __ ldrshw(r28, Address(__ pre(r23, 10)));          //        ldrsh        w28, [x23, 10]!
 358     __ ldrsw(r30, Address(__ pre(r27, -64)));          //        ldrsw        x30, [x27, -64]!
 359     __ ldrd(v20, Address(__ pre(r30, -242)));          //        ldr        d20, [x30, -242]!
 360     __ ldrs(v17, Address(__ pre(r27, 20)));            //        ldr        s17, [x27, 20]!
 361     __ strd(v7, Address(__ pre(r3, 17)));              //        str        d7, [x3, 17]!
 362     __ strs(v13, Address(__ pre(r11, -16)));           //        str        s13, [x11, -16]!
 363 
 364 // post
 365 // LoadStoreOp
 366     __ str(r6, Address(__ post(r9, -61)));             //        str        x6, [x9], -61
 367     __ strw(r16, Address(__ post(r5, -29)));           //        str        w16, [x5], -29
 368     __ strb(r29, Address(__ post(r29, 15)));           //        strb        w29, [x29], 15
 369     __ strh(r4, Address(__ post(r20, 18)));            //        strh        w4, [x20], 18
 370     __ ldr(r19, Address(__ post(r18, 46)));            //        ldr        x19, [x18], 46
 371     __ ldrw(r22, Address(__ post(r2, 23)));            //        ldr        w22, [x2], 23
 372     __ ldrb(r7, Address(__ post(r3, -30)));            //        ldrb        w7, [x3], -30
 373     __ ldrh(r11, Address(__ post(r12, -29)));          //        ldrh        w11, [x12], -29
 374     __ ldrsb(r8, Address(__ post(r6, -29)));           //        ldrsb        x8, [x6], -29
 375     __ ldrsh(r24, Address(__ post(r23, 4)));           //        ldrsh        x24, [x23], 4
 376     __ ldrshw(r17, Address(__ post(r16, 0)));          //        ldrsh        w17, [x16], 0
 377     __ ldrsw(r0, Address(__ post(r20, -8)));           //        ldrsw        x0, [x20], -8
 378     __ ldrd(v20, Address(__ post(r2, -126)));          //        ldr        d20, [x2], -126
 379     __ ldrs(v19, Address(__ post(r30, -104)));         //        ldr        s19, [x30], -104
 380     __ strd(v4, Address(__ post(r17, 118)));           //        str        d4, [x17], 118
 381     __ strs(v21, Address(__ post(r19, -112)));         //        str        s21, [x19], -112
 382 
 383 // base_plus_reg
 384 // LoadStoreOp
 385     __ str(r26, Address(r2, r19, Address::lsl(3)));    //        str        x26, [x2, x19, lsl #3]
 386     __ strw(r9, Address(r0, r15, Address::sxtw(2)));   //        str        w9, [x0, w15, sxtw #2]
 387     __ strb(r26, Address(r12, r1, Address::lsl(0)));   //        strb        w26, [x12, x1, lsl #0]
 388     __ strh(r21, Address(r11, r10, Address::lsl(1)));  //        strh        w21, [x11, x10, lsl #1]
 389     __ ldr(r16, Address(r23, r16, Address::sxtx(0)));  //        ldr        x16, [x23, x16, sxtx #0]
 390     __ ldrw(r10, Address(r11, r17, Address::sxtw(2))); //        ldr        w10, [x11, w17, sxtw #2]
 391     __ ldrb(r13, Address(r23, r11, Address::lsl(0)));  //        ldrb        w13, [x23, x11, lsl #0]
 392     __ ldrh(r27, Address(r4, r21, Address::lsl(0)));   //        ldrh        w27, [x4, x21, lsl #0]
 393     __ ldrsb(r26, Address(r8, r15, Address::sxtw(0))); //        ldrsb        x26, [x8, w15, sxtw #0]
 394     __ ldrsh(r21, Address(r10, r2, Address::sxtw(0))); //        ldrsh        x21, [x10, w2, sxtw #0]
 395     __ ldrshw(r8, Address(r30, r14, Address::lsl(0))); //        ldrsh        w8, [x30, x14, lsl #0]
 396     __ ldrsw(r29, Address(r14, r20, Address::sxtx(2))); //        ldrsw        x29, [x14, x20, sxtx #2]
 397     __ ldrd(v30, Address(r27, r22, Address::sxtx(0))); //        ldr        d30, [x27, x22, sxtx #0]
 398     __ ldrs(v13, Address(r9, r22, Address::lsl(0)));   //        ldr        s13, [x9, x22, lsl #0]
 399     __ strd(v8, Address(r25, r17, Address::sxtw(3)));  //        str        d8, [x25, w17, sxtw #3]
 400     __ strs(v1, Address(r24, r5, Address::uxtw(2)));   //        str        s1, [x24, w5, uxtw #2]
 401 
 402 // base_plus_scaled_offset
 403 // LoadStoreOp
 404     __ str(r10, Address(r21, 14496));                  //        str        x10, [x21, 14496]
 405     __ strw(r18, Address(r29, 7228));                  //        str        w18, [x29, 7228]
 406     __ strb(r23, Address(r3, 2018));                   //        strb        w23, [x3, 2018]
 407     __ strh(r28, Address(r11, 3428));                  //        strh        w28, [x11, 3428]
 408     __ ldr(r24, Address(r26, 14376));                  //        ldr        x24, [x26, 14376]
 409     __ ldrw(r21, Address(r2, 6972));                   //        ldr        w21, [x2, 6972]
 410     __ ldrb(r4, Address(r5, 1848));                    //        ldrb        w4, [x5, 1848]
 411     __ ldrh(r14, Address(r14, 3112));                  //        ldrh        w14, [x14, 3112]
 412     __ ldrsb(r4, Address(r27, 1959));                  //        ldrsb        x4, [x27, 1959]
 413     __ ldrsh(r4, Address(r27, 3226));                  //        ldrsh        x4, [x27, 3226]
 414     __ ldrshw(r10, Address(r28, 3286));                //        ldrsh        w10, [x28, 3286]
 415     __ ldrsw(r10, Address(r17, 7912));                 //        ldrsw        x10, [x17, 7912]
 416     __ ldrd(v13, Address(r28, 13400));                 //        ldr        d13, [x28, 13400]
 417     __ ldrs(v24, Address(r3, 7596));                   //        ldr        s24, [x3, 7596]
 418     __ strd(v2, Address(r12, 15360));                  //        str        d2, [x12, 15360]
 419     __ strs(v17, Address(r1, 6492));                   //        str        s17, [x1, 6492]
 420 
 421 // pcrel
 422 // LoadStoreOp
 423     __ ldr(r16, __ pc());                              //        ldr        x16, .
 424     __ ldrw(r13, __ pc());                             //        ldr        w13, .
 425 
 426 // LoadStoreOp
 427     __ prfm(Address(r18, -127));                       //        prfm        PLDL1KEEP, [x18, -127]
 428 
 429 // LoadStoreOp
 430     __ prfm(back);                                     //        prfm        PLDL1KEEP, back
 431 
 432 // LoadStoreOp
 433     __ prfm(Address(r20, r2, Address::lsl(3)));        //        prfm        PLDL1KEEP, [x20, x2, lsl #3]
 434 
 435 // LoadStoreOp
 436     __ prfm(Address(r9, 13808));                       //        prfm        PLDL1KEEP, [x9, 13808]
 437 
 438 // AddSubCarryOp
 439     __ adcw(r8, r23, r2);                              //        adc        w8, w23, w2
 440     __ adcsw(r24, r3, r19);                            //        adcs        w24, w3, w19
 441     __ sbcw(r22, r24, r29);                            //        sbc        w22, w24, w29
 442     __ sbcsw(r12, r27, r3);                            //        sbcs        w12, w27, w3
 443     __ adc(r11, r23, r1);                              //        adc        x11, x23, x1
 444     __ adcs(r29, r5, r23);                             //        adcs        x29, x5, x23
 445     __ sbc(r9, r25, r12);                              //        sbc        x9, x25, x12
 446     __ sbcs(r12, r0, r22);                             //        sbcs        x12, x0, x22
 447 
 448 // AddSubExtendedOp
 449     __ addw(r26, r12, r3, ext::uxtw, 1);               //        add        w26, w12, w3, uxtw #1
 450     __ addsw(r20, r16, r18, ext::sxtb, 2);             //        adds        w20, w16, w18, sxtb #2
 451     __ sub(r30, r30, r7, ext::uxtw, 2);                //        sub        x30, x30, x7, uxtw #2
 452     __ subsw(r11, r21, r2, ext::uxth, 3);              //        subs        w11, w21, w2, uxth #3
 453     __ add(r2, r26, r1, ext::uxtw, 2);                 //        add        x2, x26, x1, uxtw #2
 454     __ adds(r18, r29, r20, ext::sxth, 1);              //        adds        x18, x29, x20, sxth #1
 455     __ sub(r14, r16, r4, ext::uxtw, 4);                //        sub        x14, x16, x4, uxtw #4
 456     __ subs(r0, r17, r23, ext::sxtb, 3);               //        subs        x0, x17, x23, sxtb #3
 457 
 458 // ConditionalCompareOp
 459     __ ccmnw(r20, r22, 3u, Assembler::PL);             //        ccmn        w20, w22, #3, PL
 460     __ ccmpw(r25, r2, 1u, Assembler::EQ);              //        ccmp        w25, w2, #1, EQ
 461     __ ccmn(r18, r24, 7u, Assembler::GT);              //        ccmn        x18, x24, #7, GT
 462     __ ccmp(r8, r13, 6u, Assembler::PL);               //        ccmp        x8, x13, #6, PL
 463 
 464 // ConditionalCompareImmedOp
 465     __ ccmnw(r9, 2, 4, Assembler::VS);                 //        ccmn        w9, #2, #4, VS
 466     __ ccmpw(r2, 27, 7, Assembler::EQ);                //        ccmp        w2, #27, #7, EQ
 467     __ ccmn(r16, 1, 2, Assembler::CC);                 //        ccmn        x16, #1, #2, CC
 468     __ ccmp(r17, 31, 3, Assembler::LT);                //        ccmp        x17, #31, #3, LT
 469 
 470 // ConditionalSelectOp
 471     __ cselw(r23, r27, r23, Assembler::LS);            //        csel        w23, w27, w23, LS
 472     __ csincw(r10, r0, r6, Assembler::VS);             //        csinc        w10, w0, w6, VS
 473     __ csinvw(r11, r0, r9, Assembler::CC);             //        csinv        w11, w0, w9, CC
 474     __ csnegw(r17, r27, r18, Assembler::LO);           //        csneg        w17, w27, w18, LO
 475     __ csel(r12, r16, r11, Assembler::VC);             //        csel        x12, x16, x11, VC
 476     __ csinc(r6, r28, r6, Assembler::HI);              //        csinc        x6, x28, x6, HI
 477     __ csinv(r13, r27, r26, Assembler::VC);            //        csinv        x13, x27, x26, VC
 478     __ csneg(r29, r22, r18, Assembler::PL);            //        csneg        x29, x22, x18, PL
 479 
 480 // TwoRegOp
 481     __ rbitw(r12, r19);                                //        rbit        w12, w19
 482     __ rev16w(r23, r18);                               //        rev16        w23, w18
 483     __ revw(r9, r28);                                  //        rev        w9, w28
 484     __ clzw(r2, r19);                                  //        clz        w2, w19
 485     __ clsw(r25, r29);                                 //        cls        w25, w29
 486     __ rbit(r4, r23);                                  //        rbit        x4, x23
 487     __ rev16(r29, r18);                                //        rev16        x29, x18
 488     __ rev32(r7, r8);                                  //        rev32        x7, x8
 489     __ rev(r13, r17);                                  //        rev        x13, x17
 490     __ clz(r17, r0);                                   //        clz        x17, x0
 491     __ cls(r18, r26);                                  //        cls        x18, x26
 492 
 493 // ThreeRegOp
 494     __ udivw(r11, r12, r16);                           //        udiv        w11, w12, w16
 495     __ sdivw(r4, r9, r7);                              //        sdiv        w4, w9, w7
 496     __ lslvw(r12, r7, r16);                            //        lslv        w12, w7, w16
 497     __ lsrvw(r19, r16, r23);                           //        lsrv        w19, w16, w23
 498     __ asrvw(r7, r4, r6);                              //        asrv        w7, w4, w6
 499     __ rorvw(r21, r20, r23);                           //        rorv        w21, w20, w23
 500     __ udiv(r16, r12, r28);                            //        udiv        x16, x12, x28
 501     __ sdiv(r4, r12, r13);                             //        sdiv        x4, x12, x13
 502     __ lslv(r9, r13, r7);                              //        lslv        x9, x13, x7
 503     __ lsrv(r28, r27, r15);                            //        lsrv        x28, x27, x15
 504     __ asrv(r20, r30, r14);                            //        asrv        x20, x30, x14
 505     __ rorv(r14, r18, r30);                            //        rorv        x14, x18, x30
 506     __ umulh(r3, r11, r7);                             //        umulh        x3, x11, x7
 507     __ smulh(r23, r20, r24);                           //        smulh        x23, x20, x24
 508 
 509 // FourRegMulOp
 510     __ maddw(r2, r5, r21, r9);                         //        madd        w2, w5, w21, w9
 511     __ msubw(r24, r24, r4, r8);                        //        msub        w24, w24, w4, w8
 512     __ madd(r11, r12, r15, r19);                       //        madd        x11, x12, x15, x19
 513     __ msub(r29, r25, r12, r25);                       //        msub        x29, x25, x12, x25
 514     __ smaddl(r17, r11, r12, r22);                     //        smaddl        x17, w11, w12, x22
 515     __ smsubl(r28, r3, r20, r18);                      //        smsubl        x28, w3, w20, x18
 516     __ umaddl(r7, r4, r28, r26);                       //        umaddl        x7, w4, w28, x26
 517     __ umsubl(r22, r10, r17, r5);                      //        umsubl        x22, w10, w17, x5
 518 
 519 // ThreeRegFloatOp
 520     __ fmuls(v17, v3, v17);                            //        fmul        s17, s3, s17
 521     __ fdivs(v11, v17, v6);                            //        fdiv        s11, s17, s6
 522     __ fadds(v29, v7, v9);                             //        fadd        s29, s7, s9
 523     __ fsubs(v7, v12, v19);                            //        fsub        s7, s12, s19
 524     __ fmuls(v0, v23, v3);                             //        fmul        s0, s23, s3
 525     __ fmuld(v26, v3, v21);                            //        fmul        d26, d3, d21
 526     __ fdivd(v0, v19, v5);                             //        fdiv        d0, d19, d5
 527     __ faddd(v0, v26, v9);                             //        fadd        d0, d26, d9
 528     __ fsubd(v25, v21, v21);                           //        fsub        d25, d21, d21
 529     __ fmuld(v16, v13, v19);                           //        fmul        d16, d13, d19
 530 
 531 // FourRegFloatOp
 532     __ fmadds(v29, v18, v0, v16);                      //        fmadd        s29, s18, s0, s16
 533     __ fmsubs(v23, v13, v29, v5);                      //        fmsub        s23, s13, s29, s5
 534     __ fnmadds(v9, v7, v10, v14);                      //        fnmadd        s9, s7, s10, s14
 535     __ fnmadds(v25, v28, v15, v23);                    //        fnmadd        s25, s28, s15, s23
 536     __ fmaddd(v6, v13, v21, v17);                      //        fmadd        d6, d13, d21, d17
 537     __ fmsubd(v3, v21, v2, v7);                        //        fmsub        d3, d21, d2, d7
 538     __ fnmaddd(v10, v25, v5, v17);                     //        fnmadd        d10, d25, d5, d17
 539     __ fnmaddd(v14, v14, v20, v18);                    //        fnmadd        d14, d14, d20, d18
 540 
 541 // TwoRegFloatOp
 542     __ fmovs(v15, v2);                                 //        fmov        s15, s2
 543     __ fabss(v18, v7);                                 //        fabs        s18, s7
 544     __ fnegs(v3, v6);                                  //        fneg        s3, s6
 545     __ fsqrts(v12, v1);                                //        fsqrt        s12, s1
 546     __ fcvts(v9, v0);                                  //        fcvt        d9, s0
 547     __ fmovd(v4, v5);                                  //        fmov        d4, d5
 548     __ fabsd(v3, v15);                                 //        fabs        d3, d15
 549     __ fnegd(v17, v25);                                //        fneg        d17, d25
 550     __ fsqrtd(v12, v24);                               //        fsqrt        d12, d24
 551     __ fcvtd(v21, v5);                                 //        fcvt        s21, d5
 552 
 553 // FloatConvertOp
 554     __ fcvtzsw(r4, v21);                               //        fcvtzs        w4, s21
 555     __ fcvtzs(r27, v3);                                //        fcvtzs        x27, s3
 556     __ fcvtzdw(r29, v8);                               //        fcvtzs        w29, d8
 557     __ fcvtzd(r9, v21);                                //        fcvtzs        x9, d21
 558     __ scvtfws(v20, r29);                              //        scvtf        s20, w29
 559     __ scvtfs(v7, r8);                                 //        scvtf        s7, x8
 560     __ scvtfwd(v12, r21);                              //        scvtf        d12, w21
 561     __ scvtfd(v16, r21);                               //        scvtf        d16, x21
 562     __ fmovs(r18, v5);                                 //        fmov        w18, s5
 563     __ fmovd(r25, v8);                                 //        fmov        x25, d8
 564     __ fmovs(v18, r26);                                //        fmov        s18, w26
 565     __ fmovd(v0, r11);                                 //        fmov        d0, x11
 566 
 567 // TwoRegFloatOp
 568     __ fcmps(v16, v6);                                 //        fcmp        s16, s6
 569     __ fcmpd(v16, v29);                                //        fcmp        d16, d29
 570     __ fcmps(v30, 0.0);                                //        fcmp        s30, #0.0
 571     __ fcmpd(v9, 0.0);                                 //        fcmp        d9, #0.0
 572 
 573 // LoadStorePairOp
 574     __ stpw(r27, r4, Address(r12, -16));               //        stp        w27, w4, [x12, #-16]
 575     __ ldpw(r3, r9, Address(r10, 80));                 //        ldp        w3, w9, [x10, #80]
 576     __ ldpsw(r16, r3, Address(r3, 64));                //        ldpsw        x16, x3, [x3, #64]
 577     __ stp(r10, r28, Address(r19, -192));              //        stp        x10, x28, [x19, #-192]
 578     __ ldp(r19, r18, Address(r7, -192));               //        ldp        x19, x18, [x7, #-192]
 579 
 580 // LoadStorePairOp
 581     __ stpw(r10, r16, Address(__ pre(r30, 16)));       //        stp        w10, w16, [x30, #16]!
 582     __ ldpw(r2, r4, Address(__ pre(r18, -240)));       //        ldp        w2, w4, [x18, #-240]!
 583     __ ldpsw(r24, r19, Address(__ pre(r13, 48)));      //        ldpsw        x24, x19, [x13, #48]!
 584     __ stp(r17, r0, Address(__ pre(r24, 0)));          //        stp        x17, x0, [x24, #0]!
 585     __ ldp(r14, r26, Address(__ pre(r3, -192)));       //        ldp        x14, x26, [x3, #-192]!
 586 
 587 // LoadStorePairOp
 588     __ stpw(r22, r1, Address(__ post(r0, 80)));        //        stp        w22, w1, [x0], #80
 589     __ ldpw(r18, r10, Address(__ post(r0, -16)));      //        ldp        w18, w10, [x0], #-16
 590     __ ldpsw(r24, r24, Address(__ post(r22, -16)));    //        ldpsw        x24, x24, [x22], #-16
 591     __ stp(r12, r12, Address(__ post(r4, 80)));        //        stp        x12, x12, [x4], #80
 592     __ ldp(r4, r9, Address(__ post(r19, -240)));       //        ldp        x4, x9, [x19], #-240
 593 
 594 // LoadStorePairOp
 595     __ stnpw(r18, r26, Address(r6, -224));             //        stnp        w18, w26, [x6, #-224]
 596     __ ldnpw(r21, r20, Address(r1, 112));              //        ldnp        w21, w20, [x1, #112]
 597     __ stnp(r25, r29, Address(r20, -224));             //        stnp        x25, x29, [x20, #-224]
 598     __ ldnp(r1, r5, Address(r23, 112));                //        ldnp        x1, x5, [x23, #112]
 599 
 600 // LdStSIMDOp
 601     __ ld1(v4, __ T8B, Address(r20));                  //        ld1        {v4.8B}, [x20]
 602     __ ld1(v24, v25, __ T16B, Address(__ post(r10, 32))); //        ld1        {v24.16B, v25.16B}, [x10], 32
 603     __ ld1(v24, v25, v26, __ T1D, Address(__ post(r6, r15))); //        ld1        {v24.1D, v25.1D, v26.1D}, [x6], x15
 604     __ ld1(v3, v4, v5, v6, __ T8H, Address(__ post(r4, 64))); //        ld1        {v3.8H, v4.8H, v5.8H, v6.8H}, [x4], 64
 605     __ ld1r(v2, __ T8B, Address(r6));                  //        ld1r        {v2.8B}, [x6]
 606     __ ld1r(v13, __ T4S, Address(__ post(r14, 4)));    //        ld1r        {v13.4S}, [x14], 4
 607     __ ld1r(v15, __ T1D, Address(__ post(r21, r24)));  //        ld1r        {v15.1D}, [x21], x24
 608     __ ld2(v9, v10, __ T2D, Address(r21));             //        ld2        {v9.2D, v10.2D}, [x21]
 609     __ ld2(v29, v30, __ T4H, Address(__ post(r21, 16))); //        ld2        {v29.4H, v30.4H}, [x21], 16
 610     __ ld2r(v8, v9, __ T16B, Address(r14));            //        ld2r        {v8.16B, v9.16B}, [x14]
 611     __ ld2r(v7, v8, __ T2S, Address(__ post(r20, 8))); //        ld2r        {v7.2S, v8.2S}, [x20], 8
 612     __ ld2r(v28, v29, __ T2D, Address(__ post(r3, r3))); //        ld2r        {v28.2D, v29.2D}, [x3], x3
 613     __ ld3(v27, v28, v29, __ T4S, Address(__ post(r11, r29))); //        ld3        {v27.4S, v28.4S, v29.4S}, [x11], x29
 614     __ ld3(v16, v17, v18, __ T2S, Address(r10));       //        ld3        {v16.2S, v17.2S, v18.2S}, [x10]
 615     __ ld3r(v21, v22, v23, __ T8H, Address(r12));      //        ld3r        {v21.8H, v22.8H, v23.8H}, [x12]
 616     __ ld3r(v4, v5, v6, __ T4S, Address(__ post(r29, 12))); //        ld3r        {v4.4S, v5.4S, v6.4S}, [x29], 12
 617     __ ld3r(v24, v25, v26, __ T1D, Address(__ post(r9, r19))); //        ld3r        {v24.1D, v25.1D, v26.1D}, [x9], x19
 618     __ ld4(v10, v11, v12, v13, __ T8H, Address(__ post(r3, 64))); //        ld4        {v10.8H, v11.8H, v12.8H, v13.8H}, [x3], 64
 619     __ ld4(v27, v28, v29, v30, __ T8B, Address(__ post(r28, r9))); //        ld4        {v27.8B, v28.8B, v29.8B, v30.8B}, [x28], x9
 620     __ ld4r(v21, v22, v23, v24, __ T8B, Address(r30)); //        ld4r        {v21.8B, v22.8B, v23.8B, v24.8B}, [x30]
 621     __ ld4r(v23, v24, v25, v26, __ T4H, Address(__ post(r14, 8))); //        ld4r        {v23.4H, v24.4H, v25.4H, v26.4H}, [x14], 8
 622     __ ld4r(v4, v5, v6, v7, __ T2S, Address(__ post(r13, r20))); //        ld4r        {v4.2S, v5.2S, v6.2S, v7.2S}, [x13], x20
 623 
 624 // SpecialCases
 625     __ ccmn(zr, zr, 3u, Assembler::LE);                //        ccmn        xzr, xzr, #3, LE
 626     __ ccmnw(zr, zr, 5u, Assembler::EQ);               //        ccmn        wzr, wzr, #5, EQ
 627     __ ccmp(zr, 1, 4u, Assembler::NE);                 //        ccmp        xzr, 1, #4, NE
 628     __ ccmpw(zr, 2, 2, Assembler::GT);                 //        ccmp        wzr, 2, #2, GT
 629     __ extr(zr, zr, zr, 0);                            //        extr        xzr, xzr, xzr, 0
 630     __ stlxp(r0, zr, zr, sp);                          //        stlxp        w0, xzr, xzr, [sp]
 631     __ stlxpw(r2, zr, zr, r3);                         //        stlxp        w2, wzr, wzr, [x3]
 632     __ stxp(r4, zr, zr, r5);                           //        stxp        w4, xzr, xzr, [x5]
 633     __ stxpw(r6, zr, zr, sp);                          //        stxp        w6, wzr, wzr, [sp]
 634     __ dup(v0, __ T16B, zr);                           //        dup        v0.16b, wzr
 635     __ mov(v1, __ T1D, 0, zr);                         //        mov        v1.d[0], xzr
 636     __ mov(v1, __ T2S, 1, zr);                         //        mov        v1.s[1], wzr
 637     __ mov(v1, __ T4H, 2, zr);                         //        mov        v1.h[2], wzr
 638     __ mov(v1, __ T8B, 3, zr);                         //        mov        v1.b[3], wzr
 639     __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); //        ld1        {v31.2d, v0.2d}, [x1], x0
 640 
 641 // FloatImmediateOp
 642     __ fmovd(v0, 2.0);                                 //        fmov d0, #2.0
 643     __ fmovd(v0, 2.125);                               //        fmov d0, #2.125
 644     __ fmovd(v0, 4.0);                                 //        fmov d0, #4.0
 645     __ fmovd(v0, 4.25);                                //        fmov d0, #4.25
 646     __ fmovd(v0, 8.0);                                 //        fmov d0, #8.0
 647     __ fmovd(v0, 8.5);                                 //        fmov d0, #8.5
 648     __ fmovd(v0, 16.0);                                //        fmov d0, #16.0
 649     __ fmovd(v0, 17.0);                                //        fmov d0, #17.0
 650     __ fmovd(v0, 0.125);                               //        fmov d0, #0.125
 651     __ fmovd(v0, 0.1328125);                           //        fmov d0, #0.1328125
 652     __ fmovd(v0, 0.25);                                //        fmov d0, #0.25
 653     __ fmovd(v0, 0.265625);                            //        fmov d0, #0.265625
 654     __ fmovd(v0, 0.5);                                 //        fmov d0, #0.5
 655     __ fmovd(v0, 0.53125);                             //        fmov d0, #0.53125
 656     __ fmovd(v0, 1.0);                                 //        fmov d0, #1.0
 657     __ fmovd(v0, 1.0625);                              //        fmov d0, #1.0625
 658     __ fmovd(v0, -2.0);                                //        fmov d0, #-2.0
 659     __ fmovd(v0, -2.125);                              //        fmov d0, #-2.125
 660     __ fmovd(v0, -4.0);                                //        fmov d0, #-4.0
 661     __ fmovd(v0, -4.25);                               //        fmov d0, #-4.25
 662     __ fmovd(v0, -8.0);                                //        fmov d0, #-8.0
 663     __ fmovd(v0, -8.5);                                //        fmov d0, #-8.5
 664     __ fmovd(v0, -16.0);                               //        fmov d0, #-16.0
 665     __ fmovd(v0, -17.0);                               //        fmov d0, #-17.0
 666     __ fmovd(v0, -0.125);                              //        fmov d0, #-0.125
 667     __ fmovd(v0, -0.1328125);                          //        fmov d0, #-0.1328125
 668     __ fmovd(v0, -0.25);                               //        fmov d0, #-0.25
 669     __ fmovd(v0, -0.265625);                           //        fmov d0, #-0.265625
 670     __ fmovd(v0, -0.5);                                //        fmov d0, #-0.5
 671     __ fmovd(v0, -0.53125);                            //        fmov d0, #-0.53125
 672     __ fmovd(v0, -1.0);                                //        fmov d0, #-1.0
 673     __ fmovd(v0, -1.0625);                             //        fmov d0, #-1.0625
 674 
 675 // LSEOp
 676     __ swp(Assembler::xword, r21, r5, r24);            //        swp        x21, x5, [x24]
 677     __ ldadd(Assembler::xword, r13, r13, r15);         //        ldadd        x13, x13, [x15]
 678     __ ldbic(Assembler::xword, r22, r19, r26);         //        ldclr        x22, x19, [x26]
 679     __ ldeor(Assembler::xword, r25, r10, r26);         //        ldeor        x25, x10, [x26]
 680     __ ldorr(Assembler::xword, r5, r27, r15);          //        ldset        x5, x27, [x15]
 681     __ ldsmin(Assembler::xword, r19, r5, r11);         //        ldsmin        x19, x5, [x11]
 682     __ ldsmax(Assembler::xword, r26, r0, r4);          //        ldsmax        x26, x0, [x4]
 683     __ ldumin(Assembler::xword, r22, r23, r30);        //        ldumin        x22, x23, [x30]
 684     __ ldumax(Assembler::xword, r18, r28, r8);         //        ldumax        x18, x28, [x8]
 685 
 686 // LSEOp
 687     __ swpa(Assembler::xword, r13, r29, r27);          //        swpa        x13, x29, [x27]
 688     __ ldadda(Assembler::xword, r11, r5, r13);         //        ldadda        x11, x5, [x13]
 689     __ ldbica(Assembler::xword, r1, r24, r21);         //        ldclra        x1, x24, [x21]
 690     __ ldeora(Assembler::xword, r27, r17, r24);        //        ldeora        x27, x17, [x24]
 691     __ ldorra(Assembler::xword, r18, r30, r5);         //        ldseta        x18, x30, [x5]
 692     __ ldsmina(Assembler::xword, r7, r22, r25);        //        ldsmina        x7, x22, [x25]
 693     __ ldsmaxa(Assembler::xword, r4, r26, r19);        //        ldsmaxa        x4, x26, [x19]
 694     __ ldumina(Assembler::xword, r6, r30, r3);         //        ldumina        x6, x30, [x3]
 695     __ ldumaxa(Assembler::xword, r24, r23, r5);        //        ldumaxa        x24, x23, [x5]
 696 
 697 // LSEOp
 698     __ swpal(Assembler::xword, r24, r18, r28);         //        swpal        x24, x18, [x28]
 699     __ ldaddal(Assembler::xword, r19, zr, r7);         //        ldaddal        x19, xzr, [x7]
 700     __ ldbical(Assembler::xword, r13, r6, r28);        //        ldclral        x13, x6, [x28]
 701     __ ldeoral(Assembler::xword, r8, r15, r21);        //        ldeoral        x8, x15, [x21]
 702     __ ldorral(Assembler::xword, r2, r13, r1);         //        ldsetal        x2, x13, [x1]
 703     __ ldsminal(Assembler::xword, r17, r29, r25);      //        ldsminal        x17, x29, [x25]
 704     __ ldsmaxal(Assembler::xword, r25, r18, r14);      //        ldsmaxal        x25, x18, [x14]
 705     __ lduminal(Assembler::xword, zr, r6, r27);        //        lduminal        xzr, x6, [x27]
 706     __ ldumaxal(Assembler::xword, r16, r5, r15);       //        ldumaxal        x16, x5, [x15]
 707 
 708 // LSEOp
 709     __ swpl(Assembler::xword, r11, r18, r3);           //        swpl        x11, x18, [x3]
 710     __ ldaddl(Assembler::xword, r26, r20, r2);         //        ldaddl        x26, x20, [x2]
 711     __ ldbicl(Assembler::xword, r11, r4, r11);         //        ldclrl        x11, x4, [x11]
 712     __ ldeorl(Assembler::xword, r30, r19, r23);        //        ldeorl        x30, x19, [x23]
 713     __ ldorrl(Assembler::xword, r3, r15, r14);         //        ldsetl        x3, x15, [x14]
 714     __ ldsminl(Assembler::xword, r30, r22, r20);       //        ldsminl        x30, x22, [x20]
 715     __ ldsmaxl(Assembler::xword, r7, r5, r24);         //        ldsmaxl        x7, x5, [x24]
 716     __ lduminl(Assembler::xword, r23, r16, r15);       //        lduminl        x23, x16, [x15]
 717     __ ldumaxl(Assembler::xword, r11, r19, r0);        //        ldumaxl        x11, x19, [x0]
 718 
 719 // LSEOp
 720     __ swp(Assembler::word, r28, r28, r1);             //        swp        w28, w28, [x1]
 721     __ ldadd(Assembler::word, r11, r21, r12);          //        ldadd        w11, w21, [x12]
 722     __ ldbic(Assembler::word, r29, r0, r18);           //        ldclr        w29, w0, [x18]
 723     __ ldeor(Assembler::word, r5, r0, r25);            //        ldeor        w5, w0, [x25]
 724     __ ldorr(Assembler::word, r14, r0, r26);           //        ldset        w14, w0, [x26]
 725     __ ldsmin(Assembler::word, r28, r18, r29);         //        ldsmin        w28, w18, [x29]
 726     __ ldsmax(Assembler::word, r15, r1, r29);          //        ldsmax        w15, w1, [x29]
 727     __ ldumin(Assembler::word, r8, r26, r28);          //        ldumin        w8, w26, [x28]
 728     __ ldumax(Assembler::word, r17, r14, r4);          //        ldumax        w17, w14, [x4]
 729 
 730 // LSEOp
 731     __ swpa(Assembler::word, r24, r25, r1);            //        swpa        w24, w25, [x1]
 732     __ ldadda(Assembler::word, r10, r17, r17);         //        ldadda        w10, w17, [x17]
 733     __ ldbica(Assembler::word, r29, r20, r21);         //        ldclra        w29, w20, [x21]
 734     __ ldeora(Assembler::word, r29, r9, r12);          //        ldeora        w29, w9, [x12]
 735     __ ldorra(Assembler::word, r11, r6, r5);           //        ldseta        w11, w6, [x5]
 736     __ ldsmina(Assembler::word, r21, r7, r21);         //        ldsmina        w21, w7, [x21]
 737     __ ldsmaxa(Assembler::word, r10, r23, r12);        //        ldsmaxa        w10, w23, [x12]
 738     __ ldumina(Assembler::word, r21, r5, r10);         //        ldumina        w21, w5, [x10]
 739     __ ldumaxa(Assembler::word, r30, r20, r18);        //        ldumaxa        w30, w20, [x18]
 740 
 741 // LSEOp
 742     __ swpal(Assembler::word, r13, r23, r5);           //        swpal        w13, w23, [x5]
 743     __ ldaddal(Assembler::word, r15, r24, r5);         //        ldaddal        w15, w24, [x5]
 744     __ ldbical(Assembler::word, r9, r10, r25);         //        ldclral        w9, w10, [x25]
 745     __ ldeoral(Assembler::word, r20, r17, r17);        //        ldeoral        w20, w17, [x17]
 746     __ ldorral(Assembler::word, r12, r18, r30);        //        ldsetal        w12, w18, [x30]
 747     __ ldsminal(Assembler::word, r3, r3, r25);         //        ldsminal        w3, w3, [x25]
 748     __ ldsmaxal(Assembler::word, r26, r25, r10);       //        ldsmaxal        w26, w25, [x10]
 749     __ lduminal(Assembler::word, r2, r11, sp);         //        lduminal        w2, w11, [sp]
 750     __ ldumaxal(Assembler::word, r7, r2, r5);          //        ldumaxal        w7, w2, [x5]
 751 
 752 // LSEOp
 753     __ swpl(Assembler::word, r0, r7, r20);             //        swpl        w0, w7, [x20]
 754     __ ldaddl(Assembler::word, r5, zr, r2);            //        ldaddl        w5, wzr, [x2]
 755     __ ldbicl(Assembler::word, r27, r25, r27);         //        ldclrl        w27, w25, [x27]
 756     __ ldeorl(Assembler::word, r30, r24, r26);         //        ldeorl        w30, w24, [x26]
 757     __ ldorrl(Assembler::word, r15, r2, r22);          //        ldsetl        w15, w2, [x22]
 758     __ ldsminl(Assembler::word, r0, r3, sp);           //        ldsminl        w0, w3, [sp]
 759     __ ldsmaxl(Assembler::word, r15, r20, r10);        //        ldsmaxl        w15, w20, [x10]
 760     __ lduminl(Assembler::word, r22, r21, r14);        //        lduminl        w22, w21, [x14]
 761     __ ldumaxl(Assembler::word, r6, r30, r2);          //        ldumaxl        w6, w30, [x2]
 762 
 763     __ bind(forth);
 764 
 765 /*
 766 aarch64ops.o:     file format elf64-littleaarch64
 767 
 768 
 769 Disassembly of section .text:
 770 
 771 0000000000000000 <back>:
 772    0:        8b50798f         add        x15, x12, x16, lsr #30
 773    4:        cb4381e1         sub        x1, x15, x3, lsr #32
 774    8:        ab05372d         adds        x13, x25, x5, lsl #13
 775    c:        eb864796         subs        x22, x28, x6, asr #17
 776   10:        0b961920         add        w0, w9, w22, asr #6
 777   14:        4b195473         sub        w19, w3, w25, lsl #21
 778   18:        2b0b5264         adds        w4, w19, w11, lsl #20
 779   1c:        6b9300f8         subs        w24, w7, w19, asr #0
 780   20:        8a0bc0fe         and        x30, x7, x11, lsl #48
 781   24:        aa0f3118         orr        x24, x8, x15, lsl #12
 782   28:        ca170531         eor        x17, x9, x23, lsl #1
 783   2c:        ea44dd6e         ands        x14, x11, x4, lsr #55
 784   30:        0a4c44f3         and        w19, w7, w12, lsr #17
 785   34:        2a8b7373         orr        w19, w27, w11, asr #28
 786   38:        4a567c7e         eor        w30, w3, w22, lsr #31
 787   3c:        6a9c0353         ands        w19, w26, w28, asr #0
 788   40:        8a3accdd         bic        x29, x6, x26, lsl #51
 789   44:        aa318f7a         orn        x26, x27, x17, lsl #35
 790   48:        ca2e1495         eon        x21, x4, x14, lsl #5
 791   4c:        eaa015e2         bics        x2, x15, x0, asr #5
 792   50:        0a2274e2         bic        w2, w7, w2, lsl #29
 793   54:        2a751598         orn        w24, w12, w21, lsr #5
 794   58:        4a3309fe         eon        w30, w15, w19, lsl #2
 795   5c:        6ab172fe         bics        w30, w23, w17, asr #28
 796   60:        110a5284         add        w4, w20, #0x294
 797   64:        310b1942         adds        w2, w10, #0x2c6
 798   68:        5103d353         sub        w19, w26, #0xf4
 799   6c:        710125bc         subs        w28, w13, #0x49
 800   70:        910d7bc2         add        x2, x30, #0x35e
 801   74:        b108fa1b         adds        x27, x16, #0x23e
 802   78:        d1093536         sub        x22, x9, #0x24d
 803   7c:        f10ae824         subs        x4, x1, #0x2ba
 804   80:        120e667c         and        w28, w19, #0xfffc0fff
 805   84:        321f6cbb         orr        w27, w5, #0x1ffffffe
 806   88:        520f6a9e         eor        w30, w20, #0xfffe0fff
 807   8c:        72136f56         ands        w22, w26, #0xffffe1ff
 808   90:        927e4ce5         and        x5, x7, #0x3ffffc
 809   94:        b278b4ed         orr        x13, x7, #0x3fffffffffff00
 810   98:        d24c6527         eor        x7, x9, #0xfff0000000003fff
 811   9c:        f2485803         ands        x3, x0, #0xff00000000007fff
 812   a0:        14000000         b        a0 <back+0xa0>
 813   a4:        17ffffd7         b        0 <back>
 814   a8:        140001ee         b        860 <forth>
 815   ac:        94000000         bl        ac <back+0xac>
 816   b0:        97ffffd4         bl        0 <back>
 817   b4:        940001eb         bl        860 <forth>
 818   b8:        34000010         cbz        w16, b8 <back+0xb8>
 819   bc:        34fffa30         cbz        w16, 0 <back>
 820   c0:        34003d10         cbz        w16, 860 <forth>
 821   c4:        35000013         cbnz        w19, c4 <back+0xc4>
 822   c8:        35fff9d3         cbnz        w19, 0 <back>
 823   cc:        35003cb3         cbnz        w19, 860 <forth>
 824   d0:        b4000005         cbz        x5, d0 <back+0xd0>
 825   d4:        b4fff965         cbz        x5, 0 <back>
 826   d8:        b4003c45         cbz        x5, 860 <forth>
 827   dc:        b5000004         cbnz        x4, dc <back+0xdc>
 828   e0:        b5fff904         cbnz        x4, 0 <back>
 829   e4:        b5003be4         cbnz        x4, 860 <forth>
 830   e8:        1000001b         adr        x27, e8 <back+0xe8>
 831   ec:        10fff8bb         adr        x27, 0 <back>
 832   f0:        10003b9b         adr        x27, 860 <forth>
 833   f4:        90000010         adrp        x16, 0 <back>
 834   f8:        3640001c         tbz        w28, #8, f8 <back+0xf8>
 835   fc:        3647f83c         tbz        w28, #8, 0 <back>
 836  100:        36403b1c         tbz        w28, #8, 860 <forth>
 837  104:        37080001         tbnz        w1, #1, 104 <back+0x104>
 838  108:        370ff7c1         tbnz        w1, #1, 0 <back>
 839  10c:        37083aa1         tbnz        w1, #1, 860 <forth>
 840  110:        12a437f4         mov        w20, #0xde40ffff                    // #-566165505
 841  114:        528c9d67         mov        w7, #0x64eb                        // #25835
 842  118:        72838bb1         movk        w17, #0x1c5d
 843  11c:        92c1062e         mov        x14, #0xfffff7ceffffffff            // #-9006546419713
 844  120:        d287da49         mov        x9, #0x3ed2                        // #16082
 845  124:        f2a6d153         movk        x19, #0x368a, lsl #16
 846  128:        93465ac9         sbfx        x9, x22, #6, #17
 847  12c:        330b0013         bfi        w19, w0, #21, #1
 848  130:        530b4e6a         ubfx        w10, w19, #11, #9
 849  134:        934545e4         sbfx        x4, x15, #5, #13
 850  138:        b35370a3         bfxil        x3, x5, #19, #10
 851  13c:        d3510b8c         ubfiz        x12, x28, #47, #3
 852  140:        13960c0f         extr        w15, w0, w22, #3
 853  144:        93ceddc6         ror        x6, x14, #55
 854  148:        54000000         b.eq        148 <back+0x148>  // b.none
 855  14c:        54fff5a0         b.eq        0 <back>  // b.none
 856  150:        54003880         b.eq        860 <forth>  // b.none
 857  154:        54000001         b.ne        154 <back+0x154>  // b.any
 858  158:        54fff541         b.ne        0 <back>  // b.any
 859  15c:        54003821         b.ne        860 <forth>  // b.any
 860  160:        54000002         b.cs        160 <back+0x160>  // b.hs, b.nlast
 861  164:        54fff4e2         b.cs        0 <back>  // b.hs, b.nlast
 862  168:        540037c2         b.cs        860 <forth>  // b.hs, b.nlast
 863  16c:        54000002         b.cs        16c <back+0x16c>  // b.hs, b.nlast
 864  170:        54fff482         b.cs        0 <back>  // b.hs, b.nlast
 865  174:        54003762         b.cs        860 <forth>  // b.hs, b.nlast
 866  178:        54000003         b.cc        178 <back+0x178>  // b.lo, b.ul, b.last
 867  17c:        54fff423         b.cc        0 <back>  // b.lo, b.ul, b.last
 868  180:        54003703         b.cc        860 <forth>  // b.lo, b.ul, b.last
 869  184:        54000003         b.cc        184 <back+0x184>  // b.lo, b.ul, b.last
 870  188:        54fff3c3         b.cc        0 <back>  // b.lo, b.ul, b.last
 871  18c:        540036a3         b.cc        860 <forth>  // b.lo, b.ul, b.last
 872  190:        54000004         b.mi        190 <back+0x190>  // b.first
 873  194:        54fff364         b.mi        0 <back>  // b.first
 874  198:        54003644         b.mi        860 <forth>  // b.first
 875  19c:        54000005         b.pl        19c <back+0x19c>  // b.nfrst
 876  1a0:        54fff305         b.pl        0 <back>  // b.nfrst
 877  1a4:        540035e5         b.pl        860 <forth>  // b.nfrst
 878  1a8:        54000006         b.vs        1a8 <back+0x1a8>
 879  1ac:        54fff2a6         b.vs        0 <back>
 880  1b0:        54003586         b.vs        860 <forth>
 881  1b4:        54000007         b.vc        1b4 <back+0x1b4>
 882  1b8:        54fff247         b.vc        0 <back>
 883  1bc:        54003527         b.vc        860 <forth>
 884  1c0:        54000008         b.hi        1c0 <back+0x1c0>  // b.pmore
 885  1c4:        54fff1e8         b.hi        0 <back>  // b.pmore
 886  1c8:        540034c8         b.hi        860 <forth>  // b.pmore
 887  1cc:        54000009         b.ls        1cc <back+0x1cc>  // b.plast
 888  1d0:        54fff189         b.ls        0 <back>  // b.plast
 889  1d4:        54003469         b.ls        860 <forth>  // b.plast
 890  1d8:        5400000a         b.ge        1d8 <back+0x1d8>  // b.tcont
 891  1dc:        54fff12a         b.ge        0 <back>  // b.tcont
 892  1e0:        5400340a         b.ge        860 <forth>  // b.tcont
 893  1e4:        5400000b         b.lt        1e4 <back+0x1e4>  // b.tstop
 894  1e8:        54fff0cb         b.lt        0 <back>  // b.tstop
 895  1ec:        540033ab         b.lt        860 <forth>  // b.tstop
 896  1f0:        5400000c         b.gt        1f0 <back+0x1f0>
 897  1f4:        54fff06c         b.gt        0 <back>
 898  1f8:        5400334c         b.gt        860 <forth>
 899  1fc:        5400000d         b.le        1fc <back+0x1fc>
 900  200:        54fff00d         b.le        0 <back>
 901  204:        540032ed         b.le        860 <forth>
 902  208:        5400000e         b.al        208 <back+0x208>
 903  20c:        54ffefae         b.al        0 <back>
 904  210:        5400328e         b.al        860 <forth>
 905  214:        5400000f         b.nv        214 <back+0x214>
 906  218:        54ffef4f         b.nv        0 <back>
 907  21c:        5400322f         b.nv        860 <forth>
 908  220:        d40ac601         svc        #0x5630
 909  224:        d40042a2         hvc        #0x215
 910  228:        d404dac3         smc        #0x26d6
 911  22c:        d4224d40         brk        #0x126a
 912  230:        d44219c0         hlt        #0x10ce
 913  234:        d503201f         nop
 914  238:        d69f03e0         eret
 915  23c:        d6bf03e0         drps
 916  240:        d5033fdf         isb
 917  244:        d503339f         dsb        osh
 918  248:        d50335bf         dmb        nshld
 919  24c:        d61f0280         br        x20
 920  250:        d63f0040         blr        x2
 921  254:        c8127c17         stxr        w18, x23, [x0]
 922  258:        c81efec5         stlxr        w30, x5, [x22]
 923  25c:        c85f7d05         ldxr        x5, [x8]
 924  260:        c85ffe14         ldaxr        x20, [x16]
 925  264:        c89ffd66         stlr        x6, [x11]
 926  268:        c8dfff66         ldar        x6, [x27]
 927  26c:        880a7cb1         stxr        w10, w17, [x5]
 928  270:        8816fd89         stlxr        w22, w9, [x12]
 929  274:        885f7d1b         ldxr        w27, [x8]
 930  278:        885ffc57         ldaxr        w23, [x2]
 931  27c:        889fffba         stlr        w26, [x29]
 932  280:        88dffd4d         ldar        w13, [x10]
 933  284:        48197f7c         stxrh        w25, w28, [x27]
 934  288:        481dfd96         stlxrh        w29, w22, [x12]
 935  28c:        485f7f96         ldxrh        w22, [x28]
 936  290:        485fffc3         ldaxrh        w3, [x30]
 937  294:        489ffdf8         stlrh        w24, [x15]
 938  298:        48dfff5b         ldarh        w27, [x26]
 939  29c:        080b7e6a         stxrb        w11, w10, [x19]
 940  2a0:        0817fedb         stlxrb        w23, w27, [x22]
 941  2a4:        085f7e18         ldxrb        w24, [x16]
 942  2a8:        085ffc38         ldaxrb        w24, [x1]
 943  2ac:        089fffa5         stlrb        w5, [x29]
 944  2b0:        08dffe18         ldarb        w24, [x16]
 945  2b4:        c87f6239         ldxp        x25, x24, [x17]
 946  2b8:        c87fb276         ldaxp        x22, x12, [x19]
 947  2bc:        c820573a         stxp        w0, x26, x21, [x25]
 948  2c0:        c821aca6         stlxp        w1, x6, x11, [x5]
 949  2c4:        887f388d         ldxp        w13, w14, [x4]
 950  2c8:        887f88d1         ldaxp        w17, w2, [x6]
 951  2cc:        882f2643         stxp        w15, w3, w9, [x18]
 952  2d0:        88329131         stlxp        w18, w17, w4, [x9]
 953  2d4:        f81cf2b7         stur        x23, [x21, #-49]
 954  2d8:        b803f055         stur        w21, [x2, #63]
 955  2dc:        39002f9b         strb        w27, [x28, #11]
 956  2e0:        781f31fd         sturh        w29, [x15, #-13]
 957  2e4:        f85d33ce         ldur        x14, [x30, #-45]
 958  2e8:        b843539d         ldur        w29, [x28, #53]
 959  2ec:        39401f54         ldrb        w20, [x26, #7]
 960  2f0:        785ce059         ldurh        w25, [x2, #-50]
 961  2f4:        389f1143         ldursb        x3, [x10, #-15]
 962  2f8:        788131ee         ldursh        x14, [x15, #19]
 963  2fc:        78dfb17d         ldursh        w29, [x11, #-5]
 964  300:        b89b90af         ldursw        x15, [x5, #-71]
 965  304:        fc403193         ldur        d19, [x12, #3]
 966  308:        bc42a36c         ldur        s12, [x27, #42]
 967  30c:        fc07d396         stur        d22, [x28, #125]
 968  310:        bc1ec1f8         stur        s24, [x15, #-20]
 969  314:        f81e8f88         str        x8, [x28, #-24]!
 970  318:        b8025de6         str        w6, [x15, #37]!
 971  31c:        38007c27         strb        w7, [x1, #7]!
 972  320:        7801ee20         strh        w0, [x17, #30]!
 973  324:        f8454fb9         ldr        x25, [x29, #84]!
 974  328:        b85cce9a         ldr        w26, [x20, #-52]!
 975  32c:        385e7fba         ldrb        w26, [x29, #-25]!
 976  330:        7841af24         ldrh        w4, [x25, #26]!
 977  334:        389ebd1c         ldrsb        x28, [x8, #-21]!
 978  338:        789fadd1         ldrsh        x17, [x14, #-6]!
 979  33c:        78c0aefc         ldrsh        w28, [x23, #10]!
 980  340:        b89c0f7e         ldrsw        x30, [x27, #-64]!
 981  344:        fc50efd4         ldr        d20, [x30, #-242]!
 982  348:        bc414f71         ldr        s17, [x27, #20]!
 983  34c:        fc011c67         str        d7, [x3, #17]!
 984  350:        bc1f0d6d         str        s13, [x11, #-16]!
 985  354:        f81c3526         str        x6, [x9], #-61
 986  358:        b81e34b0         str        w16, [x5], #-29
 987  35c:        3800f7bd         strb        w29, [x29], #15
 988  360:        78012684         strh        w4, [x20], #18
 989  364:        f842e653         ldr        x19, [x18], #46
 990  368:        b8417456         ldr        w22, [x2], #23
 991  36c:        385e2467         ldrb        w7, [x3], #-30
 992  370:        785e358b         ldrh        w11, [x12], #-29
 993  374:        389e34c8         ldrsb        x8, [x6], #-29
 994  378:        788046f8         ldrsh        x24, [x23], #4
 995  37c:        78c00611         ldrsh        w17, [x16], #0
 996  380:        b89f8680         ldrsw        x0, [x20], #-8
 997  384:        fc582454         ldr        d20, [x2], #-126
 998  388:        bc5987d3         ldr        s19, [x30], #-104
 999  38c:        fc076624         str        d4, [x17], #118
1000  390:        bc190675         str        s21, [x19], #-112
1001  394:        f833785a         str        x26, [x2, x19, lsl #3]
1002  398:        b82fd809         str        w9, [x0, w15, sxtw #2]
1003  39c:        3821799a         strb        w26, [x12, x1, lsl #0]
1004  3a0:        782a7975         strh        w21, [x11, x10, lsl #1]
1005  3a4:        f870eaf0         ldr        x16, [x23, x16, sxtx]
1006  3a8:        b871d96a         ldr        w10, [x11, w17, sxtw #2]
1007  3ac:        386b7aed         ldrb        w13, [x23, x11, lsl #0]
1008  3b0:        7875689b         ldrh        w27, [x4, x21]
1009  3b4:        38afd91a         ldrsb        x26, [x8, w15, sxtw #0]
1010  3b8:        78a2c955         ldrsh        x21, [x10, w2, sxtw]
1011  3bc:        78ee6bc8         ldrsh        w8, [x30, x14]
1012  3c0:        b8b4f9dd         ldrsw        x29, [x14, x20, sxtx #2]
1013  3c4:        fc76eb7e         ldr        d30, [x27, x22, sxtx]
1014  3c8:        bc76692d         ldr        s13, [x9, x22]
1015  3cc:        fc31db28         str        d8, [x25, w17, sxtw #3]
1016  3d0:        bc255b01         str        s1, [x24, w5, uxtw #2]
1017  3d4:        f91c52aa         str        x10, [x21, #14496]
1018  3d8:        b91c3fb2         str        w18, [x29, #7228]
1019  3dc:        391f8877         strb        w23, [x3, #2018]
1020  3e0:        791ac97c         strh        w28, [x11, #3428]
1021  3e4:        f95c1758         ldr        x24, [x26, #14376]
1022  3e8:        b95b3c55         ldr        w21, [x2, #6972]
1023  3ec:        395ce0a4         ldrb        w4, [x5, #1848]
1024  3f0:        795851ce         ldrh        w14, [x14, #3112]
1025  3f4:        399e9f64         ldrsb        x4, [x27, #1959]
1026  3f8:        79993764         ldrsh        x4, [x27, #3226]
1027  3fc:        79d9af8a         ldrsh        w10, [x28, #3286]
1028  400:        b99eea2a         ldrsw        x10, [x17, #7912]
1029  404:        fd5a2f8d         ldr        d13, [x28, #13400]
1030  408:        bd5dac78         ldr        s24, [x3, #7596]
1031  40c:        fd1e0182         str        d2, [x12, #15360]
1032  410:        bd195c31         str        s17, [x1, #6492]
1033  414:        58000010         ldr        x16, 414 <back+0x414>
1034  418:        1800000d         ldr        w13, 418 <back+0x418>
1035  41c:        f8981240         prfum        pldl1keep, [x18, #-127]
1036  420:        d8ffdf00         prfm        pldl1keep, 0 <back>
1037  424:        f8a27a80         prfm        pldl1keep, [x20, x2, lsl #3]
1038  428:        f99af920         prfm        pldl1keep, [x9, #13808]
1039  42c:        1a0202e8         adc        w8, w23, w2
1040  430:        3a130078         adcs        w24, w3, w19
1041  434:        5a1d0316         sbc        w22, w24, w29
1042  438:        7a03036c         sbcs        w12, w27, w3
1043  43c:        9a0102eb         adc        x11, x23, x1
1044  440:        ba1700bd         adcs        x29, x5, x23
1045  444:        da0c0329         sbc        x9, x25, x12
1046  448:        fa16000c         sbcs        x12, x0, x22
1047  44c:        0b23459a         add        w26, w12, w3, uxtw #1
1048  450:        2b328a14         adds        w20, w16, w18, sxtb #2
1049  454:        cb274bde         sub        x30, x30, w7, uxtw #2
1050  458:        6b222eab         subs        w11, w21, w2, uxth #3
1051  45c:        8b214b42         add        x2, x26, w1, uxtw #2
1052  460:        ab34a7b2         adds        x18, x29, w20, sxth #1
1053  464:        cb24520e         sub        x14, x16, w4, uxtw #4
1054  468:        eb378e20         subs        x0, x17, w23, sxtb #3
1055  46c:        3a565283         ccmn        w20, w22, #0x3, pl  // pl = nfrst
1056  470:        7a420321         ccmp        w25, w2, #0x1, eq  // eq = none
1057  474:        ba58c247         ccmn        x18, x24, #0x7, gt
1058  478:        fa4d5106         ccmp        x8, x13, #0x6, pl  // pl = nfrst
1059  47c:        3a426924         ccmn        w9, #0x2, #0x4, vs
1060  480:        7a5b0847         ccmp        w2, #0x1b, #0x7, eq  // eq = none
1061  484:        ba413a02         ccmn        x16, #0x1, #0x2, cc  // cc = lo, ul, last
1062  488:        fa5fba23         ccmp        x17, #0x1f, #0x3, lt  // lt = tstop
1063  48c:        1a979377         csel        w23, w27, w23, ls  // ls = plast
1064  490:        1a86640a         csinc        w10, w0, w6, vs
1065  494:        5a89300b         csinv        w11, w0, w9, cc  // cc = lo, ul, last
1066  498:        5a923771         csneg        w17, w27, w18, cc  // cc = lo, ul, last
1067  49c:        9a8b720c         csel        x12, x16, x11, vc
1068  4a0:        9a868786         csinc        x6, x28, x6, hi  // hi = pmore
1069  4a4:        da9a736d         csinv        x13, x27, x26, vc
1070  4a8:        da9256dd         csneg        x29, x22, x18, pl  // pl = nfrst
1071  4ac:        5ac0026c         rbit        w12, w19
1072  4b0:        5ac00657         rev16        w23, w18
1073  4b4:        5ac00b89         rev        w9, w28
1074  4b8:        5ac01262         clz        w2, w19
1075  4bc:        5ac017b9         cls        w25, w29
1076  4c0:        dac002e4         rbit        x4, x23
1077  4c4:        dac0065d         rev16        x29, x18
1078  4c8:        dac00907         rev32        x7, x8
1079  4cc:        dac00e2d         rev        x13, x17
1080  4d0:        dac01011         clz        x17, x0
1081  4d4:        dac01752         cls        x18, x26
1082  4d8:        1ad0098b         udiv        w11, w12, w16
1083  4dc:        1ac70d24         sdiv        w4, w9, w7
1084  4e0:        1ad020ec         lsl        w12, w7, w16
1085  4e4:        1ad72613         lsr        w19, w16, w23
1086  4e8:        1ac62887         asr        w7, w4, w6
1087  4ec:        1ad72e95         ror        w21, w20, w23
1088  4f0:        9adc0990         udiv        x16, x12, x28
1089  4f4:        9acd0d84         sdiv        x4, x12, x13
1090  4f8:        9ac721a9         lsl        x9, x13, x7
1091  4fc:        9acf277c         lsr        x28, x27, x15
1092  500:        9ace2bd4         asr        x20, x30, x14
1093  504:        9ade2e4e         ror        x14, x18, x30
1094  508:        9bc77d63         umulh        x3, x11, x7
1095  50c:        9b587e97         smulh        x23, x20, x24
1096  510:        1b1524a2         madd        w2, w5, w21, w9
1097  514:        1b04a318         msub        w24, w24, w4, w8
1098  518:        9b0f4d8b         madd        x11, x12, x15, x19
1099  51c:        9b0ce73d         msub        x29, x25, x12, x25
1100  520:        9b2c5971         smaddl        x17, w11, w12, x22
1101  524:        9b34c87c         smsubl        x28, w3, w20, x18
1102  528:        9bbc6887         umaddl        x7, w4, w28, x26
1103  52c:        9bb19556         umsubl        x22, w10, w17, x5
1104  530:        1e310871         fmul        s17, s3, s17
1105  534:        1e261a2b         fdiv        s11, s17, s6
1106  538:        1e2928fd         fadd        s29, s7, s9
1107  53c:        1e333987         fsub        s7, s12, s19
1108  540:        1e230ae0         fmul        s0, s23, s3
1109  544:        1e75087a         fmul        d26, d3, d21
1110  548:        1e651a60         fdiv        d0, d19, d5
1111  54c:        1e692b40         fadd        d0, d26, d9
1112  550:        1e753ab9         fsub        d25, d21, d21
1113  554:        1e7309b0         fmul        d16, d13, d19
1114  558:        1f00425d         fmadd        s29, s18, s0, s16
1115  55c:        1f1d95b7         fmsub        s23, s13, s29, s5
1116  560:        1f2a38e9         fnmadd        s9, s7, s10, s14
1117  564:        1f2f5f99         fnmadd        s25, s28, s15, s23
1118  568:        1f5545a6         fmadd        d6, d13, d21, d17
1119  56c:        1f429ea3         fmsub        d3, d21, d2, d7
1120  570:        1f65472a         fnmadd        d10, d25, d5, d17
1121  574:        1f7449ce         fnmadd        d14, d14, d20, d18
1122  578:        1e20404f         fmov        s15, s2
1123  57c:        1e20c0f2         fabs        s18, s7
1124  580:        1e2140c3         fneg        s3, s6
1125  584:        1e21c02c         fsqrt        s12, s1
1126  588:        1e22c009         fcvt        d9, s0
1127  58c:        1e6040a4         fmov        d4, d5
1128  590:        1e60c1e3         fabs        d3, d15
1129  594:        1e614331         fneg        d17, d25
1130  598:        1e61c30c         fsqrt        d12, d24
1131  59c:        1e6240b5         fcvt        s21, d5
1132  5a0:        1e3802a4         fcvtzs        w4, s21
1133  5a4:        9e38007b         fcvtzs        x27, s3
1134  5a8:        1e78011d         fcvtzs        w29, d8
1135  5ac:        9e7802a9         fcvtzs        x9, d21
1136  5b0:        1e2203b4         scvtf        s20, w29
1137  5b4:        9e220107         scvtf        s7, x8
1138  5b8:        1e6202ac         scvtf        d12, w21
1139  5bc:        9e6202b0         scvtf        d16, x21
1140  5c0:        1e2600b2         fmov        w18, s5
1141  5c4:        9e660119         fmov        x25, d8
1142  5c8:        1e270352         fmov        s18, w26
1143  5cc:        9e670160         fmov        d0, x11
1144  5d0:        1e262200         fcmp        s16, s6
1145  5d4:        1e7d2200         fcmp        d16, d29
1146  5d8:        1e2023c8         fcmp        s30, #0.0
1147  5dc:        1e602128         fcmp        d9, #0.0
1148  5e0:        293e119b         stp        w27, w4, [x12, #-16]
1149  5e4:        294a2543         ldp        w3, w9, [x10, #80]
1150  5e8:        69480c70         ldpsw        x16, x3, [x3, #64]
1151  5ec:        a934726a         stp        x10, x28, [x19, #-192]
1152  5f0:        a97448f3         ldp        x19, x18, [x7, #-192]
1153  5f4:        298243ca         stp        w10, w16, [x30, #16]!
1154  5f8:        29e21242         ldp        w2, w4, [x18, #-240]!
1155  5fc:        69c64db8         ldpsw        x24, x19, [x13, #48]!
1156  600:        a9800311         stp        x17, x0, [x24, #0]!
1157  604:        a9f4686e         ldp        x14, x26, [x3, #-192]!
1158  608:        288a0416         stp        w22, w1, [x0], #80
1159  60c:        28fe2812         ldp        w18, w10, [x0], #-16
1160  610:        68fe62d8         .inst        0x68fe62d8 ; undefined
1161  614:        a885308c         stp        x12, x12, [x4], #80
1162  618:        a8f12664         ldp        x4, x9, [x19], #-240
1163  61c:        282468d2         stnp        w18, w26, [x6, #-224]
1164  620:        284e5035         ldnp        w21, w20, [x1, #112]
1165  624:        a8327699         stnp        x25, x29, [x20, #-224]
1166  628:        a84716e1         ldnp        x1, x5, [x23, #112]
1167  62c:        0c407284         ld1        {v4.8b}, [x20]
1168  630:        4cdfa158         ld1        {v24.16b, v25.16b}, [x10], #32
1169  634:        0ccf6cd8         ld1        {v24.1d-v26.1d}, [x6], x15
1170  638:        4cdf2483         ld1        {v3.8h-v6.8h}, [x4], #64
1171  63c:        0d40c0c2         ld1r        {v2.8b}, [x6]
1172  640:        4ddfc9cd         ld1r        {v13.4s}, [x14], #4
1173  644:        0dd8ceaf         ld1r        {v15.1d}, [x21], x24
1174  648:        4c408ea9         ld2        {v9.2d, v10.2d}, [x21]
1175  64c:        0cdf86bd         ld2        {v29.4h, v30.4h}, [x21], #16
1176  650:        4d60c1c8         ld2r        {v8.16b, v9.16b}, [x14]
1177  654:        0dffca87         ld2r        {v7.2s, v8.2s}, [x20], #8
1178  658:        4de3cc7c         ld2r        {v28.2d, v29.2d}, [x3], x3
1179  65c:        4cdd497b         ld3        {v27.4s-v29.4s}, [x11], x29
1180  660:        0c404950         ld3        {v16.2s-v18.2s}, [x10]
1181  664:        4d40e595         ld3r        {v21.8h-v23.8h}, [x12]
1182  668:        4ddfeba4         ld3r        {v4.4s-v6.4s}, [x29], #12
1183  66c:        0dd3ed38         ld3r        {v24.1d-v26.1d}, [x9], x19
1184  670:        4cdf046a         ld4        {v10.8h-v13.8h}, [x3], #64
1185  674:        0cc9039b         ld4        {v27.8b-v30.8b}, [x28], x9
1186  678:        0d60e3d5         ld4r        {v21.8b-v24.8b}, [x30]
1187  67c:        0dffe5d7         ld4r        {v23.4h-v26.4h}, [x14], #8
1188  680:        0df4e9a4         ld4r        {v4.2s-v7.2s}, [x13], x20
1189  684:        ba5fd3e3         ccmn        xzr, xzr, #0x3, le
1190  688:        3a5f03e5         ccmn        wzr, wzr, #0x5, eq  // eq = none
1191  68c:        fa411be4         ccmp        xzr, #0x1, #0x4, ne  // ne = any
1192  690:        7a42cbe2         ccmp        wzr, #0x2, #0x2, gt
1193  694:        93df03ff         ror        xzr, xzr, #0
1194  698:        c820ffff         stlxp        w0, xzr, xzr, [sp]
1195  69c:        8822fc7f         stlxp        w2, wzr, wzr, [x3]
1196  6a0:        c8247cbf         stxp        w4, xzr, xzr, [x5]
1197  6a4:        88267fff         stxp        w6, wzr, wzr, [sp]
1198  6a8:        4e010fe0         dup        v0.16b, wzr
1199  6ac:        4e081fe1         mov        v1.d[0], xzr
1200  6b0:        4e0c1fe1         mov        v1.s[1], wzr
1201  6b4:        4e0a1fe1         mov        v1.h[2], wzr
1202  6b8:        4e071fe1         mov        v1.b[3], wzr
1203  6bc:        4cc0ac3f         ld1        {v31.2d, v0.2d}, [x1], x0
1204  6c0:        1e601000         fmov        d0, #2.000000000000000000e+00
1205  6c4:        1e603000         fmov        d0, #2.125000000000000000e+00
1206  6c8:        1e621000         fmov        d0, #4.000000000000000000e+00
1207  6cc:        1e623000         fmov        d0, #4.250000000000000000e+00
1208  6d0:        1e641000         fmov        d0, #8.000000000000000000e+00
1209  6d4:        1e643000         fmov        d0, #8.500000000000000000e+00
1210  6d8:        1e661000         fmov        d0, #1.600000000000000000e+01
1211  6dc:        1e663000         fmov        d0, #1.700000000000000000e+01
1212  6e0:        1e681000         fmov        d0, #1.250000000000000000e-01
1213  6e4:        1e683000         fmov        d0, #1.328125000000000000e-01
1214  6e8:        1e6a1000         fmov        d0, #2.500000000000000000e-01
1215  6ec:        1e6a3000         fmov        d0, #2.656250000000000000e-01
1216  6f0:        1e6c1000         fmov        d0, #5.000000000000000000e-01
1217  6f4:        1e6c3000         fmov        d0, #5.312500000000000000e-01
1218  6f8:        1e6e1000         fmov        d0, #1.000000000000000000e+00
1219  6fc:        1e6e3000         fmov        d0, #1.062500000000000000e+00
1220  700:        1e701000         fmov        d0, #-2.000000000000000000e+00
1221  704:        1e703000         fmov        d0, #-2.125000000000000000e+00
1222  708:        1e721000         fmov        d0, #-4.000000000000000000e+00
1223  70c:        1e723000         fmov        d0, #-4.250000000000000000e+00
1224  710:        1e741000         fmov        d0, #-8.000000000000000000e+00
1225  714:        1e743000         fmov        d0, #-8.500000000000000000e+00
1226  718:        1e761000         fmov        d0, #-1.600000000000000000e+01
1227  71c:        1e763000         fmov        d0, #-1.700000000000000000e+01
1228  720:        1e781000         fmov        d0, #-1.250000000000000000e-01
1229  724:        1e783000         fmov        d0, #-1.328125000000000000e-01
1230  728:        1e7a1000         fmov        d0, #-2.500000000000000000e-01
1231  72c:        1e7a3000         fmov        d0, #-2.656250000000000000e-01
1232  730:        1e7c1000         fmov        d0, #-5.000000000000000000e-01
1233  734:        1e7c3000         fmov        d0, #-5.312500000000000000e-01
1234  738:        1e7e1000         fmov        d0, #-1.000000000000000000e+00
1235  73c:        1e7e3000         fmov        d0, #-1.062500000000000000e+00
1236  740:        f8358305         swp        x21, x5, [x24]
1237  744:        f82d01ed         ldadd        x13, x13, [x15]
1238  748:        f8361353         ldclr        x22, x19, [x26]
1239  74c:        f839234a         ldeor        x25, x10, [x26]
1240  750:        f82531fb         ldset        x5, x27, [x15]
1241  754:        f8335165         ldsmin        x19, x5, [x11]
1242  758:        f83a4080         ldsmax        x26, x0, [x4]
1243  75c:        f83673d7         ldumin        x22, x23, [x30]
1244  760:        f832611c         ldumax        x18, x28, [x8]
1245  764:        f8ad837d         swpa        x13, x29, [x27]
1246  768:        f8ab01a5         ldadda        x11, x5, [x13]
1247  76c:        f8a112b8         ldclra        x1, x24, [x21]
1248  770:        f8bb2311         ldeora        x27, x17, [x24]
1249  774:        f8b230be         ldseta        x18, x30, [x5]
1250  778:        f8a75336         ldsmina        x7, x22, [x25]
1251  77c:        f8a4427a         ldsmaxa        x4, x26, [x19]
1252  780:        f8a6707e         ldumina        x6, x30, [x3]
1253  784:        f8b860b7         ldumaxa        x24, x23, [x5]
1254  788:        f8f88392         swpal        x24, x18, [x28]
1255  78c:        f8f300ff         ldaddal        x19, xzr, [x7]
1256  790:        f8ed1386         ldclral        x13, x6, [x28]
1257  794:        f8e822af         ldeoral        x8, x15, [x21]
1258  798:        f8e2302d         ldsetal        x2, x13, [x1]
1259  79c:        f8f1533d         ldsminal        x17, x29, [x25]
1260  7a0:        f8f941d2         ldsmaxal        x25, x18, [x14]
1261  7a4:        f8ff7366         lduminal        xzr, x6, [x27]
1262  7a8:        f8f061e5         ldumaxal        x16, x5, [x15]
1263  7ac:        f86b8072         swpl        x11, x18, [x3]
1264  7b0:        f87a0054         ldaddl        x26, x20, [x2]
1265  7b4:        f86b1164         ldclrl        x11, x4, [x11]
1266  7b8:        f87e22f3         ldeorl        x30, x19, [x23]
1267  7bc:        f86331cf         ldsetl        x3, x15, [x14]
1268  7c0:        f87e5296         ldsminl        x30, x22, [x20]
1269  7c4:        f8674305         ldsmaxl        x7, x5, [x24]
1270  7c8:        f87771f0         lduminl        x23, x16, [x15]
1271  7cc:        f86b6013         ldumaxl        x11, x19, [x0]
1272  7d0:        b83c803c         swp        w28, w28, [x1]
1273  7d4:        b82b0195         ldadd        w11, w21, [x12]
1274  7d8:        b83d1240         ldclr        w29, w0, [x18]
1275  7dc:        b8252320         ldeor        w5, w0, [x25]
1276  7e0:        b82e3340         ldset        w14, w0, [x26]
1277  7e4:        b83c53b2         ldsmin        w28, w18, [x29]
1278  7e8:        b82f43a1         ldsmax        w15, w1, [x29]
1279  7ec:        b828739a         ldumin        w8, w26, [x28]
1280  7f0:        b831608e         ldumax        w17, w14, [x4]
1281  7f4:        b8b88039         swpa        w24, w25, [x1]
1282  7f8:        b8aa0231         ldadda        w10, w17, [x17]
1283  7fc:        b8bd12b4         ldclra        w29, w20, [x21]
1284  800:        b8bd2189         ldeora        w29, w9, [x12]
1285  804:        b8ab30a6         ldseta        w11, w6, [x5]
1286  808:        b8b552a7         ldsmina        w21, w7, [x21]
1287  80c:        b8aa4197         ldsmaxa        w10, w23, [x12]
1288  810:        b8b57145         ldumina        w21, w5, [x10]
1289  814:        b8be6254         ldumaxa        w30, w20, [x18]
1290  818:        b8ed80b7         swpal        w13, w23, [x5]
1291  81c:        b8ef00b8         ldaddal        w15, w24, [x5]
1292  820:        b8e9132a         ldclral        w9, w10, [x25]
1293  824:        b8f42231         ldeoral        w20, w17, [x17]
1294  828:        b8ec33d2         ldsetal        w12, w18, [x30]
1295  82c:        b8e35323         ldsminal        w3, w3, [x25]
1296  830:        b8fa4159         ldsmaxal        w26, w25, [x10]
1297  834:        b8e273eb         lduminal        w2, w11, [sp]
1298  838:        b8e760a2         ldumaxal        w7, w2, [x5]
1299  83c:        b8608287         swpl        w0, w7, [x20]
1300  840:        b865005f         staddl        w5, [x2]
1301  844:        b87b1379         ldclrl        w27, w25, [x27]
1302  848:        b87e2358         ldeorl        w30, w24, [x26]
1303  84c:        b86f32c2         ldsetl        w15, w2, [x22]
1304  850:        b86053e3         ldsminl        w0, w3, [sp]
1305  854:        b86f4154         ldsmaxl        w15, w20, [x10]
1306  858:        b87671d5         lduminl        w22, w21, [x14]
1307  85c:        b866605e         ldumaxl        w6, w30, [x2]
1308  */
1309 
1310   static const unsigned int insns[] =
1311   {
1312     0x8b50798f,     0xcb4381e1,     0xab05372d,     0xeb864796,
1313     0x0b961920,     0x4b195473,     0x2b0b5264,     0x6b9300f8,
1314     0x8a0bc0fe,     0xaa0f3118,     0xca170531,     0xea44dd6e,
1315     0x0a4c44f3,     0x2a8b7373,     0x4a567c7e,     0x6a9c0353,
1316     0x8a3accdd,     0xaa318f7a,     0xca2e1495,     0xeaa015e2,
1317     0x0a2274e2,     0x2a751598,     0x4a3309fe,     0x6ab172fe,
1318     0x110a5284,     0x310b1942,     0x5103d353,     0x710125bc,
1319     0x910d7bc2,     0xb108fa1b,     0xd1093536,     0xf10ae824,
1320     0x120e667c,     0x321f6cbb,     0x520f6a9e,     0x72136f56,
1321     0x927e4ce5,     0xb278b4ed,     0xd24c6527,     0xf2485803,
1322     0x14000000,     0x17ffffd7,     0x140001ee,     0x94000000,
1323     0x97ffffd4,     0x940001eb,     0x34000010,     0x34fffa30,
1324     0x34003d10,     0x35000013,     0x35fff9d3,     0x35003cb3,
1325     0xb4000005,     0xb4fff965,     0xb4003c45,     0xb5000004,
1326     0xb5fff904,     0xb5003be4,     0x1000001b,     0x10fff8bb,
1327     0x10003b9b,     0x90000010,     0x3640001c,     0x3647f83c,
1328     0x36403b1c,     0x37080001,     0x370ff7c1,     0x37083aa1,
1329     0x12a437f4,     0x528c9d67,     0x72838bb1,     0x92c1062e,
1330     0xd287da49,     0xf2a6d153,     0x93465ac9,     0x330b0013,
1331     0x530b4e6a,     0x934545e4,     0xb35370a3,     0xd3510b8c,
1332     0x13960c0f,     0x93ceddc6,     0x54000000,     0x54fff5a0,
1333     0x54003880,     0x54000001,     0x54fff541,     0x54003821,
1334     0x54000002,     0x54fff4e2,     0x540037c2,     0x54000002,
1335     0x54fff482,     0x54003762,     0x54000003,     0x54fff423,
1336     0x54003703,     0x54000003,     0x54fff3c3,     0x540036a3,
1337     0x54000004,     0x54fff364,     0x54003644,     0x54000005,
1338     0x54fff305,     0x540035e5,     0x54000006,     0x54fff2a6,
1339     0x54003586,     0x54000007,     0x54fff247,     0x54003527,
1340     0x54000008,     0x54fff1e8,     0x540034c8,     0x54000009,
1341     0x54fff189,     0x54003469,     0x5400000a,     0x54fff12a,
1342     0x5400340a,     0x5400000b,     0x54fff0cb,     0x540033ab,
1343     0x5400000c,     0x54fff06c,     0x5400334c,     0x5400000d,
1344     0x54fff00d,     0x540032ed,     0x5400000e,     0x54ffefae,
1345     0x5400328e,     0x5400000f,     0x54ffef4f,     0x5400322f,
1346     0xd40ac601,     0xd40042a2,     0xd404dac3,     0xd4224d40,
1347     0xd44219c0,     0xd503201f,     0xd69f03e0,     0xd6bf03e0,
1348     0xd5033fdf,     0xd503339f,     0xd50335bf,     0xd61f0280,
1349     0xd63f0040,     0xc8127c17,     0xc81efec5,     0xc85f7d05,
1350     0xc85ffe14,     0xc89ffd66,     0xc8dfff66,     0x880a7cb1,
1351     0x8816fd89,     0x885f7d1b,     0x885ffc57,     0x889fffba,
1352     0x88dffd4d,     0x48197f7c,     0x481dfd96,     0x485f7f96,
1353     0x485fffc3,     0x489ffdf8,     0x48dfff5b,     0x080b7e6a,
1354     0x0817fedb,     0x085f7e18,     0x085ffc38,     0x089fffa5,
1355     0x08dffe18,     0xc87f6239,     0xc87fb276,     0xc820573a,
1356     0xc821aca6,     0x887f388d,     0x887f88d1,     0x882f2643,
1357     0x88329131,     0xf81cf2b7,     0xb803f055,     0x39002f9b,
1358     0x781f31fd,     0xf85d33ce,     0xb843539d,     0x39401f54,
1359     0x785ce059,     0x389f1143,     0x788131ee,     0x78dfb17d,
1360     0xb89b90af,     0xfc403193,     0xbc42a36c,     0xfc07d396,
1361     0xbc1ec1f8,     0xf81e8f88,     0xb8025de6,     0x38007c27,
1362     0x7801ee20,     0xf8454fb9,     0xb85cce9a,     0x385e7fba,
1363     0x7841af24,     0x389ebd1c,     0x789fadd1,     0x78c0aefc,
1364     0xb89c0f7e,     0xfc50efd4,     0xbc414f71,     0xfc011c67,
1365     0xbc1f0d6d,     0xf81c3526,     0xb81e34b0,     0x3800f7bd,
1366     0x78012684,     0xf842e653,     0xb8417456,     0x385e2467,
1367     0x785e358b,     0x389e34c8,     0x788046f8,     0x78c00611,
1368     0xb89f8680,     0xfc582454,     0xbc5987d3,     0xfc076624,
1369     0xbc190675,     0xf833785a,     0xb82fd809,     0x3821799a,
1370     0x782a7975,     0xf870eaf0,     0xb871d96a,     0x386b7aed,
1371     0x7875689b,     0x38afd91a,     0x78a2c955,     0x78ee6bc8,
1372     0xb8b4f9dd,     0xfc76eb7e,     0xbc76692d,     0xfc31db28,
1373     0xbc255b01,     0xf91c52aa,     0xb91c3fb2,     0x391f8877,
1374     0x791ac97c,     0xf95c1758,     0xb95b3c55,     0x395ce0a4,
1375     0x795851ce,     0x399e9f64,     0x79993764,     0x79d9af8a,
1376     0xb99eea2a,     0xfd5a2f8d,     0xbd5dac78,     0xfd1e0182,
1377     0xbd195c31,     0x58000010,     0x1800000d,     0xf8981240,
1378     0xd8ffdf00,     0xf8a27a80,     0xf99af920,     0x1a0202e8,
1379     0x3a130078,     0x5a1d0316,     0x7a03036c,     0x9a0102eb,
1380     0xba1700bd,     0xda0c0329,     0xfa16000c,     0x0b23459a,
1381     0x2b328a14,     0xcb274bde,     0x6b222eab,     0x8b214b42,
1382     0xab34a7b2,     0xcb24520e,     0xeb378e20,     0x3a565283,
1383     0x7a420321,     0xba58c247,     0xfa4d5106,     0x3a426924,
1384     0x7a5b0847,     0xba413a02,     0xfa5fba23,     0x1a979377,
1385     0x1a86640a,     0x5a89300b,     0x5a923771,     0x9a8b720c,
1386     0x9a868786,     0xda9a736d,     0xda9256dd,     0x5ac0026c,
1387     0x5ac00657,     0x5ac00b89,     0x5ac01262,     0x5ac017b9,
1388     0xdac002e4,     0xdac0065d,     0xdac00907,     0xdac00e2d,
1389     0xdac01011,     0xdac01752,     0x1ad0098b,     0x1ac70d24,
1390     0x1ad020ec,     0x1ad72613,     0x1ac62887,     0x1ad72e95,
1391     0x9adc0990,     0x9acd0d84,     0x9ac721a9,     0x9acf277c,
1392     0x9ace2bd4,     0x9ade2e4e,     0x9bc77d63,     0x9b587e97,
1393     0x1b1524a2,     0x1b04a318,     0x9b0f4d8b,     0x9b0ce73d,
1394     0x9b2c5971,     0x9b34c87c,     0x9bbc6887,     0x9bb19556,
1395     0x1e310871,     0x1e261a2b,     0x1e2928fd,     0x1e333987,
1396     0x1e230ae0,     0x1e75087a,     0x1e651a60,     0x1e692b40,
1397     0x1e753ab9,     0x1e7309b0,     0x1f00425d,     0x1f1d95b7,
1398     0x1f2a38e9,     0x1f2f5f99,     0x1f5545a6,     0x1f429ea3,
1399     0x1f65472a,     0x1f7449ce,     0x1e20404f,     0x1e20c0f2,
1400     0x1e2140c3,     0x1e21c02c,     0x1e22c009,     0x1e6040a4,
1401     0x1e60c1e3,     0x1e614331,     0x1e61c30c,     0x1e6240b5,
1402     0x1e3802a4,     0x9e38007b,     0x1e78011d,     0x9e7802a9,
1403     0x1e2203b4,     0x9e220107,     0x1e6202ac,     0x9e6202b0,
1404     0x1e2600b2,     0x9e660119,     0x1e270352,     0x9e670160,
1405     0x1e262200,     0x1e7d2200,     0x1e2023c8,     0x1e602128,
1406     0x293e119b,     0x294a2543,     0x69480c70,     0xa934726a,
1407     0xa97448f3,     0x298243ca,     0x29e21242,     0x69c64db8,
1408     0xa9800311,     0xa9f4686e,     0x288a0416,     0x28fe2812,
1409     0x68fe62d8,     0xa885308c,     0xa8f12664,     0x282468d2,
1410     0x284e5035,     0xa8327699,     0xa84716e1,     0x0c407284,
1411     0x4cdfa158,     0x0ccf6cd8,     0x4cdf2483,     0x0d40c0c2,
1412     0x4ddfc9cd,     0x0dd8ceaf,     0x4c408ea9,     0x0cdf86bd,
1413     0x4d60c1c8,     0x0dffca87,     0x4de3cc7c,     0x4cdd497b,
1414     0x0c404950,     0x4d40e595,     0x4ddfeba4,     0x0dd3ed38,
1415     0x4cdf046a,     0x0cc9039b,     0x0d60e3d5,     0x0dffe5d7,
1416     0x0df4e9a4,     0xba5fd3e3,     0x3a5f03e5,     0xfa411be4,
1417     0x7a42cbe2,     0x93df03ff,     0xc820ffff,     0x8822fc7f,
1418     0xc8247cbf,     0x88267fff,     0x4e010fe0,     0x4e081fe1,
1419     0x4e0c1fe1,     0x4e0a1fe1,     0x4e071fe1,     0x4cc0ac3f,
1420     0x1e601000,     0x1e603000,     0x1e621000,     0x1e623000,
1421     0x1e641000,     0x1e643000,     0x1e661000,     0x1e663000,
1422     0x1e681000,     0x1e683000,     0x1e6a1000,     0x1e6a3000,
1423     0x1e6c1000,     0x1e6c3000,     0x1e6e1000,     0x1e6e3000,
1424     0x1e701000,     0x1e703000,     0x1e721000,     0x1e723000,
1425     0x1e741000,     0x1e743000,     0x1e761000,     0x1e763000,
1426     0x1e781000,     0x1e783000,     0x1e7a1000,     0x1e7a3000,
1427     0x1e7c1000,     0x1e7c3000,     0x1e7e1000,     0x1e7e3000,
1428     0xf8358305,     0xf82d01ed,     0xf8361353,     0xf839234a,
1429     0xf82531fb,     0xf8335165,     0xf83a4080,     0xf83673d7,
1430     0xf832611c,     0xf8ad837d,     0xf8ab01a5,     0xf8a112b8,
1431     0xf8bb2311,     0xf8b230be,     0xf8a75336,     0xf8a4427a,
1432     0xf8a6707e,     0xf8b860b7,     0xf8f88392,     0xf8f300ff,
1433     0xf8ed1386,     0xf8e822af,     0xf8e2302d,     0xf8f1533d,
1434     0xf8f941d2,     0xf8ff7366,     0xf8f061e5,     0xf86b8072,
1435     0xf87a0054,     0xf86b1164,     0xf87e22f3,     0xf86331cf,
1436     0xf87e5296,     0xf8674305,     0xf87771f0,     0xf86b6013,
1437     0xb83c803c,     0xb82b0195,     0xb83d1240,     0xb8252320,
1438     0xb82e3340,     0xb83c53b2,     0xb82f43a1,     0xb828739a,
1439     0xb831608e,     0xb8b88039,     0xb8aa0231,     0xb8bd12b4,
1440     0xb8bd2189,     0xb8ab30a6,     0xb8b552a7,     0xb8aa4197,
1441     0xb8b57145,     0xb8be6254,     0xb8ed80b7,     0xb8ef00b8,
1442     0xb8e9132a,     0xb8f42231,     0xb8ec33d2,     0xb8e35323,
1443     0xb8fa4159,     0xb8e273eb,     0xb8e760a2,     0xb8608287,
1444     0xb865005f,     0xb87b1379,     0xb87e2358,     0xb86f32c2,
1445     0xb86053e3,     0xb86f4154,     0xb87671d5,     0xb866605e,
1446 
1447   };
1448 // END  Generated code -- do not edit
1449 
1450   asm_check((unsigned int *)entry, insns, sizeof insns / sizeof insns[0]);
1451 
1452   {
1453     address PC = __ pc();
1454     __ ld1(v0, __ T16B, Address(r16));      // No offset
1455     __ ld1(v0, __ T8H, __ post(r16, 16));   // Post-index
1456     __ ld2(v0, v1, __ T8H, __ post(r24, 16 * 2));   // Post-index
1457     __ ld1(v0, __ T16B, __ post(r16, r17)); // Register post-index
1458     static const unsigned int vector_insns[] = {
1459        0x4c407200, // ld1   {v0.16b}, [x16]
1460        0x4cdf7600, // ld1   {v0.8h}, [x16], #16
1461        0x4cdf8700, // ld2   {v0.8h, v1.8h}, [x24], #32
1462        0x4cd17200, // ld1   {v0.16b}, [x16], x17
1463       };
1464     asm_check((unsigned int *)PC, vector_insns,
1465               sizeof vector_insns / sizeof vector_insns[0]);
1466   }
1467 
1468 #endif // ASSERT
1469 }
1470 
1471 #undef __
1472 
1473 void Assembler::emit_data64(jlong data,
1474                             relocInfo::relocType rtype,
1475                             int format) {
1476   if (rtype == relocInfo::none) {
1477     emit_int64(data);
1478   } else {
1479     emit_data64(data, Relocation::spec_simple(rtype), format);
1480   }
1481 }
1482 
1483 void Assembler::emit_data64(jlong data,
1484                             RelocationHolder const& rspec,
1485                             int format) {
1486 
1487   assert(inst_mark() != NULL, "must be inside InstructionMark");
1488   // Do not use AbstractAssembler::relocate, which is not intended for
1489   // embedded words.  Instead, relocate to the enclosing instruction.
1490   code_section()->relocate(inst_mark(), rspec, format);
1491   emit_int64(data);
1492 }
1493 
1494 extern "C" {
1495   void das(uint64_t start, int len) {
1496     ResourceMark rm;
1497     len <<= 2;
1498     if (len < 0)
1499       Disassembler::decode((address)start + len, (address)start);
1500     else
1501       Disassembler::decode((address)start, (address)start + len);
1502   }
1503 
1504   JNIEXPORT void das1(unsigned long insn) {
1505     das(insn, 1);
1506   }
1507 }
1508 
1509 #define gas_assert(ARG1) assert(ARG1, #ARG1)
1510 
1511 #define __ as->
1512 
1513 void Address::lea(MacroAssembler *as, Register r) const {
1514   Relocation* reloc = _rspec.reloc();
1515   relocInfo::relocType rtype = (relocInfo::relocType) reloc->type();
1516 
1517   switch(_mode) {
1518   case base_plus_offset: {
1519     if (_offset == 0 && _base == r) // it's a nop
1520       break;
1521     if (_offset > 0)
1522       __ add(r, _base, _offset);
1523     else
1524       __ sub(r, _base, -_offset);
1525       break;
1526   }
1527   case base_plus_offset_reg: {
1528     __ add(r, _base, _index, _ext.op(), MAX(_ext.shift(), 0));
1529     break;
1530   }
1531   case literal: {
1532     if (rtype == relocInfo::none)
1533       __ mov(r, target());
1534     else
1535       __ movptr(r, (uint64_t)target());
1536     break;
1537   }
1538   default:
1539     ShouldNotReachHere();
1540   }
1541 }
1542 
1543 void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
1544   ShouldNotReachHere();
1545 }
1546 
1547 #undef __
1548 
1549 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
1550 
1551   void Assembler::adr(Register Rd, address adr) {
1552     long offset = adr - pc();
1553     int offset_lo = offset & 3;
1554     offset >>= 2;
1555     starti;
1556     f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1557     rf(Rd, 0);
1558   }
1559 
1560   void Assembler::_adrp(Register Rd, address adr) {
1561     uint64_t pc_page = (uint64_t)pc() >> 12;
1562     uint64_t adr_page = (uint64_t)adr >> 12;
1563     long offset = adr_page - pc_page;
1564     int offset_lo = offset & 3;
1565     offset >>= 2;
1566     starti;
1567     f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1568     rf(Rd, 0);
1569   }
1570 
1571 #undef starti
1572 
1573 Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
1574   _is_lval = false;
1575   _target = target;
1576   switch (rtype) {
1577   case relocInfo::oop_type:
1578   case relocInfo::metadata_type:
1579     // Oops are a special case. Normally they would be their own section
1580     // but in cases like icBuffer they are literals in the code stream that
1581     // we don't have a section for. We use none so that we get a literal address
1582     // which is always patchable.
1583     break;
1584   case relocInfo::external_word_type:
1585     _rspec = external_word_Relocation::spec(target);
1586     break;
1587   case relocInfo::internal_word_type:
1588     _rspec = internal_word_Relocation::spec(target);
1589     break;
1590   case relocInfo::opt_virtual_call_type:
1591     _rspec = opt_virtual_call_Relocation::spec();
1592     break;
1593   case relocInfo::static_call_type:
1594     _rspec = static_call_Relocation::spec();
1595     break;
1596   case relocInfo::runtime_call_type:
1597     _rspec = runtime_call_Relocation::spec();
1598     break;
1599   case relocInfo::poll_type:
1600   case relocInfo::poll_return_type:
1601     _rspec = Relocation::spec_simple(rtype);
1602     break;
1603   case relocInfo::none:
1604     _rspec = RelocationHolder::none;
1605     break;
1606   default:
1607     ShouldNotReachHere();
1608     break;
1609   }
1610 }
1611 
1612 void Assembler::b(const Address &dest) {
1613   code_section()->relocate(pc(), dest.rspec());
1614   b(dest.target());
1615 }
1616 
1617 void Assembler::bl(const Address &dest) {
1618   code_section()->relocate(pc(), dest.rspec());
1619   bl(dest.target());
1620 }
1621 
1622 void Assembler::adr(Register r, const Address &dest) {
1623   code_section()->relocate(pc(), dest.rspec());
1624   adr(r, dest.target());
1625 }
1626 
1627 void Assembler::br(Condition cc, Label &L) {
1628   if (L.is_bound()) {
1629     br(cc, target(L));
1630   } else {
1631     L.add_patch_at(code(), locator());
1632     br(cc, pc());
1633   }
1634 }
1635 
1636 void Assembler::wrap_label(Label &L,
1637                                  Assembler::uncond_branch_insn insn) {
1638   if (L.is_bound()) {
1639     (this->*insn)(target(L));
1640   } else {
1641     L.add_patch_at(code(), locator());
1642     (this->*insn)(pc());
1643   }
1644 }
1645 
1646 void Assembler::wrap_label(Register r, Label &L,
1647                                  compare_and_branch_insn insn) {
1648   if (L.is_bound()) {
1649     (this->*insn)(r, target(L));
1650   } else {
1651     L.add_patch_at(code(), locator());
1652     (this->*insn)(r, pc());
1653   }
1654 }
1655 
1656 void Assembler::wrap_label(Register r, int bitpos, Label &L,
1657                                  test_and_branch_insn insn) {
1658   if (L.is_bound()) {
1659     (this->*insn)(r, bitpos, target(L));
1660   } else {
1661     L.add_patch_at(code(), locator());
1662     (this->*insn)(r, bitpos, pc());
1663   }
1664 }
1665 
1666 void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
1667   if (L.is_bound()) {
1668     (this->*insn)(target(L), op);
1669   } else {
1670     L.add_patch_at(code(), locator());
1671     (this->*insn)(pc(), op);
1672   }
1673 }
1674 
1675 // An "all-purpose" add/subtract immediate, per ARM documentation:
1676 // A "programmer-friendly" assembler may accept a negative immediate
1677 // between -(2^24 -1) and -1 inclusive, causing it to convert a
1678 // requested ADD operation to a SUB, or vice versa, and then encode
1679 // the absolute value of the immediate as for uimm24.
1680 void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
1681                                   int negated_op) {
1682   bool sets_flags = op & 1;   // this op sets flags
1683   union {
1684     unsigned u;
1685     int imm;
1686   };
1687   u = uimm;
1688   bool shift = false;
1689   bool neg = imm < 0;
1690   if (neg) {
1691     imm = -imm;
1692     op = negated_op;
1693   }
1694   assert(Rd != sp || imm % 16 == 0, "misaligned stack");
1695   if (imm >= (1 << 11)
1696       && ((imm >> 12) << 12 == imm)) {
1697     imm >>= 12;
1698     shift = true;
1699   }
1700   f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
1701 
1702   // add/subtract immediate ops with the S bit set treat r31 as zr;
1703   // with S unset they use sp.
1704   if (sets_flags)
1705     zrf(Rd, 0);
1706   else
1707     srf(Rd, 0);
1708 
1709   srf(Rn, 5);
1710 }
1711 
1712 bool Assembler::operand_valid_for_add_sub_immediate(long imm) {
1713   bool shift = false;
1714   unsigned long uimm = uabs(imm);
1715   if (uimm < (1 << 12))
1716     return true;
1717   if (uimm < (1 << 24)
1718       && ((uimm >> 12) << 12 == uimm)) {
1719     return true;
1720   }
1721   return false;
1722 }
1723 
1724 bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) {
1725   return encode_logical_immediate(is32, imm) != 0xffffffff;
1726 }
1727 
1728 static uint64_t doubleTo64Bits(jdouble d) {
1729   union {
1730     jdouble double_value;
1731     uint64_t double_bits;
1732   };
1733 
1734   double_value = d;
1735   return double_bits;
1736 }
1737 
1738 bool Assembler::operand_valid_for_float_immediate(double imm) {
1739   // If imm is all zero bits we can use ZR as the source of a
1740   // floating-point value.
1741   if (doubleTo64Bits(imm) == 0)
1742     return true;
1743 
1744   // Otherwise try to encode imm then convert the encoded value back
1745   // and make sure it's the exact same bit pattern.
1746   unsigned result = encoding_for_fp_immediate(imm);
1747   return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true);
1748 }
1749 
1750 int AbstractAssembler::code_fill_byte() {
1751   return 0;
1752 }
1753 
1754 // n.b. this is implemented in subclass MacroAssembler
1755 void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); }
1756 
1757 
1758 // these are the functions provided by the simulator which are used to
1759 // encode and decode logical immediates and floating point immediates
1760 //
1761 //   u_int64_t logical_immediate_for_encoding(u_int32_t encoding);
1762 //
1763 //   u_int32_t encoding_for_logical_immediate(u_int64_t immediate);
1764 //
1765 //   u_int64_t fp_immediate_for_encoding(u_int32_t imm8, int is_dp);
1766 //
1767 //   u_int32_t encoding_for_fp_immediate(float immediate);
1768 //
1769 // we currently import these from the simulator librray but the
1770 // definitions will need to be moved to here when we switch to real
1771 // hardware.
1772 
1773 // and now the routines called by the assembler which encapsulate the
1774 // above encode and decode functions
1775 
1776 uint32_t
1777 asm_util::encode_logical_immediate(bool is32, uint64_t imm)
1778 {
1779   if (is32) {
1780     /* Allow all zeros or all ones in top 32-bits, so that
1781        constant expressions like ~1 are permitted. */
1782     if (imm >> 32 != 0 && imm >> 32 != 0xffffffff)
1783       return 0xffffffff;
1784     /* Replicate the 32 lower bits to the 32 upper bits.  */
1785     imm &= 0xffffffff;
1786     imm |= imm << 32;
1787   }
1788 
1789   return encoding_for_logical_immediate(imm);
1790 }
1791 
1792 unsigned Assembler::pack(double value) {
1793   float val = (float)value;
1794   unsigned result = encoding_for_fp_immediate(val);
1795   guarantee(unpack(result) == value,
1796             "Invalid floating-point immediate operand");
1797   return result;
1798 }
1799 
1800 // Packed operands for  Floating-point Move (immediate)
1801 
1802 static float unpack(unsigned value) {
1803   union {
1804     unsigned ival;
1805     float val;
1806   };
1807   ival = fp_immediate_for_encoding(value, 0);
1808   return val;
1809 }