1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_ASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/register.hpp"
  30 
  31 // definitions of various symbolic names for machine registers
  32 
  33 // First intercalls between C and Java which use 8 general registers
  34 // and 8 floating registers
  35 
  36 // we also have to copy between x86 and ARM registers but that's a
  37 // secondary complication -- not all code employing C call convention
  38 // executes as x86 code though -- we generate some of it
  39 
  40 class Argument {
  41  public:
  42   enum {
  43     n_int_register_parameters_c   = 8,  // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
  44     n_float_register_parameters_c = 8,  // v0, v1, ... v7 (c_farg0, c_farg1, ... )
  45 
  46     n_int_register_parameters_j   = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
  47     n_float_register_parameters_j = 8  // v0, v1, ... v7 (j_farg0, j_farg1, ...
  48   };
  49 };
  50 
  51 REGISTER_DECLARATION(Register, c_rarg0, r0);
  52 REGISTER_DECLARATION(Register, c_rarg1, r1);
  53 REGISTER_DECLARATION(Register, c_rarg2, r2);
  54 REGISTER_DECLARATION(Register, c_rarg3, r3);
  55 REGISTER_DECLARATION(Register, c_rarg4, r4);
  56 REGISTER_DECLARATION(Register, c_rarg5, r5);
  57 REGISTER_DECLARATION(Register, c_rarg6, r6);
  58 REGISTER_DECLARATION(Register, c_rarg7, r7);
  59 
  60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
  61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
  62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
  63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
  64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
  65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
  66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
  67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
  68 
  69 // Symbolically name the register arguments used by the Java calling convention.
  70 // We have control over the convention for java so we can do what we please.
  71 // What pleases us is to offset the java calling convention so that when
  72 // we call a suitable jni method the arguments are lined up and we don't
  73 // have to do much shuffling. A suitable jni method is non-static and a
  74 // small number of arguments
  75 //
  76 //  |--------------------------------------------------------------------|
  77 //  | c_rarg0  c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7  |
  78 //  |--------------------------------------------------------------------|
  79 //  | r0       r1       r2      r3      r4      r5      r6      r7       |
  80 //  |--------------------------------------------------------------------|
  81 //  | j_rarg7  j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6  |
  82 //  |--------------------------------------------------------------------|
  83 
  84 
  85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
  86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
  87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
  88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
  89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
  90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
  91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
  92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
  93 
  94 // Java floating args are passed as per C
  95 
  96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
  97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
  98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
  99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
 100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
 101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
 102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
 103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
 104 
 105 // registers used to hold VM data either temporarily within a method
 106 // or across method calls
 107 
 108 // volatile (caller-save) registers
 109 
 110 // r8 is used for indirect result location return
 111 // we use it and r9 as scratch registers
 112 REGISTER_DECLARATION(Register, rscratch1, r8);
 113 REGISTER_DECLARATION(Register, rscratch2, r9);
 114 
 115 // current method -- must be in a call-clobbered register
 116 REGISTER_DECLARATION(Register, rmethod,   r12);
 117 
 118 // non-volatile (callee-save) registers are r16-29
 119 // of which the following are dedicated global state
 120 
 121 // link register
 122 REGISTER_DECLARATION(Register, lr,        r30);
 123 // frame pointer
 124 REGISTER_DECLARATION(Register, rfp,       r29);
 125 // current thread
 126 REGISTER_DECLARATION(Register, rthread,   r28);
 127 // base of heap
 128 REGISTER_DECLARATION(Register, rheapbase, r27);
 129 // constant pool cache
 130 REGISTER_DECLARATION(Register, rcpool,    r26);
 131 // monitors allocated on stack
 132 REGISTER_DECLARATION(Register, rmonitors, r25);
 133 // locals on stack
 134 REGISTER_DECLARATION(Register, rlocals,   r24);
 135 // bytecode pointer
 136 REGISTER_DECLARATION(Register, rbcp,      r22);
 137 // Dispatch table base
 138 REGISTER_DECLARATION(Register, rdispatch, r21);
 139 // Java stack pointer
 140 REGISTER_DECLARATION(Register, esp,      r20);
 141 
 142 #define assert_cond(ARG1) assert(ARG1, #ARG1)
 143 
 144 namespace asm_util {
 145   uint32_t encode_logical_immediate(bool is32, uint64_t imm);
 146 };
 147 
 148 using namespace asm_util;
 149 
 150 
 151 class Assembler;
 152 
 153 class Instruction_aarch64 {
 154   unsigned insn;
 155 #ifdef ASSERT
 156   unsigned bits;
 157 #endif
 158   Assembler *assem;
 159 
 160 public:
 161 
 162   Instruction_aarch64(class Assembler *as) {
 163 #ifdef ASSERT
 164     bits = 0;
 165 #endif
 166     insn = 0;
 167     assem = as;
 168   }
 169 
 170   inline ~Instruction_aarch64();
 171 
 172   unsigned &get_insn() { return insn; }
 173 #ifdef ASSERT
 174   unsigned &get_bits() { return bits; }
 175 #endif
 176 
 177   static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
 178     union {
 179       unsigned u;
 180       int n;
 181     };
 182 
 183     u = val << (31 - hi);
 184     n = n >> (31 - hi + lo);
 185     return n;
 186   }
 187 
 188   static inline uint32_t extract(uint32_t val, int msb, int lsb) {
 189     int nbits = msb - lsb + 1;
 190     assert_cond(msb >= lsb);
 191     uint32_t mask = (1U << nbits) - 1;
 192     uint32_t result = val >> lsb;
 193     result &= mask;
 194     return result;
 195   }
 196 
 197   static inline int32_t sextract(uint32_t val, int msb, int lsb) {
 198     uint32_t uval = extract(val, msb, lsb);
 199     return extend(uval, msb - lsb);
 200   }
 201 
 202   static void patch(address a, int msb, int lsb, unsigned long val) {
 203     int nbits = msb - lsb + 1;
 204     guarantee(val < (1U << nbits), "Field too big for insn");
 205     assert_cond(msb >= lsb);
 206     unsigned mask = (1U << nbits) - 1;
 207     val <<= lsb;
 208     mask <<= lsb;
 209     unsigned target = *(unsigned *)a;
 210     target &= ~mask;
 211     target |= val;
 212     *(unsigned *)a = target;
 213   }
 214 
 215   static void spatch(address a, int msb, int lsb, long val) {
 216     int nbits = msb - lsb + 1;
 217     long chk = val >> (nbits - 1);
 218     guarantee (chk == -1 || chk == 0, "Field too big for insn");
 219     unsigned uval = val;
 220     unsigned mask = (1U << nbits) - 1;
 221     uval &= mask;
 222     uval <<= lsb;
 223     mask <<= lsb;
 224     unsigned target = *(unsigned *)a;
 225     target &= ~mask;
 226     target |= uval;
 227     *(unsigned *)a = target;
 228   }
 229 
 230   void f(unsigned val, int msb, int lsb) {
 231     int nbits = msb - lsb + 1;
 232     guarantee(val < (1U << nbits), "Field too big for insn");
 233     assert_cond(msb >= lsb);
 234     unsigned mask = (1U << nbits) - 1;
 235     val <<= lsb;
 236     mask <<= lsb;
 237     insn |= val;
 238     assert_cond((bits & mask) == 0);
 239 #ifdef ASSERT
 240     bits |= mask;
 241 #endif
 242   }
 243 
 244   void f(unsigned val, int bit) {
 245     f(val, bit, bit);
 246   }
 247 
 248   void sf(long val, int msb, int lsb) {
 249     int nbits = msb - lsb + 1;
 250     long chk = val >> (nbits - 1);
 251     guarantee (chk == -1 || chk == 0, "Field too big for insn");
 252     unsigned uval = val;
 253     unsigned mask = (1U << nbits) - 1;
 254     uval &= mask;
 255     f(uval, lsb + nbits - 1, lsb);
 256   }
 257 
 258   void rf(Register r, int lsb) {
 259     f(r->encoding_nocheck(), lsb + 4, lsb);
 260   }
 261 
 262   // reg|ZR
 263   void zrf(Register r, int lsb) {
 264     f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
 265   }
 266 
 267   // reg|SP
 268   void srf(Register r, int lsb) {
 269     f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
 270   }
 271 
 272   void rf(FloatRegister r, int lsb) {
 273     f(r->encoding_nocheck(), lsb + 4, lsb);
 274   }
 275 
 276   unsigned get(int msb = 31, int lsb = 0) {
 277     int nbits = msb - lsb + 1;
 278     unsigned mask = ((1U << nbits) - 1) << lsb;
 279     assert_cond((bits & mask) == mask);
 280     return (insn & mask) >> lsb;
 281   }
 282 
 283   void fixed(unsigned value, unsigned mask) {
 284     assert_cond ((mask & bits) == 0);
 285 #ifdef ASSERT
 286     bits |= mask;
 287 #endif
 288     insn |= value;
 289   }
 290 };
 291 
 292 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
 293 
 294 class PrePost {
 295   int _offset;
 296   Register _r;
 297 public:
 298   PrePost(Register reg, int o) : _offset(o), _r(reg) { }
 299   int offset() { return _offset; }
 300   Register reg() { return _r; }
 301 };
 302 
 303 class Pre : public PrePost {
 304 public:
 305   Pre(Register reg, int o) : PrePost(reg, o) { }
 306 };
 307 class Post : public PrePost {
 308   Register _idx;
 309   bool _is_postreg;
 310 public:
 311   Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; _is_postreg = false; }
 312   Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; _is_postreg = true; }
 313   Register idx_reg() { return _idx; }
 314   bool is_postreg() {return _is_postreg; }
 315 };
 316 
 317 namespace ext
 318 {
 319   enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
 320 };
 321 
 322 // Addressing modes
 323 class Address {
 324  public:
 325 
 326   enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
 327               base_plus_offset_reg, literal };
 328 
 329   // Shift and extend for base reg + reg offset addressing
 330   class extend {
 331     int _option, _shift;
 332     ext::operation _op;
 333   public:
 334     extend() { }
 335     extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
 336     int option() const{ return _option; }
 337     int shift() const { return _shift; }
 338     ext::operation op() const { return _op; }
 339   };
 340   class uxtw : public extend {
 341   public:
 342     uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
 343   };
 344   class lsl : public extend {
 345   public:
 346     lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
 347   };
 348   class sxtw : public extend {
 349   public:
 350     sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
 351   };
 352   class sxtx : public extend {
 353   public:
 354     sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
 355   };
 356 
 357  private:
 358   Register _base;
 359   Register _index;
 360   long _offset;
 361   enum mode _mode;
 362   extend _ext;
 363 
 364   RelocationHolder _rspec;
 365 
 366   // Typically we use AddressLiterals we want to use their rval
 367   // However in some situations we want the lval (effect address) of
 368   // the item.  We provide a special factory for making those lvals.
 369   bool _is_lval;
 370 
 371   // If the target is far we'll need to load the ea of this to a
 372   // register to reach it. Otherwise if near we can do PC-relative
 373   // addressing.
 374   address          _target;
 375 
 376  public:
 377   Address()
 378     : _mode(no_mode) { }
 379   Address(Register r)
 380     : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
 381   Address(Register r, int o)
 382     : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
 383   Address(Register r, long o)
 384     : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
 385   Address(Register r, unsigned long o)
 386     : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
 387 #ifdef ASSERT
 388   Address(Register r, ByteSize disp)
 389     : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }
 390 #endif
 391   Address(Register r, Register r1, extend ext = lsl())
 392     : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),
 393       _ext(ext), _target(0) { }
 394   Address(Pre p)
 395     : _base(p.reg()), _offset(p.offset()), _mode(pre) { }
 396   Address(Post p)
 397     : _base(p.reg()),  _index(p.idx_reg()), _offset(p.offset()),
 398       _mode(p.is_postreg() ? post_reg : post), _target(0) { }
 399   Address(address target, RelocationHolder const& rspec)
 400     : _mode(literal),
 401       _rspec(rspec),
 402       _is_lval(false),
 403       _target(target)  { }
 404   Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
 405   Address(Register base, RegisterOrConstant index, extend ext = lsl())
 406     : _base (base),
 407       _offset(0), _ext(ext), _target(0) {
 408     if (index.is_register()) {
 409       _mode = base_plus_offset_reg;
 410       _index = index.as_register();
 411     } else {
 412       guarantee(ext.option() == ext::uxtx, "should be");
 413       assert(index.is_constant(), "should be");
 414       _mode = base_plus_offset;
 415       _offset = index.as_constant() << ext.shift();
 416     }
 417   }
 418 
 419   Register base() const {
 420     guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
 421                | _mode == post | _mode == post_reg),
 422               "wrong mode");
 423     return _base;
 424   }
 425   long offset() const {
 426     return _offset;
 427   }
 428   Register index() const {
 429     return _index;
 430   }
 431   mode getMode() const {
 432     return _mode;
 433   }
 434   bool uses(Register reg) const { return _base == reg || _index == reg; }
 435   address target() const { return _target; }
 436   const RelocationHolder& rspec() const { return _rspec; }
 437 
 438   void encode(Instruction_aarch64 *i) const {
 439     i->f(0b111, 29, 27);
 440     i->srf(_base, 5);
 441 
 442     switch(_mode) {
 443     case base_plus_offset:
 444       {
 445         unsigned size = i->get(31, 30);
 446         if (i->get(26, 26) && i->get(23, 23)) {
 447           // SIMD Q Type - Size = 128 bits
 448           assert(size == 0, "bad size");
 449           size = 0b100;
 450         }
 451         unsigned mask = (1 << size) - 1;
 452         if (_offset < 0 || _offset & mask)
 453           {
 454             i->f(0b00, 25, 24);
 455             i->f(0, 21), i->f(0b00, 11, 10);
 456             i->sf(_offset, 20, 12);
 457           } else {
 458             i->f(0b01, 25, 24);
 459             i->f(_offset >> size, 21, 10);
 460           }
 461       }
 462       break;
 463 
 464     case base_plus_offset_reg:
 465       {
 466         i->f(0b00, 25, 24);
 467         i->f(1, 21);
 468         i->rf(_index, 16);
 469         i->f(_ext.option(), 15, 13);
 470         unsigned size = i->get(31, 30);
 471         if (i->get(26, 26) && i->get(23, 23)) {
 472           // SIMD Q Type - Size = 128 bits
 473           assert(size == 0, "bad size");
 474           size = 0b100;
 475         }
 476         if (size == 0) // It's a byte
 477           i->f(_ext.shift() >= 0, 12);
 478         else {
 479           if (_ext.shift() > 0)
 480             assert(_ext.shift() == (int)size, "bad shift");
 481           i->f(_ext.shift() > 0, 12);
 482         }
 483         i->f(0b10, 11, 10);
 484       }
 485       break;
 486 
 487     case pre:
 488       i->f(0b00, 25, 24);
 489       i->f(0, 21), i->f(0b11, 11, 10);
 490       i->sf(_offset, 20, 12);
 491       break;
 492 
 493     case post:
 494       i->f(0b00, 25, 24);
 495       i->f(0, 21), i->f(0b01, 11, 10);
 496       i->sf(_offset, 20, 12);
 497       break;
 498 
 499     default:
 500       ShouldNotReachHere();
 501     }
 502   }
 503 
 504   void encode_pair(Instruction_aarch64 *i) const {
 505     switch(_mode) {
 506     case base_plus_offset:
 507       i->f(0b010, 25, 23);
 508       break;
 509     case pre:
 510       i->f(0b011, 25, 23);
 511       break;
 512     case post:
 513       i->f(0b001, 25, 23);
 514       break;
 515     default:
 516       ShouldNotReachHere();
 517     }
 518 
 519     unsigned size; // Operand shift in 32-bit words
 520 
 521     if (i->get(26, 26)) { // float
 522       switch(i->get(31, 30)) {
 523       case 0b10:
 524         size = 2; break;
 525       case 0b01:
 526         size = 1; break;
 527       case 0b00:
 528         size = 0; break;
 529       default:
 530         ShouldNotReachHere();
 531         size = 0;  // unreachable
 532       }
 533     } else {
 534       size = i->get(31, 31);
 535     }
 536 
 537     size = 4 << size;
 538     guarantee(_offset % size == 0, "bad offset");
 539     i->sf(_offset / size, 21, 15);
 540     i->srf(_base, 5);
 541   }
 542 
 543   void encode_nontemporal_pair(Instruction_aarch64 *i) const {
 544     // Only base + offset is allowed
 545     i->f(0b000, 25, 23);
 546     unsigned size = i->get(31, 31);
 547     size = 4 << size;
 548     guarantee(_offset % size == 0, "bad offset");
 549     i->sf(_offset / size, 21, 15);
 550     i->srf(_base, 5);
 551     guarantee(_mode == Address::base_plus_offset,
 552               "Bad addressing mode for non-temporal op");
 553   }
 554 
 555   void lea(MacroAssembler *, Register) const;
 556 
 557   static bool offset_ok_for_immed(long offset, int shift = 0) {
 558     unsigned mask = (1 << shift) - 1;
 559     if (offset < 0 || offset & mask) {
 560       return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
 561     } else {
 562       return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
 563     }
 564   }
 565 };
 566 
 567 // Convience classes
 568 class RuntimeAddress: public Address {
 569 
 570   public:
 571 
 572   RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
 573 
 574 };
 575 
 576 class OopAddress: public Address {
 577 
 578   public:
 579 
 580   OopAddress(address target) : Address(target, relocInfo::oop_type){}
 581 
 582 };
 583 
 584 class ExternalAddress: public Address {
 585  private:
 586   static relocInfo::relocType reloc_for_target(address target) {
 587     // Sometimes ExternalAddress is used for values which aren't
 588     // exactly addresses, like the card table base.
 589     // external_word_type can't be used for values in the first page
 590     // so just skip the reloc in that case.
 591     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 592   }
 593 
 594  public:
 595 
 596   ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
 597 
 598 };
 599 
 600 class InternalAddress: public Address {
 601 
 602   public:
 603 
 604   InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
 605 };
 606 
 607 const int FPUStateSizeInWords = 32 * 2;
 608 typedef enum {
 609   PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
 610   PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
 611   PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
 612 } prfop;
 613 
 614 class Assembler : public AbstractAssembler {
 615 
 616 #ifndef PRODUCT
 617   static const unsigned long asm_bp;
 618 
 619   void emit_long(jint x) {
 620     if ((unsigned long)pc() == asm_bp)
 621       asm volatile ("nop");
 622     AbstractAssembler::emit_int32(x);
 623   }
 624 #else
 625   void emit_long(jint x) {
 626     AbstractAssembler::emit_int32(x);
 627   }
 628 #endif
 629 
 630 public:
 631 
 632   enum { instruction_size = 4 };
 633 
 634   //---<  calculate length of instruction  >---
 635   // We just use the values set above.
 636   // instruction must start at passed address
 637   static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
 638 
 639   //---<  longest instructions  >---
 640   static unsigned int instr_maxlen() { return instruction_size; }
 641 
 642   Address adjust(Register base, int offset, bool preIncrement) {
 643     if (preIncrement)
 644       return Address(Pre(base, offset));
 645     else
 646       return Address(Post(base, offset));
 647   }
 648 
 649   Address pre(Register base, int offset) {
 650     return adjust(base, offset, true);
 651   }
 652 
 653   Address post(Register base, int offset) {
 654     return adjust(base, offset, false);
 655   }
 656 
 657   Address post(Register base, Register idx) {
 658     return Address(Post(base, idx));
 659   }
 660 
 661   Instruction_aarch64* current;
 662 
 663   void set_current(Instruction_aarch64* i) { current = i; }
 664 
 665   void f(unsigned val, int msb, int lsb) {
 666     current->f(val, msb, lsb);
 667   }
 668   void f(unsigned val, int msb) {
 669     current->f(val, msb, msb);
 670   }
 671   void sf(long val, int msb, int lsb) {
 672     current->sf(val, msb, lsb);
 673   }
 674   void rf(Register reg, int lsb) {
 675     current->rf(reg, lsb);
 676   }
 677   void srf(Register reg, int lsb) {
 678     current->srf(reg, lsb);
 679   }
 680   void zrf(Register reg, int lsb) {
 681     current->zrf(reg, lsb);
 682   }
 683   void rf(FloatRegister reg, int lsb) {
 684     current->rf(reg, lsb);
 685   }
 686   void fixed(unsigned value, unsigned mask) {
 687     current->fixed(value, mask);
 688   }
 689 
 690   void emit() {
 691     emit_long(current->get_insn());
 692     assert_cond(current->get_bits() == 0xffffffff);
 693     current = NULL;
 694   }
 695 
 696   typedef void (Assembler::* uncond_branch_insn)(address dest);
 697   typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
 698   typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
 699   typedef void (Assembler::* prefetch_insn)(address target, prfop);
 700 
 701   void wrap_label(Label &L, uncond_branch_insn insn);
 702   void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
 703   void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
 704   void wrap_label(Label &L, prfop, prefetch_insn insn);
 705 
 706   // PC-rel. addressing
 707 
 708   void adr(Register Rd, address dest);
 709   void _adrp(Register Rd, address dest);
 710 
 711   void adr(Register Rd, const Address &dest);
 712   void _adrp(Register Rd, const Address &dest);
 713 
 714   void adr(Register Rd, Label &L) {
 715     wrap_label(Rd, L, &Assembler::Assembler::adr);
 716   }
 717   void _adrp(Register Rd, Label &L) {
 718     wrap_label(Rd, L, &Assembler::_adrp);
 719   }
 720 
 721   void adrp(Register Rd, const Address &dest, unsigned long &offset);
 722 
 723 #undef INSN
 724 
 725   void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
 726                          int negated_op);
 727 
 728   // Add/subtract (immediate)
 729 #define INSN(NAME, decode, negated)                                     \
 730   void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) {   \
 731     starti;                                                             \
 732     f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
 733     zrf(Rd, 0), srf(Rn, 5);                                             \
 734   }                                                                     \
 735                                                                         \
 736   void NAME(Register Rd, Register Rn, unsigned imm) {                   \
 737     starti;                                                             \
 738     add_sub_immediate(Rd, Rn, imm, decode, negated);                    \
 739   }
 740 
 741   INSN(addsw, 0b001, 0b011);
 742   INSN(subsw, 0b011, 0b001);
 743   INSN(adds,  0b101, 0b111);
 744   INSN(subs,  0b111, 0b101);
 745 
 746 #undef INSN
 747 
 748 #define INSN(NAME, decode, negated)                     \
 749   void NAME(Register Rd, Register Rn, unsigned imm) {   \
 750     starti;                                             \
 751     add_sub_immediate(Rd, Rn, imm, decode, negated);    \
 752   }
 753 
 754   INSN(addw, 0b000, 0b010);
 755   INSN(subw, 0b010, 0b000);
 756   INSN(add,  0b100, 0b110);
 757   INSN(sub,  0b110, 0b100);
 758 
 759 #undef INSN
 760 
 761  // Logical (immediate)
 762 #define INSN(NAME, decode, is32)                                \
 763   void NAME(Register Rd, Register Rn, uint64_t imm) {           \
 764     starti;                                                     \
 765     uint32_t val = encode_logical_immediate(is32, imm);         \
 766     f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10);     \
 767     srf(Rd, 0), zrf(Rn, 5);                                     \
 768   }
 769 
 770   INSN(andw, 0b000, true);
 771   INSN(orrw, 0b001, true);
 772   INSN(eorw, 0b010, true);
 773   INSN(andr,  0b100, false);
 774   INSN(orr,  0b101, false);
 775   INSN(eor,  0b110, false);
 776 
 777 #undef INSN
 778 
 779 #define INSN(NAME, decode, is32)                                \
 780   void NAME(Register Rd, Register Rn, uint64_t imm) {           \
 781     starti;                                                     \
 782     uint32_t val = encode_logical_immediate(is32, imm);         \
 783     f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10);     \
 784     zrf(Rd, 0), zrf(Rn, 5);                                     \
 785   }
 786 
 787   INSN(ands, 0b111, false);
 788   INSN(andsw, 0b011, true);
 789 
 790 #undef INSN
 791 
 792   // Move wide (immediate)
 793 #define INSN(NAME, opcode)                                              \
 794   void NAME(Register Rd, unsigned imm, unsigned shift = 0) {            \
 795     assert_cond((shift/16)*16 == shift);                                \
 796     starti;                                                             \
 797     f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21),        \
 798       f(imm, 20, 5);                                                    \
 799     rf(Rd, 0);                                                          \
 800   }
 801 
 802   INSN(movnw, 0b000);
 803   INSN(movzw, 0b010);
 804   INSN(movkw, 0b011);
 805   INSN(movn, 0b100);
 806   INSN(movz, 0b110);
 807   INSN(movk, 0b111);
 808 
 809 #undef INSN
 810 
 811   // Bitfield
 812 #define INSN(NAME, opcode, size)                                        \
 813   void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) {   \
 814     starti;                                                             \
 815     guarantee(size == 1 || (immr < 32 && imms < 32), "incorrect immr/imms");\
 816     f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10);                \
 817     zrf(Rn, 5), rf(Rd, 0);                                              \
 818   }
 819 
 820   INSN(sbfmw, 0b0001001100, 0);
 821   INSN(bfmw,  0b0011001100, 0);
 822   INSN(ubfmw, 0b0101001100, 0);
 823   INSN(sbfm,  0b1001001101, 1);
 824   INSN(bfm,   0b1011001101, 1);
 825   INSN(ubfm,  0b1101001101, 1);
 826 
 827 #undef INSN
 828 
 829   // Extract
 830 #define INSN(NAME, opcode, size)                                        \
 831   void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) {     \
 832     starti;                                                             \
 833     guarantee(size == 1 || imms < 32, "incorrect imms");                \
 834     f(opcode, 31, 21), f(imms, 15, 10);                                 \
 835     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                                \
 836   }
 837 
 838   INSN(extrw, 0b00010011100, 0);
 839   INSN(extr,  0b10010011110, 1);
 840 
 841 #undef INSN
 842 
 843   // The maximum range of a branch is fixed for the AArch64
 844   // architecture.  In debug mode we shrink it in order to test
 845   // trampolines, but not so small that branches in the interpreter
 846   // are out of range.
 847   static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
 848 
 849   static bool reachable_from_branch_at(address branch, address target) {
 850     return uabs(target - branch) < branch_range;
 851   }
 852 
 853   // Unconditional branch (immediate)
 854 #define INSN(NAME, opcode)                                              \
 855   void NAME(address dest) {                                             \
 856     starti;                                                             \
 857     long offset = (dest - pc()) >> 2;                                   \
 858     DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
 859     f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0);               \
 860   }                                                                     \
 861   void NAME(Label &L) {                                                 \
 862     wrap_label(L, &Assembler::NAME);                                    \
 863   }                                                                     \
 864   void NAME(const Address &dest);
 865 
 866   INSN(b, 0);
 867   INSN(bl, 1);
 868 
 869 #undef INSN
 870 
 871   // Compare & branch (immediate)
 872 #define INSN(NAME, opcode)                              \
 873   void NAME(Register Rt, address dest) {                \
 874     long offset = (dest - pc()) >> 2;                   \
 875     starti;                                             \
 876     f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0);    \
 877   }                                                     \
 878   void NAME(Register Rt, Label &L) {                    \
 879     wrap_label(Rt, L, &Assembler::NAME);                \
 880   }
 881 
 882   INSN(cbzw,  0b00110100);
 883   INSN(cbnzw, 0b00110101);
 884   INSN(cbz,   0b10110100);
 885   INSN(cbnz,  0b10110101);
 886 
 887 #undef INSN
 888 
 889   // Test & branch (immediate)
 890 #define INSN(NAME, opcode)                                              \
 891   void NAME(Register Rt, int bitpos, address dest) {                    \
 892     long offset = (dest - pc()) >> 2;                                   \
 893     int b5 = bitpos >> 5;                                               \
 894     bitpos &= 0x1f;                                                     \
 895     starti;                                                             \
 896     f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
 897     rf(Rt, 0);                                                          \
 898   }                                                                     \
 899   void NAME(Register Rt, int bitpos, Label &L) {                        \
 900     wrap_label(Rt, bitpos, L, &Assembler::NAME);                        \
 901   }
 902 
 903   INSN(tbz,  0b0110110);
 904   INSN(tbnz, 0b0110111);
 905 
 906 #undef INSN
 907 
 908   // Conditional branch (immediate)
 909   enum Condition
 910     {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
 911 
 912   void br(Condition  cond, address dest) {
 913     long offset = (dest - pc()) >> 2;
 914     starti;
 915     f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
 916   }
 917 
 918 #define INSN(NAME, cond)                        \
 919   void NAME(address dest) {                     \
 920     br(cond, dest);                             \
 921   }
 922 
 923   INSN(beq, EQ);
 924   INSN(bne, NE);
 925   INSN(bhs, HS);
 926   INSN(bcs, CS);
 927   INSN(blo, LO);
 928   INSN(bcc, CC);
 929   INSN(bmi, MI);
 930   INSN(bpl, PL);
 931   INSN(bvs, VS);
 932   INSN(bvc, VC);
 933   INSN(bhi, HI);
 934   INSN(bls, LS);
 935   INSN(bge, GE);
 936   INSN(blt, LT);
 937   INSN(bgt, GT);
 938   INSN(ble, LE);
 939   INSN(bal, AL);
 940   INSN(bnv, NV);
 941 
 942   void br(Condition cc, Label &L);
 943 
 944 #undef INSN
 945 
 946   // Exception generation
 947   void generate_exception(int opc, int op2, int LL, unsigned imm) {
 948     starti;
 949     f(0b11010100, 31, 24);
 950     f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
 951   }
 952 
 953 #define INSN(NAME, opc, op2, LL)                \
 954   void NAME(unsigned imm) {                     \
 955     generate_exception(opc, op2, LL, imm);      \
 956   }
 957 
 958   INSN(svc, 0b000, 0, 0b01);
 959   INSN(hvc, 0b000, 0, 0b10);
 960   INSN(smc, 0b000, 0, 0b11);
 961   INSN(brk, 0b001, 0, 0b00);
 962   INSN(hlt, 0b010, 0, 0b00);
 963   INSN(dpcs1, 0b101, 0, 0b01);
 964   INSN(dpcs2, 0b101, 0, 0b10);
 965   INSN(dpcs3, 0b101, 0, 0b11);
 966 
 967 #undef INSN
 968 
 969   // System
 970   void system(int op0, int op1, int CRn, int CRm, int op2,
 971               Register rt = dummy_reg)
 972   {
 973     starti;
 974     f(0b11010101000, 31, 21);
 975     f(op0, 20, 19);
 976     f(op1, 18, 16);
 977     f(CRn, 15, 12);
 978     f(CRm, 11, 8);
 979     f(op2, 7, 5);
 980     rf(rt, 0);
 981   }
 982 
 983   void hint(int imm) {
 984     system(0b00, 0b011, 0b0010, 0b0000, imm);
 985   }
 986 
 987   void nop() {
 988     hint(0);
 989   }
 990 
 991   void yield() {
 992     hint(1);
 993   }
 994 
 995   void wfe() {
 996     hint(2);
 997   }
 998 
 999   void wfi() {
1000     hint(3);
1001   }
1002 
1003   void sev() {
1004     hint(4);
1005   }
1006 
1007   void sevl() {
1008     hint(5);
1009   }
1010 
1011   // we only provide mrs and msr for the special purpose system
1012   // registers where op1 (instr[20:19]) == 11 and, (currently) only
1013   // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1014 
1015   void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1016     starti;
1017     f(0b1101010100011, 31, 19);
1018     f(op1, 18, 16);
1019     f(CRn, 15, 12);
1020     f(CRm, 11, 8);
1021     f(op2, 7, 5);
1022     // writing zr is ok
1023     zrf(rt, 0);
1024   }
1025 
1026   void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1027     starti;
1028     f(0b1101010100111, 31, 19);
1029     f(op1, 18, 16);
1030     f(CRn, 15, 12);
1031     f(CRm, 11, 8);
1032     f(op2, 7, 5);
1033     // reading to zr is a mistake
1034     rf(rt, 0);
1035   }
1036 
1037   enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1038                 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1039 
1040   void dsb(barrier imm) {
1041     system(0b00, 0b011, 0b00011, imm, 0b100);
1042   }
1043 
1044   void dmb(barrier imm) {
1045     system(0b00, 0b011, 0b00011, imm, 0b101);
1046   }
1047 
1048   void isb() {
1049     system(0b00, 0b011, 0b00011, SY, 0b110);
1050   }
1051 
1052   void sys(int op1, int CRn, int CRm, int op2,
1053            Register rt = (Register)0b11111) {
1054     system(0b01, op1, CRn, CRm, op2, rt);
1055   }
1056 
1057   // Only implement operations accessible from EL0 or higher, i.e.,
1058   //            op1    CRn    CRm    op2
1059   // IC IVAU     3      7      5      1
1060   // DC CVAC     3      7      10     1
1061   // DC CVAU     3      7      11     1
1062   // DC CIVAC    3      7      14     1
1063   // DC ZVA      3      7      4      1
1064   // So only deal with the CRm field.
1065   enum icache_maintenance {IVAU = 0b0101};
1066   enum dcache_maintenance {CVAC = 0b1010, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1067 
1068   void dc(dcache_maintenance cm, Register Rt) {
1069     sys(0b011, 0b0111, cm, 0b001, Rt);
1070   }
1071 
1072   void ic(icache_maintenance cm, Register Rt) {
1073     sys(0b011, 0b0111, cm, 0b001, Rt);
1074   }
1075 
1076   // A more convenient access to dmb for our purposes
1077   enum Membar_mask_bits {
1078     // We can use ISH for a barrier because the ARM ARM says "This
1079     // architecture assumes that all Processing Elements that use the
1080     // same operating system or hypervisor are in the same Inner
1081     // Shareable shareability domain."
1082     StoreStore = ISHST,
1083     LoadStore  = ISHLD,
1084     LoadLoad   = ISHLD,
1085     StoreLoad  = ISH,
1086     AnyAny     = ISH
1087   };
1088 
1089   void membar(Membar_mask_bits order_constraint) {
1090     dmb(Assembler::barrier(order_constraint));
1091   }
1092 
1093   // Unconditional branch (register)
1094   void branch_reg(Register R, int opc) {
1095     starti;
1096     f(0b1101011, 31, 25);
1097     f(opc, 24, 21);
1098     f(0b11111000000, 20, 10);
1099     rf(R, 5);
1100     f(0b00000, 4, 0);
1101   }
1102 
1103 #define INSN(NAME, opc)                         \
1104   void NAME(Register R) {                       \
1105     branch_reg(R, opc);                         \
1106   }
1107 
1108   INSN(br, 0b0000);
1109   INSN(blr, 0b0001);
1110   INSN(ret, 0b0010);
1111 
1112   void ret(void *p); // This forces a compile-time error for ret(0)
1113 
1114 #undef INSN
1115 
1116 #define INSN(NAME, opc)                         \
1117   void NAME() {                 \
1118     branch_reg(dummy_reg, opc);         \
1119   }
1120 
1121   INSN(eret, 0b0100);
1122   INSN(drps, 0b0101);
1123 
1124 #undef INSN
1125 
1126   // Load/store exclusive
1127   enum operand_size { byte, halfword, word, xword };
1128 
1129   void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1130     Register Rn, enum operand_size sz, int op, bool ordered) {
1131     starti;
1132     f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1133     rf(Rs, 16), f(ordered, 15), zrf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
1134   }
1135 
1136   void load_exclusive(Register dst, Register addr,
1137                       enum operand_size sz, bool ordered) {
1138     load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1139                          sz, 0b010, ordered);
1140   }
1141 
1142   void store_exclusive(Register status, Register new_val, Register addr,
1143                        enum operand_size sz, bool ordered) {
1144     load_store_exclusive(status, new_val, dummy_reg, addr,
1145                          sz, 0b000, ordered);
1146   }
1147 
1148 #define INSN4(NAME, sz, op, o0) /* Four registers */                    \
1149   void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) {     \
1150     guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1151     load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0);                 \
1152   }
1153 
1154 #define INSN3(NAME, sz, op, o0) /* Three registers */                   \
1155   void NAME(Register Rs, Register Rt, Register Rn) {                    \
1156     guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction");       \
1157     load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1158   }
1159 
1160 #define INSN2(NAME, sz, op, o0) /* Two registers */                     \
1161   void NAME(Register Rt, Register Rn) {                                 \
1162     load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1163                          Rn, sz, op, o0);                               \
1164   }
1165 
1166 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1167   void NAME(Register Rt1, Register Rt2, Register Rn) {                  \
1168     guarantee(Rt1 != Rt2, "unpredictable instruction");                 \
1169     load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0);          \
1170   }
1171 
1172   // bytes
1173   INSN3(stxrb, byte, 0b000, 0);
1174   INSN3(stlxrb, byte, 0b000, 1);
1175   INSN2(ldxrb, byte, 0b010, 0);
1176   INSN2(ldaxrb, byte, 0b010, 1);
1177   INSN2(stlrb, byte, 0b100, 1);
1178   INSN2(ldarb, byte, 0b110, 1);
1179 
1180   // halfwords
1181   INSN3(stxrh, halfword, 0b000, 0);
1182   INSN3(stlxrh, halfword, 0b000, 1);
1183   INSN2(ldxrh, halfword, 0b010, 0);
1184   INSN2(ldaxrh, halfword, 0b010, 1);
1185   INSN2(stlrh, halfword, 0b100, 1);
1186   INSN2(ldarh, halfword, 0b110, 1);
1187 
1188   // words
1189   INSN3(stxrw, word, 0b000, 0);
1190   INSN3(stlxrw, word, 0b000, 1);
1191   INSN4(stxpw, word, 0b001, 0);
1192   INSN4(stlxpw, word, 0b001, 1);
1193   INSN2(ldxrw, word, 0b010, 0);
1194   INSN2(ldaxrw, word, 0b010, 1);
1195   INSN_FOO(ldxpw, word, 0b011, 0);
1196   INSN_FOO(ldaxpw, word, 0b011, 1);
1197   INSN2(stlrw, word, 0b100, 1);
1198   INSN2(ldarw, word, 0b110, 1);
1199 
1200   // xwords
1201   INSN3(stxr, xword, 0b000, 0);
1202   INSN3(stlxr, xword, 0b000, 1);
1203   INSN4(stxp, xword, 0b001, 0);
1204   INSN4(stlxp, xword, 0b001, 1);
1205   INSN2(ldxr, xword, 0b010, 0);
1206   INSN2(ldaxr, xword, 0b010, 1);
1207   INSN_FOO(ldxp, xword, 0b011, 0);
1208   INSN_FOO(ldaxp, xword, 0b011, 1);
1209   INSN2(stlr, xword, 0b100, 1);
1210   INSN2(ldar, xword, 0b110, 1);
1211 
1212 #undef INSN2
1213 #undef INSN3
1214 #undef INSN4
1215 #undef INSN_FOO
1216 
1217   // 8.1 Compare and swap extensions
1218   void lse_cas(Register Rs, Register Rt, Register Rn,
1219                         enum operand_size sz, bool a, bool r, bool not_pair) {
1220     starti;
1221     if (! not_pair) { // Pair
1222       assert(sz == word || sz == xword, "invalid size");
1223       /* The size bit is in bit 30, not 31 */
1224       sz = (operand_size)(sz == word ? 0b00:0b01);
1225     }
1226     f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
1227     zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
1228   }
1229 
1230   // CAS
1231 #define INSN(NAME, a, r)                                                \
1232   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
1233     assert(Rs != Rn && Rs != Rt, "unpredictable instruction");          \
1234     lse_cas(Rs, Rt, Rn, sz, a, r, true);                                \
1235   }
1236   INSN(cas,    false, false)
1237   INSN(casa,   true,  false)
1238   INSN(casl,   false, true)
1239   INSN(casal,  true,  true)
1240 #undef INSN
1241 
1242   // CASP
1243 #define INSN(NAME, a, r)                                                \
1244   void NAME(operand_size sz, Register Rs, Register Rs1,                 \
1245             Register Rt, Register Rt1, Register Rn) {                   \
1246     assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 &&    \
1247            Rs->successor() == Rs1 && Rt->successor() == Rt1 &&          \
1248            Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers");     \
1249     lse_cas(Rs, Rt, Rn, sz, a, r, false);                               \
1250   }
1251   INSN(casp,    false, false)
1252   INSN(caspa,   true,  false)
1253   INSN(caspl,   false, true)
1254   INSN(caspal,  true,  true)
1255 #undef INSN
1256 
1257   // 8.1 Atomic operations
1258   void lse_atomic(Register Rs, Register Rt, Register Rn,
1259                   enum operand_size sz, int op1, int op2, bool a, bool r) {
1260     starti;
1261     f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1262     zrf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
1263   }
1264 
1265 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2)                   \
1266   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
1267     lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false);                 \
1268   }                                                                     \
1269   void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1270     lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false);                  \
1271   }                                                                     \
1272   void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1273     lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true);                  \
1274   }                                                                     \
1275   void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1276     lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true);                   \
1277   }
1278   INSN(ldadd,  ldadda,  ldaddl,  ldaddal,  0, 0b000);
1279   INSN(ldbic,  ldbica,  ldbicl,  ldbical,  0, 0b001);
1280   INSN(ldeor,  ldeora,  ldeorl,  ldeoral,  0, 0b010);
1281   INSN(ldorr,  ldorra,  ldorrl,  ldorral,  0, 0b011);
1282   INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1283   INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1284   INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1285   INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1286   INSN(swp,    swpa,    swpl,    swpal,    1, 0b000);
1287 #undef INSN
1288 
1289   // Load register (literal)
1290 #define INSN(NAME, opc, V)                                              \
1291   void NAME(Register Rt, address dest) {                                \
1292     long offset = (dest - pc()) >> 2;                                   \
1293     starti;                                                             \
1294     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1295       sf(offset, 23, 5);                                                \
1296     rf(Rt, 0);                                                          \
1297   }                                                                     \
1298   void NAME(Register Rt, address dest, relocInfo::relocType rtype) {    \
1299     InstructionMark im(this);                                           \
1300     guarantee(rtype == relocInfo::internal_word_type,                   \
1301               "only internal_word_type relocs make sense here");        \
1302     code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1303     NAME(Rt, dest);                                                     \
1304   }                                                                     \
1305   void NAME(Register Rt, Label &L) {                                    \
1306     wrap_label(Rt, L, &Assembler::NAME);                                \
1307   }
1308 
1309   INSN(ldrw, 0b00, 0);
1310   INSN(ldr, 0b01, 0);
1311   INSN(ldrsw, 0b10, 0);
1312 
1313 #undef INSN
1314 
1315 #define INSN(NAME, opc, V)                                              \
1316   void NAME(FloatRegister Rt, address dest) {                           \
1317     long offset = (dest - pc()) >> 2;                                   \
1318     starti;                                                             \
1319     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1320       sf(offset, 23, 5);                                                \
1321     rf((Register)Rt, 0);                                                \
1322   }
1323 
1324   INSN(ldrs, 0b00, 1);
1325   INSN(ldrd, 0b01, 1);
1326   INSN(ldrq, 0b10, 1);
1327 
1328 #undef INSN
1329 
1330 #define INSN(NAME, opc, V)                                              \
1331   void NAME(address dest, prfop op = PLDL1KEEP) {                       \
1332     long offset = (dest - pc()) >> 2;                                   \
1333     starti;                                                             \
1334     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1335       sf(offset, 23, 5);                                                \
1336     f(op, 4, 0);                                                        \
1337   }                                                                     \
1338   void NAME(Label &L, prfop op = PLDL1KEEP) {                           \
1339     wrap_label(L, op, &Assembler::NAME);                                \
1340   }
1341 
1342   INSN(prfm, 0b11, 0);
1343 
1344 #undef INSN
1345 
1346   // Load/store
1347   void ld_st1(int opc, int p1, int V, int L,
1348               Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1349     starti;
1350     f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1351     zrf(Rt2, 10), zrf(Rt1, 0);
1352     if (no_allocate) {
1353       adr.encode_nontemporal_pair(current);
1354     } else {
1355       adr.encode_pair(current);
1356     }
1357   }
1358 
1359   // Load/store register pair (offset)
1360 #define INSN(NAME, size, p1, V, L, no_allocate)         \
1361   void NAME(Register Rt1, Register Rt2, Address adr) {  \
1362     ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1363    }
1364 
1365   INSN(stpw, 0b00, 0b101, 0, 0, false);
1366   INSN(ldpw, 0b00, 0b101, 0, 1, false);
1367   INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1368   INSN(stp, 0b10, 0b101, 0, 0, false);
1369   INSN(ldp, 0b10, 0b101, 0, 1, false);
1370 
1371   // Load/store no-allocate pair (offset)
1372   INSN(stnpw, 0b00, 0b101, 0, 0, true);
1373   INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1374   INSN(stnp, 0b10, 0b101, 0, 0, true);
1375   INSN(ldnp, 0b10, 0b101, 0, 1, true);
1376 
1377 #undef INSN
1378 
1379 #define INSN(NAME, size, p1, V, L, no_allocate)                         \
1380   void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) {        \
1381     ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1382    }
1383 
1384   INSN(stps, 0b00, 0b101, 1, 0, false);
1385   INSN(ldps, 0b00, 0b101, 1, 1, false);
1386   INSN(stpd, 0b01, 0b101, 1, 0, false);
1387   INSN(ldpd, 0b01, 0b101, 1, 1, false);
1388   INSN(stpq, 0b10, 0b101, 1, 0, false);
1389   INSN(ldpq, 0b10, 0b101, 1, 1, false);
1390 
1391 #undef INSN
1392 
1393   // Load/store register (all modes)
1394   void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1395     starti;
1396 
1397     f(V, 26); // general reg?
1398     zrf(Rt, 0);
1399 
1400     // Encoding for literal loads is done here (rather than pushed
1401     // down into Address::encode) because the encoding of this
1402     // instruction is too different from all of the other forms to
1403     // make it worth sharing.
1404     if (adr.getMode() == Address::literal) {
1405       assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1406       assert(op == 0b01, "literal form can only be used with loads");
1407       f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1408       long offset = (adr.target() - pc()) >> 2;
1409       sf(offset, 23, 5);
1410       code_section()->relocate(pc(), adr.rspec());
1411       return;
1412     }
1413 
1414     f(size, 31, 30);
1415     f(op, 23, 22); // str
1416     adr.encode(current);
1417   }
1418 
1419 #define INSN(NAME, size, op)                            \
1420   void NAME(Register Rt, const Address &adr) {          \
1421     ld_st2(Rt, adr, size, op);                          \
1422   }                                                     \
1423 
1424   INSN(str, 0b11, 0b00);
1425   INSN(strw, 0b10, 0b00);
1426   INSN(strb, 0b00, 0b00);
1427   INSN(strh, 0b01, 0b00);
1428 
1429   INSN(ldr, 0b11, 0b01);
1430   INSN(ldrw, 0b10, 0b01);
1431   INSN(ldrb, 0b00, 0b01);
1432   INSN(ldrh, 0b01, 0b01);
1433 
1434   INSN(ldrsb, 0b00, 0b10);
1435   INSN(ldrsbw, 0b00, 0b11);
1436   INSN(ldrsh, 0b01, 0b10);
1437   INSN(ldrshw, 0b01, 0b11);
1438   INSN(ldrsw, 0b10, 0b10);
1439 
1440 #undef INSN
1441 
1442 #define INSN(NAME, size, op)                                    \
1443   void NAME(const Address &adr, prfop pfop = PLDL1KEEP) {       \
1444     ld_st2((Register)pfop, adr, size, op);                      \
1445   }
1446 
1447   INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1448                           // writeback modes, but the assembler
1449                           // doesn't enfore that.
1450 
1451 #undef INSN
1452 
1453 #define INSN(NAME, size, op)                            \
1454   void NAME(FloatRegister Rt, const Address &adr) {     \
1455     ld_st2((Register)Rt, adr, size, op, 1);             \
1456   }
1457 
1458   INSN(strd, 0b11, 0b00);
1459   INSN(strs, 0b10, 0b00);
1460   INSN(ldrd, 0b11, 0b01);
1461   INSN(ldrs, 0b10, 0b01);
1462   INSN(strq, 0b00, 0b10);
1463   INSN(ldrq, 0x00, 0b11);
1464 
1465 #undef INSN
1466 
1467   enum shift_kind { LSL, LSR, ASR, ROR };
1468 
1469   void op_shifted_reg(unsigned decode,
1470                       enum shift_kind kind, unsigned shift,
1471                       unsigned size, unsigned op) {
1472     f(size, 31);
1473     f(op, 30, 29);
1474     f(decode, 28, 24);
1475     f(shift, 15, 10);
1476     f(kind, 23, 22);
1477   }
1478 
1479   // Logical (shifted register)
1480 #define INSN(NAME, size, op, N)                                 \
1481   void NAME(Register Rd, Register Rn, Register Rm,              \
1482             enum shift_kind kind = LSL, unsigned shift = 0) {   \
1483     starti;                                                     \
1484     guarantee(size == 1 || shift < 32, "incorrect shift");      \
1485     f(N, 21);                                                   \
1486     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                        \
1487     op_shifted_reg(0b01010, kind, shift, size, op);             \
1488   }
1489 
1490   INSN(andr, 1, 0b00, 0);
1491   INSN(orr, 1, 0b01, 0);
1492   INSN(eor, 1, 0b10, 0);
1493   INSN(ands, 1, 0b11, 0);
1494   INSN(andw, 0, 0b00, 0);
1495   INSN(orrw, 0, 0b01, 0);
1496   INSN(eorw, 0, 0b10, 0);
1497   INSN(andsw, 0, 0b11, 0);
1498 
1499 #undef INSN
1500 
1501 #define INSN(NAME, size, op, N)                                         \
1502   void NAME(Register Rd, Register Rn, Register Rm,                      \
1503             enum shift_kind kind = LSL, unsigned shift = 0) {           \
1504     starti;                                                             \
1505     f(N, 21);                                                           \
1506     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                                \
1507     op_shifted_reg(0b01010, kind, shift, size, op);                     \
1508   }                                                                     \
1509                                                                         \
1510   /* These instructions have no immediate form. Provide an overload so  \
1511      that if anyone does try to use an immediate operand -- this has    \
1512      happened! -- we'll get a compile-time error. */                    \
1513   void NAME(Register Rd, Register Rn, unsigned imm,                     \
1514             enum shift_kind kind = LSL, unsigned shift = 0) {           \
1515     assert(false, " can't be used with immediate operand");             \
1516   }
1517 
1518   INSN(bic, 1, 0b00, 1);
1519   INSN(orn, 1, 0b01, 1);
1520   INSN(eon, 1, 0b10, 1);
1521   INSN(bics, 1, 0b11, 1);
1522   INSN(bicw, 0, 0b00, 1);
1523   INSN(ornw, 0, 0b01, 1);
1524   INSN(eonw, 0, 0b10, 1);
1525   INSN(bicsw, 0, 0b11, 1);
1526 
1527 #undef INSN
1528 
1529   // Aliases for short forms of orn
1530 void mvn(Register Rd, Register Rm,
1531             enum shift_kind kind = LSL, unsigned shift = 0) {
1532   orn(Rd, zr, Rm, kind, shift);
1533 }
1534 
1535 void mvnw(Register Rd, Register Rm,
1536             enum shift_kind kind = LSL, unsigned shift = 0) {
1537   ornw(Rd, zr, Rm, kind, shift);
1538 }
1539 
1540   // Add/subtract (shifted register)
1541 #define INSN(NAME, size, op)                            \
1542   void NAME(Register Rd, Register Rn, Register Rm,      \
1543             enum shift_kind kind, unsigned shift = 0) { \
1544     starti;                                             \
1545     f(0, 21);                                           \
1546     assert_cond(kind != ROR);                           \
1547     guarantee(size == 1 || shift < 32, "incorrect shift");\
1548     zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16);                \
1549     op_shifted_reg(0b01011, kind, shift, size, op);     \
1550   }
1551 
1552   INSN(add, 1, 0b000);
1553   INSN(sub, 1, 0b10);
1554   INSN(addw, 0, 0b000);
1555   INSN(subw, 0, 0b10);
1556 
1557   INSN(adds, 1, 0b001);
1558   INSN(subs, 1, 0b11);
1559   INSN(addsw, 0, 0b001);
1560   INSN(subsw, 0, 0b11);
1561 
1562 #undef INSN
1563 
1564   // Add/subtract (extended register)
1565 #define INSN(NAME, op)                                                  \
1566   void NAME(Register Rd, Register Rn, Register Rm,                      \
1567            ext::operation option, int amount = 0) {                     \
1568     starti;                                                             \
1569     zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0);                                \
1570     add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1571   }
1572 
1573   void add_sub_extended_reg(unsigned op, unsigned decode,
1574     Register Rd, Register Rn, Register Rm,
1575     unsigned opt, ext::operation option, unsigned imm) {
1576     guarantee(imm <= 4, "shift amount must be <= 4");
1577     f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1578     f(option, 15, 13), f(imm, 12, 10);
1579   }
1580 
1581   INSN(addw, 0b000);
1582   INSN(subw, 0b010);
1583   INSN(add, 0b100);
1584   INSN(sub, 0b110);
1585 
1586 #undef INSN
1587 
1588 #define INSN(NAME, op)                                                  \
1589   void NAME(Register Rd, Register Rn, Register Rm,                      \
1590            ext::operation option, int amount = 0) {                     \
1591     starti;                                                             \
1592     zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0);                                \
1593     add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1594   }
1595 
1596   INSN(addsw, 0b001);
1597   INSN(subsw, 0b011);
1598   INSN(adds, 0b101);
1599   INSN(subs, 0b111);
1600 
1601 #undef INSN
1602 
1603   // Aliases for short forms of add and sub
1604 #define INSN(NAME)                                      \
1605   void NAME(Register Rd, Register Rn, Register Rm) {    \
1606     if (Rd == sp || Rn == sp)                           \
1607       NAME(Rd, Rn, Rm, ext::uxtx);                      \
1608     else                                                \
1609       NAME(Rd, Rn, Rm, LSL);                            \
1610   }
1611 
1612   INSN(addw);
1613   INSN(subw);
1614   INSN(add);
1615   INSN(sub);
1616 
1617   INSN(addsw);
1618   INSN(subsw);
1619   INSN(adds);
1620   INSN(subs);
1621 
1622 #undef INSN
1623 
1624   // Add/subtract (with carry)
1625   void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1626     starti;
1627     f(op, 31, 29);
1628     f(0b11010000, 28, 21);
1629     f(0b000000, 15, 10);
1630     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1631   }
1632 
1633   #define INSN(NAME, op)                                \
1634     void NAME(Register Rd, Register Rn, Register Rm) {  \
1635       add_sub_carry(op, Rd, Rn, Rm);                    \
1636     }
1637 
1638   INSN(adcw, 0b000);
1639   INSN(adcsw, 0b001);
1640   INSN(sbcw, 0b010);
1641   INSN(sbcsw, 0b011);
1642   INSN(adc, 0b100);
1643   INSN(adcs, 0b101);
1644   INSN(sbc,0b110);
1645   INSN(sbcs, 0b111);
1646 
1647 #undef INSN
1648 
1649   // Conditional compare (both kinds)
1650   void conditional_compare(unsigned op, int o1, int o2, int o3,
1651                            Register Rn, unsigned imm5, unsigned nzcv,
1652                            unsigned cond) {
1653     starti;
1654     f(op, 31, 29);
1655     f(0b11010010, 28, 21);
1656     f(cond, 15, 12);
1657     f(o1, 11);
1658     f(o2, 10);
1659     f(o3, 4);
1660     f(nzcv, 3, 0);
1661     f(imm5, 20, 16), zrf(Rn, 5);
1662   }
1663 
1664 #define INSN(NAME, op)                                                  \
1665   void NAME(Register Rn, Register Rm, int imm, Condition cond) {        \
1666     int regNumber = (Rm == zr ? 31 : (uintptr_t)Rm);                    \
1667     conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond);         \
1668   }                                                                     \
1669                                                                         \
1670   void NAME(Register Rn, int imm5, int imm, Condition cond) {           \
1671     conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond);              \
1672   }
1673 
1674   INSN(ccmnw, 0b001);
1675   INSN(ccmpw, 0b011);
1676   INSN(ccmn, 0b101);
1677   INSN(ccmp, 0b111);
1678 
1679 #undef INSN
1680 
1681   // Conditional select
1682   void conditional_select(unsigned op, unsigned op2,
1683                           Register Rd, Register Rn, Register Rm,
1684                           unsigned cond) {
1685     starti;
1686     f(op, 31, 29);
1687     f(0b11010100, 28, 21);
1688     f(cond, 15, 12);
1689     f(op2, 11, 10);
1690     zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1691   }
1692 
1693 #define INSN(NAME, op, op2)                                             \
1694   void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1695     conditional_select(op, op2, Rd, Rn, Rm, cond);                      \
1696   }
1697 
1698   INSN(cselw, 0b000, 0b00);
1699   INSN(csincw, 0b000, 0b01);
1700   INSN(csinvw, 0b010, 0b00);
1701   INSN(csnegw, 0b010, 0b01);
1702   INSN(csel, 0b100, 0b00);
1703   INSN(csinc, 0b100, 0b01);
1704   INSN(csinv, 0b110, 0b00);
1705   INSN(csneg, 0b110, 0b01);
1706 
1707 #undef INSN
1708 
1709   // Data processing
1710   void data_processing(unsigned op29, unsigned opcode,
1711                        Register Rd, Register Rn) {
1712     f(op29, 31, 29), f(0b11010110, 28, 21);
1713     f(opcode, 15, 10);
1714     rf(Rn, 5), rf(Rd, 0);
1715   }
1716 
1717   // (1 source)
1718 #define INSN(NAME, op29, opcode2, opcode)       \
1719   void NAME(Register Rd, Register Rn) {         \
1720     starti;                                     \
1721     f(opcode2, 20, 16);                         \
1722     data_processing(op29, opcode, Rd, Rn);      \
1723   }
1724 
1725   INSN(rbitw,  0b010, 0b00000, 0b00000);
1726   INSN(rev16w, 0b010, 0b00000, 0b00001);
1727   INSN(revw,   0b010, 0b00000, 0b00010);
1728   INSN(clzw,   0b010, 0b00000, 0b00100);
1729   INSN(clsw,   0b010, 0b00000, 0b00101);
1730 
1731   INSN(rbit,   0b110, 0b00000, 0b00000);
1732   INSN(rev16,  0b110, 0b00000, 0b00001);
1733   INSN(rev32,  0b110, 0b00000, 0b00010);
1734   INSN(rev,    0b110, 0b00000, 0b00011);
1735   INSN(clz,    0b110, 0b00000, 0b00100);
1736   INSN(cls,    0b110, 0b00000, 0b00101);
1737 
1738 #undef INSN
1739 
1740   // (2 sources)
1741 #define INSN(NAME, op29, opcode)                        \
1742   void NAME(Register Rd, Register Rn, Register Rm) {    \
1743     starti;                                             \
1744     rf(Rm, 16);                                         \
1745     data_processing(op29, opcode, Rd, Rn);              \
1746   }
1747 
1748   INSN(udivw, 0b000, 0b000010);
1749   INSN(sdivw, 0b000, 0b000011);
1750   INSN(lslvw, 0b000, 0b001000);
1751   INSN(lsrvw, 0b000, 0b001001);
1752   INSN(asrvw, 0b000, 0b001010);
1753   INSN(rorvw, 0b000, 0b001011);
1754 
1755   INSN(udiv, 0b100, 0b000010);
1756   INSN(sdiv, 0b100, 0b000011);
1757   INSN(lslv, 0b100, 0b001000);
1758   INSN(lsrv, 0b100, 0b001001);
1759   INSN(asrv, 0b100, 0b001010);
1760   INSN(rorv, 0b100, 0b001011);
1761 
1762 #undef INSN
1763 
1764   // (3 sources)
1765   void data_processing(unsigned op54, unsigned op31, unsigned o0,
1766                        Register Rd, Register Rn, Register Rm,
1767                        Register Ra) {
1768     starti;
1769     f(op54, 31, 29), f(0b11011, 28, 24);
1770     f(op31, 23, 21), f(o0, 15);
1771     zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1772   }
1773 
1774 #define INSN(NAME, op54, op31, o0)                                      \
1775   void NAME(Register Rd, Register Rn, Register Rm, Register Ra) {       \
1776     data_processing(op54, op31, o0, Rd, Rn, Rm, Ra);                    \
1777   }
1778 
1779   INSN(maddw, 0b000, 0b000, 0);
1780   INSN(msubw, 0b000, 0b000, 1);
1781   INSN(madd, 0b100, 0b000, 0);
1782   INSN(msub, 0b100, 0b000, 1);
1783   INSN(smaddl, 0b100, 0b001, 0);
1784   INSN(smsubl, 0b100, 0b001, 1);
1785   INSN(umaddl, 0b100, 0b101, 0);
1786   INSN(umsubl, 0b100, 0b101, 1);
1787 
1788 #undef INSN
1789 
1790 #define INSN(NAME, op54, op31, o0)                      \
1791   void NAME(Register Rd, Register Rn, Register Rm) {    \
1792     data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31);  \
1793   }
1794 
1795   INSN(smulh, 0b100, 0b010, 0);
1796   INSN(umulh, 0b100, 0b110, 0);
1797 
1798 #undef INSN
1799 
1800   // Floating-point data-processing (1 source)
1801   void data_processing(unsigned op31, unsigned type, unsigned opcode,
1802                        FloatRegister Vd, FloatRegister Vn) {
1803     starti;
1804     f(op31, 31, 29);
1805     f(0b11110, 28, 24);
1806     f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1807     rf(Vn, 5), rf(Vd, 0);
1808   }
1809 
1810 #define INSN(NAME, op31, type, opcode)                  \
1811   void NAME(FloatRegister Vd, FloatRegister Vn) {       \
1812     data_processing(op31, type, opcode, Vd, Vn);        \
1813   }
1814 
1815 private:
1816   INSN(i_fmovs, 0b000, 0b00, 0b000000);
1817 public:
1818   INSN(fabss, 0b000, 0b00, 0b000001);
1819   INSN(fnegs, 0b000, 0b00, 0b000010);
1820   INSN(fsqrts, 0b000, 0b00, 0b000011);
1821   INSN(fcvts, 0b000, 0b00, 0b000101);   // Single-precision to double-precision
1822 
1823 private:
1824   INSN(i_fmovd, 0b000, 0b01, 0b000000);
1825 public:
1826   INSN(fabsd, 0b000, 0b01, 0b000001);
1827   INSN(fnegd, 0b000, 0b01, 0b000010);
1828   INSN(fsqrtd, 0b000, 0b01, 0b000011);
1829   INSN(fcvtd, 0b000, 0b01, 0b000100);   // Double-precision to single-precision
1830 
1831   void fmovd(FloatRegister Vd, FloatRegister Vn) {
1832     assert(Vd != Vn, "should be");
1833     i_fmovd(Vd, Vn);
1834   }
1835 
1836   void fmovs(FloatRegister Vd, FloatRegister Vn) {
1837     assert(Vd != Vn, "should be");
1838     i_fmovs(Vd, Vn);
1839   }
1840 
1841 #undef INSN
1842 
1843   // Floating-point data-processing (2 source)
1844   void data_processing(unsigned op31, unsigned type, unsigned opcode,
1845                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1846     starti;
1847     f(op31, 31, 29);
1848     f(0b11110, 28, 24);
1849     f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1850     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1851   }
1852 
1853 #define INSN(NAME, op31, type, opcode)                  \
1854   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {     \
1855     data_processing(op31, type, opcode, Vd, Vn, Vm);    \
1856   }
1857 
1858   INSN(fmuls, 0b000, 0b00, 0b0000);
1859   INSN(fdivs, 0b000, 0b00, 0b0001);
1860   INSN(fadds, 0b000, 0b00, 0b0010);
1861   INSN(fsubs, 0b000, 0b00, 0b0011);
1862   INSN(fmaxs, 0b000, 0b00, 0b0100);
1863   INSN(fmins, 0b000, 0b00, 0b0101);
1864   INSN(fnmuls, 0b000, 0b00, 0b1000);
1865 
1866   INSN(fmuld, 0b000, 0b01, 0b0000);
1867   INSN(fdivd, 0b000, 0b01, 0b0001);
1868   INSN(faddd, 0b000, 0b01, 0b0010);
1869   INSN(fsubd, 0b000, 0b01, 0b0011);
1870   INSN(fmaxd, 0b000, 0b01, 0b0100);
1871   INSN(fmind, 0b000, 0b01, 0b0101);
1872   INSN(fnmuld, 0b000, 0b01, 0b1000);
1873 
1874 #undef INSN
1875 
1876    // Floating-point data-processing (3 source)
1877   void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1878                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1879                        FloatRegister Va) {
1880     starti;
1881     f(op31, 31, 29);
1882     f(0b11111, 28, 24);
1883     f(type, 23, 22), f(o1, 21), f(o0, 15);
1884     rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1885   }
1886 
1887 #define INSN(NAME, op31, type, o1, o0)                                  \
1888   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,       \
1889             FloatRegister Va) {                                         \
1890     data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va);                \
1891   }
1892 
1893   INSN(fmadds, 0b000, 0b00, 0, 0);
1894   INSN(fmsubs, 0b000, 0b00, 0, 1);
1895   INSN(fnmadds, 0b000, 0b00, 1, 0);
1896   INSN(fnmsubs, 0b000, 0b00, 1, 1);
1897 
1898   INSN(fmaddd, 0b000, 0b01, 0, 0);
1899   INSN(fmsubd, 0b000, 0b01, 0, 1);
1900   INSN(fnmaddd, 0b000, 0b01, 1, 0);
1901   INSN(fnmsub, 0b000, 0b01, 1, 1);
1902 
1903 #undef INSN
1904 
1905    // Floating-point conditional select
1906   void fp_conditional_select(unsigned op31, unsigned type,
1907                              unsigned op1, unsigned op2,
1908                              Condition cond, FloatRegister Vd,
1909                              FloatRegister Vn, FloatRegister Vm) {
1910     starti;
1911     f(op31, 31, 29);
1912     f(0b11110, 28, 24);
1913     f(type, 23, 22);
1914     f(op1, 21, 21);
1915     f(op2, 11, 10);
1916     f(cond, 15, 12);
1917     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1918   }
1919 
1920 #define INSN(NAME, op31, type, op1, op2)                                \
1921   void NAME(FloatRegister Vd, FloatRegister Vn,                         \
1922             FloatRegister Vm, Condition cond) {                         \
1923     fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm);      \
1924   }
1925 
1926   INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1927   INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1928 
1929 #undef INSN
1930 
1931    // Floating-point<->integer conversions
1932   void float_int_convert(unsigned op31, unsigned type,
1933                          unsigned rmode, unsigned opcode,
1934                          Register Rd, Register Rn) {
1935     starti;
1936     f(op31, 31, 29);
1937     f(0b11110, 28, 24);
1938     f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1939     f(opcode, 18, 16), f(0b000000, 15, 10);
1940     zrf(Rn, 5), zrf(Rd, 0);
1941   }
1942 
1943 #define INSN(NAME, op31, type, rmode, opcode)                           \
1944   void NAME(Register Rd, FloatRegister Vn) {                            \
1945     float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn);     \
1946   }
1947 
1948   INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1949   INSN(fcvtzs,  0b100, 0b00, 0b11, 0b000);
1950   INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1951   INSN(fcvtzd,  0b100, 0b01, 0b11, 0b000);
1952 
1953   INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1954   INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1955 
1956   // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1957 
1958 #undef INSN
1959 
1960 #define INSN(NAME, op31, type, rmode, opcode)                           \
1961   void NAME(FloatRegister Vd, Register Rn) {                            \
1962     float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn);     \
1963   }
1964 
1965   INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1966   INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1967 
1968   INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1969   INSN(scvtfs,  0b100, 0b00, 0b00, 0b010);
1970   INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1971   INSN(scvtfd,  0b100, 0b01, 0b00, 0b010);
1972 
1973   // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1974 
1975 #undef INSN
1976 
1977   // Floating-point compare
1978   void float_compare(unsigned op31, unsigned type,
1979                      unsigned op, unsigned op2,
1980                      FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1981     starti;
1982     f(op31, 31, 29);
1983     f(0b11110, 28, 24);
1984     f(type, 23, 22), f(1, 21);
1985     f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1986     rf(Vn, 5), rf(Vm, 16);
1987   }
1988 
1989 
1990 #define INSN(NAME, op31, type, op, op2)                 \
1991   void NAME(FloatRegister Vn, FloatRegister Vm) {       \
1992     float_compare(op31, type, op, op2, Vn, Vm);         \
1993   }
1994 
1995 #define INSN1(NAME, op31, type, op, op2)        \
1996   void NAME(FloatRegister Vn, double d) {       \
1997     assert_cond(d == 0.0);                      \
1998     float_compare(op31, type, op, op2, Vn);     \
1999   }
2000 
2001   INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
2002   INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
2003   // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
2004   // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
2005 
2006   INSN(fcmpd, 0b000,   0b01, 0b00, 0b00000);
2007   INSN1(fcmpd, 0b000,  0b01, 0b00, 0b01000);
2008   // INSN(fcmped, 0b000,  0b01, 0b00, 0b10000);
2009   // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
2010 
2011 #undef INSN
2012 #undef INSN1
2013 
2014   // Floating-point Move (immediate)
2015 private:
2016   unsigned pack(double value);
2017 
2018   void fmov_imm(FloatRegister Vn, double value, unsigned size) {
2019     starti;
2020     f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2021     f(pack(value), 20, 13), f(0b10000000, 12, 5);
2022     rf(Vn, 0);
2023   }
2024 
2025 public:
2026 
2027   void fmovs(FloatRegister Vn, double value) {
2028     if (value)
2029       fmov_imm(Vn, value, 0b00);
2030     else
2031       fmovs(Vn, zr);
2032   }
2033   void fmovd(FloatRegister Vn, double value) {
2034     if (value)
2035       fmov_imm(Vn, value, 0b01);
2036     else
2037       fmovd(Vn, zr);
2038   }
2039 
2040    // Floating-point rounding
2041    // type: half-precision = 11
2042    //       single         = 00
2043    //       double         = 01
2044    // rmode: A = Away     = 100
2045    //        I = current  = 111
2046    //        M = MinusInf = 010
2047    //        N = eveN     = 000
2048    //        P = PlusInf  = 001
2049    //        X = eXact    = 110
2050    //        Z = Zero     = 011
2051   void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) {
2052     starti;
2053     f(0b00011110, 31, 24);
2054     f(type, 23, 22);
2055     f(0b1001, 21, 18);
2056     f(rmode, 17, 15);
2057     f(0b10000, 14, 10);
2058     rf(Rn, 5), rf(Rd, 0);
2059   }
2060 #define INSN(NAME, type, rmode)                   \
2061   void NAME(FloatRegister Vd, FloatRegister Vn) { \
2062     float_round(type, rmode, Vd, Vn);             \
2063   }
2064 
2065 public:
2066   INSN(frintah, 0b11, 0b100);
2067   INSN(frintih, 0b11, 0b111);
2068   INSN(frintmh, 0b11, 0b010);
2069   INSN(frintnh, 0b11, 0b000);
2070   INSN(frintph, 0b11, 0b001);
2071   INSN(frintxh, 0b11, 0b110);
2072   INSN(frintzh, 0b11, 0b011);
2073 
2074   INSN(frintas, 0b00, 0b100);
2075   INSN(frintis, 0b00, 0b111);
2076   INSN(frintms, 0b00, 0b010);
2077   INSN(frintns, 0b00, 0b000);
2078   INSN(frintps, 0b00, 0b001);
2079   INSN(frintxs, 0b00, 0b110);
2080   INSN(frintzs, 0b00, 0b011);
2081 
2082   INSN(frintad, 0b01, 0b100);
2083   INSN(frintid, 0b01, 0b111);
2084   INSN(frintmd, 0b01, 0b010);
2085   INSN(frintnd, 0b01, 0b000);
2086   INSN(frintpd, 0b01, 0b001);
2087   INSN(frintxd, 0b01, 0b110);
2088   INSN(frintzd, 0b01, 0b011);
2089 #undef INSN
2090 
2091 /* SIMD extensions
2092  *
2093  * We just use FloatRegister in the following. They are exactly the same
2094  * as SIMD registers.
2095  */
2096  public:
2097 
2098   enum SIMD_Arrangement {
2099        T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
2100   };
2101 
2102   enum SIMD_RegVariant {
2103        B, H, S, D, Q
2104   };
2105 
2106 private:
2107   static short SIMD_Size_in_bytes[];
2108 
2109 public:
2110 #define INSN(NAME, op)                                            \
2111   void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) {   \
2112     ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2113   }                                                                      \
2114 
2115   INSN(ldr, 1);
2116   INSN(str, 0);
2117 
2118 #undef INSN
2119 
2120  private:
2121 
2122   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2123     starti;
2124     f(0,31), f((int)T & 1, 30);
2125     f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2126     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2127   }
2128   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2129              int imm, int op1, int op2, int regs) {
2130 
2131     bool replicate = op2 >> 2 == 3;
2132     // post-index value (imm) is formed differently for replicate/non-replicate ld* instructions
2133     int expectedImmediate = replicate ? regs * (1 << (T >> 1)) : SIMD_Size_in_bytes[T] * regs;
2134     guarantee(T < T1Q , "incorrect arrangement");
2135     guarantee(imm == expectedImmediate, "bad offset");
2136     starti;
2137     f(0,31), f((int)T & 1, 30);
2138     f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2139     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2140   }
2141   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2142              Register Xm, int op1, int op2) {
2143     starti;
2144     f(0,31), f((int)T & 1, 30);
2145     f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2146     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2147   }
2148 
2149   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
2150     switch (a.getMode()) {
2151     case Address::base_plus_offset:
2152       guarantee(a.offset() == 0, "no offset allowed here");
2153       ld_st(Vt, T, a.base(), op1, op2);
2154       break;
2155     case Address::post:
2156       ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
2157       break;
2158     case Address::post_reg:
2159       ld_st(Vt, T, a.base(), a.index(), op1, op2);
2160       break;
2161     default:
2162       ShouldNotReachHere();
2163     }
2164   }
2165 
2166  public:
2167 
2168 #define INSN1(NAME, op1, op2)                                           \
2169   void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) {   \
2170     ld_st(Vt, T, a, op1, op2, 1);                                       \
2171  }
2172 
2173 #define INSN2(NAME, op1, op2)                                           \
2174   void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2175     assert(Vt->successor() == Vt2, "Registers must be ordered");        \
2176     ld_st(Vt, T, a, op1, op2, 2);                                       \
2177   }
2178 
2179 #define INSN3(NAME, op1, op2)                                           \
2180   void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
2181             SIMD_Arrangement T, const Address &a) {                     \
2182     assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3,           \
2183            "Registers must be ordered");                                \
2184     ld_st(Vt, T, a, op1, op2, 3);                                       \
2185   }
2186 
2187 #define INSN4(NAME, op1, op2)                                           \
2188   void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
2189             FloatRegister Vt4, SIMD_Arrangement T, const Address &a) {  \
2190     assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 &&         \
2191            Vt3->successor() == Vt4, "Registers must be ordered");       \
2192     ld_st(Vt, T, a, op1, op2, 4);                                       \
2193   }
2194 
2195   INSN1(ld1,  0b001100010, 0b0111);
2196   INSN2(ld1,  0b001100010, 0b1010);
2197   INSN3(ld1,  0b001100010, 0b0110);
2198   INSN4(ld1,  0b001100010, 0b0010);
2199 
2200   INSN2(ld2,  0b001100010, 0b1000);
2201   INSN3(ld3,  0b001100010, 0b0100);
2202   INSN4(ld4,  0b001100010, 0b0000);
2203 
2204   INSN1(st1,  0b001100000, 0b0111);
2205   INSN2(st1,  0b001100000, 0b1010);
2206   INSN3(st1,  0b001100000, 0b0110);
2207   INSN4(st1,  0b001100000, 0b0010);
2208 
2209   INSN2(st2,  0b001100000, 0b1000);
2210   INSN3(st3,  0b001100000, 0b0100);
2211   INSN4(st4,  0b001100000, 0b0000);
2212 
2213   INSN1(ld1r, 0b001101010, 0b1100);
2214   INSN2(ld2r, 0b001101011, 0b1100);
2215   INSN3(ld3r, 0b001101010, 0b1110);
2216   INSN4(ld4r, 0b001101011, 0b1110);
2217 
2218 #undef INSN1
2219 #undef INSN2
2220 #undef INSN3
2221 #undef INSN4
2222 
2223 #define INSN(NAME, opc)                                                                 \
2224   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2225     starti;                                                                             \
2226     assert(T == T8B || T == T16B, "must be T8B or T16B");                               \
2227     f(0, 31), f((int)T & 1, 30), f(opc, 29, 21);                                        \
2228     rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0);                              \
2229   }
2230 
2231   INSN(eor,  0b101110001);
2232   INSN(orr,  0b001110101);
2233   INSN(andr, 0b001110001);
2234   INSN(bic,  0b001110011);
2235   INSN(bif,  0b101110111);
2236   INSN(bit,  0b101110101);
2237   INSN(bsl,  0b101110011);
2238   INSN(orn,  0b001110111);
2239 
2240 #undef INSN
2241 
2242 #define INSN(NAME, opc, opc2, acceptT2D)                                                \
2243   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2244     guarantee(T != T1Q && T != T1D, "incorrect arrangement");                           \
2245     if (!acceptT2D) guarantee(T != T2D, "incorrect arrangement");                       \
2246     starti;                                                                             \
2247     f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24);                        \
2248     f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10);                      \
2249     rf(Vn, 5), rf(Vd, 0);                                                               \
2250   }
2251 
2252   INSN(addv,   0, 0b100001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2253   INSN(subv,   1, 0b100001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2254   INSN(mulv,   0, 0b100111, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2255   INSN(mlav,   0, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2256   INSN(mlsv,   1, 0b100101, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2257   INSN(sshl,   0, 0b010001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2258   INSN(ushl,   1, 0b010001, true);  // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2259   INSN(umullv, 1, 0b110000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2260   INSN(umlalv, 1, 0b100000, false); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S
2261 
2262 #undef INSN
2263 
2264 #define INSN(NAME, opc, opc2, accepted) \
2265   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
2266     guarantee(T != T1Q && T != T1D, "incorrect arrangement");                           \
2267     if (accepted < 2) guarantee(T != T2S && T != T2D, "incorrect arrangement");         \
2268     if (accepted == 0) guarantee(T == T8B || T == T16B, "incorrect arrangement");       \
2269     starti;                                                                             \
2270     f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24);                        \
2271     f((int)T >> 1, 23, 22), f(opc2, 21, 10);                                            \
2272     rf(Vn, 5), rf(Vd, 0);                                                               \
2273   }
2274 
2275   INSN(absr,   0, 0b100000101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2276   INSN(negr,   1, 0b100000101110, 2); // accepted arrangements: T8B, T16B, T4H, T8H, T2S, T4S, T2D
2277   INSN(notr,   1, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2278   INSN(addv,   0, 0b110001101110, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2279   INSN(cls,    0, 0b100000010010, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2280   INSN(clz,    1, 0b100000010010, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2281   INSN(cnt,    0, 0b100000010110, 0); // accepted arrangements: T8B, T16B
2282   INSN(uaddlv, 1, 0b110000001110, 1); // accepted arrangements: T8B, T16B, T4H, T8H,      T4S
2283 
2284 #undef INSN
2285 
2286 #define INSN(NAME, opc) \
2287   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                  \
2288     starti;                                                                            \
2289     assert(T == T4S, "arrangement must be T4S");                                       \
2290     f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23),                      \
2291     f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0);          \
2292   }
2293 
2294   INSN(fmaxv, 0);
2295   INSN(fminv, 1);
2296 
2297 #undef INSN
2298 
2299 #define INSN(NAME, op0, cmode0) \
2300   void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) {   \
2301     unsigned cmode = cmode0;                                                           \
2302     unsigned op = op0;                                                                 \
2303     starti;                                                                            \
2304     assert(lsl == 0 ||                                                                 \
2305            ((T == T4H || T == T8H) && lsl == 8) ||                                     \
2306            ((T == T2S || T == T4S) && ((lsl >> 3) < 4) && ((lsl & 7) == 0)), "invalid shift");\
2307     cmode |= lsl >> 2;                                                                 \
2308     if (T == T4H || T == T8H) cmode |= 0b1000;                                         \
2309     if (!(T == T4H || T == T8H || T == T2S || T == T4S)) {                             \
2310       assert(op == 0 && cmode0 == 0, "must be MOVI");                                  \
2311       cmode = 0b1110;                                                                  \
2312       if (T == T1D || T == T2D) op = 1;                                                \
2313     }                                                                                  \
2314     f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19);                   \
2315     f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5);  \
2316     rf(Vd, 0);                                                                         \
2317   }
2318 
2319   INSN(movi, 0, 0);
2320   INSN(orri, 0, 1);
2321   INSN(mvni, 1, 0);
2322   INSN(bici, 1, 1);
2323 
2324 #undef INSN
2325 
2326 #define INSN(NAME, op1, op2, op3) \
2327   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2328     starti;                                                                             \
2329     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");                    \
2330     f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23);            \
2331     f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0);    \
2332   }
2333 
2334   INSN(fadd, 0, 0, 0b110101);
2335   INSN(fdiv, 1, 0, 0b111111);
2336   INSN(fmul, 1, 0, 0b110111);
2337   INSN(fsub, 0, 1, 0b110101);
2338   INSN(fmla, 0, 0, 0b110011);
2339   INSN(fmls, 0, 1, 0b110011);
2340   INSN(fmax, 0, 0, 0b111101);
2341   INSN(fmin, 0, 1, 0b111101);
2342 
2343 #undef INSN
2344 
2345 #define INSN(NAME, opc)                                                                 \
2346   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2347     starti;                                                                             \
2348     assert(T == T4S, "arrangement must be T4S");                                        \
2349     f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);         \
2350   }
2351 
2352   INSN(sha1c,     0b000000);
2353   INSN(sha1m,     0b001000);
2354   INSN(sha1p,     0b000100);
2355   INSN(sha1su0,   0b001100);
2356   INSN(sha256h2,  0b010100);
2357   INSN(sha256h,   0b010000);
2358   INSN(sha256su1, 0b011000);
2359 
2360 #undef INSN
2361 
2362 #define INSN(NAME, opc)                                                                 \
2363   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
2364     starti;                                                                             \
2365     assert(T == T4S, "arrangement must be T4S");                                        \
2366     f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);                \
2367   }
2368 
2369   INSN(sha1h,     0b000010);
2370   INSN(sha1su1,   0b000110);
2371   INSN(sha256su0, 0b001010);
2372 
2373 #undef INSN
2374 
2375 #define INSN(NAME, opc)                           \
2376   void NAME(FloatRegister Vd, FloatRegister Vn) { \
2377     starti;                                       \
2378     f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0);         \
2379   }
2380 
2381   INSN(aese, 0b0100111000101000010010);
2382   INSN(aesd, 0b0100111000101000010110);
2383   INSN(aesmc, 0b0100111000101000011010);
2384   INSN(aesimc, 0b0100111000101000011110);
2385 
2386 #undef INSN
2387 
2388 #define INSN(NAME, op1, op2) \
2389   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2390     starti;                                                                                            \
2391     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");                                   \
2392     assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index");     \
2393     f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23);                                      \
2394     f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16);                              \
2395     f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10);                                  \
2396     rf(Vn, 5), rf(Vd, 0);                                                                              \
2397   }
2398 
2399   // FMLA/FMLS - Vector - Scalar
2400   INSN(fmlavs, 0, 0b0001);
2401   INSN(fmlsvs, 0, 0b0101);
2402   // FMULX - Vector - Scalar
2403   INSN(fmulxvs, 1, 0b1001);
2404 
2405 #undef INSN
2406 
2407   // Floating-point Reciprocal Estimate
2408   void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2409     assert(type == D || type == S, "Wrong type for frecpe");
2410     starti;
2411     f(0b010111101, 31, 23);
2412     f(type == D ? 1 : 0, 22);
2413     f(0b100001110110, 21, 10);
2414     rf(Vn, 5), rf(Vd, 0);
2415   }
2416 
2417   // (double) {a, b} -> (a + b)
2418   void faddpd(FloatRegister Vd, FloatRegister Vn) {
2419     starti;
2420     f(0b0111111001110000110110, 31, 10);
2421     rf(Vn, 5), rf(Vd, 0);
2422   }
2423 
2424   void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2425     starti;
2426     assert(T != Q, "invalid register variant");
2427     f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2428     f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2429   }
2430 
2431   void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2432     starti;
2433     f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2434     f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2435     rf(Vn, 5), rf(Rd, 0);
2436   }
2437 
2438 #define INSN(NAME, opc, opc2, isSHR)                                    \
2439   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2440     starti;                                                             \
2441     /* The encodings for the immh:immb fields (bits 22:16) in *SHR are  \
2442      *   0001 xxx       8B/16B, shift = 16  - UInt(immh:immb)           \
2443      *   001x xxx       4H/8H,  shift = 32  - UInt(immh:immb)           \
2444      *   01xx xxx       2S/4S,  shift = 64  - UInt(immh:immb)           \
2445      *   1xxx xxx       1D/2D,  shift = 128 - UInt(immh:immb)           \
2446      *   (1D is RESERVED)                                               \
2447      * for SHL shift is calculated as:                                  \
2448      *   0001 xxx       8B/16B, shift = UInt(immh:immb) - 8             \
2449      *   001x xxx       4H/8H,  shift = UInt(immh:immb) - 16            \
2450      *   01xx xxx       2S/4S,  shift = UInt(immh:immb) - 32            \
2451      *   1xxx xxx       1D/2D,  shift = UInt(immh:immb) - 64            \
2452      *   (1D is RESERVED)                                               \
2453      */                                                                 \
2454     assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value");           \
2455     int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0)));               \
2456     int encodedShift = isSHR ? cVal - shift : cVal + shift;             \
2457     f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23),            \
2458     f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0);     \
2459   }
2460 
2461   INSN(shl,  0, 0b010101, /* isSHR = */ false);
2462   INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2463   INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2464 
2465 #undef INSN
2466 
2467 private:
2468   void _ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2469     starti;
2470     /* The encodings for the immh:immb fields (bits 22:16) are
2471      *   0001 xxx       8H, 8B/16b shift = xxx
2472      *   001x xxx       4S, 4H/8H  shift = xxxx
2473      *   01xx xxx       2D, 2S/4S  shift = xxxxx
2474      *   1xxx xxx       RESERVED
2475      */
2476     assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2477     assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2478     f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2479     f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2480   }
2481 
2482 public:
2483   void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
2484     assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
2485     _ushll(Vd, Ta, Vn, Tb, shift);
2486   }
2487 
2488   void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
2489     assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
2490     _ushll(Vd, Ta, Vn, Tb, shift);
2491   }
2492 
2493   // Move from general purpose register
2494   //   mov  Vd.T[index], Rn
2495   void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2496     starti;
2497     f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2498     f(0b000111, 15, 10), zrf(Xn, 5), rf(Vd, 0);
2499   }
2500 
2501   // Move to general purpose register
2502   //   mov  Rd, Vn.T[index]
2503   void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2504     guarantee(T >= T2S && T < T1Q, "only D and S arrangements are supported");
2505     starti;
2506     f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2507     f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2508     f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2509   }
2510 
2511 private:
2512   void _pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2513     starti;
2514     assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2515            (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2516     int size = (Ta == T1Q) ? 0b11 : 0b00;
2517     f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2518     f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2519   }
2520 
2521 public:
2522   void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2523     assert(Tb == T1D || Tb == T8B, "pmull assumes T1D or T8B as the second size specifier");
2524     _pmull(Vd, Ta, Vn, Vm, Tb);
2525   }
2526 
2527   void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2528     assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2529     _pmull(Vd, Ta, Vn, Vm, Tb);
2530   }
2531 
2532   void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2533     starti;
2534     int size_b = (int)Tb >> 1;
2535     int size_a = (int)Ta >> 1;
2536     assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2537     f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2538     f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2539   }
2540 
2541   void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2542   {
2543     starti;
2544     assert(T != T1D, "reserved encoding");
2545     f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2546     f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), zrf(Xs, 5), rf(Vd, 0);
2547   }
2548 
2549   void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2550   {
2551     starti;
2552     assert(T != T1D, "reserved encoding");
2553     f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2554     f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2555     f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2556   }
2557 
2558   // AdvSIMD ZIP/UZP/TRN
2559 #define INSN(NAME, opcode)                                              \
2560   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2561     guarantee(T != T1D && T != T1Q, "invalid arrangement");             \
2562     starti;                                                             \
2563     f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15);                  \
2564     f(opcode, 14, 12), f(0b10, 11, 10);                                 \
2565     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);                                   \
2566     f(T & 1, 30), f(T >> 1, 23, 22);                                    \
2567   }
2568 
2569   INSN(uzp1, 0b001);
2570   INSN(trn1, 0b010);
2571   INSN(zip1, 0b011);
2572   INSN(uzp2, 0b101);
2573   INSN(trn2, 0b110);
2574   INSN(zip2, 0b111);
2575 
2576 #undef INSN
2577 
2578   // CRC32 instructions
2579 #define INSN(NAME, c, sf, sz)                                             \
2580   void NAME(Register Rd, Register Rn, Register Rm) {                      \
2581     starti;                                                               \
2582     f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12);       \
2583     f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0);                      \
2584   }
2585 
2586   INSN(crc32b,  0, 0, 0b00);
2587   INSN(crc32h,  0, 0, 0b01);
2588   INSN(crc32w,  0, 0, 0b10);
2589   INSN(crc32x,  0, 1, 0b11);
2590   INSN(crc32cb, 1, 0, 0b00);
2591   INSN(crc32ch, 1, 0, 0b01);
2592   INSN(crc32cw, 1, 0, 0b10);
2593   INSN(crc32cx, 1, 1, 0b11);
2594 
2595 #undef INSN
2596 
2597   // Table vector lookup
2598 #define INSN(NAME, op)                                                  \
2599   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2600     starti;                                                             \
2601     assert(T == T8B || T == T16B, "invalid arrangement");               \
2602     assert(0 < registers && registers <= 4, "invalid number of registers"); \
2603     f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2604     f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2605   }
2606 
2607   INSN(tbl, 0);
2608   INSN(tbx, 1);
2609 
2610 #undef INSN
2611 
2612   // AdvSIMD two-reg misc
2613 #define INSN(NAME, U, opcode)                                                       \
2614   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {               \
2615        starti;                                                                      \
2616        assert((ASSERTION), MSG);                                                    \
2617        f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24);                   \
2618        f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12);             \
2619        f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0);                                       \
2620  }
2621 
2622 #define MSG "invalid arrangement"
2623 
2624 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2625   INSN(fsqrt, 1, 0b11111);
2626   INSN(fabs,  0, 0b01111);
2627   INSN(fneg,  1, 0b01111);
2628 #undef ASSERTION
2629 
2630 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2631   INSN(rev64, 0, 0b00000);
2632 #undef ASSERTION
2633 
2634 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2635   INSN(rev32, 1, 0b00000);
2636 private:
2637   INSN(_rbit, 1, 0b00101);
2638 public:
2639 
2640 #undef ASSERTION
2641 
2642 #define ASSERTION (T == T8B || T == T16B)
2643   INSN(rev16, 0, 0b00001);
2644   // RBIT only allows T8B and T16B but encodes them oddly.  Argh...
2645   void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
2646     assert((ASSERTION), MSG);
2647     _rbit(Vd, SIMD_Arrangement((T & 1) | 0b010), Vn);
2648   }
2649 #undef ASSERTION
2650 
2651 #undef MSG
2652 
2653 #undef INSN
2654 
2655 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2656   {
2657     starti;
2658     assert(T == T8B || T == T16B, "invalid arrangement");
2659     assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2660     f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2661     rf(Vm, 16), f(0, 15), f(index, 14, 11);
2662     f(0, 10), rf(Vn, 5), rf(Vd, 0);
2663   }
2664 
2665 /* Simulator extensions to the ISA
2666 
2667    haltsim
2668 
2669    takes no arguments, causes the sim to enter a debug break and then
2670    return from the simulator run() call with STATUS_HALT? The linking
2671    code will call fatal() when it sees STATUS_HALT.
2672 
2673    blrt Xn, Wm
2674    blrt Xn, #gpargs, #fpargs, #type
2675    Xn holds the 64 bit x86 branch_address
2676    call format is encoded either as immediate data in the call
2677    or in register Wm. In the latter case
2678      Wm[13..6] = #gpargs,
2679      Wm[5..2] = #fpargs,
2680      Wm[1,0] = #type
2681 
2682    calls the x86 code address 'branch_address' supplied in Xn passing
2683    arguments taken from the general and floating point registers according
2684    to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0
2685    or v0 according to the the return type #type' where
2686 
2687    address branch_address;
2688    uimm4 gpargs;
2689    uimm4 fpargs;
2690    enum ReturnType type;
2691 
2692    enum ReturnType
2693      {
2694        void_ret = 0,
2695        int_ret = 1,
2696        long_ret = 1,
2697        obj_ret = 1, // i.e. same as long
2698        float_ret = 2,
2699        double_ret = 3
2700      }
2701 
2702    notify
2703 
2704    notifies the simulator of a transfer of control. instr[14:0]
2705    identifies the type of change of control.
2706 
2707    0 ==> initial entry to a method.
2708 
2709    1 ==> return into a method from a submethod call.
2710 
2711    2 ==> exit out of Java method code.
2712 
2713    3 ==> start execution for a new bytecode.
2714 
2715    in cases 1 and 2 the simulator is expected to use a JVM callback to
2716    identify the name of the specific method being executed. in case 4
2717    the simulator is expected to use a JVM callback to identify the
2718    bytecode index.
2719 
2720    Instruction encodings
2721    ---------------------
2722 
2723    These are encoded in the space with instr[28:25] = 00 which is
2724    unallocated. Encodings are
2725 
2726                      10987654321098765432109876543210
2727    PSEUDO_HALT   = 0x11100000000000000000000000000000
2728    PSEUDO_BLRT  = 0x11000000000000000_______________
2729    PSEUDO_BLRTR = 0x1100000000000000100000__________
2730    PSEUDO_NOTIFY = 0x10100000000000000_______________
2731 
2732    instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY
2733 
2734    for BLRT
2735      instr[14,11] = #gpargs, instr[10,7] = #fpargs
2736      instr[6,5] = #type, instr[4,0] = Rn
2737    for BLRTR
2738      instr[9,5] = Rm, instr[4,0] = Rn
2739    for NOTIFY
2740      instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart
2741 */
2742 
2743   enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start };
2744 
2745   virtual void notify(int type) {
2746     if (UseBuiltinSim) {
2747       starti;
2748       //  109
2749       f(0b101, 31, 29);
2750       //  87654321098765
2751       f(0b00000000000000, 28, 15);
2752       f(type, 14, 0);
2753     }
2754   }
2755 
2756   void blrt(Register Rn, int gpargs, int fpargs, int type) {
2757     if (UseBuiltinSim) {
2758       starti;
2759       f(0b110, 31 ,29);
2760       f(0b00, 28, 25);
2761       //  4321098765
2762       f(0b0000000000, 24, 15);
2763       f(gpargs, 14, 11);
2764       f(fpargs, 10, 7);
2765       f(type, 6, 5);
2766       rf(Rn, 0);
2767     } else {
2768       blr(Rn);
2769     }
2770   }
2771 
2772   void blrt(Register Rn, Register Rm) {
2773     if (UseBuiltinSim) {
2774       starti;
2775       f(0b110, 31 ,29);
2776       f(0b00, 28, 25);
2777       //  4321098765
2778       f(0b0000000001, 24, 15);
2779       //  43210
2780       f(0b00000, 14, 10);
2781       rf(Rm, 5);
2782       rf(Rn, 0);
2783     } else {
2784       blr(Rn);
2785     }
2786   }
2787 
2788   void haltsim() {
2789     starti;
2790     f(0b111, 31 ,29);
2791     f(0b00, 28, 27);
2792     //  654321098765432109876543210
2793     f(0b000000000000000000000000000, 26, 0);
2794   }
2795 
2796   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2797   }
2798 
2799   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2800                                                 Register tmp,
2801                                                 int offset) {
2802     ShouldNotCallThis();
2803     return RegisterOrConstant();
2804   }
2805 
2806   // Stack overflow checking
2807   virtual void bang_stack_with_offset(int offset);
2808 
2809   static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2810   static bool operand_valid_for_add_sub_immediate(long imm);
2811   static bool operand_valid_for_float_immediate(double imm);
2812 
2813   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2814   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2815 };
2816 
2817 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2818                                              Assembler::Membar_mask_bits b) {
2819   return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2820 }
2821 
2822 Instruction_aarch64::~Instruction_aarch64() {
2823   assem->emit();
2824 }
2825 
2826 #undef starti
2827 
2828 // Invert a condition
2829 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2830   return Assembler::Condition(int(cond) ^ 1);
2831 }
2832 
2833 class BiasedLockingCounters;
2834 
2835 extern "C" void das(uint64_t start, int len);
2836 
2837 #endif // CPU_AARCH64_ASSEMBLER_AARCH64_HPP