1 /*
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   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
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  24  */
  25 
  26 #ifndef CPU_AARCH64_ASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_ASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/register.hpp"
  30 
  31 // definitions of various symbolic names for machine registers
  32 
  33 // First intercalls between C and Java which use 8 general registers
  34 // and 8 floating registers
  35 
  36 // we also have to copy between x86 and ARM registers but that's a
  37 // secondary complication -- not all code employing C call convention
  38 // executes as x86 code though -- we generate some of it
  39 
  40 class Argument {
  41  public:
  42   enum {
  43     n_int_register_parameters_c   = 8,  // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
  44     n_float_register_parameters_c = 8,  // v0, v1, ... v7 (c_farg0, c_farg1, ... )
  45 
  46     n_int_register_parameters_j   = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
  47     n_float_register_parameters_j = 8  // v0, v1, ... v7 (j_farg0, j_farg1, ...
  48   };
  49 };
  50 
  51 REGISTER_DECLARATION(Register, c_rarg0, r0);
  52 REGISTER_DECLARATION(Register, c_rarg1, r1);
  53 REGISTER_DECLARATION(Register, c_rarg2, r2);
  54 REGISTER_DECLARATION(Register, c_rarg3, r3);
  55 REGISTER_DECLARATION(Register, c_rarg4, r4);
  56 REGISTER_DECLARATION(Register, c_rarg5, r5);
  57 REGISTER_DECLARATION(Register, c_rarg6, r6);
  58 REGISTER_DECLARATION(Register, c_rarg7, r7);
  59 
  60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
  61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
  62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
  63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
  64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
  65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
  66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
  67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
  68 
  69 // Symbolically name the register arguments used by the Java calling convention.
  70 // We have control over the convention for java so we can do what we please.
  71 // What pleases us is to offset the java calling convention so that when
  72 // we call a suitable jni method the arguments are lined up and we don't
  73 // have to do much shuffling. A suitable jni method is non-static and a
  74 // small number of arguments
  75 //
  76 //  |--------------------------------------------------------------------|
  77 //  | c_rarg0  c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7  |
  78 //  |--------------------------------------------------------------------|
  79 //  | r0       r1       r2      r3      r4      r5      r6      r7       |
  80 //  |--------------------------------------------------------------------|
  81 //  | j_rarg7  j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6  |
  82 //  |--------------------------------------------------------------------|
  83 
  84 
  85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
  86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
  87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
  88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
  89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
  90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
  91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
  92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
  93 
  94 // Java floating args are passed as per C
  95 
  96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
  97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
  98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
  99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
 100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
 101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
 102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
 103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
 104 
 105 // registers used to hold VM data either temporarily within a method
 106 // or across method calls
 107 
 108 // volatile (caller-save) registers
 109 
 110 // r8 is used for indirect result location return
 111 // we use it and r9 as scratch registers
 112 REGISTER_DECLARATION(Register, rscratch1, r8);
 113 REGISTER_DECLARATION(Register, rscratch2, r9);
 114 
 115 // current method -- must be in a call-clobbered register
 116 REGISTER_DECLARATION(Register, rmethod,   r12);
 117 
 118 // non-volatile (callee-save) registers are r16-29
 119 // of which the following are dedicated global state
 120 
 121 // link register
 122 REGISTER_DECLARATION(Register, lr,        r30);
 123 // frame pointer
 124 REGISTER_DECLARATION(Register, rfp,       r29);
 125 // current thread
 126 REGISTER_DECLARATION(Register, rthread,   r28);
 127 // base of heap
 128 REGISTER_DECLARATION(Register, rheapbase, r27);
 129 // constant pool cache
 130 REGISTER_DECLARATION(Register, rcpool,    r26);
 131 // monitors allocated on stack
 132 REGISTER_DECLARATION(Register, rmonitors, r25);
 133 // locals on stack
 134 REGISTER_DECLARATION(Register, rlocals,   r24);
 135 // bytecode pointer
 136 REGISTER_DECLARATION(Register, rbcp,      r22);
 137 // Dispatch table base
 138 REGISTER_DECLARATION(Register, rdispatch, r21);
 139 // Java stack pointer
 140 REGISTER_DECLARATION(Register, esp,      r20);
 141 
 142 #define assert_cond(ARG1) assert(ARG1, #ARG1)
 143 
 144 namespace asm_util {
 145   uint32_t encode_logical_immediate(bool is32, uint64_t imm);
 146 };
 147 
 148 using namespace asm_util;
 149 
 150 
 151 class Assembler;
 152 
 153 class Instruction_aarch64 {
 154   unsigned insn;
 155 #ifdef ASSERT
 156   unsigned bits;
 157 #endif
 158   Assembler *assem;
 159 
 160 public:
 161 
 162   Instruction_aarch64(class Assembler *as) {
 163 #ifdef ASSERT
 164     bits = 0;
 165 #endif
 166     insn = 0;
 167     assem = as;
 168   }
 169 
 170   inline ~Instruction_aarch64();
 171 
 172   unsigned &get_insn() { return insn; }
 173 #ifdef ASSERT
 174   unsigned &get_bits() { return bits; }
 175 #endif
 176 
 177   static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
 178     union {
 179       unsigned u;
 180       int n;
 181     };
 182 
 183     u = val << (31 - hi);
 184     n = n >> (31 - hi + lo);
 185     return n;
 186   }
 187 
 188   static inline uint32_t extract(uint32_t val, int msb, int lsb) {
 189     int nbits = msb - lsb + 1;
 190     assert_cond(msb >= lsb);
 191     uint32_t mask = (1U << nbits) - 1;
 192     uint32_t result = val >> lsb;
 193     result &= mask;
 194     return result;
 195   }
 196 
 197   static inline int32_t sextract(uint32_t val, int msb, int lsb) {
 198     uint32_t uval = extract(val, msb, lsb);
 199     return extend(uval, msb - lsb);
 200   }
 201 
 202   static void patch(address a, int msb, int lsb, unsigned long val) {
 203     int nbits = msb - lsb + 1;
 204     guarantee(val < (1U << nbits), "Field too big for insn");
 205     assert_cond(msb >= lsb);
 206     unsigned mask = (1U << nbits) - 1;
 207     val <<= lsb;
 208     mask <<= lsb;
 209     unsigned target = *(unsigned *)a;
 210     target &= ~mask;
 211     target |= val;
 212     *(unsigned *)a = target;
 213   }
 214 
 215   static void spatch(address a, int msb, int lsb, long val) {
 216     int nbits = msb - lsb + 1;
 217     long chk = val >> (nbits - 1);
 218     guarantee (chk == -1 || chk == 0, "Field too big for insn");
 219     unsigned uval = val;
 220     unsigned mask = (1U << nbits) - 1;
 221     uval &= mask;
 222     uval <<= lsb;
 223     mask <<= lsb;
 224     unsigned target = *(unsigned *)a;
 225     target &= ~mask;
 226     target |= uval;
 227     *(unsigned *)a = target;
 228   }
 229 
 230   void f(unsigned val, int msb, int lsb) {
 231     int nbits = msb - lsb + 1;
 232     guarantee(val < (1U << nbits), "Field too big for insn");
 233     assert_cond(msb >= lsb);
 234     unsigned mask = (1U << nbits) - 1;
 235     val <<= lsb;
 236     mask <<= lsb;
 237     insn |= val;
 238     assert_cond((bits & mask) == 0);
 239 #ifdef ASSERT
 240     bits |= mask;
 241 #endif
 242   }
 243 
 244   void f(unsigned val, int bit) {
 245     f(val, bit, bit);
 246   }
 247 
 248   void sf(long val, int msb, int lsb) {
 249     int nbits = msb - lsb + 1;
 250     long chk = val >> (nbits - 1);
 251     guarantee (chk == -1 || chk == 0, "Field too big for insn");
 252     unsigned uval = val;
 253     unsigned mask = (1U << nbits) - 1;
 254     uval &= mask;
 255     f(uval, lsb + nbits - 1, lsb);
 256   }
 257 
 258   void rf(Register r, int lsb) {
 259     f(r->encoding_nocheck(), lsb + 4, lsb);
 260   }
 261 
 262   // reg|ZR
 263   void zrf(Register r, int lsb) {
 264     f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
 265   }
 266 
 267   // reg|SP
 268   void srf(Register r, int lsb) {
 269     f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
 270   }
 271 
 272   void rf(FloatRegister r, int lsb) {
 273     f(r->encoding_nocheck(), lsb + 4, lsb);
 274   }
 275 
 276   unsigned get(int msb = 31, int lsb = 0) {
 277     int nbits = msb - lsb + 1;
 278     unsigned mask = ((1U << nbits) - 1) << lsb;
 279     assert_cond(bits & mask == mask);
 280     return (insn & mask) >> lsb;
 281   }
 282 
 283   void fixed(unsigned value, unsigned mask) {
 284     assert_cond ((mask & bits) == 0);
 285 #ifdef ASSERT
 286     bits |= mask;
 287 #endif
 288     insn |= value;
 289   }
 290 };
 291 
 292 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
 293 
 294 class PrePost {
 295   int _offset;
 296   Register _r;
 297 public:
 298   PrePost(Register reg, int o) : _offset(o), _r(reg) { }
 299   int offset() { return _offset; }
 300   Register reg() { return _r; }
 301 };
 302 
 303 class Pre : public PrePost {
 304 public:
 305   Pre(Register reg, int o) : PrePost(reg, o) { }
 306 };
 307 class Post : public PrePost {
 308   Register _idx;
 309 public:
 310   Post(Register reg, int o) : PrePost(reg, o) { _idx = NULL; }
 311   Post(Register reg, Register idx) : PrePost(reg, 0) { _idx = idx; }
 312   Register idx_reg() { return _idx; }
 313 };
 314 
 315 namespace ext
 316 {
 317   enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
 318 };
 319 
 320 // Addressing modes
 321 class Address {
 322  public:
 323 
 324   enum mode { no_mode, base_plus_offset, pre, post, post_reg, pcrel,
 325               base_plus_offset_reg, literal };
 326 
 327   // Shift and extend for base reg + reg offset addressing
 328   class extend {
 329     int _option, _shift;
 330     ext::operation _op;
 331   public:
 332     extend() { }
 333     extend(int s, int o, ext::operation op) : _option(o), _shift(s), _op(op) { }
 334     int option() const{ return _option; }
 335     int shift() const { return _shift; }
 336     ext::operation op() const { return _op; }
 337   };
 338   class uxtw : public extend {
 339   public:
 340     uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
 341   };
 342   class lsl : public extend {
 343   public:
 344     lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
 345   };
 346   class sxtw : public extend {
 347   public:
 348     sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
 349   };
 350   class sxtx : public extend {
 351   public:
 352     sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
 353   };
 354 
 355  private:
 356   Register _base;
 357   Register _index;
 358   long _offset;
 359   enum mode _mode;
 360   extend _ext;
 361 
 362   RelocationHolder _rspec;
 363 
 364   // Typically we use AddressLiterals we want to use their rval
 365   // However in some situations we want the lval (effect address) of
 366   // the item.  We provide a special factory for making those lvals.
 367   bool _is_lval;
 368 
 369   // If the target is far we'll need to load the ea of this to a
 370   // register to reach it. Otherwise if near we can do PC-relative
 371   // addressing.
 372   address          _target;
 373 
 374  public:
 375   Address()
 376     : _mode(no_mode) { }
 377   Address(Register r)
 378     : _base(r), _index(noreg), _offset(0), _mode(base_plus_offset), _target(0) { }
 379   Address(Register r, int o)
 380     : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
 381   Address(Register r, long o)
 382     : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
 383   Address(Register r, unsigned long o)
 384     : _base(r), _index(noreg), _offset(o), _mode(base_plus_offset), _target(0) { }
 385 #ifdef ASSERT
 386   Address(Register r, ByteSize disp)
 387     : _base(r), _index(noreg), _offset(in_bytes(disp)), _mode(base_plus_offset), _target(0) { }
 388 #endif
 389   Address(Register r, Register r1, extend ext = lsl())
 390     : _base(r), _index(r1), _offset(0), _mode(base_plus_offset_reg),
 391       _ext(ext), _target(0) { }
 392   Address(Pre p)
 393     : _base(p.reg()), _offset(p.offset()), _mode(pre) { }
 394   Address(Post p)
 395     : _base(p.reg()),  _index(p.idx_reg()), _offset(p.offset()),
 396       _mode(p.idx_reg() == NULL ? post : post_reg), _target(0) { }
 397   Address(address target, RelocationHolder const& rspec)
 398     : _mode(literal),
 399       _rspec(rspec),
 400       _is_lval(false),
 401       _target(target)  { }
 402   Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
 403   Address(Register base, RegisterOrConstant index, extend ext = lsl())
 404     : _base (base),
 405       _offset(0), _ext(ext), _target(0) {
 406     if (index.is_register()) {
 407       _mode = base_plus_offset_reg;
 408       _index = index.as_register();
 409     } else {
 410       guarantee(ext.option() == ext::uxtx, "should be");
 411       assert(index.is_constant(), "should be");
 412       _mode = base_plus_offset;
 413       _offset = index.as_constant() << ext.shift();
 414     }
 415   }
 416 
 417   Register base() const {
 418     guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
 419                | _mode == post | _mode == post_reg),
 420               "wrong mode");
 421     return _base;
 422   }
 423   long offset() const {
 424     return _offset;
 425   }
 426   Register index() const {
 427     return _index;
 428   }
 429   mode getMode() const {
 430     return _mode;
 431   }
 432   bool uses(Register reg) const { return _base == reg || _index == reg; }
 433   address target() const { return _target; }
 434   const RelocationHolder& rspec() const { return _rspec; }
 435 
 436   void encode(Instruction_aarch64 *i) const {
 437     i->f(0b111, 29, 27);
 438     i->srf(_base, 5);
 439 
 440     switch(_mode) {
 441     case base_plus_offset:
 442       {
 443         unsigned size = i->get(31, 30);
 444         if (i->get(26, 26) && i->get(23, 23)) {
 445           // SIMD Q Type - Size = 128 bits
 446           assert(size == 0, "bad size");
 447           size = 0b100;
 448         }
 449         unsigned mask = (1 << size) - 1;
 450         if (_offset < 0 || _offset & mask)
 451           {
 452             i->f(0b00, 25, 24);
 453             i->f(0, 21), i->f(0b00, 11, 10);
 454             i->sf(_offset, 20, 12);
 455           } else {
 456             i->f(0b01, 25, 24);
 457             i->f(_offset >> size, 21, 10);
 458           }
 459       }
 460       break;
 461 
 462     case base_plus_offset_reg:
 463       {
 464         i->f(0b00, 25, 24);
 465         i->f(1, 21);
 466         i->rf(_index, 16);
 467         i->f(_ext.option(), 15, 13);
 468         unsigned size = i->get(31, 30);
 469         if (i->get(26, 26) && i->get(23, 23)) {
 470           // SIMD Q Type - Size = 128 bits
 471           assert(size == 0, "bad size");
 472           size = 0b100;
 473         }
 474         if (size == 0) // It's a byte
 475           i->f(_ext.shift() >= 0, 12);
 476         else {
 477           if (_ext.shift() > 0)
 478             assert(_ext.shift() == (int)size, "bad shift");
 479           i->f(_ext.shift() > 0, 12);
 480         }
 481         i->f(0b10, 11, 10);
 482       }
 483       break;
 484 
 485     case pre:
 486       i->f(0b00, 25, 24);
 487       i->f(0, 21), i->f(0b11, 11, 10);
 488       i->sf(_offset, 20, 12);
 489       break;
 490 
 491     case post:
 492       i->f(0b00, 25, 24);
 493       i->f(0, 21), i->f(0b01, 11, 10);
 494       i->sf(_offset, 20, 12);
 495       break;
 496 
 497     default:
 498       ShouldNotReachHere();
 499     }
 500   }
 501 
 502   void encode_pair(Instruction_aarch64 *i) const {
 503     switch(_mode) {
 504     case base_plus_offset:
 505       i->f(0b010, 25, 23);
 506       break;
 507     case pre:
 508       i->f(0b011, 25, 23);
 509       break;
 510     case post:
 511       i->f(0b001, 25, 23);
 512       break;
 513     default:
 514       ShouldNotReachHere();
 515     }
 516 
 517     unsigned size; // Operand shift in 32-bit words
 518 
 519     if (i->get(26, 26)) { // float
 520       switch(i->get(31, 30)) {
 521       case 0b10:
 522         size = 2; break;
 523       case 0b01:
 524         size = 1; break;
 525       case 0b00:
 526         size = 0; break;
 527       default:
 528         ShouldNotReachHere();
 529         size = 0;  // unreachable
 530       }
 531     } else {
 532       size = i->get(31, 31);
 533     }
 534 
 535     size = 4 << size;
 536     guarantee(_offset % size == 0, "bad offset");
 537     i->sf(_offset / size, 21, 15);
 538     i->srf(_base, 5);
 539   }
 540 
 541   void encode_nontemporal_pair(Instruction_aarch64 *i) const {
 542     // Only base + offset is allowed
 543     i->f(0b000, 25, 23);
 544     unsigned size = i->get(31, 31);
 545     size = 4 << size;
 546     guarantee(_offset % size == 0, "bad offset");
 547     i->sf(_offset / size, 21, 15);
 548     i->srf(_base, 5);
 549     guarantee(_mode == Address::base_plus_offset,
 550               "Bad addressing mode for non-temporal op");
 551   }
 552 
 553   void lea(MacroAssembler *, Register) const;
 554 
 555   static bool offset_ok_for_immed(long offset, int shift = 0) {
 556     unsigned mask = (1 << shift) - 1;
 557     if (offset < 0 || offset & mask) {
 558       return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
 559     } else {
 560       return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
 561     }
 562   }
 563 };
 564 
 565 // Convience classes
 566 class RuntimeAddress: public Address {
 567 
 568   public:
 569 
 570   RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
 571 
 572 };
 573 
 574 class OopAddress: public Address {
 575 
 576   public:
 577 
 578   OopAddress(address target) : Address(target, relocInfo::oop_type){}
 579 
 580 };
 581 
 582 class ExternalAddress: public Address {
 583  private:
 584   static relocInfo::relocType reloc_for_target(address target) {
 585     // Sometimes ExternalAddress is used for values which aren't
 586     // exactly addresses, like the card table base.
 587     // external_word_type can't be used for values in the first page
 588     // so just skip the reloc in that case.
 589     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 590   }
 591 
 592  public:
 593 
 594   ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
 595 
 596 };
 597 
 598 class InternalAddress: public Address {
 599 
 600   public:
 601 
 602   InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
 603 };
 604 
 605 const int FPUStateSizeInWords = 32 * 2;
 606 typedef enum {
 607   PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
 608   PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
 609   PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
 610 } prfop;
 611 
 612 class Assembler : public AbstractAssembler {
 613 
 614 #ifndef PRODUCT
 615   static const unsigned long asm_bp;
 616 
 617   void emit_long(jint x) {
 618     if ((unsigned long)pc() == asm_bp)
 619       asm volatile ("nop");
 620     AbstractAssembler::emit_int32(x);
 621   }
 622 #else
 623   void emit_long(jint x) {
 624     AbstractAssembler::emit_int32(x);
 625   }
 626 #endif
 627 
 628 public:
 629 
 630   enum { instruction_size = 4 };
 631 
 632   //---<  calculate length of instruction  >---
 633   // We just use the values set above.
 634   // instruction must start at passed address
 635   static unsigned int instr_len(unsigned char *instr) { return instruction_size; }
 636 
 637   //---<  longest instructions  >---
 638   static unsigned int instr_maxlen() { return instruction_size; }
 639 
 640   Address adjust(Register base, int offset, bool preIncrement) {
 641     if (preIncrement)
 642       return Address(Pre(base, offset));
 643     else
 644       return Address(Post(base, offset));
 645   }
 646 
 647   Address pre(Register base, int offset) {
 648     return adjust(base, offset, true);
 649   }
 650 
 651   Address post(Register base, int offset) {
 652     return adjust(base, offset, false);
 653   }
 654 
 655   Address post(Register base, Register idx) {
 656     return Address(Post(base, idx));
 657   }
 658 
 659   Instruction_aarch64* current;
 660 
 661   void set_current(Instruction_aarch64* i) { current = i; }
 662 
 663   void f(unsigned val, int msb, int lsb) {
 664     current->f(val, msb, lsb);
 665   }
 666   void f(unsigned val, int msb) {
 667     current->f(val, msb, msb);
 668   }
 669   void sf(long val, int msb, int lsb) {
 670     current->sf(val, msb, lsb);
 671   }
 672   void rf(Register reg, int lsb) {
 673     current->rf(reg, lsb);
 674   }
 675   void srf(Register reg, int lsb) {
 676     current->srf(reg, lsb);
 677   }
 678   void zrf(Register reg, int lsb) {
 679     current->zrf(reg, lsb);
 680   }
 681   void rf(FloatRegister reg, int lsb) {
 682     current->rf(reg, lsb);
 683   }
 684   void fixed(unsigned value, unsigned mask) {
 685     current->fixed(value, mask);
 686   }
 687 
 688   void emit() {
 689     emit_long(current->get_insn());
 690     assert_cond(current->get_bits() == 0xffffffff);
 691     current = NULL;
 692   }
 693 
 694   typedef void (Assembler::* uncond_branch_insn)(address dest);
 695   typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
 696   typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
 697   typedef void (Assembler::* prefetch_insn)(address target, prfop);
 698 
 699   void wrap_label(Label &L, uncond_branch_insn insn);
 700   void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
 701   void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
 702   void wrap_label(Label &L, prfop, prefetch_insn insn);
 703 
 704   // PC-rel. addressing
 705 
 706   void adr(Register Rd, address dest);
 707   void _adrp(Register Rd, address dest);
 708 
 709   void adr(Register Rd, const Address &dest);
 710   void _adrp(Register Rd, const Address &dest);
 711 
 712   void adr(Register Rd, Label &L) {
 713     wrap_label(Rd, L, &Assembler::Assembler::adr);
 714   }
 715   void _adrp(Register Rd, Label &L) {
 716     wrap_label(Rd, L, &Assembler::_adrp);
 717   }
 718 
 719   void adrp(Register Rd, const Address &dest, unsigned long &offset);
 720 
 721 #undef INSN
 722 
 723   void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
 724                          int negated_op);
 725 
 726   // Add/subtract (immediate)
 727 #define INSN(NAME, decode, negated)                                     \
 728   void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) {   \
 729     starti;                                                             \
 730     f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
 731     zrf(Rd, 0), srf(Rn, 5);                                             \
 732   }                                                                     \
 733                                                                         \
 734   void NAME(Register Rd, Register Rn, unsigned imm) {                   \
 735     starti;                                                             \
 736     add_sub_immediate(Rd, Rn, imm, decode, negated);                    \
 737   }
 738 
 739   INSN(addsw, 0b001, 0b011);
 740   INSN(subsw, 0b011, 0b001);
 741   INSN(adds,  0b101, 0b111);
 742   INSN(subs,  0b111, 0b101);
 743 
 744 #undef INSN
 745 
 746 #define INSN(NAME, decode, negated)                     \
 747   void NAME(Register Rd, Register Rn, unsigned imm) {   \
 748     starti;                                             \
 749     add_sub_immediate(Rd, Rn, imm, decode, negated);    \
 750   }
 751 
 752   INSN(addw, 0b000, 0b010);
 753   INSN(subw, 0b010, 0b000);
 754   INSN(add,  0b100, 0b110);
 755   INSN(sub,  0b110, 0b100);
 756 
 757 #undef INSN
 758 
 759  // Logical (immediate)
 760 #define INSN(NAME, decode, is32)                                \
 761   void NAME(Register Rd, Register Rn, uint64_t imm) {           \
 762     starti;                                                     \
 763     uint32_t val = encode_logical_immediate(is32, imm);         \
 764     f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10);     \
 765     srf(Rd, 0), zrf(Rn, 5);                                     \
 766   }
 767 
 768   INSN(andw, 0b000, true);
 769   INSN(orrw, 0b001, true);
 770   INSN(eorw, 0b010, true);
 771   INSN(andr,  0b100, false);
 772   INSN(orr,  0b101, false);
 773   INSN(eor,  0b110, false);
 774 
 775 #undef INSN
 776 
 777 #define INSN(NAME, decode, is32)                                \
 778   void NAME(Register Rd, Register Rn, uint64_t imm) {           \
 779     starti;                                                     \
 780     uint32_t val = encode_logical_immediate(is32, imm);         \
 781     f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10);     \
 782     zrf(Rd, 0), zrf(Rn, 5);                                     \
 783   }
 784 
 785   INSN(ands, 0b111, false);
 786   INSN(andsw, 0b011, true);
 787 
 788 #undef INSN
 789 
 790   // Move wide (immediate)
 791 #define INSN(NAME, opcode)                                              \
 792   void NAME(Register Rd, unsigned imm, unsigned shift = 0) {            \
 793     assert_cond((shift/16)*16 == shift);                                \
 794     starti;                                                             \
 795     f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21),        \
 796       f(imm, 20, 5);                                                    \
 797     rf(Rd, 0);                                                          \
 798   }
 799 
 800   INSN(movnw, 0b000);
 801   INSN(movzw, 0b010);
 802   INSN(movkw, 0b011);
 803   INSN(movn, 0b100);
 804   INSN(movz, 0b110);
 805   INSN(movk, 0b111);
 806 
 807 #undef INSN
 808 
 809   // Bitfield
 810 #define INSN(NAME, opcode)                                              \
 811   void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) {   \
 812     starti;                                                             \
 813     f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10);                \
 814     zrf(Rn, 5), rf(Rd, 0);                                              \
 815   }
 816 
 817   INSN(sbfmw, 0b0001001100);
 818   INSN(bfmw,  0b0011001100);
 819   INSN(ubfmw, 0b0101001100);
 820   INSN(sbfm,  0b1001001101);
 821   INSN(bfm,   0b1011001101);
 822   INSN(ubfm,  0b1101001101);
 823 
 824 #undef INSN
 825 
 826   // Extract
 827 #define INSN(NAME, opcode)                                              \
 828   void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) {     \
 829     starti;                                                             \
 830     f(opcode, 31, 21), f(imms, 15, 10);                                 \
 831     rf(Rm, 16), rf(Rn, 5), rf(Rd, 0);                                   \
 832   }
 833 
 834   INSN(extrw, 0b00010011100);
 835   INSN(extr,  0b10010011110);
 836 
 837 #undef INSN
 838 
 839   // The maximum range of a branch is fixed for the AArch64
 840   // architecture.  In debug mode we shrink it in order to test
 841   // trampolines, but not so small that branches in the interpreter
 842   // are out of range.
 843   static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
 844 
 845   static bool reachable_from_branch_at(address branch, address target) {
 846     return uabs(target - branch) < branch_range;
 847   }
 848 
 849   // Unconditional branch (immediate)
 850 #define INSN(NAME, opcode)                                              \
 851   void NAME(address dest) {                                             \
 852     starti;                                                             \
 853     long offset = (dest - pc()) >> 2;                                   \
 854     DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
 855     f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0);               \
 856   }                                                                     \
 857   void NAME(Label &L) {                                                 \
 858     wrap_label(L, &Assembler::NAME);                                    \
 859   }                                                                     \
 860   void NAME(const Address &dest);
 861 
 862   INSN(b, 0);
 863   INSN(bl, 1);
 864 
 865 #undef INSN
 866 
 867   // Compare & branch (immediate)
 868 #define INSN(NAME, opcode)                              \
 869   void NAME(Register Rt, address dest) {                \
 870     long offset = (dest - pc()) >> 2;                   \
 871     starti;                                             \
 872     f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0);    \
 873   }                                                     \
 874   void NAME(Register Rt, Label &L) {                    \
 875     wrap_label(Rt, L, &Assembler::NAME);                \
 876   }
 877 
 878   INSN(cbzw,  0b00110100);
 879   INSN(cbnzw, 0b00110101);
 880   INSN(cbz,   0b10110100);
 881   INSN(cbnz,  0b10110101);
 882 
 883 #undef INSN
 884 
 885   // Test & branch (immediate)
 886 #define INSN(NAME, opcode)                                              \
 887   void NAME(Register Rt, int bitpos, address dest) {                    \
 888     long offset = (dest - pc()) >> 2;                                   \
 889     int b5 = bitpos >> 5;                                               \
 890     bitpos &= 0x1f;                                                     \
 891     starti;                                                             \
 892     f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
 893     rf(Rt, 0);                                                          \
 894   }                                                                     \
 895   void NAME(Register Rt, int bitpos, Label &L) {                        \
 896     wrap_label(Rt, bitpos, L, &Assembler::NAME);                        \
 897   }
 898 
 899   INSN(tbz,  0b0110110);
 900   INSN(tbnz, 0b0110111);
 901 
 902 #undef INSN
 903 
 904   // Conditional branch (immediate)
 905   enum Condition
 906     {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
 907 
 908   void br(Condition  cond, address dest) {
 909     long offset = (dest - pc()) >> 2;
 910     starti;
 911     f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
 912   }
 913 
 914 #define INSN(NAME, cond)                        \
 915   void NAME(address dest) {                     \
 916     br(cond, dest);                             \
 917   }
 918 
 919   INSN(beq, EQ);
 920   INSN(bne, NE);
 921   INSN(bhs, HS);
 922   INSN(bcs, CS);
 923   INSN(blo, LO);
 924   INSN(bcc, CC);
 925   INSN(bmi, MI);
 926   INSN(bpl, PL);
 927   INSN(bvs, VS);
 928   INSN(bvc, VC);
 929   INSN(bhi, HI);
 930   INSN(bls, LS);
 931   INSN(bge, GE);
 932   INSN(blt, LT);
 933   INSN(bgt, GT);
 934   INSN(ble, LE);
 935   INSN(bal, AL);
 936   INSN(bnv, NV);
 937 
 938   void br(Condition cc, Label &L);
 939 
 940 #undef INSN
 941 
 942   // Exception generation
 943   void generate_exception(int opc, int op2, int LL, unsigned imm) {
 944     starti;
 945     f(0b11010100, 31, 24);
 946     f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
 947   }
 948 
 949 #define INSN(NAME, opc, op2, LL)                \
 950   void NAME(unsigned imm) {                     \
 951     generate_exception(opc, op2, LL, imm);      \
 952   }
 953 
 954   INSN(svc, 0b000, 0, 0b01);
 955   INSN(hvc, 0b000, 0, 0b10);
 956   INSN(smc, 0b000, 0, 0b11);
 957   INSN(brk, 0b001, 0, 0b00);
 958   INSN(hlt, 0b010, 0, 0b00);
 959   INSN(dpcs1, 0b101, 0, 0b01);
 960   INSN(dpcs2, 0b101, 0, 0b10);
 961   INSN(dpcs3, 0b101, 0, 0b11);
 962 
 963 #undef INSN
 964 
 965   // System
 966   void system(int op0, int op1, int CRn, int CRm, int op2,
 967               Register rt = dummy_reg)
 968   {
 969     starti;
 970     f(0b11010101000, 31, 21);
 971     f(op0, 20, 19);
 972     f(op1, 18, 16);
 973     f(CRn, 15, 12);
 974     f(CRm, 11, 8);
 975     f(op2, 7, 5);
 976     rf(rt, 0);
 977   }
 978 
 979   void hint(int imm) {
 980     system(0b00, 0b011, 0b0010, 0b0000, imm);
 981   }
 982 
 983   void nop() {
 984     hint(0);
 985   }
 986 
 987   void yield() {
 988     hint(1);
 989   }
 990 
 991   void wfe() {
 992     hint(2);
 993   }
 994 
 995   void wfi() {
 996     hint(3);
 997   }
 998 
 999   void sev() {
1000     hint(4);
1001   }
1002 
1003   void sevl() {
1004     hint(5);
1005   }
1006 
1007   // we only provide mrs and msr for the special purpose system
1008   // registers where op1 (instr[20:19]) == 11 and, (currently) only
1009   // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1010 
1011   void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1012     starti;
1013     f(0b1101010100011, 31, 19);
1014     f(op1, 18, 16);
1015     f(CRn, 15, 12);
1016     f(CRm, 11, 8);
1017     f(op2, 7, 5);
1018     // writing zr is ok
1019     zrf(rt, 0);
1020   }
1021 
1022   void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1023     starti;
1024     f(0b1101010100111, 31, 19);
1025     f(op1, 18, 16);
1026     f(CRn, 15, 12);
1027     f(CRm, 11, 8);
1028     f(op2, 7, 5);
1029     // reading to zr is a mistake
1030     rf(rt, 0);
1031   }
1032 
1033   enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1034                 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1035 
1036   void dsb(barrier imm) {
1037     system(0b00, 0b011, 0b00011, imm, 0b100);
1038   }
1039 
1040   void dmb(barrier imm) {
1041     system(0b00, 0b011, 0b00011, imm, 0b101);
1042   }
1043 
1044   void isb() {
1045     system(0b00, 0b011, 0b00011, SY, 0b110);
1046   }
1047 
1048   void sys(int op1, int CRn, int CRm, int op2,
1049            Register rt = (Register)0b11111) {
1050     system(0b01, op1, CRn, CRm, op2, rt);
1051   }
1052 
1053   // Only implement operations accessible from EL0 or higher, i.e.,
1054   //            op1    CRn    CRm    op2
1055   // IC IVAU     3      7      5      1
1056   // DC CVAC     3      7      10     1
1057   // DC CVAU     3      7      11     1
1058   // DC CIVAC    3      7      14     1
1059   // DC ZVA      3      7      4      1
1060   // So only deal with the CRm field.
1061   enum icache_maintenance {IVAU = 0b0101};
1062   enum dcache_maintenance {CVAC = 0b1010, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1063 
1064   void dc(dcache_maintenance cm, Register Rt) {
1065     sys(0b011, 0b0111, cm, 0b001, Rt);
1066   }
1067 
1068   void ic(icache_maintenance cm, Register Rt) {
1069     sys(0b011, 0b0111, cm, 0b001, Rt);
1070   }
1071 
1072   // A more convenient access to dmb for our purposes
1073   enum Membar_mask_bits {
1074     // We can use ISH for a barrier because the ARM ARM says "This
1075     // architecture assumes that all Processing Elements that use the
1076     // same operating system or hypervisor are in the same Inner
1077     // Shareable shareability domain."
1078     StoreStore = ISHST,
1079     LoadStore  = ISHLD,
1080     LoadLoad   = ISHLD,
1081     StoreLoad  = ISH,
1082     AnyAny     = ISH
1083   };
1084 
1085   void membar(Membar_mask_bits order_constraint) {
1086     dmb(Assembler::barrier(order_constraint));
1087   }
1088 
1089   // Unconditional branch (register)
1090   void branch_reg(Register R, int opc) {
1091     starti;
1092     f(0b1101011, 31, 25);
1093     f(opc, 24, 21);
1094     f(0b11111000000, 20, 10);
1095     rf(R, 5);
1096     f(0b00000, 4, 0);
1097   }
1098 
1099 #define INSN(NAME, opc)                         \
1100   void NAME(Register R) {                       \
1101     branch_reg(R, opc);                         \
1102   }
1103 
1104   INSN(br, 0b0000);
1105   INSN(blr, 0b0001);
1106   INSN(ret, 0b0010);
1107 
1108   void ret(void *p); // This forces a compile-time error for ret(0)
1109 
1110 #undef INSN
1111 
1112 #define INSN(NAME, opc)                         \
1113   void NAME() {                 \
1114     branch_reg(dummy_reg, opc);         \
1115   }
1116 
1117   INSN(eret, 0b0100);
1118   INSN(drps, 0b0101);
1119 
1120 #undef INSN
1121 
1122   // Load/store exclusive
1123   enum operand_size { byte, halfword, word, xword };
1124 
1125   void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1126     Register Rn, enum operand_size sz, int op, bool ordered) {
1127     starti;
1128     f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1129     rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), srf(Rn, 5), zrf(Rt1, 0);
1130   }
1131 
1132   void load_exclusive(Register dst, Register addr,
1133                       enum operand_size sz, bool ordered) {
1134     load_store_exclusive(dummy_reg, dst, dummy_reg, addr,
1135                          sz, 0b010, ordered);
1136   }
1137 
1138   void store_exclusive(Register status, Register new_val, Register addr,
1139                        enum operand_size sz, bool ordered) {
1140     load_store_exclusive(status, new_val, dummy_reg, addr,
1141                          sz, 0b000, ordered);
1142   }
1143 
1144 #define INSN4(NAME, sz, op, o0) /* Four registers */                    \
1145   void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) {     \
1146     guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \
1147     load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0);                 \
1148   }
1149 
1150 #define INSN3(NAME, sz, op, o0) /* Three registers */                   \
1151   void NAME(Register Rs, Register Rt, Register Rn) {                    \
1152     guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction");       \
1153     load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \
1154   }
1155 
1156 #define INSN2(NAME, sz, op, o0) /* Two registers */                     \
1157   void NAME(Register Rt, Register Rn) {                                 \
1158     load_store_exclusive(dummy_reg, Rt, dummy_reg, \
1159                          Rn, sz, op, o0);                               \
1160   }
1161 
1162 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1163   void NAME(Register Rt1, Register Rt2, Register Rn) {                  \
1164     guarantee(Rt1 != Rt2, "unpredictable instruction");                 \
1165     load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0);          \
1166   }
1167 
1168   // bytes
1169   INSN3(stxrb, byte, 0b000, 0);
1170   INSN3(stlxrb, byte, 0b000, 1);
1171   INSN2(ldxrb, byte, 0b010, 0);
1172   INSN2(ldaxrb, byte, 0b010, 1);
1173   INSN2(stlrb, byte, 0b100, 1);
1174   INSN2(ldarb, byte, 0b110, 1);
1175 
1176   // halfwords
1177   INSN3(stxrh, halfword, 0b000, 0);
1178   INSN3(stlxrh, halfword, 0b000, 1);
1179   INSN2(ldxrh, halfword, 0b010, 0);
1180   INSN2(ldaxrh, halfword, 0b010, 1);
1181   INSN2(stlrh, halfword, 0b100, 1);
1182   INSN2(ldarh, halfword, 0b110, 1);
1183 
1184   // words
1185   INSN3(stxrw, word, 0b000, 0);
1186   INSN3(stlxrw, word, 0b000, 1);
1187   INSN4(stxpw, word, 0b001, 0);
1188   INSN4(stlxpw, word, 0b001, 1);
1189   INSN2(ldxrw, word, 0b010, 0);
1190   INSN2(ldaxrw, word, 0b010, 1);
1191   INSN_FOO(ldxpw, word, 0b011, 0);
1192   INSN_FOO(ldaxpw, word, 0b011, 1);
1193   INSN2(stlrw, word, 0b100, 1);
1194   INSN2(ldarw, word, 0b110, 1);
1195 
1196   // xwords
1197   INSN3(stxr, xword, 0b000, 0);
1198   INSN3(stlxr, xword, 0b000, 1);
1199   INSN4(stxp, xword, 0b001, 0);
1200   INSN4(stlxp, xword, 0b001, 1);
1201   INSN2(ldxr, xword, 0b010, 0);
1202   INSN2(ldaxr, xword, 0b010, 1);
1203   INSN_FOO(ldxp, xword, 0b011, 0);
1204   INSN_FOO(ldaxp, xword, 0b011, 1);
1205   INSN2(stlr, xword, 0b100, 1);
1206   INSN2(ldar, xword, 0b110, 1);
1207 
1208 #undef INSN2
1209 #undef INSN3
1210 #undef INSN4
1211 #undef INSN_FOO
1212 
1213   // 8.1 Compare and swap extensions
1214   void lse_cas(Register Rs, Register Rt, Register Rn,
1215                         enum operand_size sz, bool a, bool r, bool not_pair) {
1216     starti;
1217     if (! not_pair) { // Pair
1218       assert(sz == word || sz == xword, "invalid size");
1219       /* The size bit is in bit 30, not 31 */
1220       sz = (operand_size)(sz == word ? 0b00:0b01);
1221     }
1222     f(sz, 31, 30), f(0b001000, 29, 24), f(not_pair ? 1 : 0, 23), f(a, 22), f(1, 21);
1223     zrf(Rs, 16), f(r, 15), f(0b11111, 14, 10), srf(Rn, 5), zrf(Rt, 0);
1224   }
1225 
1226   // CAS
1227 #define INSN(NAME, a, r)                                                \
1228   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
1229     assert(Rs != Rn && Rs != Rt, "unpredictable instruction");          \
1230     lse_cas(Rs, Rt, Rn, sz, a, r, true);                                \
1231   }
1232   INSN(cas,    false, false)
1233   INSN(casa,   true,  false)
1234   INSN(casl,   false, true)
1235   INSN(casal,  true,  true)
1236 #undef INSN
1237 
1238   // CASP
1239 #define INSN(NAME, a, r)                                                \
1240   void NAME(operand_size sz, Register Rs, Register Rs1,                 \
1241             Register Rt, Register Rt1, Register Rn) {                   \
1242     assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 &&    \
1243            Rs->successor() == Rs1 && Rt->successor() == Rt1 &&          \
1244            Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers");     \
1245     lse_cas(Rs, Rt, Rn, sz, a, r, false);                               \
1246   }
1247   INSN(casp,    false, false)
1248   INSN(caspa,   true,  false)
1249   INSN(caspl,   false, true)
1250   INSN(caspal,  true,  true)
1251 #undef INSN
1252 
1253   // 8.1 Atomic operations
1254   void lse_atomic(Register Rs, Register Rt, Register Rn,
1255                   enum operand_size sz, int op1, int op2, bool a, bool r) {
1256     starti;
1257     f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21);
1258     rf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), srf(Rn, 5), zrf(Rt, 0);
1259   }
1260 
1261 #define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2)                   \
1262   void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) {   \
1263     lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false);                 \
1264   }                                                                     \
1265   void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1266     lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false);                  \
1267   }                                                                     \
1268   void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \
1269     lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true);                  \
1270   }                                                                     \
1271   void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\
1272     lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true);                   \
1273   }
1274   INSN(ldadd,  ldadda,  ldaddl,  ldaddal,  0, 0b000);
1275   INSN(ldbic,  ldbica,  ldbicl,  ldbical,  0, 0b001);
1276   INSN(ldeor,  ldeora,  ldeorl,  ldeoral,  0, 0b010);
1277   INSN(ldorr,  ldorra,  ldorrl,  ldorral,  0, 0b011);
1278   INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100);
1279   INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101);
1280   INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110);
1281   INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111);
1282   INSN(swp,    swpa,    swpl,    swpal,    1, 0b000);
1283 #undef INSN
1284 
1285   // Load register (literal)
1286 #define INSN(NAME, opc, V)                                              \
1287   void NAME(Register Rt, address dest) {                                \
1288     long offset = (dest - pc()) >> 2;                                   \
1289     starti;                                                             \
1290     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1291       sf(offset, 23, 5);                                                \
1292     rf(Rt, 0);                                                          \
1293   }                                                                     \
1294   void NAME(Register Rt, address dest, relocInfo::relocType rtype) {    \
1295     InstructionMark im(this);                                           \
1296     guarantee(rtype == relocInfo::internal_word_type,                   \
1297               "only internal_word_type relocs make sense here");        \
1298     code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1299     NAME(Rt, dest);                                                     \
1300   }                                                                     \
1301   void NAME(Register Rt, Label &L) {                                    \
1302     wrap_label(Rt, L, &Assembler::NAME);                                \
1303   }
1304 
1305   INSN(ldrw, 0b00, 0);
1306   INSN(ldr, 0b01, 0);
1307   INSN(ldrsw, 0b10, 0);
1308 
1309 #undef INSN
1310 
1311 #define INSN(NAME, opc, V)                                              \
1312   void NAME(FloatRegister Rt, address dest) {                           \
1313     long offset = (dest - pc()) >> 2;                                   \
1314     starti;                                                             \
1315     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1316       sf(offset, 23, 5);                                                \
1317     rf((Register)Rt, 0);                                                \
1318   }
1319 
1320   INSN(ldrs, 0b00, 1);
1321   INSN(ldrd, 0b01, 1);
1322   INSN(ldrq, 0b10, 1);
1323 
1324 #undef INSN
1325 
1326 #define INSN(NAME, opc, V)                                              \
1327   void NAME(address dest, prfop op = PLDL1KEEP) {                       \
1328     long offset = (dest - pc()) >> 2;                                   \
1329     starti;                                                             \
1330     f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24),        \
1331       sf(offset, 23, 5);                                                \
1332     f(op, 4, 0);                                                        \
1333   }                                                                     \
1334   void NAME(Label &L, prfop op = PLDL1KEEP) {                           \
1335     wrap_label(L, op, &Assembler::NAME);                                \
1336   }
1337 
1338   INSN(prfm, 0b11, 0);
1339 
1340 #undef INSN
1341 
1342   // Load/store
1343   void ld_st1(int opc, int p1, int V, int L,
1344               Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1345     starti;
1346     f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1347     zrf(Rt2, 10), zrf(Rt1, 0);
1348     if (no_allocate) {
1349       adr.encode_nontemporal_pair(current);
1350     } else {
1351       adr.encode_pair(current);
1352     }
1353   }
1354 
1355   // Load/store register pair (offset)
1356 #define INSN(NAME, size, p1, V, L, no_allocate)         \
1357   void NAME(Register Rt1, Register Rt2, Address adr) {  \
1358     ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1359    }
1360 
1361   INSN(stpw, 0b00, 0b101, 0, 0, false);
1362   INSN(ldpw, 0b00, 0b101, 0, 1, false);
1363   INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1364   INSN(stp, 0b10, 0b101, 0, 0, false);
1365   INSN(ldp, 0b10, 0b101, 0, 1, false);
1366 
1367   // Load/store no-allocate pair (offset)
1368   INSN(stnpw, 0b00, 0b101, 0, 0, true);
1369   INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1370   INSN(stnp, 0b10, 0b101, 0, 0, true);
1371   INSN(ldnp, 0b10, 0b101, 0, 1, true);
1372 
1373 #undef INSN
1374 
1375 #define INSN(NAME, size, p1, V, L, no_allocate)                         \
1376   void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) {        \
1377     ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1378    }
1379 
1380   INSN(stps, 0b00, 0b101, 1, 0, false);
1381   INSN(ldps, 0b00, 0b101, 1, 1, false);
1382   INSN(stpd, 0b01, 0b101, 1, 0, false);
1383   INSN(ldpd, 0b01, 0b101, 1, 1, false);
1384   INSN(stpq, 0b10, 0b101, 1, 0, false);
1385   INSN(ldpq, 0b10, 0b101, 1, 1, false);
1386 
1387 #undef INSN
1388 
1389   // Load/store register (all modes)
1390   void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1391     starti;
1392 
1393     f(V, 26); // general reg?
1394     zrf(Rt, 0);
1395 
1396     // Encoding for literal loads is done here (rather than pushed
1397     // down into Address::encode) because the encoding of this
1398     // instruction is too different from all of the other forms to
1399     // make it worth sharing.
1400     if (adr.getMode() == Address::literal) {
1401       assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1402       assert(op == 0b01, "literal form can only be used with loads");
1403       f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1404       long offset = (adr.target() - pc()) >> 2;
1405       sf(offset, 23, 5);
1406       code_section()->relocate(pc(), adr.rspec());
1407       return;
1408     }
1409 
1410     f(size, 31, 30);
1411     f(op, 23, 22); // str
1412     adr.encode(current);
1413   }
1414 
1415 #define INSN(NAME, size, op)                            \
1416   void NAME(Register Rt, const Address &adr) {          \
1417     ld_st2(Rt, adr, size, op);                          \
1418   }                                                     \
1419 
1420   INSN(str, 0b11, 0b00);
1421   INSN(strw, 0b10, 0b00);
1422   INSN(strb, 0b00, 0b00);
1423   INSN(strh, 0b01, 0b00);
1424 
1425   INSN(ldr, 0b11, 0b01);
1426   INSN(ldrw, 0b10, 0b01);
1427   INSN(ldrb, 0b00, 0b01);
1428   INSN(ldrh, 0b01, 0b01);
1429 
1430   INSN(ldrsb, 0b00, 0b10);
1431   INSN(ldrsbw, 0b00, 0b11);
1432   INSN(ldrsh, 0b01, 0b10);
1433   INSN(ldrshw, 0b01, 0b11);
1434   INSN(ldrsw, 0b10, 0b10);
1435 
1436 #undef INSN
1437 
1438 #define INSN(NAME, size, op)                                    \
1439   void NAME(const Address &adr, prfop pfop = PLDL1KEEP) {       \
1440     ld_st2((Register)pfop, adr, size, op);                      \
1441   }
1442 
1443   INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1444                           // writeback modes, but the assembler
1445                           // doesn't enfore that.
1446 
1447 #undef INSN
1448 
1449 #define INSN(NAME, size, op)                            \
1450   void NAME(FloatRegister Rt, const Address &adr) {     \
1451     ld_st2((Register)Rt, adr, size, op, 1);             \
1452   }
1453 
1454   INSN(strd, 0b11, 0b00);
1455   INSN(strs, 0b10, 0b00);
1456   INSN(ldrd, 0b11, 0b01);
1457   INSN(ldrs, 0b10, 0b01);
1458   INSN(strq, 0b00, 0b10);
1459   INSN(ldrq, 0x00, 0b11);
1460 
1461 #undef INSN
1462 
1463   enum shift_kind { LSL, LSR, ASR, ROR };
1464 
1465   void op_shifted_reg(unsigned decode,
1466                       enum shift_kind kind, unsigned shift,
1467                       unsigned size, unsigned op) {
1468     f(size, 31);
1469     f(op, 30, 29);
1470     f(decode, 28, 24);
1471     f(shift, 15, 10);
1472     f(kind, 23, 22);
1473   }
1474 
1475   // Logical (shifted register)
1476 #define INSN(NAME, size, op, N)                                 \
1477   void NAME(Register Rd, Register Rn, Register Rm,              \
1478             enum shift_kind kind = LSL, unsigned shift = 0) {   \
1479     starti;                                                     \
1480     f(N, 21);                                                   \
1481     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                        \
1482     op_shifted_reg(0b01010, kind, shift, size, op);             \
1483   }
1484 
1485   INSN(andr, 1, 0b00, 0);
1486   INSN(orr, 1, 0b01, 0);
1487   INSN(eor, 1, 0b10, 0);
1488   INSN(ands, 1, 0b11, 0);
1489   INSN(andw, 0, 0b00, 0);
1490   INSN(orrw, 0, 0b01, 0);
1491   INSN(eorw, 0, 0b10, 0);
1492   INSN(andsw, 0, 0b11, 0);
1493 
1494 #undef INSN
1495 
1496 #define INSN(NAME, size, op, N)                                         \
1497   void NAME(Register Rd, Register Rn, Register Rm,                      \
1498             enum shift_kind kind = LSL, unsigned shift = 0) {           \
1499     starti;                                                             \
1500     f(N, 21);                                                           \
1501     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);                                \
1502     op_shifted_reg(0b01010, kind, shift, size, op);                     \
1503   }                                                                     \
1504                                                                         \
1505   /* These instructions have no immediate form. Provide an overload so  \
1506      that if anyone does try to use an immediate operand -- this has    \
1507      happened! -- we'll get a compile-time error. */                    \
1508   void NAME(Register Rd, Register Rn, unsigned imm,                     \
1509             enum shift_kind kind = LSL, unsigned shift = 0) {           \
1510     assert(false, " can't be used with immediate operand");             \
1511   }
1512 
1513   INSN(bic, 1, 0b00, 1);
1514   INSN(orn, 1, 0b01, 1);
1515   INSN(eon, 1, 0b10, 1);
1516   INSN(bics, 1, 0b11, 1);
1517   INSN(bicw, 0, 0b00, 1);
1518   INSN(ornw, 0, 0b01, 1);
1519   INSN(eonw, 0, 0b10, 1);
1520   INSN(bicsw, 0, 0b11, 1);
1521 
1522 #undef INSN
1523 
1524   // Aliases for short forms of orn
1525 void mvn(Register Rd, Register Rm,
1526             enum shift_kind kind = LSL, unsigned shift = 0) {
1527   orn(Rd, zr, Rm, kind, shift);
1528 }
1529 
1530 void mvnw(Register Rd, Register Rm,
1531             enum shift_kind kind = LSL, unsigned shift = 0) {
1532   ornw(Rd, zr, Rm, kind, shift);
1533 }
1534 
1535   // Add/subtract (shifted register)
1536 #define INSN(NAME, size, op)                            \
1537   void NAME(Register Rd, Register Rn, Register Rm,      \
1538             enum shift_kind kind, unsigned shift = 0) { \
1539     starti;                                             \
1540     f(0, 21);                                           \
1541     assert_cond(kind != ROR);                           \
1542     zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16);                \
1543     op_shifted_reg(0b01011, kind, shift, size, op);     \
1544   }
1545 
1546   INSN(add, 1, 0b000);
1547   INSN(sub, 1, 0b10);
1548   INSN(addw, 0, 0b000);
1549   INSN(subw, 0, 0b10);
1550 
1551   INSN(adds, 1, 0b001);
1552   INSN(subs, 1, 0b11);
1553   INSN(addsw, 0, 0b001);
1554   INSN(subsw, 0, 0b11);
1555 
1556 #undef INSN
1557 
1558   // Add/subtract (extended register)
1559 #define INSN(NAME, op)                                                  \
1560   void NAME(Register Rd, Register Rn, Register Rm,                      \
1561            ext::operation option, int amount = 0) {                     \
1562     starti;                                                             \
1563     zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0);                                \
1564     add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1565   }
1566 
1567   void add_sub_extended_reg(unsigned op, unsigned decode,
1568     Register Rd, Register Rn, Register Rm,
1569     unsigned opt, ext::operation option, unsigned imm) {
1570     guarantee(imm <= 4, "shift amount must be < 4");
1571     f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1572     f(option, 15, 13), f(imm, 12, 10);
1573   }
1574 
1575   INSN(addw, 0b000);
1576   INSN(subw, 0b010);
1577   INSN(add, 0b100);
1578   INSN(sub, 0b110);
1579 
1580 #undef INSN
1581 
1582 #define INSN(NAME, op)                                                  \
1583   void NAME(Register Rd, Register Rn, Register Rm,                      \
1584            ext::operation option, int amount = 0) {                     \
1585     starti;                                                             \
1586     zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0);                                \
1587     add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1588   }
1589 
1590   INSN(addsw, 0b001);
1591   INSN(subsw, 0b011);
1592   INSN(adds, 0b101);
1593   INSN(subs, 0b111);
1594 
1595 #undef INSN
1596 
1597   // Aliases for short forms of add and sub
1598 #define INSN(NAME)                                      \
1599   void NAME(Register Rd, Register Rn, Register Rm) {    \
1600     if (Rd == sp || Rn == sp)                           \
1601       NAME(Rd, Rn, Rm, ext::uxtx);                      \
1602     else                                                \
1603       NAME(Rd, Rn, Rm, LSL);                            \
1604   }
1605 
1606   INSN(addw);
1607   INSN(subw);
1608   INSN(add);
1609   INSN(sub);
1610 
1611   INSN(addsw);
1612   INSN(subsw);
1613   INSN(adds);
1614   INSN(subs);
1615 
1616 #undef INSN
1617 
1618   // Add/subtract (with carry)
1619   void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1620     starti;
1621     f(op, 31, 29);
1622     f(0b11010000, 28, 21);
1623     f(0b000000, 15, 10);
1624     zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1625   }
1626 
1627   #define INSN(NAME, op)                                \
1628     void NAME(Register Rd, Register Rn, Register Rm) {  \
1629       add_sub_carry(op, Rd, Rn, Rm);                    \
1630     }
1631 
1632   INSN(adcw, 0b000);
1633   INSN(adcsw, 0b001);
1634   INSN(sbcw, 0b010);
1635   INSN(sbcsw, 0b011);
1636   INSN(adc, 0b100);
1637   INSN(adcs, 0b101);
1638   INSN(sbc,0b110);
1639   INSN(sbcs, 0b111);
1640 
1641 #undef INSN
1642 
1643   // Conditional compare (both kinds)
1644   void conditional_compare(unsigned op, int o1, int o2, int o3,
1645                            Register Rn, unsigned imm5, unsigned nzcv,
1646                            unsigned cond) {
1647     starti;
1648     f(op, 31, 29);
1649     f(0b11010010, 28, 21);
1650     f(cond, 15, 12);
1651     f(o1, 11);
1652     f(o2, 10);
1653     f(o3, 4);
1654     f(nzcv, 3, 0);
1655     f(imm5, 20, 16), rf(Rn, 5);
1656   }
1657 
1658 #define INSN(NAME, op)                                                  \
1659   void NAME(Register Rn, Register Rm, int imm, Condition cond) {        \
1660     int regNumber = (Rm == zr ? 31 : (uintptr_t)Rm);                    \
1661     conditional_compare(op, 0, 0, 0, Rn, regNumber, imm, cond);         \
1662   }                                                                     \
1663                                                                         \
1664   void NAME(Register Rn, int imm5, int imm, Condition cond) {           \
1665     conditional_compare(op, 1, 0, 0, Rn, imm5, imm, cond);              \
1666   }
1667 
1668   INSN(ccmnw, 0b001);
1669   INSN(ccmpw, 0b011);
1670   INSN(ccmn, 0b101);
1671   INSN(ccmp, 0b111);
1672 
1673 #undef INSN
1674 
1675   // Conditional select
1676   void conditional_select(unsigned op, unsigned op2,
1677                           Register Rd, Register Rn, Register Rm,
1678                           unsigned cond) {
1679     starti;
1680     f(op, 31, 29);
1681     f(0b11010100, 28, 21);
1682     f(cond, 15, 12);
1683     f(op2, 11, 10);
1684     zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1685   }
1686 
1687 #define INSN(NAME, op, op2)                                             \
1688   void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1689     conditional_select(op, op2, Rd, Rn, Rm, cond);                      \
1690   }
1691 
1692   INSN(cselw, 0b000, 0b00);
1693   INSN(csincw, 0b000, 0b01);
1694   INSN(csinvw, 0b010, 0b00);
1695   INSN(csnegw, 0b010, 0b01);
1696   INSN(csel, 0b100, 0b00);
1697   INSN(csinc, 0b100, 0b01);
1698   INSN(csinv, 0b110, 0b00);
1699   INSN(csneg, 0b110, 0b01);
1700 
1701 #undef INSN
1702 
1703   // Data processing
1704   void data_processing(unsigned op29, unsigned opcode,
1705                        Register Rd, Register Rn) {
1706     f(op29, 31, 29), f(0b11010110, 28, 21);
1707     f(opcode, 15, 10);
1708     rf(Rn, 5), rf(Rd, 0);
1709   }
1710 
1711   // (1 source)
1712 #define INSN(NAME, op29, opcode2, opcode)       \
1713   void NAME(Register Rd, Register Rn) {         \
1714     starti;                                     \
1715     f(opcode2, 20, 16);                         \
1716     data_processing(op29, opcode, Rd, Rn);      \
1717   }
1718 
1719   INSN(rbitw,  0b010, 0b00000, 0b00000);
1720   INSN(rev16w, 0b010, 0b00000, 0b00001);
1721   INSN(revw,   0b010, 0b00000, 0b00010);
1722   INSN(clzw,   0b010, 0b00000, 0b00100);
1723   INSN(clsw,   0b010, 0b00000, 0b00101);
1724 
1725   INSN(rbit,   0b110, 0b00000, 0b00000);
1726   INSN(rev16,  0b110, 0b00000, 0b00001);
1727   INSN(rev32,  0b110, 0b00000, 0b00010);
1728   INSN(rev,    0b110, 0b00000, 0b00011);
1729   INSN(clz,    0b110, 0b00000, 0b00100);
1730   INSN(cls,    0b110, 0b00000, 0b00101);
1731 
1732 #undef INSN
1733 
1734   // (2 sources)
1735 #define INSN(NAME, op29, opcode)                        \
1736   void NAME(Register Rd, Register Rn, Register Rm) {    \
1737     starti;                                             \
1738     rf(Rm, 16);                                         \
1739     data_processing(op29, opcode, Rd, Rn);              \
1740   }
1741 
1742   INSN(udivw, 0b000, 0b000010);
1743   INSN(sdivw, 0b000, 0b000011);
1744   INSN(lslvw, 0b000, 0b001000);
1745   INSN(lsrvw, 0b000, 0b001001);
1746   INSN(asrvw, 0b000, 0b001010);
1747   INSN(rorvw, 0b000, 0b001011);
1748 
1749   INSN(udiv, 0b100, 0b000010);
1750   INSN(sdiv, 0b100, 0b000011);
1751   INSN(lslv, 0b100, 0b001000);
1752   INSN(lsrv, 0b100, 0b001001);
1753   INSN(asrv, 0b100, 0b001010);
1754   INSN(rorv, 0b100, 0b001011);
1755 
1756 #undef INSN
1757 
1758   // (3 sources)
1759   void data_processing(unsigned op54, unsigned op31, unsigned o0,
1760                        Register Rd, Register Rn, Register Rm,
1761                        Register Ra) {
1762     starti;
1763     f(op54, 31, 29), f(0b11011, 28, 24);
1764     f(op31, 23, 21), f(o0, 15);
1765     zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1766   }
1767 
1768 #define INSN(NAME, op54, op31, o0)                                      \
1769   void NAME(Register Rd, Register Rn, Register Rm, Register Ra) {       \
1770     data_processing(op54, op31, o0, Rd, Rn, Rm, Ra);                    \
1771   }
1772 
1773   INSN(maddw, 0b000, 0b000, 0);
1774   INSN(msubw, 0b000, 0b000, 1);
1775   INSN(madd, 0b100, 0b000, 0);
1776   INSN(msub, 0b100, 0b000, 1);
1777   INSN(smaddl, 0b100, 0b001, 0);
1778   INSN(smsubl, 0b100, 0b001, 1);
1779   INSN(umaddl, 0b100, 0b101, 0);
1780   INSN(umsubl, 0b100, 0b101, 1);
1781 
1782 #undef INSN
1783 
1784 #define INSN(NAME, op54, op31, o0)                      \
1785   void NAME(Register Rd, Register Rn, Register Rm) {    \
1786     data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31);  \
1787   }
1788 
1789   INSN(smulh, 0b100, 0b010, 0);
1790   INSN(umulh, 0b100, 0b110, 0);
1791 
1792 #undef INSN
1793 
1794   // Floating-point data-processing (1 source)
1795   void data_processing(unsigned op31, unsigned type, unsigned opcode,
1796                        FloatRegister Vd, FloatRegister Vn) {
1797     starti;
1798     f(op31, 31, 29);
1799     f(0b11110, 28, 24);
1800     f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1801     rf(Vn, 5), rf(Vd, 0);
1802   }
1803 
1804 #define INSN(NAME, op31, type, opcode)                  \
1805   void NAME(FloatRegister Vd, FloatRegister Vn) {       \
1806     data_processing(op31, type, opcode, Vd, Vn);        \
1807   }
1808 
1809 private:
1810   INSN(i_fmovs, 0b000, 0b00, 0b000000);
1811 public:
1812   INSN(fabss, 0b000, 0b00, 0b000001);
1813   INSN(fnegs, 0b000, 0b00, 0b000010);
1814   INSN(fsqrts, 0b000, 0b00, 0b000011);
1815   INSN(fcvts, 0b000, 0b00, 0b000101);   // Single-precision to double-precision
1816 
1817 private:
1818   INSN(i_fmovd, 0b000, 0b01, 0b000000);
1819 public:
1820   INSN(fabsd, 0b000, 0b01, 0b000001);
1821   INSN(fnegd, 0b000, 0b01, 0b000010);
1822   INSN(fsqrtd, 0b000, 0b01, 0b000011);
1823   INSN(fcvtd, 0b000, 0b01, 0b000100);   // Double-precision to single-precision
1824 
1825   void fmovd(FloatRegister Vd, FloatRegister Vn) {
1826     assert(Vd != Vn, "should be");
1827     i_fmovd(Vd, Vn);
1828   }
1829 
1830   void fmovs(FloatRegister Vd, FloatRegister Vn) {
1831     assert(Vd != Vn, "should be");
1832     i_fmovs(Vd, Vn);
1833   }
1834 
1835 #undef INSN
1836 
1837   // Floating-point data-processing (2 source)
1838   void data_processing(unsigned op31, unsigned type, unsigned opcode,
1839                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1840     starti;
1841     f(op31, 31, 29);
1842     f(0b11110, 28, 24);
1843     f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1844     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1845   }
1846 
1847 #define INSN(NAME, op31, type, opcode)                  \
1848   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {     \
1849     data_processing(op31, type, opcode, Vd, Vn, Vm);    \
1850   }
1851 
1852   INSN(fmuls, 0b000, 0b00, 0b0000);
1853   INSN(fdivs, 0b000, 0b00, 0b0001);
1854   INSN(fadds, 0b000, 0b00, 0b0010);
1855   INSN(fsubs, 0b000, 0b00, 0b0011);
1856   INSN(fmaxs, 0b000, 0b00, 0b0100);
1857   INSN(fmins, 0b000, 0b00, 0b0101);
1858   INSN(fnmuls, 0b000, 0b00, 0b1000);
1859 
1860   INSN(fmuld, 0b000, 0b01, 0b0000);
1861   INSN(fdivd, 0b000, 0b01, 0b0001);
1862   INSN(faddd, 0b000, 0b01, 0b0010);
1863   INSN(fsubd, 0b000, 0b01, 0b0011);
1864   INSN(fmaxd, 0b000, 0b01, 0b0100);
1865   INSN(fmind, 0b000, 0b01, 0b0101);
1866   INSN(fnmuld, 0b000, 0b01, 0b1000);
1867 
1868 #undef INSN
1869 
1870    // Floating-point data-processing (3 source)
1871   void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1872                        FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1873                        FloatRegister Va) {
1874     starti;
1875     f(op31, 31, 29);
1876     f(0b11111, 28, 24);
1877     f(type, 23, 22), f(o1, 21), f(o0, 15);
1878     rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1879   }
1880 
1881 #define INSN(NAME, op31, type, o1, o0)                                  \
1882   void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,       \
1883             FloatRegister Va) {                                         \
1884     data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va);                \
1885   }
1886 
1887   INSN(fmadds, 0b000, 0b00, 0, 0);
1888   INSN(fmsubs, 0b000, 0b00, 0, 1);
1889   INSN(fnmadds, 0b000, 0b00, 1, 0);
1890   INSN(fnmsubs, 0b000, 0b00, 1, 1);
1891 
1892   INSN(fmaddd, 0b000, 0b01, 0, 0);
1893   INSN(fmsubd, 0b000, 0b01, 0, 1);
1894   INSN(fnmaddd, 0b000, 0b01, 1, 0);
1895   INSN(fnmsub, 0b000, 0b01, 1, 1);
1896 
1897 #undef INSN
1898 
1899    // Floating-point conditional select
1900   void fp_conditional_select(unsigned op31, unsigned type,
1901                              unsigned op1, unsigned op2,
1902                              Condition cond, FloatRegister Vd,
1903                              FloatRegister Vn, FloatRegister Vm) {
1904     starti;
1905     f(op31, 31, 29);
1906     f(0b11110, 28, 24);
1907     f(type, 23, 22);
1908     f(op1, 21, 21);
1909     f(op2, 11, 10);
1910     f(cond, 15, 12);
1911     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1912   }
1913 
1914 #define INSN(NAME, op31, type, op1, op2)                                \
1915   void NAME(FloatRegister Vd, FloatRegister Vn,                         \
1916             FloatRegister Vm, Condition cond) {                         \
1917     fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm);      \
1918   }
1919 
1920   INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1921   INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1922 
1923 #undef INSN
1924 
1925    // Floating-point<->integer conversions
1926   void float_int_convert(unsigned op31, unsigned type,
1927                          unsigned rmode, unsigned opcode,
1928                          Register Rd, Register Rn) {
1929     starti;
1930     f(op31, 31, 29);
1931     f(0b11110, 28, 24);
1932     f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1933     f(opcode, 18, 16), f(0b000000, 15, 10);
1934     zrf(Rn, 5), zrf(Rd, 0);
1935   }
1936 
1937 #define INSN(NAME, op31, type, rmode, opcode)                           \
1938   void NAME(Register Rd, FloatRegister Vn) {                            \
1939     float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn);     \
1940   }
1941 
1942   INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1943   INSN(fcvtzs,  0b100, 0b00, 0b11, 0b000);
1944   INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1945   INSN(fcvtzd,  0b100, 0b01, 0b11, 0b000);
1946 
1947   INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1948   INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1949 
1950   // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1951 
1952 #undef INSN
1953 
1954 #define INSN(NAME, op31, type, rmode, opcode)                           \
1955   void NAME(FloatRegister Vd, Register Rn) {                            \
1956     float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn);     \
1957   }
1958 
1959   INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1960   INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1961 
1962   INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1963   INSN(scvtfs,  0b100, 0b00, 0b00, 0b010);
1964   INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1965   INSN(scvtfd,  0b100, 0b01, 0b00, 0b010);
1966 
1967   // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1968 
1969 #undef INSN
1970 
1971   // Floating-point compare
1972   void float_compare(unsigned op31, unsigned type,
1973                      unsigned op, unsigned op2,
1974                      FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1975     starti;
1976     f(op31, 31, 29);
1977     f(0b11110, 28, 24);
1978     f(type, 23, 22), f(1, 21);
1979     f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1980     rf(Vn, 5), rf(Vm, 16);
1981   }
1982 
1983 
1984 #define INSN(NAME, op31, type, op, op2)                 \
1985   void NAME(FloatRegister Vn, FloatRegister Vm) {       \
1986     float_compare(op31, type, op, op2, Vn, Vm);         \
1987   }
1988 
1989 #define INSN1(NAME, op31, type, op, op2)        \
1990   void NAME(FloatRegister Vn, double d) {       \
1991     assert_cond(d == 0.0);                      \
1992     float_compare(op31, type, op, op2, Vn);     \
1993   }
1994 
1995   INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
1996   INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
1997   // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
1998   // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
1999 
2000   INSN(fcmpd, 0b000,   0b01, 0b00, 0b00000);
2001   INSN1(fcmpd, 0b000,  0b01, 0b00, 0b01000);
2002   // INSN(fcmped, 0b000,  0b01, 0b00, 0b10000);
2003   // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
2004 
2005 #undef INSN
2006 #undef INSN1
2007 
2008   // Floating-point Move (immediate)
2009 private:
2010   unsigned pack(double value);
2011 
2012   void fmov_imm(FloatRegister Vn, double value, unsigned size) {
2013     starti;
2014     f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
2015     f(pack(value), 20, 13), f(0b10000000, 12, 5);
2016     rf(Vn, 0);
2017   }
2018 
2019 public:
2020 
2021   void fmovs(FloatRegister Vn, double value) {
2022     if (value)
2023       fmov_imm(Vn, value, 0b00);
2024     else
2025       fmovs(Vn, zr);
2026   }
2027   void fmovd(FloatRegister Vn, double value) {
2028     if (value)
2029       fmov_imm(Vn, value, 0b01);
2030     else
2031       fmovd(Vn, zr);
2032   }
2033 
2034    // Floating-point rounding
2035    // type: half-precision = 11
2036    //       single         = 00
2037    //       double         = 01
2038    // rmode: A = Away     = 100
2039    //        I = current  = 111
2040    //        M = MinusInf = 010
2041    //        N = eveN     = 000
2042    //        P = PlusInf  = 001
2043    //        X = eXact    = 110
2044    //        Z = Zero     = 011
2045   void float_round(unsigned type, unsigned rmode, FloatRegister Rd, FloatRegister Rn) {
2046     starti;
2047     f(0b00011110, 31, 24);
2048     f(type, 23, 22);
2049     f(0b1001, 21, 18);
2050     f(rmode, 17, 15);
2051     f(0b10000, 14, 10);
2052     rf(Rn, 5), rf(Rd, 0);
2053   }
2054 #define INSN(NAME, type, rmode)                   \
2055   void NAME(FloatRegister Vd, FloatRegister Vn) { \
2056     float_round(type, rmode, Vd, Vn);             \
2057   }
2058 
2059 public:
2060   INSN(frintah, 0b11, 0b100);
2061   INSN(frintih, 0b11, 0b111);
2062   INSN(frintmh, 0b11, 0b010);
2063   INSN(frintnh, 0b11, 0b000);
2064   INSN(frintph, 0b11, 0b001);
2065   INSN(frintxh, 0b11, 0b110);
2066   INSN(frintzh, 0b11, 0b011);
2067 
2068   INSN(frintas, 0b00, 0b100);
2069   INSN(frintis, 0b00, 0b111);
2070   INSN(frintms, 0b00, 0b010);
2071   INSN(frintns, 0b00, 0b000);
2072   INSN(frintps, 0b00, 0b001);
2073   INSN(frintxs, 0b00, 0b110);
2074   INSN(frintzs, 0b00, 0b011);
2075 
2076   INSN(frintad, 0b01, 0b100);
2077   INSN(frintid, 0b01, 0b111);
2078   INSN(frintmd, 0b01, 0b010);
2079   INSN(frintnd, 0b01, 0b000);
2080   INSN(frintpd, 0b01, 0b001);
2081   INSN(frintxd, 0b01, 0b110);
2082   INSN(frintzd, 0b01, 0b011);
2083 #undef INSN
2084 
2085 /* SIMD extensions
2086  *
2087  * We just use FloatRegister in the following. They are exactly the same
2088  * as SIMD registers.
2089  */
2090  public:
2091 
2092   enum SIMD_Arrangement {
2093        T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
2094   };
2095 
2096   enum SIMD_RegVariant {
2097        B, H, S, D, Q
2098   };
2099 
2100 private:
2101   static short SIMD_Size_in_bytes[];
2102 
2103 public:
2104 #define INSN(NAME, op)                                            \
2105   void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) {   \
2106     ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
2107   }                                                                      \
2108 
2109   INSN(ldr, 1);
2110   INSN(str, 0);
2111 
2112 #undef INSN
2113 
2114  private:
2115 
2116   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
2117     starti;
2118     f(0,31), f((int)T & 1, 30);
2119     f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
2120     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2121   }
2122   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2123              int imm, int op1, int op2, int regs) {
2124     guarantee(T <= T1Q && imm == SIMD_Size_in_bytes[T] * regs, "bad offset");
2125     starti;
2126     f(0,31), f((int)T & 1, 30);
2127     f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
2128     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2129   }
2130   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
2131              Register Xm, int op1, int op2) {
2132     starti;
2133     f(0,31), f((int)T & 1, 30);
2134     f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
2135     f((int)T >> 1, 11, 10), srf(Xn, 5), rf(Vt, 0);
2136   }
2137 
2138   void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2, int regs) {
2139     switch (a.getMode()) {
2140     case Address::base_plus_offset:
2141       guarantee(a.offset() == 0, "no offset allowed here");
2142       ld_st(Vt, T, a.base(), op1, op2);
2143       break;
2144     case Address::post:
2145       ld_st(Vt, T, a.base(), a.offset(), op1, op2, regs);
2146       break;
2147     case Address::post_reg:
2148       ld_st(Vt, T, a.base(), a.index(), op1, op2);
2149       break;
2150     default:
2151       ShouldNotReachHere();
2152     }
2153   }
2154 
2155  public:
2156 
2157 #define INSN1(NAME, op1, op2)                                           \
2158   void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) {   \
2159     ld_st(Vt, T, a, op1, op2, 1);                                       \
2160  }
2161 
2162 #define INSN2(NAME, op1, op2)                                           \
2163   void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
2164     assert(Vt->successor() == Vt2, "Registers must be ordered");        \
2165     ld_st(Vt, T, a, op1, op2, 2);                                       \
2166   }
2167 
2168 #define INSN3(NAME, op1, op2)                                           \
2169   void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
2170             SIMD_Arrangement T, const Address &a) {                     \
2171     assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3,           \
2172            "Registers must be ordered");                                \
2173     ld_st(Vt, T, a, op1, op2, 3);                                       \
2174   }
2175 
2176 #define INSN4(NAME, op1, op2)                                           \
2177   void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3,     \
2178             FloatRegister Vt4, SIMD_Arrangement T, const Address &a) {  \
2179     assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 &&         \
2180            Vt3->successor() == Vt4, "Registers must be ordered");       \
2181     ld_st(Vt, T, a, op1, op2, 4);                                       \
2182   }
2183 
2184   INSN1(ld1,  0b001100010, 0b0111);
2185   INSN2(ld1,  0b001100010, 0b1010);
2186   INSN3(ld1,  0b001100010, 0b0110);
2187   INSN4(ld1,  0b001100010, 0b0010);
2188 
2189   INSN2(ld2,  0b001100010, 0b1000);
2190   INSN3(ld3,  0b001100010, 0b0100);
2191   INSN4(ld4,  0b001100010, 0b0000);
2192 
2193   INSN1(st1,  0b001100000, 0b0111);
2194   INSN2(st1,  0b001100000, 0b1010);
2195   INSN3(st1,  0b001100000, 0b0110);
2196   INSN4(st1,  0b001100000, 0b0010);
2197 
2198   INSN2(st2,  0b001100000, 0b1000);
2199   INSN3(st3,  0b001100000, 0b0100);
2200   INSN4(st4,  0b001100000, 0b0000);
2201 
2202   INSN1(ld1r, 0b001101010, 0b1100);
2203   INSN2(ld2r, 0b001101011, 0b1100);
2204   INSN3(ld3r, 0b001101010, 0b1110);
2205   INSN4(ld4r, 0b001101011, 0b1110);
2206 
2207 #undef INSN1
2208 #undef INSN2
2209 #undef INSN3
2210 #undef INSN4
2211 
2212 #define INSN(NAME, opc)                                                                 \
2213   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2214     starti;                                                                             \
2215     assert(T == T8B || T == T16B, "must be T8B or T16B");                               \
2216     f(0, 31), f((int)T & 1, 30), f(opc, 29, 21);                                        \
2217     rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0);                              \
2218   }
2219 
2220   INSN(eor,  0b101110001);
2221   INSN(orr,  0b001110101);
2222   INSN(andr, 0b001110001);
2223   INSN(bic,  0b001110011);
2224   INSN(bif,  0b101110111);
2225   INSN(bit,  0b101110101);
2226   INSN(bsl,  0b101110011);
2227   INSN(orn,  0b001110111);
2228 
2229 #undef INSN
2230 
2231 #define INSN(NAME, opc, opc2)                                                                 \
2232   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2233     starti;                                                                             \
2234     f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24);                        \
2235     f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10);                      \
2236     rf(Vn, 5), rf(Vd, 0);                                                               \
2237   }
2238 
2239   INSN(addv,   0, 0b100001);
2240   INSN(subv,   1, 0b100001);
2241   INSN(mulv,   0, 0b100111);
2242   INSN(mlav,   0, 0b100101);
2243   INSN(mlsv,   1, 0b100101);
2244   INSN(sshl,   0, 0b010001);
2245   INSN(ushl,   1, 0b010001);
2246   INSN(umullv, 1, 0b110000);
2247   INSN(umlalv, 1, 0b100000);
2248 
2249 #undef INSN
2250 
2251 #define INSN(NAME, opc, opc2) \
2252   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
2253     starti;                                                                             \
2254     f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24);                        \
2255     f((int)T >> 1, 23, 22), f(opc2, 21, 10);                                            \
2256     rf(Vn, 5), rf(Vd, 0);                                                               \
2257   }
2258 
2259   INSN(absr,   0, 0b100000101110);
2260   INSN(negr,   1, 0b100000101110);
2261   INSN(notr,   1, 0b100000010110);
2262   INSN(addv,   0, 0b110001101110);
2263   INSN(cls,    0, 0b100000010010);
2264   INSN(clz,    1, 0b100000010010);
2265   INSN(cnt,    0, 0b100000010110);
2266   INSN(uaddlv, 1, 0b110000001110);
2267 
2268 #undef INSN
2269 
2270 #define INSN(NAME, opc) \
2271   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                  \
2272     starti;                                                                            \
2273     assert(T == T4S, "arrangement must be T4S");                                       \
2274     f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24), f(opc, 23),                      \
2275     f(T == T4S ? 0 : 1, 22), f(0b110000111110, 21, 10); rf(Vn, 5), rf(Vd, 0);          \
2276   }
2277 
2278   INSN(fmaxv, 0);
2279   INSN(fminv, 1);
2280 
2281 #undef INSN
2282 
2283 #define INSN(NAME, op0, cmode0) \
2284   void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) {   \
2285     unsigned cmode = cmode0;                                                           \
2286     unsigned op = op0;                                                                 \
2287     starti;                                                                            \
2288     assert(lsl == 0 ||                                                                 \
2289            ((T == T4H || T == T8H) && lsl == 8) ||                                     \
2290            ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift");             \
2291     cmode |= lsl >> 2;                                                                 \
2292     if (T == T4H || T == T8H) cmode |= 0b1000;                                         \
2293     if (!(T == T4H || T == T8H || T == T2S || T == T4S)) {                             \
2294       assert(op == 0 && cmode0 == 0, "must be MOVI");                                  \
2295       cmode = 0b1110;                                                                  \
2296       if (T == T1D || T == T2D) op = 1;                                                \
2297     }                                                                                  \
2298     f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19);                   \
2299     f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5);  \
2300     rf(Vd, 0);                                                                         \
2301   }
2302 
2303   INSN(movi, 0, 0);
2304   INSN(orri, 0, 1);
2305   INSN(mvni, 1, 0);
2306   INSN(bici, 1, 1);
2307 
2308 #undef INSN
2309 
2310 #define INSN(NAME, op1, op2, op3) \
2311   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2312     starti;                                                                             \
2313     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");                    \
2314     f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23);            \
2315     f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0);    \
2316   }
2317 
2318   INSN(fadd, 0, 0, 0b110101);
2319   INSN(fdiv, 1, 0, 0b111111);
2320   INSN(fmul, 1, 0, 0b110111);
2321   INSN(fsub, 0, 1, 0b110101);
2322   INSN(fmla, 0, 0, 0b110011);
2323   INSN(fmls, 0, 1, 0b110011);
2324   INSN(fmax, 0, 0, 0b111101);
2325   INSN(fmin, 0, 1, 0b111101);
2326 
2327 #undef INSN
2328 
2329 #define INSN(NAME, opc)                                                                 \
2330   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2331     starti;                                                                             \
2332     assert(T == T4S, "arrangement must be T4S");                                        \
2333     f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);         \
2334   }
2335 
2336   INSN(sha1c,     0b000000);
2337   INSN(sha1m,     0b001000);
2338   INSN(sha1p,     0b000100);
2339   INSN(sha1su0,   0b001100);
2340   INSN(sha256h2,  0b010100);
2341   INSN(sha256h,   0b010000);
2342   INSN(sha256su1, 0b011000);
2343 
2344 #undef INSN
2345 
2346 #define INSN(NAME, opc)                                                                 \
2347   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {                   \
2348     starti;                                                                             \
2349     assert(T == T4S, "arrangement must be T4S");                                        \
2350     f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0);                \
2351   }
2352 
2353   INSN(sha1h,     0b000010);
2354   INSN(sha1su1,   0b000110);
2355   INSN(sha256su0, 0b001010);
2356 
2357 #undef INSN
2358 
2359 #define INSN(NAME, opc)                           \
2360   void NAME(FloatRegister Vd, FloatRegister Vn) { \
2361     starti;                                       \
2362     f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0);         \
2363   }
2364 
2365   INSN(aese, 0b0100111000101000010010);
2366   INSN(aesd, 0b0100111000101000010110);
2367   INSN(aesmc, 0b0100111000101000011010);
2368   INSN(aesimc, 0b0100111000101000011110);
2369 
2370 #undef INSN
2371 
2372 #define INSN(NAME, op1, op2) \
2373   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index = 0) { \
2374     starti;                                                                                            \
2375     assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");                                   \
2376     assert(index >= 0 && ((T == T2D && index <= 1) || (T != T2D && index <= 3)), "invalid index");     \
2377     f(0, 31), f((int)T & 1, 30), f(op1, 29); f(0b011111, 28, 23);                                      \
2378     f(T == T2D ? 1 : 0, 22), f(T == T2D ? 0 : index & 1, 21), rf(Vm, 16);                              \
2379     f(op2, 15, 12), f(T == T2D ? index : (index >> 1), 11), f(0, 10);                                  \
2380     rf(Vn, 5), rf(Vd, 0);                                                                              \
2381   }
2382 
2383   // FMLA/FMLS - Vector - Scalar
2384   INSN(fmlavs, 0, 0b0001);
2385   INSN(fmlsvs, 0, 0b0101);
2386   // FMULX - Vector - Scalar
2387   INSN(fmulxvs, 1, 0b1001);
2388 
2389 #undef INSN
2390 
2391   // Floating-point Reciprocal Estimate
2392   void frecpe(FloatRegister Vd, FloatRegister Vn, SIMD_RegVariant type) {
2393     assert(type == D || type == S, "Wrong type for frecpe");
2394     starti;
2395     f(0b010111101, 31, 23);
2396     f(type == D ? 1 : 0, 22);
2397     f(0b100001110110, 21, 10);
2398     rf(Vn, 5), rf(Vd, 0);
2399   }
2400 
2401   // (double) {a, b} -> (a + b)
2402   void faddpd(FloatRegister Vd, FloatRegister Vn) {
2403     starti;
2404     f(0b0111111001110000110110, 31, 10);
2405     rf(Vn, 5), rf(Vd, 0);
2406   }
2407 
2408   void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2409     starti;
2410     assert(T != Q, "invalid register variant");
2411     f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2412     f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2413   }
2414 
2415   void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2416     starti;
2417     f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2418     f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2419     rf(Vn, 5), rf(Rd, 0);
2420   }
2421 
2422 #define INSN(NAME, opc, opc2, isSHR)                                    \
2423   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2424     starti;                                                             \
2425     /* The encodings for the immh:immb fields (bits 22:16) in *SHR are  \
2426      *   0001 xxx       8B/16B, shift = 16  - UInt(immh:immb)           \
2427      *   001x xxx       4H/8H,  shift = 32  - UInt(immh:immb)           \
2428      *   01xx xxx       2S/4S,  shift = 64  - UInt(immh:immb)           \
2429      *   1xxx xxx       1D/2D,  shift = 128 - UInt(immh:immb)           \
2430      *   (1D is RESERVED)                                               \
2431      * for SHL shift is calculated as:                                  \
2432      *   0001 xxx       8B/16B, shift = UInt(immh:immb) - 8             \
2433      *   001x xxx       4H/8H,  shift = UInt(immh:immb) - 16            \
2434      *   01xx xxx       2S/4S,  shift = UInt(immh:immb) - 32            \
2435      *   1xxx xxx       1D/2D,  shift = UInt(immh:immb) - 64            \
2436      *   (1D is RESERVED)                                               \
2437      */                                                                 \
2438     assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value");           \
2439     int cVal = (1 << (((T >> 1) + 3) + (isSHR ? 1 : 0)));               \
2440     int encodedShift = isSHR ? cVal - shift : cVal + shift;             \
2441     f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23),            \
2442     f(encodedShift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0);     \
2443   }
2444 
2445   INSN(shl,  0, 0b010101, /* isSHR = */ false);
2446   INSN(sshr, 0, 0b000001, /* isSHR = */ true);
2447   INSN(ushr, 1, 0b000001, /* isSHR = */ true);
2448 
2449 #undef INSN
2450 
2451   void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2452     starti;
2453     /* The encodings for the immh:immb fields (bits 22:16) are
2454      *   0001 xxx       8H, 8B/16b shift = xxx
2455      *   001x xxx       4S, 4H/8H  shift = xxxx
2456      *   01xx xxx       2D, 2S/4S  shift = xxxxx
2457      *   1xxx xxx       RESERVED
2458      */
2459     assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2460     assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2461     f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2462     f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2463   }
2464   void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn,  SIMD_Arrangement Tb, int shift) {
2465     ushll(Vd, Ta, Vn, Tb, shift);
2466   }
2467 
2468   // Move from general purpose register
2469   //   mov  Vd.T[index], Rn
2470   void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2471     starti;
2472     f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2473     f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0);
2474   }
2475 
2476   // Move to general purpose register
2477   //   mov  Rd, Vn.T[index]
2478   void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2479     starti;
2480     f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2481     f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2482     f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2483   }
2484 
2485   void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2486     starti;
2487     assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) ||
2488            (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier");
2489     int size = (Ta == T1Q) ? 0b11 : 0b00;
2490     f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22);
2491     f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0);
2492   }
2493   void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2494     assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier");
2495     pmull(Vd, Ta, Vn, Vm, Tb);
2496   }
2497 
2498   void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2499     starti;
2500     int size_b = (int)Tb >> 1;
2501     int size_a = (int)Ta >> 1;
2502     assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2503     f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2504     f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2505   }
2506 
2507   void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2508   {
2509     starti;
2510     assert(T != T1D, "reserved encoding");
2511     f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2512     f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0);
2513   }
2514 
2515   void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2516   {
2517     starti;
2518     assert(T != T1D, "reserved encoding");
2519     f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2520     f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2521     f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2522   }
2523 
2524   // AdvSIMD ZIP/UZP/TRN
2525 #define INSN(NAME, opcode)                                              \
2526   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2527     starti;                                                             \
2528     f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0, 15);                  \
2529     f(opcode, 14, 12), f(0b10, 11, 10);                                 \
2530     rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);                                   \
2531     f(T & 1, 30), f(T >> 1, 23, 22);                                    \
2532   }
2533 
2534   INSN(uzp1, 0b001);
2535   INSN(trn1, 0b010);
2536   INSN(zip1, 0b011);
2537   INSN(uzp2, 0b101);
2538   INSN(trn2, 0b110);
2539   INSN(zip2, 0b111);
2540 
2541 #undef INSN
2542 
2543   // CRC32 instructions
2544 #define INSN(NAME, c, sf, sz)                                             \
2545   void NAME(Register Rd, Register Rn, Register Rm) {                      \
2546     starti;                                                               \
2547     f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12);       \
2548     f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0);                      \
2549   }
2550 
2551   INSN(crc32b,  0, 0, 0b00);
2552   INSN(crc32h,  0, 0, 0b01);
2553   INSN(crc32w,  0, 0, 0b10);
2554   INSN(crc32x,  0, 1, 0b11);
2555   INSN(crc32cb, 1, 0, 0b00);
2556   INSN(crc32ch, 1, 0, 0b01);
2557   INSN(crc32cw, 1, 0, 0b10);
2558   INSN(crc32cx, 1, 1, 0b11);
2559 
2560 #undef INSN
2561 
2562   // Table vector lookup
2563 #define INSN(NAME, op)                                                  \
2564   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \
2565     starti;                                                             \
2566     assert(T == T8B || T == T16B, "invalid arrangement");               \
2567     assert(0 < registers && registers <= 4, "invalid number of registers"); \
2568     f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \
2569     f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \
2570   }
2571 
2572   INSN(tbl, 0);
2573   INSN(tbx, 1);
2574 
2575 #undef INSN
2576 
2577   // AdvSIMD two-reg misc
2578 #define INSN(NAME, U, opcode)                                                       \
2579   void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {               \
2580        starti;                                                                      \
2581        assert((ASSERTION), MSG);                                                    \
2582        f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24);                   \
2583        f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12);             \
2584        f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0);                                       \
2585  }
2586 
2587 #define MSG "invalid arrangement"
2588 
2589 #define ASSERTION (T == T2S || T == T4S || T == T2D)
2590   INSN(fsqrt, 1, 0b11111);
2591   INSN(fabs,  0, 0b01111);
2592   INSN(fneg,  1, 0b01111);
2593 #undef ASSERTION
2594 
2595 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
2596   INSN(rev64, 0, 0b00000);
2597 #undef ASSERTION
2598 
2599 #define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H)
2600   INSN(rev32, 1, 0b00000);
2601 private:
2602   INSN(_rbit, 1, 0b00101);
2603 public:
2604 
2605 #undef ASSERTION
2606 
2607 #define ASSERTION (T == T8B || T == T16B)
2608   INSN(rev16, 0, 0b00001);
2609   // RBIT only allows T8B and T16B but encodes them oddly.  Argh...
2610   void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
2611     assert((ASSERTION), MSG);
2612     _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn);
2613   }
2614 #undef ASSERTION
2615 
2616 #undef MSG
2617 
2618 #undef INSN
2619 
2620 void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index)
2621   {
2622     starti;
2623     assert(T == T8B || T == T16B, "invalid arrangement");
2624     assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value");
2625     f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21);
2626     rf(Vm, 16), f(0, 15), f(index, 14, 11);
2627     f(0, 10), rf(Vn, 5), rf(Vd, 0);
2628   }
2629 
2630 /* Simulator extensions to the ISA
2631 
2632    haltsim
2633 
2634    takes no arguments, causes the sim to enter a debug break and then
2635    return from the simulator run() call with STATUS_HALT? The linking
2636    code will call fatal() when it sees STATUS_HALT.
2637 
2638    blrt Xn, Wm
2639    blrt Xn, #gpargs, #fpargs, #type
2640    Xn holds the 64 bit x86 branch_address
2641    call format is encoded either as immediate data in the call
2642    or in register Wm. In the latter case
2643      Wm[13..6] = #gpargs,
2644      Wm[5..2] = #fpargs,
2645      Wm[1,0] = #type
2646 
2647    calls the x86 code address 'branch_address' supplied in Xn passing
2648    arguments taken from the general and floating point registers according
2649    to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0
2650    or v0 according to the the return type #type' where
2651 
2652    address branch_address;
2653    uimm4 gpargs;
2654    uimm4 fpargs;
2655    enum ReturnType type;
2656 
2657    enum ReturnType
2658      {
2659        void_ret = 0,
2660        int_ret = 1,
2661        long_ret = 1,
2662        obj_ret = 1, // i.e. same as long
2663        float_ret = 2,
2664        double_ret = 3
2665      }
2666 
2667    notify
2668 
2669    notifies the simulator of a transfer of control. instr[14:0]
2670    identifies the type of change of control.
2671 
2672    0 ==> initial entry to a method.
2673 
2674    1 ==> return into a method from a submethod call.
2675 
2676    2 ==> exit out of Java method code.
2677 
2678    3 ==> start execution for a new bytecode.
2679 
2680    in cases 1 and 2 the simulator is expected to use a JVM callback to
2681    identify the name of the specific method being executed. in case 4
2682    the simulator is expected to use a JVM callback to identify the
2683    bytecode index.
2684 
2685    Instruction encodings
2686    ---------------------
2687 
2688    These are encoded in the space with instr[28:25] = 00 which is
2689    unallocated. Encodings are
2690 
2691                      10987654321098765432109876543210
2692    PSEUDO_HALT   = 0x11100000000000000000000000000000
2693    PSEUDO_BLRT  = 0x11000000000000000_______________
2694    PSEUDO_BLRTR = 0x1100000000000000100000__________
2695    PSEUDO_NOTIFY = 0x10100000000000000_______________
2696 
2697    instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY
2698 
2699    for BLRT
2700      instr[14,11] = #gpargs, instr[10,7] = #fpargs
2701      instr[6,5] = #type, instr[4,0] = Rn
2702    for BLRTR
2703      instr[9,5] = Rm, instr[4,0] = Rn
2704    for NOTIFY
2705      instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart
2706 */
2707 
2708   enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start };
2709 
2710   virtual void notify(int type) {
2711     if (UseBuiltinSim) {
2712       starti;
2713       //  109
2714       f(0b101, 31, 29);
2715       //  87654321098765
2716       f(0b00000000000000, 28, 15);
2717       f(type, 14, 0);
2718     }
2719   }
2720 
2721   void blrt(Register Rn, int gpargs, int fpargs, int type) {
2722     if (UseBuiltinSim) {
2723       starti;
2724       f(0b110, 31 ,29);
2725       f(0b00, 28, 25);
2726       //  4321098765
2727       f(0b0000000000, 24, 15);
2728       f(gpargs, 14, 11);
2729       f(fpargs, 10, 7);
2730       f(type, 6, 5);
2731       rf(Rn, 0);
2732     } else {
2733       blr(Rn);
2734     }
2735   }
2736 
2737   void blrt(Register Rn, Register Rm) {
2738     if (UseBuiltinSim) {
2739       starti;
2740       f(0b110, 31 ,29);
2741       f(0b00, 28, 25);
2742       //  4321098765
2743       f(0b0000000001, 24, 15);
2744       //  43210
2745       f(0b00000, 14, 10);
2746       rf(Rm, 5);
2747       rf(Rn, 0);
2748     } else {
2749       blr(Rn);
2750     }
2751   }
2752 
2753   void haltsim() {
2754     starti;
2755     f(0b111, 31 ,29);
2756     f(0b00, 28, 27);
2757     //  654321098765432109876543210
2758     f(0b000000000000000000000000000, 26, 0);
2759   }
2760 
2761   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2762   }
2763 
2764   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2765                                                 Register tmp,
2766                                                 int offset) {
2767     ShouldNotCallThis();
2768     return RegisterOrConstant();
2769   }
2770 
2771   // Stack overflow checking
2772   virtual void bang_stack_with_offset(int offset);
2773 
2774   static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2775   static bool operand_valid_for_add_sub_immediate(long imm);
2776   static bool operand_valid_for_float_immediate(double imm);
2777 
2778   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2779   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2780 };
2781 
2782 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2783                                              Assembler::Membar_mask_bits b) {
2784   return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2785 }
2786 
2787 Instruction_aarch64::~Instruction_aarch64() {
2788   assem->emit();
2789 }
2790 
2791 #undef starti
2792 
2793 // Invert a condition
2794 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2795   return Assembler::Condition(int(cond) ^ 1);
2796 }
2797 
2798 class BiasedLockingCounters;
2799 
2800 extern "C" void das(uint64_t start, int len);
2801 
2802 #endif // CPU_AARCH64_ASSEMBLER_AARCH64_HPP