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src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

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   1 /*
   2  * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.


 998     case T_BOOLEAN: {
 999       __ ldrb(dest->as_register(), as_Address(from_addr));
1000       break;
1001     }
1002 
1003     case T_CHAR:
1004       __ ldrh(dest->as_register(), as_Address(from_addr));
1005       break;
1006     case T_SHORT:
1007       __ ldrsh(dest->as_register(), as_Address(from_addr));
1008       break;
1009 
1010     default:
1011       ShouldNotReachHere();
1012   }
1013 
1014   if (type == T_ARRAY || type == T_OBJECT) {
1015     if (UseCompressedOops && !wide) {
1016       __ decode_heap_oop(dest->as_register());
1017     }
1018 
1019     if (!UseZGC) {
1020       // Load barrier has not yet been applied, so ZGC can't verify the oop here
1021       __ verify_oop(dest->as_register());
1022     }
1023   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1024     if (UseCompressedClassPointers) {
1025       __ decode_klass_not_null(dest->as_register());
1026     }
1027   }
1028 }
1029 
1030 
1031 int LIR_Assembler::array_element_size(BasicType type) const {
1032   int elem_size = type2aelembytes(type);
1033   return exact_log2(elem_size);
1034 }
1035 
1036 
1037 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1038   switch (op->code()) {
1039   case lir_idiv:
1040   case lir_irem:
1041     arithmetic_idiv(op->code(),
1042                     op->in_opr1(),


1061   }
1062 }
1063 
1064 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1065 #ifdef ASSERT
1066   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1067   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1068   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1069 #endif
1070 
1071   if (op->cond() == lir_cond_always) {
1072     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1073     __ b(*(op->label()));
1074   } else {
1075     Assembler::Condition acond;
1076     if (op->code() == lir_cond_float_branch) {
1077       bool is_unordered = (op->ublock() == op->block());
1078       // Assembler::EQ does not permit unordered branches, so we add
1079       // another branch here.  Likewise, Assembler::NE does not permit
1080       // ordered branches.
1081       if ((is_unordered && op->cond() == lir_cond_equal)
1082           || (!is_unordered && op->cond() == lir_cond_notEqual))
1083         __ br(Assembler::VS, *(op->ublock()->label()));
1084       switch(op->cond()) {
1085       case lir_cond_equal:        acond = Assembler::EQ; break;
1086       case lir_cond_notEqual:     acond = Assembler::NE; break;
1087       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1088       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1089       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1090       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1091       default:                    ShouldNotReachHere();
1092         acond = Assembler::EQ;  // unreachable
1093       }
1094     } else {
1095       switch (op->cond()) {
1096         case lir_cond_equal:        acond = Assembler::EQ; break;
1097         case lir_cond_notEqual:     acond = Assembler::NE; break;
1098         case lir_cond_less:         acond = Assembler::LT; break;
1099         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1100         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1101         case lir_cond_greater:      acond = Assembler::GT; break;
1102         case lir_cond_belowEqual:   acond = Assembler::LS; break;


1772             __ mov(dreg, zr);
1773           } else {
1774             // use rscratch1 as intermediate result register
1775             __ negs(rscratch1, lreg_lo);
1776             __ andr(dreg, lreg_lo, c - 1);
1777             __ andr(rscratch1, rscratch1, c - 1);
1778             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1779           }
1780           break;
1781         default:
1782           ShouldNotReachHere();
1783       }
1784     } else {
1785       ShouldNotReachHere();
1786     }
1787   } else if (left->is_single_fpu()) {
1788     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1789     switch (code) {
1790     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1791     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1792     case lir_mul_strictfp: // fall through
1793     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1794     case lir_div_strictfp: // fall through
1795     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1796     default:
1797       ShouldNotReachHere();
1798     }
1799   } else if (left->is_double_fpu()) {
1800     if (right->is_double_fpu()) {
1801       // fpu register - fpu register
1802       switch (code) {
1803       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1804       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1805       case lir_mul_strictfp: // fall through
1806       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1807       case lir_div_strictfp: // fall through
1808       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1809       default:
1810         ShouldNotReachHere();
1811       }
1812     } else {
1813       if (right->is_constant()) {
1814         ShouldNotReachHere();
1815       }
1816       ShouldNotReachHere();
1817     }
1818   } else if (left->is_single_stack() || left->is_address()) {
1819     assert(left == dest, "left and dest must be equal");
1820     ShouldNotReachHere();
1821   } else {
1822     ShouldNotReachHere();
1823   }
1824 }
1825 
1826 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1827 


2860   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2861 
2862   if (left->is_single_cpu()) {
2863     assert(dest->is_single_cpu(), "expect single result reg");
2864     __ negw(dest->as_register(), left->as_register());
2865   } else if (left->is_double_cpu()) {
2866     assert(dest->is_double_cpu(), "expect double result reg");
2867     __ neg(dest->as_register_lo(), left->as_register_lo());
2868   } else if (left->is_single_fpu()) {
2869     assert(dest->is_single_fpu(), "expect single float result reg");
2870     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2871   } else {
2872     assert(left->is_double_fpu(), "expect double float operand reg");
2873     assert(dest->is_double_fpu(), "expect double float result reg");
2874     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2875   }
2876 }
2877 
2878 
2879 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2880   if (patch_code != lir_patch_none) {
2881     deoptimize_trap(info);
2882     return;
2883   }
2884 
2885   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2886 }
2887 
2888 
2889 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2890   assert(!tmp->is_valid(), "don't need temporary");
2891 
2892   CodeBlob *cb = CodeCache::find_blob(dest);
2893   if (cb) {
2894     __ far_call(RuntimeAddress(dest));
2895   } else {
2896     __ mov(rscratch1, RuntimeAddress(dest));
2897     int len = args->length();
2898     int type = 0;
2899     if (! result->is_illegal()) {
2900       switch (result->type()) {
2901       case T_VOID:
2902         type = 0;
2903         break;
2904       case T_INT:


   1 /*
   2  * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.


 998     case T_BOOLEAN: {
 999       __ ldrb(dest->as_register(), as_Address(from_addr));
1000       break;
1001     }
1002 
1003     case T_CHAR:
1004       __ ldrh(dest->as_register(), as_Address(from_addr));
1005       break;
1006     case T_SHORT:
1007       __ ldrsh(dest->as_register(), as_Address(from_addr));
1008       break;
1009 
1010     default:
1011       ShouldNotReachHere();
1012   }
1013 
1014   if (type == T_ARRAY || type == T_OBJECT) {
1015     if (UseCompressedOops && !wide) {
1016       __ decode_heap_oop(dest->as_register());
1017     }
1018     __ verify_oop(dest->as_register());




1019   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1020     if (UseCompressedClassPointers) {
1021       __ decode_klass_not_null(dest->as_register());
1022     }
1023   }
1024 }
1025 
1026 
1027 int LIR_Assembler::array_element_size(BasicType type) const {
1028   int elem_size = type2aelembytes(type);
1029   return exact_log2(elem_size);
1030 }
1031 
1032 
1033 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1034   switch (op->code()) {
1035   case lir_idiv:
1036   case lir_irem:
1037     arithmetic_idiv(op->code(),
1038                     op->in_opr1(),


1057   }
1058 }
1059 
1060 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1061 #ifdef ASSERT
1062   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1063   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1064   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1065 #endif
1066 
1067   if (op->cond() == lir_cond_always) {
1068     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1069     __ b(*(op->label()));
1070   } else {
1071     Assembler::Condition acond;
1072     if (op->code() == lir_cond_float_branch) {
1073       bool is_unordered = (op->ublock() == op->block());
1074       // Assembler::EQ does not permit unordered branches, so we add
1075       // another branch here.  Likewise, Assembler::NE does not permit
1076       // ordered branches.
1077       if (is_unordered && op->cond() == lir_cond_equal
1078           || !is_unordered && op->cond() == lir_cond_notEqual)
1079         __ br(Assembler::VS, *(op->ublock()->label()));
1080       switch(op->cond()) {
1081       case lir_cond_equal:        acond = Assembler::EQ; break;
1082       case lir_cond_notEqual:     acond = Assembler::NE; break;
1083       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1084       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1085       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1086       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1087       default:                    ShouldNotReachHere();
1088         acond = Assembler::EQ;  // unreachable
1089       }
1090     } else {
1091       switch (op->cond()) {
1092         case lir_cond_equal:        acond = Assembler::EQ; break;
1093         case lir_cond_notEqual:     acond = Assembler::NE; break;
1094         case lir_cond_less:         acond = Assembler::LT; break;
1095         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1096         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1097         case lir_cond_greater:      acond = Assembler::GT; break;
1098         case lir_cond_belowEqual:   acond = Assembler::LS; break;


1768             __ mov(dreg, zr);
1769           } else {
1770             // use rscratch1 as intermediate result register
1771             __ negs(rscratch1, lreg_lo);
1772             __ andr(dreg, lreg_lo, c - 1);
1773             __ andr(rscratch1, rscratch1, c - 1);
1774             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1775           }
1776           break;
1777         default:
1778           ShouldNotReachHere();
1779       }
1780     } else {
1781       ShouldNotReachHere();
1782     }
1783   } else if (left->is_single_fpu()) {
1784     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1785     switch (code) {
1786     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1787     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;

1788     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;

1789     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1790     default:
1791       ShouldNotReachHere();
1792     }
1793   } else if (left->is_double_fpu()) {
1794     if (right->is_double_fpu()) {
1795       // cpu register - cpu register
1796       switch (code) {
1797       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1798       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;

1799       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;

1800       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1801       default:
1802         ShouldNotReachHere();
1803       }
1804     } else {
1805       if (right->is_constant()) {
1806         ShouldNotReachHere();
1807       }
1808       ShouldNotReachHere();
1809     }
1810   } else if (left->is_single_stack() || left->is_address()) {
1811     assert(left == dest, "left and dest must be equal");
1812     ShouldNotReachHere();
1813   } else {
1814     ShouldNotReachHere();
1815   }
1816 }
1817 
1818 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1819 


2852   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2853 
2854   if (left->is_single_cpu()) {
2855     assert(dest->is_single_cpu(), "expect single result reg");
2856     __ negw(dest->as_register(), left->as_register());
2857   } else if (left->is_double_cpu()) {
2858     assert(dest->is_double_cpu(), "expect double result reg");
2859     __ neg(dest->as_register_lo(), left->as_register_lo());
2860   } else if (left->is_single_fpu()) {
2861     assert(dest->is_single_fpu(), "expect single float result reg");
2862     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2863   } else {
2864     assert(left->is_double_fpu(), "expect double float operand reg");
2865     assert(dest->is_double_fpu(), "expect double float result reg");
2866     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2867   }
2868 }
2869 
2870 
2871 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2872   assert(patch_code == lir_patch_none, "Patch code not supported");




2873   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2874 }
2875 
2876 
2877 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2878   assert(!tmp->is_valid(), "don't need temporary");
2879 
2880   CodeBlob *cb = CodeCache::find_blob(dest);
2881   if (cb) {
2882     __ far_call(RuntimeAddress(dest));
2883   } else {
2884     __ mov(rscratch1, RuntimeAddress(dest));
2885     int len = args->length();
2886     int type = 0;
2887     if (! result->is_illegal()) {
2888       switch (result->type()) {
2889       case T_VOID:
2890         type = 0;
2891         break;
2892       case T_INT:


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