1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "memory/resourceArea.hpp"
  30 #include "runtime/java.hpp"
  31 #include "runtime/stubCodeGenerator.hpp"
  32 #include "utilities/macros.hpp"
  33 #include "vm_version_aarch64.hpp"
  34 
  35 #include OS_HEADER_INLINE(os)
  36 
  37 #ifndef BUILTIN_SIM
  38 #include <sys/auxv.h>
  39 #include <asm/hwcap.h>
  40 #else
  41 #define getauxval(hwcap) 0
  42 #endif
  43 
  44 #ifndef HWCAP_AES
  45 #define HWCAP_AES   (1<<3)
  46 #endif
  47 
  48 #ifndef HWCAP_PMULL
  49 #define HWCAP_PMULL (1<<4)
  50 #endif
  51 
  52 #ifndef HWCAP_SHA1
  53 #define HWCAP_SHA1  (1<<5)
  54 #endif
  55 
  56 #ifndef HWCAP_SHA2
  57 #define HWCAP_SHA2  (1<<6)
  58 #endif
  59 
  60 #ifndef HWCAP_CRC32
  61 #define HWCAP_CRC32 (1<<7)
  62 #endif
  63 
  64 #ifndef HWCAP_ATOMICS
  65 #define HWCAP_ATOMICS (1<<8)
  66 #endif
  67 
  68 int VM_Version::_cpu;
  69 int VM_Version::_model;
  70 int VM_Version::_model2;
  71 int VM_Version::_variant;
  72 int VM_Version::_revision;
  73 int VM_Version::_stepping;
  74 VM_Version::PsrInfo VM_Version::_psr_info   = { 0, };
  75 
  76 static BufferBlob* stub_blob;
  77 static const int stub_size = 550;
  78 
  79 extern "C" {
  80   typedef void (*getPsrInfo_stub_t)(void*);
  81 }
  82 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
  83 
  84 
  85 class VM_Version_StubGenerator: public StubCodeGenerator {
  86  public:
  87 
  88   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  89 
  90   address generate_getPsrInfo() {
  91     StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
  92 #   define __ _masm->
  93     address start = __ pc();
  94 
  95 #ifdef BUILTIN_SIM
  96     __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
  97 #endif
  98 
  99     // void getPsrInfo(VM_Version::PsrInfo* psr_info);
 100 
 101     address entry = __ pc();
 102 
 103     __ enter();
 104 
 105     __ get_dczid_el0(rscratch1);
 106     __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
 107 
 108     __ get_ctr_el0(rscratch1);
 109     __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
 110 
 111     __ leave();
 112     __ ret(lr);
 113 
 114 #   undef __
 115 
 116     return start;
 117   }
 118 };
 119 
 120 
 121 void VM_Version::get_processor_features() {
 122   _supports_cx8 = true;
 123   _supports_atomic_getset4 = true;
 124   _supports_atomic_getadd4 = true;
 125   _supports_atomic_getset8 = true;
 126   _supports_atomic_getadd8 = true;
 127 
 128   getPsrInfo_stub(&_psr_info);
 129 
 130   int dcache_line = VM_Version::dcache_line_size();
 131 
 132   // Limit AllocatePrefetchDistance so that it does not exceed the
 133   // constraint in AllocatePrefetchDistanceConstraintFunc.
 134   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
 135     FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
 136 
 137   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
 138     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
 139   if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
 140     FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
 141   if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
 142     FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
 143   if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
 144     FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
 145 
 146   if (PrefetchCopyIntervalInBytes != -1 &&
 147        ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
 148     warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
 149     PrefetchCopyIntervalInBytes &= ~7;
 150     if (PrefetchCopyIntervalInBytes >= 32768)
 151       PrefetchCopyIntervalInBytes = 32760;
 152   }
 153 
 154   if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
 155     warning("AllocatePrefetchDistance must be multiple of 8");
 156     AllocatePrefetchDistance &= ~7;
 157   }
 158 
 159   if (AllocatePrefetchStepSize & 7) {
 160     warning("AllocatePrefetchStepSize must be multiple of 8");
 161     AllocatePrefetchStepSize &= ~7;
 162   }
 163 
 164   if (SoftwarePrefetchHintDistance != -1 &&
 165        (SoftwarePrefetchHintDistance & 7)) {
 166     warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
 167     SoftwarePrefetchHintDistance &= ~7;
 168   }
 169 
 170   unsigned long auxv = getauxval(AT_HWCAP);
 171 
 172   char buf[512];
 173 
 174   _features = auxv;
 175 
 176   int cpu_lines = 0;
 177   if (FILE *f = fopen("/proc/cpuinfo", "r")) {
 178     char buf[128], *p;
 179     while (fgets(buf, sizeof (buf), f) != NULL) {
 180       if (p = strchr(buf, ':')) {
 181         long v = strtol(p+1, NULL, 0);
 182         if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
 183           _cpu = v;
 184           cpu_lines++;
 185         } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
 186           _variant = v;
 187         } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
 188           if (_model != v)  _model2 = _model;
 189           _model = v;
 190         } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
 191           _revision = v;
 192         }
 193       }
 194     }
 195     fclose(f);
 196   }
 197 
 198   // Enable vendor specific features
 199 
 200   // Ampere eMAG
 201   if (_cpu == CPU_AMCC && (_model == 0) && (_variant == 0x3)) {
 202     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
 203       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
 204     }
 205     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
 206       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
 207     }
 208     if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
 209       FLAG_SET_DEFAULT(UseSIMDForArrayEquals, !(_revision == 1 || _revision == 2));
 210     }
 211   }
 212 
 213   // ThunderX
 214   if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
 215     if (_variant == 0) _features |= CPU_DMB_ATOMICS;
 216     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
 217       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
 218     }
 219     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
 220       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
 221     }
 222     if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
 223       FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
 224     }
 225   }
 226 
 227   // ThunderX2
 228   if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
 229       (_cpu == CPU_BROADCOM && (_model == 0x516))) {
 230     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
 231       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
 232     }
 233     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
 234       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
 235     }
 236   }
 237 
 238   // HiSilicon TSV110
 239   if (_cpu == CPU_HISILICON && _model == 0xd01) {
 240     if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
 241       FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
 242     }
 243     if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
 244       FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
 245     }
 246   }
 247 
 248   // Cortex A53
 249   if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
 250     _features |= CPU_A53MAC;
 251     if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
 252       FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
 253     }
 254   }
 255 
 256   // Cortex A73
 257   if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
 258     if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
 259       FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
 260     }
 261     // A73 is faster with short-and-easy-for-speculative-execution-loop
 262     if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
 263       FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
 264     }
 265   }
 266 
 267   if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
 268   // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
 269   // we assume the worst and assume we could be on a big little system and have
 270   // undisclosed A53 cores which we could be swapped to at any stage
 271   if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
 272 
 273   sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
 274   if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
 275   if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
 276   if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
 277   if (auxv & HWCAP_AES)   strcat(buf, ", aes");
 278   if (auxv & HWCAP_SHA1)  strcat(buf, ", sha1");
 279   if (auxv & HWCAP_SHA2)  strcat(buf, ", sha256");
 280   if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
 281 
 282   _features_string = os::strdup(buf);
 283 
 284   if (FLAG_IS_DEFAULT(UseCRC32)) {
 285     UseCRC32 = (auxv & HWCAP_CRC32) != 0;
 286   }
 287 
 288   if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
 289     warning("UseCRC32 specified, but not supported on this CPU");
 290     FLAG_SET_DEFAULT(UseCRC32, false);
 291   }
 292 
 293   if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
 294     FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
 295   }
 296 
 297   if (UseVectorizedMismatchIntrinsic) {
 298     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
 299     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
 300   }
 301 
 302   if (auxv & HWCAP_ATOMICS) {
 303     if (FLAG_IS_DEFAULT(UseLSE))
 304       FLAG_SET_DEFAULT(UseLSE, true);
 305   } else {
 306     if (UseLSE) {
 307       warning("UseLSE specified, but not supported on this CPU");
 308       FLAG_SET_DEFAULT(UseLSE, false);
 309     }
 310   }
 311 
 312   if (auxv & HWCAP_AES) {
 313     UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
 314     UseAESIntrinsics =
 315         UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
 316     if (UseAESIntrinsics && !UseAES) {
 317       warning("UseAESIntrinsics enabled, but UseAES not, enabling");
 318       UseAES = true;
 319     }
 320   } else {
 321     if (UseAES) {
 322       warning("UseAES specified, but not supported on this CPU");
 323       FLAG_SET_DEFAULT(UseAES, false);
 324     }
 325     if (UseAESIntrinsics) {
 326       warning("UseAESIntrinsics specified, but not supported on this CPU");
 327       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 328     }
 329   }
 330 
 331   if (UseAESCTRIntrinsics) {
 332     warning("AES/CTR intrinsics are not available on this CPU");
 333     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 334   }
 335 
 336   if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 337     UseCRC32Intrinsics = true;
 338   }
 339 
 340   if (auxv & HWCAP_CRC32) {
 341     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 342       FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 343     }
 344   } else if (UseCRC32CIntrinsics) {
 345     warning("CRC32C is not available on the CPU");
 346     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 347   }
 348 
 349   if (FLAG_IS_DEFAULT(UseFMA)) {
 350     FLAG_SET_DEFAULT(UseFMA, true);
 351   }
 352 
 353   if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
 354     if (FLAG_IS_DEFAULT(UseSHA)) {
 355       FLAG_SET_DEFAULT(UseSHA, true);
 356     }
 357   } else if (UseSHA) {
 358     warning("SHA instructions are not available on this CPU");
 359     FLAG_SET_DEFAULT(UseSHA, false);
 360   }
 361 
 362   if (UseSHA && (auxv & HWCAP_SHA1)) {
 363     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 364       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 365     }
 366   } else if (UseSHA1Intrinsics) {
 367     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 368     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 369   }
 370 
 371   if (UseSHA && (auxv & HWCAP_SHA2)) {
 372     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 373       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 374     }
 375   } else if (UseSHA256Intrinsics) {
 376     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 377     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 378   }
 379 
 380   if (UseSHA512Intrinsics) {
 381     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 382     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 383   }
 384 
 385   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 386     FLAG_SET_DEFAULT(UseSHA, false);
 387   }
 388 
 389   if (auxv & HWCAP_PMULL) {
 390     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 391       FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
 392     }
 393   } else if (UseGHASHIntrinsics) {
 394     warning("GHASH intrinsics are not available on this CPU");
 395     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 396   }
 397 
 398   if (is_zva_enabled()) {
 399     if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
 400       FLAG_SET_DEFAULT(UseBlockZeroing, true);
 401     }
 402     if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
 403       FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
 404     }
 405   } else if (UseBlockZeroing) {
 406     warning("DC ZVA is not available on this CPU");
 407     FLAG_SET_DEFAULT(UseBlockZeroing, false);
 408   }
 409 
 410   // This machine allows unaligned memory accesses
 411   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
 412     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
 413   }
 414 
 415   if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
 416     UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
 417   }
 418 
 419   if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 420     UsePopCountInstruction = true;
 421   }
 422 
 423 #ifdef COMPILER2
 424   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
 425     UseMultiplyToLenIntrinsic = true;
 426   }
 427 
 428   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
 429     UseSquareToLenIntrinsic = true;
 430   }
 431 
 432   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
 433     UseMulAddIntrinsic = true;
 434   }
 435 
 436   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
 437     UseMontgomeryMultiplyIntrinsic = true;
 438   }
 439   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
 440     UseMontgomerySquareIntrinsic = true;
 441   }
 442 
 443   if (FLAG_IS_DEFAULT(OptoScheduling)) {
 444     OptoScheduling = true;
 445   }
 446 #endif
 447 }
 448 
 449 void VM_Version::initialize() {
 450   ResourceMark rm;
 451 
 452   stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
 453   if (stub_blob == NULL) {
 454     vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
 455   }
 456 
 457   CodeBuffer c(stub_blob);
 458   VM_Version_StubGenerator g(&c);
 459   getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
 460                                    g.generate_getPsrInfo());
 461 
 462   get_processor_features();
 463 
 464   UNSUPPORTED_OPTION(CriticalJNINatives);
 465 }