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src/hotspot/cpu/aarch64/vm_version_aarch64.hpp

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   1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP
  27 #define CPU_AARCH64_VM_VERSION_AARCH64_HPP
  28 
  29 #include "runtime/globals_extension.hpp"
  30 #include "runtime/vm_version.hpp"
  31 #include "utilities/sizes.hpp"
  32 
  33 class VM_Version : public Abstract_VM_Version {
  34   friend class JVMCIVMStructs;
  35 
  36 protected:
  37   static int _cpu;
  38   static int _model;
  39   static int _model2;
  40   static int _variant;
  41   static int _revision;
  42   static int _stepping;
  43   static bool _dcpop;
  44   struct PsrInfo {
  45     uint32_t dczid_el0;
  46     uint32_t ctr_el0;
  47   };
  48   static PsrInfo _psr_info;
  49   static void get_processor_features();
  50 
  51 public:
  52   // Initialization
  53   static void initialize();
  54 
  55   // Asserts
  56   static void assert_is_initialized() {
  57   }
  58 
  59   static bool expensive_load(int ld_size, int scale) {
  60     if (cpu_family() == CPU_ARM) {
  61       // Half-word load with index shift by 1 (aka scale is 2) has
  62       // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
  63       if (ld_size == 2 && scale == 2) {


  89   enum Feature_Flag {
  90     CPU_FP           = (1<<0),
  91     CPU_ASIMD        = (1<<1),
  92     CPU_EVTSTRM      = (1<<2),
  93     CPU_AES          = (1<<3),
  94     CPU_PMULL        = (1<<4),
  95     CPU_SHA1         = (1<<5),
  96     CPU_SHA2         = (1<<6),
  97     CPU_CRC32        = (1<<7),
  98     CPU_LSE          = (1<<8),
  99     CPU_STXR_PREFETCH= (1 << 29),
 100     CPU_A53MAC       = (1 << 30),
 101     CPU_DMB_ATOMICS  = (1 << 31),
 102   };
 103 
 104   static int cpu_family()                     { return _cpu; }
 105   static int cpu_model()                      { return _model; }
 106   static int cpu_model2()                     { return _model2; }
 107   static int cpu_variant()                    { return _variant; }
 108   static int cpu_revision()                   { return _revision; }
 109   static bool supports_dcpop()                { return _dcpop; }
 110   static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); }
 111   static ByteSize ctr_el0_offset()   { return byte_offset_of(PsrInfo, ctr_el0); }
 112   static bool is_zva_enabled() {
 113     // Check the DZP bit (bit 4) of dczid_el0 is zero
 114     // and block size (bit 0~3) is not zero.
 115     return ((_psr_info.dczid_el0 & 0x10) == 0 &&
 116             (_psr_info.dczid_el0 & 0xf) != 0);
 117   }
 118   static int zva_length() {
 119     assert(is_zva_enabled(), "ZVA not available");
 120     return 4 << (_psr_info.dczid_el0 & 0xf);
 121   }
 122   static int icache_line_size() {
 123     return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4;
 124   }
 125   static int dcache_line_size() {
 126     return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4;
 127   }
 128   static bool supports_fast_class_init_checks() { return true; }
 129 };
 130 
 131 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP
   1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP
  27 #define CPU_AARCH64_VM_VERSION_AARCH64_HPP
  28 
  29 #include "runtime/globals_extension.hpp"
  30 #include "runtime/vm_version.hpp"
  31 #include "utilities/sizes.hpp"
  32 
  33 class VM_Version : public Abstract_VM_Version {
  34   friend class JVMCIVMStructs;
  35 
  36 protected:
  37   static int _cpu;
  38   static int _model;
  39   static int _model2;
  40   static int _variant;
  41   static int _revision;
  42   static int _stepping;
  43 
  44   struct PsrInfo {
  45     uint32_t dczid_el0;
  46     uint32_t ctr_el0;
  47   };
  48   static PsrInfo _psr_info;
  49   static void get_processor_features();
  50 
  51 public:
  52   // Initialization
  53   static void initialize();
  54 
  55   // Asserts
  56   static void assert_is_initialized() {
  57   }
  58 
  59   static bool expensive_load(int ld_size, int scale) {
  60     if (cpu_family() == CPU_ARM) {
  61       // Half-word load with index shift by 1 (aka scale is 2) has
  62       // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
  63       if (ld_size == 2 && scale == 2) {


  89   enum Feature_Flag {
  90     CPU_FP           = (1<<0),
  91     CPU_ASIMD        = (1<<1),
  92     CPU_EVTSTRM      = (1<<2),
  93     CPU_AES          = (1<<3),
  94     CPU_PMULL        = (1<<4),
  95     CPU_SHA1         = (1<<5),
  96     CPU_SHA2         = (1<<6),
  97     CPU_CRC32        = (1<<7),
  98     CPU_LSE          = (1<<8),
  99     CPU_STXR_PREFETCH= (1 << 29),
 100     CPU_A53MAC       = (1 << 30),
 101     CPU_DMB_ATOMICS  = (1 << 31),
 102   };
 103 
 104   static int cpu_family()                     { return _cpu; }
 105   static int cpu_model()                      { return _model; }
 106   static int cpu_model2()                     { return _model2; }
 107   static int cpu_variant()                    { return _variant; }
 108   static int cpu_revision()                   { return _revision; }

 109   static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); }
 110   static ByteSize ctr_el0_offset()   { return byte_offset_of(PsrInfo, ctr_el0); }
 111   static bool is_zva_enabled() {
 112     // Check the DZP bit (bit 4) of dczid_el0 is zero
 113     // and block size (bit 0~3) is not zero.
 114     return ((_psr_info.dczid_el0 & 0x10) == 0 &&
 115             (_psr_info.dczid_el0 & 0xf) != 0);
 116   }
 117   static int zva_length() {
 118     assert(is_zva_enabled(), "ZVA not available");
 119     return 4 << (_psr_info.dczid_el0 & 0xf);
 120   }
 121   static int icache_line_size() {
 122     return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4;
 123   }
 124   static int dcache_line_size() {
 125     return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4;
 126   }

 127 };
 128 
 129 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP
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