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src/hotspot/cpu/arm/arm.ad

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5259   ins_encode( /*empty encoding*/ );
5260   ins_pipe(empty);
5261 %}
5262 
5263 
5264 instruct castPP( iRegP dst ) %{
5265   match(Set dst (CastPP dst));
5266   format %{ "! castPP of $dst" %}
5267   ins_encode( /*empty encoding*/ );
5268   ins_pipe(empty);
5269 %}
5270 
5271 instruct castII( iRegI dst ) %{
5272   match(Set dst (CastII dst));
5273   format %{ "! castII of $dst" %}
5274   ins_encode( /*empty encoding*/ );
5275   ins_cost(0);
5276   ins_pipe(empty);
5277 %}
5278 
5279 instruct castLL( iRegL dst ) %{
5280   match(Set dst (CastLL dst));
5281   format %{ "! castLL of $dst" %}
5282   ins_encode( /*empty encoding*/ );
5283   ins_cost(0);
5284   ins_pipe(empty);
5285 %}
5286 
5287 //----------Arithmetic Instructions--------------------------------------------
5288 // Addition Instructions
5289 // Register Addition
5290 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
5291   match(Set dst (AddI src1 src2));
5292 
5293   size(4);
5294   format %{ "add_32 $dst,$src1,$src2\t! int" %}
5295   ins_encode %{
5296     __ add_32($dst$$Register, $src1$$Register, $src2$$Register);
5297   %}
5298   ins_pipe(ialu_reg_reg);
5299 %}
5300 
5301 instruct addshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
5302   match(Set dst (AddI (LShiftI src1 src2) src3));
5303 
5304   size(4);
5305   format %{ "add_32 $dst,$src3,$src1<<$src2\t! int" %}
5306   ins_encode %{




5259   ins_encode( /*empty encoding*/ );
5260   ins_pipe(empty);
5261 %}
5262 
5263 
5264 instruct castPP( iRegP dst ) %{
5265   match(Set dst (CastPP dst));
5266   format %{ "! castPP of $dst" %}
5267   ins_encode( /*empty encoding*/ );
5268   ins_pipe(empty);
5269 %}
5270 
5271 instruct castII( iRegI dst ) %{
5272   match(Set dst (CastII dst));
5273   format %{ "! castII of $dst" %}
5274   ins_encode( /*empty encoding*/ );
5275   ins_cost(0);
5276   ins_pipe(empty);
5277 %}
5278 








5279 //----------Arithmetic Instructions--------------------------------------------
5280 // Addition Instructions
5281 // Register Addition
5282 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
5283   match(Set dst (AddI src1 src2));
5284 
5285   size(4);
5286   format %{ "add_32 $dst,$src1,$src2\t! int" %}
5287   ins_encode %{
5288     __ add_32($dst$$Register, $src1$$Register, $src2$$Register);
5289   %}
5290   ins_pipe(ialu_reg_reg);
5291 %}
5292 
5293 instruct addshlI_reg_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3) %{
5294   match(Set dst (AddI (LShiftI src1 src2) src3));
5295 
5296   size(4);
5297   format %{ "add_32 $dst,$src3,$src1<<$src2\t! int" %}
5298   ins_encode %{


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