1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2019, SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "compiler/disassembler.hpp"
  29 #include "gc/shared/collectedHeap.inline.hpp"
  30 #include "gc/shared/barrierSet.hpp"
  31 #include "gc/shared/barrierSetAssembler.hpp"
  32 #include "interpreter/interpreter.hpp"
  33 #include "memory/resourceArea.hpp"
  34 #include "nativeInst_ppc.hpp"
  35 #include "prims/methodHandles.hpp"
  36 #include "runtime/biasedLocking.hpp"
  37 #include "runtime/icache.hpp"
  38 #include "runtime/interfaceSupport.inline.hpp"
  39 #include "runtime/objectMonitor.hpp"
  40 #include "runtime/os.hpp"
  41 #include "runtime/safepoint.hpp"
  42 #include "runtime/safepointMechanism.hpp"
  43 #include "runtime/sharedRuntime.hpp"
  44 #include "runtime/stubRoutines.hpp"
  45 #include "utilities/macros.hpp"
  46 #ifdef COMPILER2
  47 #include "opto/intrinsicnode.hpp"
  48 #endif
  49 
  50 #ifdef PRODUCT
  51 #define BLOCK_COMMENT(str) // nothing
  52 #else
  53 #define BLOCK_COMMENT(str) block_comment(str)
  54 #endif
  55 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  56 
  57 #ifdef ASSERT
  58 // On RISC, there's no benefit to verifying instruction boundaries.
  59 bool AbstractAssembler::pd_check_instruction_mark() { return false; }
  60 #endif
  61 
  62 void MacroAssembler::ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop) {
  63   assert(Assembler::is_simm(si31, 31) && si31 >= 0, "si31 out of range");
  64   if (Assembler::is_simm(si31, 16)) {
  65     ld(d, si31, a);
  66     if (emit_filler_nop) nop();
  67   } else {
  68     const int hi = MacroAssembler::largeoffset_si16_si16_hi(si31);
  69     const int lo = MacroAssembler::largeoffset_si16_si16_lo(si31);
  70     addis(d, a, hi);
  71     ld(d, lo, d);
  72   }
  73 }
  74 
  75 void MacroAssembler::ld_largeoffset(Register d, int si31, Register a, int emit_filler_nop) {
  76   assert_different_registers(d, a);
  77   ld_largeoffset_unchecked(d, si31, a, emit_filler_nop);
  78 }
  79 
  80 void MacroAssembler::load_sized_value(Register dst, RegisterOrConstant offs, Register base,
  81                                       size_t size_in_bytes, bool is_signed) {
  82   switch (size_in_bytes) {
  83   case  8:              ld(dst, offs, base);                         break;
  84   case  4:  is_signed ? lwa(dst, offs, base) : lwz(dst, offs, base); break;
  85   case  2:  is_signed ? lha(dst, offs, base) : lhz(dst, offs, base); break;
  86   case  1:  lbz(dst, offs, base); if (is_signed) extsb(dst, dst);    break; // lba doesn't exist :(
  87   default:  ShouldNotReachHere();
  88   }
  89 }
  90 
  91 void MacroAssembler::store_sized_value(Register dst, RegisterOrConstant offs, Register base,
  92                                        size_t size_in_bytes) {
  93   switch (size_in_bytes) {
  94   case  8:  std(dst, offs, base); break;
  95   case  4:  stw(dst, offs, base); break;
  96   case  2:  sth(dst, offs, base); break;
  97   case  1:  stb(dst, offs, base); break;
  98   default:  ShouldNotReachHere();
  99   }
 100 }
 101 
 102 void MacroAssembler::align(int modulus, int max, int rem) {
 103   int padding = (rem + modulus - (offset() % modulus)) % modulus;
 104   if (padding > max) return;
 105   for (int c = (padding >> 2); c > 0; --c) { nop(); }
 106 }
 107 
 108 // Issue instructions that calculate given TOC from global TOC.
 109 void MacroAssembler::calculate_address_from_global_toc(Register dst, address addr, bool hi16, bool lo16,
 110                                                        bool add_relocation, bool emit_dummy_addr) {
 111   int offset = -1;
 112   if (emit_dummy_addr) {
 113     offset = -128; // dummy address
 114   } else if (addr != (address)(intptr_t)-1) {
 115     offset = MacroAssembler::offset_to_global_toc(addr);
 116   }
 117 
 118   if (hi16) {
 119     addis(dst, R29_TOC, MacroAssembler::largeoffset_si16_si16_hi(offset));
 120   }
 121   if (lo16) {
 122     if (add_relocation) {
 123       // Relocate at the addi to avoid confusion with a load from the method's TOC.
 124       relocate(internal_word_Relocation::spec(addr));
 125     }
 126     addi(dst, dst, MacroAssembler::largeoffset_si16_si16_lo(offset));
 127   }
 128 }
 129 
 130 address MacroAssembler::patch_calculate_address_from_global_toc_at(address a, address bound, address addr) {
 131   const int offset = MacroAssembler::offset_to_global_toc(addr);
 132 
 133   const address inst2_addr = a;
 134   const int inst2 = *(int *)inst2_addr;
 135 
 136   // The relocation points to the second instruction, the addi,
 137   // and the addi reads and writes the same register dst.
 138   const int dst = inv_rt_field(inst2);
 139   assert(is_addi(inst2) && inv_ra_field(inst2) == dst, "must be addi reading and writing dst");
 140 
 141   // Now, find the preceding addis which writes to dst.
 142   int inst1 = 0;
 143   address inst1_addr = inst2_addr - BytesPerInstWord;
 144   while (inst1_addr >= bound) {
 145     inst1 = *(int *) inst1_addr;
 146     if (is_addis(inst1) && inv_rt_field(inst1) == dst) {
 147       // Stop, found the addis which writes dst.
 148       break;
 149     }
 150     inst1_addr -= BytesPerInstWord;
 151   }
 152 
 153   assert(is_addis(inst1) && inv_ra_field(inst1) == 29 /* R29 */, "source must be global TOC");
 154   set_imm((int *)inst1_addr, MacroAssembler::largeoffset_si16_si16_hi(offset));
 155   set_imm((int *)inst2_addr, MacroAssembler::largeoffset_si16_si16_lo(offset));
 156   return inst1_addr;
 157 }
 158 
 159 address MacroAssembler::get_address_of_calculate_address_from_global_toc_at(address a, address bound) {
 160   const address inst2_addr = a;
 161   const int inst2 = *(int *)inst2_addr;
 162 
 163   // The relocation points to the second instruction, the addi,
 164   // and the addi reads and writes the same register dst.
 165   const int dst = inv_rt_field(inst2);
 166   assert(is_addi(inst2) && inv_ra_field(inst2) == dst, "must be addi reading and writing dst");
 167 
 168   // Now, find the preceding addis which writes to dst.
 169   int inst1 = 0;
 170   address inst1_addr = inst2_addr - BytesPerInstWord;
 171   while (inst1_addr >= bound) {
 172     inst1 = *(int *) inst1_addr;
 173     if (is_addis(inst1) && inv_rt_field(inst1) == dst) {
 174       // stop, found the addis which writes dst
 175       break;
 176     }
 177     inst1_addr -= BytesPerInstWord;
 178   }
 179 
 180   assert(is_addis(inst1) && inv_ra_field(inst1) == 29 /* R29 */, "source must be global TOC");
 181 
 182   int offset = (get_imm(inst1_addr, 0) << 16) + get_imm(inst2_addr, 0);
 183   // -1 is a special case
 184   if (offset == -1) {
 185     return (address)(intptr_t)-1;
 186   } else {
 187     return global_toc() + offset;
 188   }
 189 }
 190 
 191 #ifdef _LP64
 192 // Patch compressed oops or klass constants.
 193 // Assembler sequence is
 194 // 1) compressed oops:
 195 //    lis  rx = const.hi
 196 //    ori rx = rx | const.lo
 197 // 2) compressed klass:
 198 //    lis  rx = const.hi
 199 //    clrldi rx = rx & 0xFFFFffff // clearMS32b, optional
 200 //    ori rx = rx | const.lo
 201 // Clrldi will be passed by.
 202 address MacroAssembler::patch_set_narrow_oop(address a, address bound, narrowOop data) {
 203   assert(UseCompressedOops, "Should only patch compressed oops");
 204 
 205   const address inst2_addr = a;
 206   const int inst2 = *(int *)inst2_addr;
 207 
 208   // The relocation points to the second instruction, the ori,
 209   // and the ori reads and writes the same register dst.
 210   const int dst = inv_rta_field(inst2);
 211   assert(is_ori(inst2) && inv_rs_field(inst2) == dst, "must be ori reading and writing dst");
 212   // Now, find the preceding addis which writes to dst.
 213   int inst1 = 0;
 214   address inst1_addr = inst2_addr - BytesPerInstWord;
 215   bool inst1_found = false;
 216   while (inst1_addr >= bound) {
 217     inst1 = *(int *)inst1_addr;
 218     if (is_lis(inst1) && inv_rs_field(inst1) == dst) { inst1_found = true; break; }
 219     inst1_addr -= BytesPerInstWord;
 220   }
 221   assert(inst1_found, "inst is not lis");
 222 
 223   int xc = (data >> 16) & 0xffff;
 224   int xd = (data >>  0) & 0xffff;
 225 
 226   set_imm((int *)inst1_addr, (short)(xc)); // see enc_load_con_narrow_hi/_lo
 227   set_imm((int *)inst2_addr,        (xd)); // unsigned int
 228   return inst1_addr;
 229 }
 230 
 231 // Get compressed oop or klass constant.
 232 narrowOop MacroAssembler::get_narrow_oop(address a, address bound) {
 233   assert(UseCompressedOops, "Should only patch compressed oops");
 234 
 235   const address inst2_addr = a;
 236   const int inst2 = *(int *)inst2_addr;
 237 
 238   // The relocation points to the second instruction, the ori,
 239   // and the ori reads and writes the same register dst.
 240   const int dst = inv_rta_field(inst2);
 241   assert(is_ori(inst2) && inv_rs_field(inst2) == dst, "must be ori reading and writing dst");
 242   // Now, find the preceding lis which writes to dst.
 243   int inst1 = 0;
 244   address inst1_addr = inst2_addr - BytesPerInstWord;
 245   bool inst1_found = false;
 246 
 247   while (inst1_addr >= bound) {
 248     inst1 = *(int *) inst1_addr;
 249     if (is_lis(inst1) && inv_rs_field(inst1) == dst) { inst1_found = true; break;}
 250     inst1_addr -= BytesPerInstWord;
 251   }
 252   assert(inst1_found, "inst is not lis");
 253 
 254   uint xl = ((unsigned int) (get_imm(inst2_addr, 0) & 0xffff));
 255   uint xh = (((get_imm(inst1_addr, 0)) & 0xffff) << 16);
 256 
 257   return (int) (xl | xh);
 258 }
 259 #endif // _LP64
 260 
 261 // Returns true if successful.
 262 bool MacroAssembler::load_const_from_method_toc(Register dst, AddressLiteral& a,
 263                                                 Register toc, bool fixed_size) {
 264   int toc_offset = 0;
 265   // Use RelocationHolder::none for the constant pool entry, otherwise
 266   // we will end up with a failing NativeCall::verify(x) where x is
 267   // the address of the constant pool entry.
 268   // FIXME: We should insert relocation information for oops at the constant
 269   // pool entries instead of inserting it at the loads; patching of a constant
 270   // pool entry should be less expensive.
 271   address const_address = address_constant((address)a.value(), RelocationHolder::none);
 272   if (const_address == NULL) { return false; } // allocation failure
 273   // Relocate at the pc of the load.
 274   relocate(a.rspec());
 275   toc_offset = (int)(const_address - code()->consts()->start());
 276   ld_largeoffset_unchecked(dst, toc_offset, toc, fixed_size);
 277   return true;
 278 }
 279 
 280 bool MacroAssembler::is_load_const_from_method_toc_at(address a) {
 281   const address inst1_addr = a;
 282   const int inst1 = *(int *)inst1_addr;
 283 
 284    // The relocation points to the ld or the addis.
 285    return (is_ld(inst1)) ||
 286           (is_addis(inst1) && inv_ra_field(inst1) != 0);
 287 }
 288 
 289 int MacroAssembler::get_offset_of_load_const_from_method_toc_at(address a) {
 290   assert(is_load_const_from_method_toc_at(a), "must be load_const_from_method_toc");
 291 
 292   const address inst1_addr = a;
 293   const int inst1 = *(int *)inst1_addr;
 294 
 295   if (is_ld(inst1)) {
 296     return inv_d1_field(inst1);
 297   } else if (is_addis(inst1)) {
 298     const int dst = inv_rt_field(inst1);
 299 
 300     // Now, find the succeeding ld which reads and writes to dst.
 301     address inst2_addr = inst1_addr + BytesPerInstWord;
 302     int inst2 = 0;
 303     while (true) {
 304       inst2 = *(int *) inst2_addr;
 305       if (is_ld(inst2) && inv_ra_field(inst2) == dst && inv_rt_field(inst2) == dst) {
 306         // Stop, found the ld which reads and writes dst.
 307         break;
 308       }
 309       inst2_addr += BytesPerInstWord;
 310     }
 311     return (inv_d1_field(inst1) << 16) + inv_d1_field(inst2);
 312   }
 313   ShouldNotReachHere();
 314   return 0;
 315 }
 316 
 317 // Get the constant from a `load_const' sequence.
 318 long MacroAssembler::get_const(address a) {
 319   assert(is_load_const_at(a), "not a load of a constant");
 320   const int *p = (const int*) a;
 321   unsigned long x = (((unsigned long) (get_imm(a,0) & 0xffff)) << 48);
 322   if (is_ori(*(p+1))) {
 323     x |= (((unsigned long) (get_imm(a,1) & 0xffff)) << 32);
 324     x |= (((unsigned long) (get_imm(a,3) & 0xffff)) << 16);
 325     x |= (((unsigned long) (get_imm(a,4) & 0xffff)));
 326   } else if (is_lis(*(p+1))) {
 327     x |= (((unsigned long) (get_imm(a,2) & 0xffff)) << 32);
 328     x |= (((unsigned long) (get_imm(a,1) & 0xffff)) << 16);
 329     x |= (((unsigned long) (get_imm(a,3) & 0xffff)));
 330   } else {
 331     ShouldNotReachHere();
 332     return (long) 0;
 333   }
 334   return (long) x;
 335 }
 336 
 337 // Patch the 64 bit constant of a `load_const' sequence. This is a low
 338 // level procedure. It neither flushes the instruction cache nor is it
 339 // mt safe.
 340 void MacroAssembler::patch_const(address a, long x) {
 341   assert(is_load_const_at(a), "not a load of a constant");
 342   int *p = (int*) a;
 343   if (is_ori(*(p+1))) {
 344     set_imm(0 + p, (x >> 48) & 0xffff);
 345     set_imm(1 + p, (x >> 32) & 0xffff);
 346     set_imm(3 + p, (x >> 16) & 0xffff);
 347     set_imm(4 + p, x & 0xffff);
 348   } else if (is_lis(*(p+1))) {
 349     set_imm(0 + p, (x >> 48) & 0xffff);
 350     set_imm(2 + p, (x >> 32) & 0xffff);
 351     set_imm(1 + p, (x >> 16) & 0xffff);
 352     set_imm(3 + p, x & 0xffff);
 353   } else {
 354     ShouldNotReachHere();
 355   }
 356 }
 357 
 358 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) {
 359   assert(oop_recorder() != NULL, "this assembler needs a Recorder");
 360   int index = oop_recorder()->allocate_metadata_index(obj);
 361   RelocationHolder rspec = metadata_Relocation::spec(index);
 362   return AddressLiteral((address)obj, rspec);
 363 }
 364 
 365 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) {
 366   assert(oop_recorder() != NULL, "this assembler needs a Recorder");
 367   int index = oop_recorder()->find_index(obj);
 368   RelocationHolder rspec = metadata_Relocation::spec(index);
 369   return AddressLiteral((address)obj, rspec);
 370 }
 371 
 372 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) {
 373   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
 374   int oop_index = oop_recorder()->allocate_oop_index(obj);
 375   return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));
 376 }
 377 
 378 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
 379   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
 380   int oop_index = oop_recorder()->find_index(obj);
 381   return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));
 382 }
 383 
 384 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
 385                                                       Register tmp, int offset) {
 386   intptr_t value = *delayed_value_addr;
 387   if (value != 0) {
 388     return RegisterOrConstant(value + offset);
 389   }
 390 
 391   // Load indirectly to solve generation ordering problem.
 392   // static address, no relocation
 393   int simm16_offset = load_const_optimized(tmp, delayed_value_addr, noreg, true);
 394   ld(tmp, simm16_offset, tmp); // must be aligned ((xa & 3) == 0)
 395 
 396   if (offset != 0) {
 397     addi(tmp, tmp, offset);
 398   }
 399 
 400   return RegisterOrConstant(tmp);
 401 }
 402 
 403 #ifndef PRODUCT
 404 void MacroAssembler::pd_print_patched_instruction(address branch) {
 405   Unimplemented(); // TODO: PPC port
 406 }
 407 #endif // ndef PRODUCT
 408 
 409 // Conditional far branch for destinations encodable in 24+2 bits.
 410 void MacroAssembler::bc_far(int boint, int biint, Label& dest, int optimize) {
 411 
 412   // If requested by flag optimize, relocate the bc_far as a
 413   // runtime_call and prepare for optimizing it when the code gets
 414   // relocated.
 415   if (optimize == bc_far_optimize_on_relocate) {
 416     relocate(relocInfo::runtime_call_type);
 417   }
 418 
 419   // variant 2:
 420   //
 421   //    b!cxx SKIP
 422   //    bxx   DEST
 423   //  SKIP:
 424   //
 425 
 426   const int opposite_boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(boint)),
 427                                                 opposite_bcond(inv_boint_bcond(boint)));
 428 
 429   // We emit two branches.
 430   // First, a conditional branch which jumps around the far branch.
 431   const address not_taken_pc = pc() + 2 * BytesPerInstWord;
 432   const address bc_pc        = pc();
 433   bc(opposite_boint, biint, not_taken_pc);
 434 
 435   const int bc_instr = *(int*)bc_pc;
 436   assert(not_taken_pc == (address)inv_bd_field(bc_instr, (intptr_t)bc_pc), "postcondition");
 437   assert(opposite_boint == inv_bo_field(bc_instr), "postcondition");
 438   assert(boint == add_bhint_to_boint(opposite_bhint(inv_boint_bhint(inv_bo_field(bc_instr))),
 439                                      opposite_bcond(inv_boint_bcond(inv_bo_field(bc_instr)))),
 440          "postcondition");
 441   assert(biint == inv_bi_field(bc_instr), "postcondition");
 442 
 443   // Second, an unconditional far branch which jumps to dest.
 444   // Note: target(dest) remembers the current pc (see CodeSection::target)
 445   //       and returns the current pc if the label is not bound yet; when
 446   //       the label gets bound, the unconditional far branch will be patched.
 447   const address target_pc = target(dest);
 448   const address b_pc  = pc();
 449   b(target_pc);
 450 
 451   assert(not_taken_pc == pc(),                     "postcondition");
 452   assert(dest.is_bound() || target_pc == b_pc, "postcondition");
 453 }
 454 
 455 // 1 or 2 instructions
 456 void MacroAssembler::bc_far_optimized(int boint, int biint, Label& dest) {
 457   if (dest.is_bound() && is_within_range_of_bcxx(target(dest), pc())) {
 458     bc(boint, biint, dest);
 459   } else {
 460     bc_far(boint, biint, dest, MacroAssembler::bc_far_optimize_on_relocate);
 461   }
 462 }
 463 
 464 bool MacroAssembler::is_bc_far_at(address instruction_addr) {
 465   return is_bc_far_variant1_at(instruction_addr) ||
 466          is_bc_far_variant2_at(instruction_addr) ||
 467          is_bc_far_variant3_at(instruction_addr);
 468 }
 469 
 470 address MacroAssembler::get_dest_of_bc_far_at(address instruction_addr) {
 471   if (is_bc_far_variant1_at(instruction_addr)) {
 472     const address instruction_1_addr = instruction_addr;
 473     const int instruction_1 = *(int*)instruction_1_addr;
 474     return (address)inv_bd_field(instruction_1, (intptr_t)instruction_1_addr);
 475   } else if (is_bc_far_variant2_at(instruction_addr)) {
 476     const address instruction_2_addr = instruction_addr + 4;
 477     return bxx_destination(instruction_2_addr);
 478   } else if (is_bc_far_variant3_at(instruction_addr)) {
 479     return instruction_addr + 8;
 480   }
 481   // variant 4 ???
 482   ShouldNotReachHere();
 483   return NULL;
 484 }
 485 void MacroAssembler::set_dest_of_bc_far_at(address instruction_addr, address dest) {
 486 
 487   if (is_bc_far_variant3_at(instruction_addr)) {
 488     // variant 3, far cond branch to the next instruction, already patched to nops:
 489     //
 490     //    nop
 491     //    endgroup
 492     //  SKIP/DEST:
 493     //
 494     return;
 495   }
 496 
 497   // first, extract boint and biint from the current branch
 498   int boint = 0;
 499   int biint = 0;
 500 
 501   ResourceMark rm;
 502   const int code_size = 2 * BytesPerInstWord;
 503   CodeBuffer buf(instruction_addr, code_size);
 504   MacroAssembler masm(&buf);
 505   if (is_bc_far_variant2_at(instruction_addr) && dest == instruction_addr + 8) {
 506     // Far branch to next instruction: Optimize it by patching nops (produce variant 3).
 507     masm.nop();
 508     masm.endgroup();
 509   } else {
 510     if (is_bc_far_variant1_at(instruction_addr)) {
 511       // variant 1, the 1st instruction contains the destination address:
 512       //
 513       //    bcxx  DEST
 514       //    nop
 515       //
 516       const int instruction_1 = *(int*)(instruction_addr);
 517       boint = inv_bo_field(instruction_1);
 518       biint = inv_bi_field(instruction_1);
 519     } else if (is_bc_far_variant2_at(instruction_addr)) {
 520       // variant 2, the 2nd instruction contains the destination address:
 521       //
 522       //    b!cxx SKIP
 523       //    bxx   DEST
 524       //  SKIP:
 525       //
 526       const int instruction_1 = *(int*)(instruction_addr);
 527       boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(inv_bo_field(instruction_1))),
 528           opposite_bcond(inv_boint_bcond(inv_bo_field(instruction_1))));
 529       biint = inv_bi_field(instruction_1);
 530     } else {
 531       // variant 4???
 532       ShouldNotReachHere();
 533     }
 534 
 535     // second, set the new branch destination and optimize the code
 536     if (dest != instruction_addr + 4 && // the bc_far is still unbound!
 537         masm.is_within_range_of_bcxx(dest, instruction_addr)) {
 538       // variant 1:
 539       //
 540       //    bcxx  DEST
 541       //    nop
 542       //
 543       masm.bc(boint, biint, dest);
 544       masm.nop();
 545     } else {
 546       // variant 2:
 547       //
 548       //    b!cxx SKIP
 549       //    bxx   DEST
 550       //  SKIP:
 551       //
 552       const int opposite_boint = add_bhint_to_boint(opposite_bhint(inv_boint_bhint(boint)),
 553                                                     opposite_bcond(inv_boint_bcond(boint)));
 554       const address not_taken_pc = masm.pc() + 2 * BytesPerInstWord;
 555       masm.bc(opposite_boint, biint, not_taken_pc);
 556       masm.b(dest);
 557     }
 558   }
 559   ICache::ppc64_flush_icache_bytes(instruction_addr, code_size);
 560 }
 561 
 562 // Emit a NOT mt-safe patchable 64 bit absolute call/jump.
 563 void MacroAssembler::bxx64_patchable(address dest, relocInfo::relocType rt, bool link) {
 564   // get current pc
 565   uint64_t start_pc = (uint64_t) pc();
 566 
 567   const address pc_of_bl = (address) (start_pc + (6*BytesPerInstWord)); // bl is last
 568   const address pc_of_b  = (address) (start_pc + (0*BytesPerInstWord)); // b is first
 569 
 570   // relocate here
 571   if (rt != relocInfo::none) {
 572     relocate(rt);
 573   }
 574 
 575   if ( ReoptimizeCallSequences &&
 576        (( link && is_within_range_of_b(dest, pc_of_bl)) ||
 577         (!link && is_within_range_of_b(dest, pc_of_b)))) {
 578     // variant 2:
 579     // Emit an optimized, pc-relative call/jump.
 580 
 581     if (link) {
 582       // some padding
 583       nop();
 584       nop();
 585       nop();
 586       nop();
 587       nop();
 588       nop();
 589 
 590       // do the call
 591       assert(pc() == pc_of_bl, "just checking");
 592       bl(dest, relocInfo::none);
 593     } else {
 594       // do the jump
 595       assert(pc() == pc_of_b, "just checking");
 596       b(dest, relocInfo::none);
 597 
 598       // some padding
 599       nop();
 600       nop();
 601       nop();
 602       nop();
 603       nop();
 604       nop();
 605     }
 606 
 607     // Assert that we can identify the emitted call/jump.
 608     assert(is_bxx64_patchable_variant2_at((address)start_pc, link),
 609            "can't identify emitted call");
 610   } else {
 611     // variant 1:
 612     mr(R0, R11);  // spill R11 -> R0.
 613 
 614     // Load the destination address into CTR,
 615     // calculate destination relative to global toc.
 616     calculate_address_from_global_toc(R11, dest, true, true, false);
 617 
 618     mtctr(R11);
 619     mr(R11, R0);  // spill R11 <- R0.
 620     nop();
 621 
 622     // do the call/jump
 623     if (link) {
 624       bctrl();
 625     } else{
 626       bctr();
 627     }
 628     // Assert that we can identify the emitted call/jump.
 629     assert(is_bxx64_patchable_variant1b_at((address)start_pc, link),
 630            "can't identify emitted call");
 631   }
 632 
 633   // Assert that we can identify the emitted call/jump.
 634   assert(is_bxx64_patchable_at((address)start_pc, link),
 635          "can't identify emitted call");
 636   assert(get_dest_of_bxx64_patchable_at((address)start_pc, link) == dest,
 637          "wrong encoding of dest address");
 638 }
 639 
 640 // Identify a bxx64_patchable instruction.
 641 bool MacroAssembler::is_bxx64_patchable_at(address instruction_addr, bool link) {
 642   return is_bxx64_patchable_variant1b_at(instruction_addr, link)
 643     //|| is_bxx64_patchable_variant1_at(instruction_addr, link)
 644       || is_bxx64_patchable_variant2_at(instruction_addr, link);
 645 }
 646 
 647 // Does the call64_patchable instruction use a pc-relative encoding of
 648 // the call destination?
 649 bool MacroAssembler::is_bxx64_patchable_pcrelative_at(address instruction_addr, bool link) {
 650   // variant 2 is pc-relative
 651   return is_bxx64_patchable_variant2_at(instruction_addr, link);
 652 }
 653 
 654 // Identify variant 1.
 655 bool MacroAssembler::is_bxx64_patchable_variant1_at(address instruction_addr, bool link) {
 656   unsigned int* instr = (unsigned int*) instruction_addr;
 657   return (link ? is_bctrl(instr[6]) : is_bctr(instr[6])) // bctr[l]
 658       && is_mtctr(instr[5]) // mtctr
 659     && is_load_const_at(instruction_addr);
 660 }
 661 
 662 // Identify variant 1b: load destination relative to global toc.
 663 bool MacroAssembler::is_bxx64_patchable_variant1b_at(address instruction_addr, bool link) {
 664   unsigned int* instr = (unsigned int*) instruction_addr;
 665   return (link ? is_bctrl(instr[6]) : is_bctr(instr[6])) // bctr[l]
 666     && is_mtctr(instr[3]) // mtctr
 667     && is_calculate_address_from_global_toc_at(instruction_addr + 2*BytesPerInstWord, instruction_addr);
 668 }
 669 
 670 // Identify variant 2.
 671 bool MacroAssembler::is_bxx64_patchable_variant2_at(address instruction_addr, bool link) {
 672   unsigned int* instr = (unsigned int*) instruction_addr;
 673   if (link) {
 674     return is_bl (instr[6])  // bl dest is last
 675       && is_nop(instr[0])  // nop
 676       && is_nop(instr[1])  // nop
 677       && is_nop(instr[2])  // nop
 678       && is_nop(instr[3])  // nop
 679       && is_nop(instr[4])  // nop
 680       && is_nop(instr[5]); // nop
 681   } else {
 682     return is_b  (instr[0])  // b  dest is first
 683       && is_nop(instr[1])  // nop
 684       && is_nop(instr[2])  // nop
 685       && is_nop(instr[3])  // nop
 686       && is_nop(instr[4])  // nop
 687       && is_nop(instr[5])  // nop
 688       && is_nop(instr[6]); // nop
 689   }
 690 }
 691 
 692 // Set dest address of a bxx64_patchable instruction.
 693 void MacroAssembler::set_dest_of_bxx64_patchable_at(address instruction_addr, address dest, bool link) {
 694   ResourceMark rm;
 695   int code_size = MacroAssembler::bxx64_patchable_size;
 696   CodeBuffer buf(instruction_addr, code_size);
 697   MacroAssembler masm(&buf);
 698   masm.bxx64_patchable(dest, relocInfo::none, link);
 699   ICache::ppc64_flush_icache_bytes(instruction_addr, code_size);
 700 }
 701 
 702 // Get dest address of a bxx64_patchable instruction.
 703 address MacroAssembler::get_dest_of_bxx64_patchable_at(address instruction_addr, bool link) {
 704   if (is_bxx64_patchable_variant1_at(instruction_addr, link)) {
 705     return (address) (unsigned long) get_const(instruction_addr);
 706   } else if (is_bxx64_patchable_variant2_at(instruction_addr, link)) {
 707     unsigned int* instr = (unsigned int*) instruction_addr;
 708     if (link) {
 709       const int instr_idx = 6; // bl is last
 710       int branchoffset = branch_destination(instr[instr_idx], 0);
 711       return instruction_addr + branchoffset + instr_idx*BytesPerInstWord;
 712     } else {
 713       const int instr_idx = 0; // b is first
 714       int branchoffset = branch_destination(instr[instr_idx], 0);
 715       return instruction_addr + branchoffset + instr_idx*BytesPerInstWord;
 716     }
 717   // Load dest relative to global toc.
 718   } else if (is_bxx64_patchable_variant1b_at(instruction_addr, link)) {
 719     return get_address_of_calculate_address_from_global_toc_at(instruction_addr + 2*BytesPerInstWord,
 720                                                                instruction_addr);
 721   } else {
 722     ShouldNotReachHere();
 723     return NULL;
 724   }
 725 }
 726 
 727 // Uses ordering which corresponds to ABI:
 728 //    _savegpr0_14:  std  r14,-144(r1)
 729 //    _savegpr0_15:  std  r15,-136(r1)
 730 //    _savegpr0_16:  std  r16,-128(r1)
 731 void MacroAssembler::save_nonvolatile_gprs(Register dst, int offset) {
 732   std(R14, offset, dst);   offset += 8;
 733   std(R15, offset, dst);   offset += 8;
 734   std(R16, offset, dst);   offset += 8;
 735   std(R17, offset, dst);   offset += 8;
 736   std(R18, offset, dst);   offset += 8;
 737   std(R19, offset, dst);   offset += 8;
 738   std(R20, offset, dst);   offset += 8;
 739   std(R21, offset, dst);   offset += 8;
 740   std(R22, offset, dst);   offset += 8;
 741   std(R23, offset, dst);   offset += 8;
 742   std(R24, offset, dst);   offset += 8;
 743   std(R25, offset, dst);   offset += 8;
 744   std(R26, offset, dst);   offset += 8;
 745   std(R27, offset, dst);   offset += 8;
 746   std(R28, offset, dst);   offset += 8;
 747   std(R29, offset, dst);   offset += 8;
 748   std(R30, offset, dst);   offset += 8;
 749   std(R31, offset, dst);   offset += 8;
 750 
 751   stfd(F14, offset, dst);   offset += 8;
 752   stfd(F15, offset, dst);   offset += 8;
 753   stfd(F16, offset, dst);   offset += 8;
 754   stfd(F17, offset, dst);   offset += 8;
 755   stfd(F18, offset, dst);   offset += 8;
 756   stfd(F19, offset, dst);   offset += 8;
 757   stfd(F20, offset, dst);   offset += 8;
 758   stfd(F21, offset, dst);   offset += 8;
 759   stfd(F22, offset, dst);   offset += 8;
 760   stfd(F23, offset, dst);   offset += 8;
 761   stfd(F24, offset, dst);   offset += 8;
 762   stfd(F25, offset, dst);   offset += 8;
 763   stfd(F26, offset, dst);   offset += 8;
 764   stfd(F27, offset, dst);   offset += 8;
 765   stfd(F28, offset, dst);   offset += 8;
 766   stfd(F29, offset, dst);   offset += 8;
 767   stfd(F30, offset, dst);   offset += 8;
 768   stfd(F31, offset, dst);
 769 }
 770 
 771 // Uses ordering which corresponds to ABI:
 772 //    _restgpr0_14:  ld   r14,-144(r1)
 773 //    _restgpr0_15:  ld   r15,-136(r1)
 774 //    _restgpr0_16:  ld   r16,-128(r1)
 775 void MacroAssembler::restore_nonvolatile_gprs(Register src, int offset) {
 776   ld(R14, offset, src);   offset += 8;
 777   ld(R15, offset, src);   offset += 8;
 778   ld(R16, offset, src);   offset += 8;
 779   ld(R17, offset, src);   offset += 8;
 780   ld(R18, offset, src);   offset += 8;
 781   ld(R19, offset, src);   offset += 8;
 782   ld(R20, offset, src);   offset += 8;
 783   ld(R21, offset, src);   offset += 8;
 784   ld(R22, offset, src);   offset += 8;
 785   ld(R23, offset, src);   offset += 8;
 786   ld(R24, offset, src);   offset += 8;
 787   ld(R25, offset, src);   offset += 8;
 788   ld(R26, offset, src);   offset += 8;
 789   ld(R27, offset, src);   offset += 8;
 790   ld(R28, offset, src);   offset += 8;
 791   ld(R29, offset, src);   offset += 8;
 792   ld(R30, offset, src);   offset += 8;
 793   ld(R31, offset, src);   offset += 8;
 794 
 795   // FP registers
 796   lfd(F14, offset, src);   offset += 8;
 797   lfd(F15, offset, src);   offset += 8;
 798   lfd(F16, offset, src);   offset += 8;
 799   lfd(F17, offset, src);   offset += 8;
 800   lfd(F18, offset, src);   offset += 8;
 801   lfd(F19, offset, src);   offset += 8;
 802   lfd(F20, offset, src);   offset += 8;
 803   lfd(F21, offset, src);   offset += 8;
 804   lfd(F22, offset, src);   offset += 8;
 805   lfd(F23, offset, src);   offset += 8;
 806   lfd(F24, offset, src);   offset += 8;
 807   lfd(F25, offset, src);   offset += 8;
 808   lfd(F26, offset, src);   offset += 8;
 809   lfd(F27, offset, src);   offset += 8;
 810   lfd(F28, offset, src);   offset += 8;
 811   lfd(F29, offset, src);   offset += 8;
 812   lfd(F30, offset, src);   offset += 8;
 813   lfd(F31, offset, src);
 814 }
 815 
 816 // For verify_oops.
 817 void MacroAssembler::save_volatile_gprs(Register dst, int offset) {
 818   std(R2,  offset, dst);   offset += 8;
 819   std(R3,  offset, dst);   offset += 8;
 820   std(R4,  offset, dst);   offset += 8;
 821   std(R5,  offset, dst);   offset += 8;
 822   std(R6,  offset, dst);   offset += 8;
 823   std(R7,  offset, dst);   offset += 8;
 824   std(R8,  offset, dst);   offset += 8;
 825   std(R9,  offset, dst);   offset += 8;
 826   std(R10, offset, dst);   offset += 8;
 827   std(R11, offset, dst);   offset += 8;
 828   std(R12, offset, dst);   offset += 8;
 829 
 830   stfd(F0, offset, dst);   offset += 8;
 831   stfd(F1, offset, dst);   offset += 8;
 832   stfd(F2, offset, dst);   offset += 8;
 833   stfd(F3, offset, dst);   offset += 8;
 834   stfd(F4, offset, dst);   offset += 8;
 835   stfd(F5, offset, dst);   offset += 8;
 836   stfd(F6, offset, dst);   offset += 8;
 837   stfd(F7, offset, dst);   offset += 8;
 838   stfd(F8, offset, dst);   offset += 8;
 839   stfd(F9, offset, dst);   offset += 8;
 840   stfd(F10, offset, dst);  offset += 8;
 841   stfd(F11, offset, dst);  offset += 8;
 842   stfd(F12, offset, dst);  offset += 8;
 843   stfd(F13, offset, dst);
 844 }
 845 
 846 // For verify_oops.
 847 void MacroAssembler::restore_volatile_gprs(Register src, int offset) {
 848   ld(R2,  offset, src);   offset += 8;
 849   ld(R3,  offset, src);   offset += 8;
 850   ld(R4,  offset, src);   offset += 8;
 851   ld(R5,  offset, src);   offset += 8;
 852   ld(R6,  offset, src);   offset += 8;
 853   ld(R7,  offset, src);   offset += 8;
 854   ld(R8,  offset, src);   offset += 8;
 855   ld(R9,  offset, src);   offset += 8;
 856   ld(R10, offset, src);   offset += 8;
 857   ld(R11, offset, src);   offset += 8;
 858   ld(R12, offset, src);   offset += 8;
 859 
 860   lfd(F0, offset, src);   offset += 8;
 861   lfd(F1, offset, src);   offset += 8;
 862   lfd(F2, offset, src);   offset += 8;
 863   lfd(F3, offset, src);   offset += 8;
 864   lfd(F4, offset, src);   offset += 8;
 865   lfd(F5, offset, src);   offset += 8;
 866   lfd(F6, offset, src);   offset += 8;
 867   lfd(F7, offset, src);   offset += 8;
 868   lfd(F8, offset, src);   offset += 8;
 869   lfd(F9, offset, src);   offset += 8;
 870   lfd(F10, offset, src);  offset += 8;
 871   lfd(F11, offset, src);  offset += 8;
 872   lfd(F12, offset, src);  offset += 8;
 873   lfd(F13, offset, src);
 874 }
 875 
 876 void MacroAssembler::save_LR_CR(Register tmp) {
 877   mfcr(tmp);
 878   std(tmp, _abi(cr), R1_SP);
 879   mflr(tmp);
 880   std(tmp, _abi(lr), R1_SP);
 881   // Tmp must contain lr on exit! (see return_addr and prolog in ppc64.ad)
 882 }
 883 
 884 void MacroAssembler::restore_LR_CR(Register tmp) {
 885   assert(tmp != R1_SP, "must be distinct");
 886   ld(tmp, _abi(lr), R1_SP);
 887   mtlr(tmp);
 888   ld(tmp, _abi(cr), R1_SP);
 889   mtcr(tmp);
 890 }
 891 
 892 address MacroAssembler::get_PC_trash_LR(Register result) {
 893   Label L;
 894   bl(L);
 895   bind(L);
 896   address lr_pc = pc();
 897   mflr(result);
 898   return lr_pc;
 899 }
 900 
 901 void MacroAssembler::resize_frame(Register offset, Register tmp) {
 902 #ifdef ASSERT
 903   assert_different_registers(offset, tmp, R1_SP);
 904   andi_(tmp, offset, frame::alignment_in_bytes-1);
 905   asm_assert_eq("resize_frame: unaligned", 0x204);
 906 #endif
 907 
 908   // tmp <- *(SP)
 909   ld(tmp, _abi(callers_sp), R1_SP);
 910   // addr <- SP + offset;
 911   // *(addr) <- tmp;
 912   // SP <- addr
 913   stdux(tmp, R1_SP, offset);
 914 }
 915 
 916 void MacroAssembler::resize_frame(int offset, Register tmp) {
 917   assert(is_simm(offset, 16), "too big an offset");
 918   assert_different_registers(tmp, R1_SP);
 919   assert((offset & (frame::alignment_in_bytes-1))==0, "resize_frame: unaligned");
 920   // tmp <- *(SP)
 921   ld(tmp, _abi(callers_sp), R1_SP);
 922   // addr <- SP + offset;
 923   // *(addr) <- tmp;
 924   // SP <- addr
 925   stdu(tmp, offset, R1_SP);
 926 }
 927 
 928 void MacroAssembler::resize_frame_absolute(Register addr, Register tmp1, Register tmp2) {
 929   // (addr == tmp1) || (addr == tmp2) is allowed here!
 930   assert(tmp1 != tmp2, "must be distinct");
 931 
 932   // compute offset w.r.t. current stack pointer
 933   // tmp_1 <- addr - SP (!)
 934   subf(tmp1, R1_SP, addr);
 935 
 936   // atomically update SP keeping back link.
 937   resize_frame(tmp1/* offset */, tmp2/* tmp */);
 938 }
 939 
 940 void MacroAssembler::push_frame(Register bytes, Register tmp) {
 941 #ifdef ASSERT
 942   assert(bytes != R0, "r0 not allowed here");
 943   andi_(R0, bytes, frame::alignment_in_bytes-1);
 944   asm_assert_eq("push_frame(Reg, Reg): unaligned", 0x203);
 945 #endif
 946   neg(tmp, bytes);
 947   stdux(R1_SP, R1_SP, tmp);
 948 }
 949 
 950 // Push a frame of size `bytes'.
 951 void MacroAssembler::push_frame(unsigned int bytes, Register tmp) {
 952   long offset = align_addr(bytes, frame::alignment_in_bytes);
 953   if (is_simm(-offset, 16)) {
 954     stdu(R1_SP, -offset, R1_SP);
 955   } else {
 956     load_const_optimized(tmp, -offset);
 957     stdux(R1_SP, R1_SP, tmp);
 958   }
 959 }
 960 
 961 // Push a frame of size `bytes' plus abi_reg_args on top.
 962 void MacroAssembler::push_frame_reg_args(unsigned int bytes, Register tmp) {
 963   push_frame(bytes + frame::abi_reg_args_size, tmp);
 964 }
 965 
 966 // Setup up a new C frame with a spill area for non-volatile GPRs and
 967 // additional space for local variables.
 968 void MacroAssembler::push_frame_reg_args_nonvolatiles(unsigned int bytes,
 969                                                       Register tmp) {
 970   push_frame(bytes + frame::abi_reg_args_size + frame::spill_nonvolatiles_size, tmp);
 971 }
 972 
 973 // Pop current C frame.
 974 void MacroAssembler::pop_frame() {
 975   ld(R1_SP, _abi(callers_sp), R1_SP);
 976 }
 977 
 978 #if defined(ABI_ELFv2)
 979 address MacroAssembler::branch_to(Register r_function_entry, bool and_link) {
 980   // TODO(asmundak): make sure the caller uses R12 as function descriptor
 981   // most of the times.
 982   if (R12 != r_function_entry) {
 983     mr(R12, r_function_entry);
 984   }
 985   mtctr(R12);
 986   // Do a call or a branch.
 987   if (and_link) {
 988     bctrl();
 989   } else {
 990     bctr();
 991   }
 992   _last_calls_return_pc = pc();
 993 
 994   return _last_calls_return_pc;
 995 }
 996 
 997 // Call a C function via a function descriptor and use full C
 998 // calling conventions. Updates and returns _last_calls_return_pc.
 999 address MacroAssembler::call_c(Register r_function_entry) {
1000   return branch_to(r_function_entry, /*and_link=*/true);
1001 }
1002 
1003 // For tail calls: only branch, don't link, so callee returns to caller of this function.
1004 address MacroAssembler::call_c_and_return_to_caller(Register r_function_entry) {
1005   return branch_to(r_function_entry, /*and_link=*/false);
1006 }
1007 
1008 address MacroAssembler::call_c(address function_entry, relocInfo::relocType rt) {
1009   load_const(R12, function_entry, R0);
1010   return branch_to(R12,  /*and_link=*/true);
1011 }
1012 
1013 #else
1014 // Generic version of a call to C function via a function descriptor
1015 // with variable support for C calling conventions (TOC, ENV, etc.).
1016 // Updates and returns _last_calls_return_pc.
1017 address MacroAssembler::branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call,
1018                                   bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee) {
1019   // we emit standard ptrgl glue code here
1020   assert((function_descriptor != R0), "function_descriptor cannot be R0");
1021 
1022   // retrieve necessary entries from the function descriptor
1023   ld(R0, in_bytes(FunctionDescriptor::entry_offset()), function_descriptor);
1024   mtctr(R0);
1025 
1026   if (load_toc_of_callee) {
1027     ld(R2_TOC, in_bytes(FunctionDescriptor::toc_offset()), function_descriptor);
1028   }
1029   if (load_env_of_callee) {
1030     ld(R11, in_bytes(FunctionDescriptor::env_offset()), function_descriptor);
1031   } else if (load_toc_of_callee) {
1032     li(R11, 0);
1033   }
1034 
1035   // do a call or a branch
1036   if (and_link) {
1037     bctrl();
1038   } else {
1039     bctr();
1040   }
1041   _last_calls_return_pc = pc();
1042 
1043   return _last_calls_return_pc;
1044 }
1045 
1046 // Call a C function via a function descriptor and use full C calling
1047 // conventions.
1048 // We don't use the TOC in generated code, so there is no need to save
1049 // and restore its value.
1050 address MacroAssembler::call_c(Register fd) {
1051   return branch_to(fd, /*and_link=*/true,
1052                        /*save toc=*/false,
1053                        /*restore toc=*/false,
1054                        /*load toc=*/true,
1055                        /*load env=*/true);
1056 }
1057 
1058 address MacroAssembler::call_c_and_return_to_caller(Register fd) {
1059   return branch_to(fd, /*and_link=*/false,
1060                        /*save toc=*/false,
1061                        /*restore toc=*/false,
1062                        /*load toc=*/true,
1063                        /*load env=*/true);
1064 }
1065 
1066 address MacroAssembler::call_c(const FunctionDescriptor* fd, relocInfo::relocType rt) {
1067   if (rt != relocInfo::none) {
1068     // this call needs to be relocatable
1069     if (!ReoptimizeCallSequences
1070         || (rt != relocInfo::runtime_call_type && rt != relocInfo::none)
1071         || fd == NULL   // support code-size estimation
1072         || !fd->is_friend_function()
1073         || fd->entry() == NULL) {
1074       // it's not a friend function as defined by class FunctionDescriptor,
1075       // so do a full call-c here.
1076       load_const(R11, (address)fd, R0);
1077 
1078       bool has_env = (fd != NULL && fd->env() != NULL);
1079       return branch_to(R11, /*and_link=*/true,
1080                             /*save toc=*/false,
1081                             /*restore toc=*/false,
1082                             /*load toc=*/true,
1083                             /*load env=*/has_env);
1084     } else {
1085       // It's a friend function. Load the entry point and don't care about
1086       // toc and env. Use an optimizable call instruction, but ensure the
1087       // same code-size as in the case of a non-friend function.
1088       nop();
1089       nop();
1090       nop();
1091       bl64_patchable(fd->entry(), rt);
1092       _last_calls_return_pc = pc();
1093       return _last_calls_return_pc;
1094     }
1095   } else {
1096     // This call does not need to be relocatable, do more aggressive
1097     // optimizations.
1098     if (!ReoptimizeCallSequences
1099       || !fd->is_friend_function()) {
1100       // It's not a friend function as defined by class FunctionDescriptor,
1101       // so do a full call-c here.
1102       load_const(R11, (address)fd, R0);
1103       return branch_to(R11, /*and_link=*/true,
1104                             /*save toc=*/false,
1105                             /*restore toc=*/false,
1106                             /*load toc=*/true,
1107                             /*load env=*/true);
1108     } else {
1109       // it's a friend function, load the entry point and don't care about
1110       // toc and env.
1111       address dest = fd->entry();
1112       if (is_within_range_of_b(dest, pc())) {
1113         bl(dest);
1114       } else {
1115         bl64_patchable(dest, rt);
1116       }
1117       _last_calls_return_pc = pc();
1118       return _last_calls_return_pc;
1119     }
1120   }
1121 }
1122 
1123 // Call a C function.  All constants needed reside in TOC.
1124 //
1125 // Read the address to call from the TOC.
1126 // Read env from TOC, if fd specifies an env.
1127 // Read new TOC from TOC.
1128 address MacroAssembler::call_c_using_toc(const FunctionDescriptor* fd,
1129                                          relocInfo::relocType rt, Register toc) {
1130   if (!ReoptimizeCallSequences
1131     || (rt != relocInfo::runtime_call_type && rt != relocInfo::none)
1132     || !fd->is_friend_function()) {
1133     // It's not a friend function as defined by class FunctionDescriptor,
1134     // so do a full call-c here.
1135     assert(fd->entry() != NULL, "function must be linked");
1136 
1137     AddressLiteral fd_entry(fd->entry());
1138     bool success = load_const_from_method_toc(R11, fd_entry, toc, /*fixed_size*/ true);
1139     mtctr(R11);
1140     if (fd->env() == NULL) {
1141       li(R11, 0);
1142       nop();
1143     } else {
1144       AddressLiteral fd_env(fd->env());
1145       success = success && load_const_from_method_toc(R11, fd_env, toc, /*fixed_size*/ true);
1146     }
1147     AddressLiteral fd_toc(fd->toc());
1148     // Set R2_TOC (load from toc)
1149     success = success && load_const_from_method_toc(R2_TOC, fd_toc, toc, /*fixed_size*/ true);
1150     bctrl();
1151     _last_calls_return_pc = pc();
1152     if (!success) { return NULL; }
1153   } else {
1154     // It's a friend function, load the entry point and don't care about
1155     // toc and env. Use an optimizable call instruction, but ensure the
1156     // same code-size as in the case of a non-friend function.
1157     nop();
1158     bl64_patchable(fd->entry(), rt);
1159     _last_calls_return_pc = pc();
1160   }
1161   return _last_calls_return_pc;
1162 }
1163 #endif // ABI_ELFv2
1164 
1165 void MacroAssembler::call_VM_base(Register oop_result,
1166                                   Register last_java_sp,
1167                                   address  entry_point,
1168                                   bool     check_exceptions) {
1169   BLOCK_COMMENT("call_VM {");
1170   // Determine last_java_sp register.
1171   if (!last_java_sp->is_valid()) {
1172     last_java_sp = R1_SP;
1173   }
1174   set_top_ijava_frame_at_SP_as_last_Java_frame(last_java_sp, R11_scratch1);
1175 
1176   // ARG1 must hold thread address.
1177   mr(R3_ARG1, R16_thread);
1178 #if defined(ABI_ELFv2)
1179   address return_pc = call_c(entry_point, relocInfo::none);
1180 #else
1181   address return_pc = call_c((FunctionDescriptor*)entry_point, relocInfo::none);
1182 #endif
1183 
1184   reset_last_Java_frame();
1185 
1186   // Check for pending exceptions.
1187   if (check_exceptions) {
1188     // We don't check for exceptions here.
1189     ShouldNotReachHere();
1190   }
1191 
1192   // Get oop result if there is one and reset the value in the thread.
1193   if (oop_result->is_valid()) {
1194     get_vm_result(oop_result);
1195   }
1196 
1197   _last_calls_return_pc = return_pc;
1198   BLOCK_COMMENT("} call_VM");
1199 }
1200 
1201 void MacroAssembler::call_VM_leaf_base(address entry_point) {
1202   BLOCK_COMMENT("call_VM_leaf {");
1203 #if defined(ABI_ELFv2)
1204   call_c(entry_point, relocInfo::none);
1205 #else
1206   call_c(CAST_FROM_FN_PTR(FunctionDescriptor*, entry_point), relocInfo::none);
1207 #endif
1208   BLOCK_COMMENT("} call_VM_leaf");
1209 }
1210 
1211 void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {
1212   call_VM_base(oop_result, noreg, entry_point, check_exceptions);
1213 }
1214 
1215 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1,
1216                              bool check_exceptions) {
1217   // R3_ARG1 is reserved for the thread.
1218   mr_if_needed(R4_ARG2, arg_1);
1219   call_VM(oop_result, entry_point, check_exceptions);
1220 }
1221 
1222 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2,
1223                              bool check_exceptions) {
1224   // R3_ARG1 is reserved for the thread
1225   mr_if_needed(R4_ARG2, arg_1);
1226   assert(arg_2 != R4_ARG2, "smashed argument");
1227   mr_if_needed(R5_ARG3, arg_2);
1228   call_VM(oop_result, entry_point, check_exceptions);
1229 }
1230 
1231 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3,
1232                              bool check_exceptions) {
1233   // R3_ARG1 is reserved for the thread
1234   mr_if_needed(R4_ARG2, arg_1);
1235   assert(arg_2 != R4_ARG2, "smashed argument");
1236   mr_if_needed(R5_ARG3, arg_2);
1237   mr_if_needed(R6_ARG4, arg_3);
1238   call_VM(oop_result, entry_point, check_exceptions);
1239 }
1240 
1241 void MacroAssembler::call_VM_leaf(address entry_point) {
1242   call_VM_leaf_base(entry_point);
1243 }
1244 
1245 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
1246   mr_if_needed(R3_ARG1, arg_1);
1247   call_VM_leaf(entry_point);
1248 }
1249 
1250 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
1251   mr_if_needed(R3_ARG1, arg_1);
1252   assert(arg_2 != R3_ARG1, "smashed argument");
1253   mr_if_needed(R4_ARG2, arg_2);
1254   call_VM_leaf(entry_point);
1255 }
1256 
1257 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
1258   mr_if_needed(R3_ARG1, arg_1);
1259   assert(arg_2 != R3_ARG1, "smashed argument");
1260   mr_if_needed(R4_ARG2, arg_2);
1261   assert(arg_3 != R3_ARG1 && arg_3 != R4_ARG2, "smashed argument");
1262   mr_if_needed(R5_ARG3, arg_3);
1263   call_VM_leaf(entry_point);
1264 }
1265 
1266 // Check whether instruction is a read access to the polling page
1267 // which was emitted by load_from_polling_page(..).
1268 bool MacroAssembler::is_load_from_polling_page(int instruction, void* ucontext,
1269                                                address* polling_address_ptr) {
1270   if (!is_ld(instruction))
1271     return false; // It's not a ld. Fail.
1272 
1273   int rt = inv_rt_field(instruction);
1274   int ra = inv_ra_field(instruction);
1275   int ds = inv_ds_field(instruction);
1276   if (!(ds == 0 && ra != 0 && rt == 0)) {
1277     return false; // It's not a ld(r0, X, ra). Fail.
1278   }
1279 
1280   if (!ucontext) {
1281     // Set polling address.
1282     if (polling_address_ptr != NULL) {
1283       *polling_address_ptr = NULL;
1284     }
1285     return true; // No ucontext given. Can't check value of ra. Assume true.
1286   }
1287 
1288 #ifdef LINUX
1289   // Ucontext given. Check that register ra contains the address of
1290   // the safepoing polling page.
1291   ucontext_t* uc = (ucontext_t*) ucontext;
1292   // Set polling address.
1293   address addr = (address)uc->uc_mcontext.regs->gpr[ra] + (ssize_t)ds;
1294   if (polling_address_ptr != NULL) {
1295     *polling_address_ptr = addr;
1296   }
1297   return os::is_poll_address(addr);
1298 #else
1299   // Not on Linux, ucontext must be NULL.
1300   ShouldNotReachHere();
1301   return false;
1302 #endif
1303 }
1304 
1305 void MacroAssembler::bang_stack_with_offset(int offset) {
1306   // When increasing the stack, the old stack pointer will be written
1307   // to the new top of stack according to the PPC64 abi.
1308   // Therefore, stack banging is not necessary when increasing
1309   // the stack by <= os::vm_page_size() bytes.
1310   // When increasing the stack by a larger amount, this method is
1311   // called repeatedly to bang the intermediate pages.
1312 
1313   // Stack grows down, caller passes positive offset.
1314   assert(offset > 0, "must bang with positive offset");
1315 
1316   long stdoffset = -offset;
1317 
1318   if (is_simm(stdoffset, 16)) {
1319     // Signed 16 bit offset, a simple std is ok.
1320     if (UseLoadInstructionsForStackBangingPPC64) {
1321       ld(R0, (int)(signed short)stdoffset, R1_SP);
1322     } else {
1323       std(R0,(int)(signed short)stdoffset, R1_SP);
1324     }
1325   } else if (is_simm(stdoffset, 31)) {
1326     const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1327     const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1328 
1329     Register tmp = R11;
1330     addis(tmp, R1_SP, hi);
1331     if (UseLoadInstructionsForStackBangingPPC64) {
1332       ld(R0,  lo, tmp);
1333     } else {
1334       std(R0, lo, tmp);
1335     }
1336   } else {
1337     ShouldNotReachHere();
1338   }
1339 }
1340 
1341 // If instruction is a stack bang of the form
1342 //    std    R0,    x(Ry),       (see bang_stack_with_offset())
1343 //    stdu   R1_SP, x(R1_SP),    (see push_frame(), resize_frame())
1344 // or stdux  R1_SP, Rx, R1_SP    (see push_frame(), resize_frame())
1345 // return the banged address. Otherwise, return 0.
1346 address MacroAssembler::get_stack_bang_address(int instruction, void *ucontext) {
1347 #ifdef LINUX
1348   ucontext_t* uc = (ucontext_t*) ucontext;
1349   int rs = inv_rs_field(instruction);
1350   int ra = inv_ra_field(instruction);
1351   if (   (is_ld(instruction)   && rs == 0 &&  UseLoadInstructionsForStackBangingPPC64)
1352       || (is_std(instruction)  && rs == 0 && !UseLoadInstructionsForStackBangingPPC64)
1353       || (is_stdu(instruction) && rs == 1)) {
1354     int ds = inv_ds_field(instruction);
1355     // return banged address
1356     return ds+(address)uc->uc_mcontext.regs->gpr[ra];
1357   } else if (is_stdux(instruction) && rs == 1) {
1358     int rb = inv_rb_field(instruction);
1359     address sp = (address)uc->uc_mcontext.regs->gpr[1];
1360     long rb_val = (long)uc->uc_mcontext.regs->gpr[rb];
1361     return ra != 1 || rb_val >= 0 ? NULL         // not a stack bang
1362                                   : sp + rb_val; // banged address
1363   }
1364   return NULL; // not a stack bang
1365 #else
1366   // workaround not needed on !LINUX :-)
1367   ShouldNotCallThis();
1368   return NULL;
1369 #endif
1370 }
1371 
1372 void MacroAssembler::reserved_stack_check(Register return_pc) {
1373   // Test if reserved zone needs to be enabled.
1374   Label no_reserved_zone_enabling;
1375 
1376   ld_ptr(R0, JavaThread::reserved_stack_activation_offset(), R16_thread);
1377   cmpld(CCR0, R1_SP, R0);
1378   blt_predict_taken(CCR0, no_reserved_zone_enabling);
1379 
1380   // Enable reserved zone again, throw stack overflow exception.
1381   push_frame_reg_args(0, R0);
1382   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), R16_thread);
1383   pop_frame();
1384   mtlr(return_pc);
1385   load_const_optimized(R0, StubRoutines::throw_delayed_StackOverflowError_entry());
1386   mtctr(R0);
1387   bctr();
1388 
1389   should_not_reach_here();
1390 
1391   bind(no_reserved_zone_enabling);
1392 }
1393 
1394 void MacroAssembler::getandsetd(Register dest_current_value, Register exchange_value, Register addr_base,
1395                                 bool cmpxchgx_hint) {
1396   Label retry;
1397   bind(retry);
1398   ldarx(dest_current_value, addr_base, cmpxchgx_hint);
1399   stdcx_(exchange_value, addr_base);
1400   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1401     bne_predict_not_taken(CCR0, retry); // StXcx_ sets CCR0.
1402   } else {
1403     bne(                  CCR0, retry); // StXcx_ sets CCR0.
1404   }
1405 }
1406 
1407 void MacroAssembler::getandaddd(Register dest_current_value, Register inc_value, Register addr_base,
1408                                 Register tmp, bool cmpxchgx_hint) {
1409   Label retry;
1410   bind(retry);
1411   ldarx(dest_current_value, addr_base, cmpxchgx_hint);
1412   add(tmp, dest_current_value, inc_value);
1413   stdcx_(tmp, addr_base);
1414   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1415     bne_predict_not_taken(CCR0, retry); // StXcx_ sets CCR0.
1416   } else {
1417     bne(                  CCR0, retry); // StXcx_ sets CCR0.
1418   }
1419 }
1420 
1421 // Word/sub-word atomic helper functions
1422 
1423 // Temps and addr_base are killed if size < 4 and processor does not support respective instructions.
1424 // Only signed types are supported with size < 4.
1425 // Atomic add always kills tmp1.
1426 void MacroAssembler::atomic_get_and_modify_generic(Register dest_current_value, Register exchange_value,
1427                                                    Register addr_base, Register tmp1, Register tmp2, Register tmp3,
1428                                                    bool cmpxchgx_hint, bool is_add, int size) {
1429   // Sub-word instructions are available since Power 8.
1430   // For older processors, instruction_type != size holds, and we
1431   // emulate the sub-word instructions by constructing a 4-byte value
1432   // that leaves the other bytes unchanged.
1433   const int instruction_type = VM_Version::has_lqarx() ? size : 4;
1434 
1435   Label retry;
1436   Register shift_amount = noreg,
1437            val32 = dest_current_value,
1438            modval = is_add ? tmp1 : exchange_value;
1439 
1440   if (instruction_type != size) {
1441     assert_different_registers(tmp1, tmp2, tmp3, dest_current_value, exchange_value, addr_base);
1442     modval = tmp1;
1443     shift_amount = tmp2;
1444     val32 = tmp3;
1445     // Need some preperation: Compute shift amount, align address. Note: shorts must be 2 byte aligned.
1446 #ifdef VM_LITTLE_ENDIAN
1447     rldic(shift_amount, addr_base, 3, 64-5); // (dest & 3) * 8;
1448     clrrdi(addr_base, addr_base, 2);
1449 #else
1450     xori(shift_amount, addr_base, (size == 1) ? 3 : 2);
1451     clrrdi(addr_base, addr_base, 2);
1452     rldic(shift_amount, shift_amount, 3, 64-5); // byte: ((3-dest) & 3) * 8; short: ((1-dest/2) & 1) * 16;
1453 #endif
1454   }
1455 
1456   // atomic emulation loop
1457   bind(retry);
1458 
1459   switch (instruction_type) {
1460     case 4: lwarx(val32, addr_base, cmpxchgx_hint); break;
1461     case 2: lharx(val32, addr_base, cmpxchgx_hint); break;
1462     case 1: lbarx(val32, addr_base, cmpxchgx_hint); break;
1463     default: ShouldNotReachHere();
1464   }
1465 
1466   if (instruction_type != size) {
1467     srw(dest_current_value, val32, shift_amount);
1468   }
1469 
1470   if (is_add) { add(modval, dest_current_value, exchange_value); }
1471 
1472   if (instruction_type != size) {
1473     // Transform exchange value such that the replacement can be done by one xor instruction.
1474     xorr(modval, dest_current_value, is_add ? modval : exchange_value);
1475     clrldi(modval, modval, (size == 1) ? 56 : 48);
1476     slw(modval, modval, shift_amount);
1477     xorr(modval, val32, modval);
1478   }
1479 
1480   switch (instruction_type) {
1481     case 4: stwcx_(modval, addr_base); break;
1482     case 2: sthcx_(modval, addr_base); break;
1483     case 1: stbcx_(modval, addr_base); break;
1484     default: ShouldNotReachHere();
1485   }
1486 
1487   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1488     bne_predict_not_taken(CCR0, retry); // StXcx_ sets CCR0.
1489   } else {
1490     bne(                  CCR0, retry); // StXcx_ sets CCR0.
1491   }
1492 
1493   // l?arx zero-extends, but Java wants byte/short values sign-extended.
1494   if (size == 1) {
1495     extsb(dest_current_value, dest_current_value);
1496   } else if (size == 2) {
1497     extsh(dest_current_value, dest_current_value);
1498   };
1499 }
1500 
1501 // Temps, addr_base and exchange_value are killed if size < 4 and processor does not support respective instructions.
1502 // Only signed types are supported with size < 4.
1503 void MacroAssembler::cmpxchg_loop_body(ConditionRegister flag, Register dest_current_value,
1504                                        Register compare_value, Register exchange_value,
1505                                        Register addr_base, Register tmp1, Register tmp2,
1506                                        Label &retry, Label &failed, bool cmpxchgx_hint, int size) {
1507   // Sub-word instructions are available since Power 8.
1508   // For older processors, instruction_type != size holds, and we
1509   // emulate the sub-word instructions by constructing a 4-byte value
1510   // that leaves the other bytes unchanged.
1511   const int instruction_type = VM_Version::has_lqarx() ? size : 4;
1512 
1513   Register shift_amount = noreg,
1514            val32 = dest_current_value,
1515            modval = exchange_value;
1516 
1517   if (instruction_type != size) {
1518     assert_different_registers(tmp1, tmp2, dest_current_value, compare_value, exchange_value, addr_base);
1519     shift_amount = tmp1;
1520     val32 = tmp2;
1521     modval = tmp2;
1522     // Need some preperation: Compute shift amount, align address. Note: shorts must be 2 byte aligned.
1523 #ifdef VM_LITTLE_ENDIAN
1524     rldic(shift_amount, addr_base, 3, 64-5); // (dest & 3) * 8;
1525     clrrdi(addr_base, addr_base, 2);
1526 #else
1527     xori(shift_amount, addr_base, (size == 1) ? 3 : 2);
1528     clrrdi(addr_base, addr_base, 2);
1529     rldic(shift_amount, shift_amount, 3, 64-5); // byte: ((3-dest) & 3) * 8; short: ((1-dest/2) & 1) * 16;
1530 #endif
1531     // Transform exchange value such that the replacement can be done by one xor instruction.
1532     xorr(exchange_value, compare_value, exchange_value);
1533     clrldi(exchange_value, exchange_value, (size == 1) ? 56 : 48);
1534     slw(exchange_value, exchange_value, shift_amount);
1535   }
1536 
1537   // atomic emulation loop
1538   bind(retry);
1539 
1540   switch (instruction_type) {
1541     case 4: lwarx(val32, addr_base, cmpxchgx_hint); break;
1542     case 2: lharx(val32, addr_base, cmpxchgx_hint); break;
1543     case 1: lbarx(val32, addr_base, cmpxchgx_hint); break;
1544     default: ShouldNotReachHere();
1545   }
1546 
1547   if (instruction_type != size) {
1548     srw(dest_current_value, val32, shift_amount);
1549   }
1550   if (size == 1) {
1551     extsb(dest_current_value, dest_current_value);
1552   } else if (size == 2) {
1553     extsh(dest_current_value, dest_current_value);
1554   };
1555 
1556   cmpw(flag, dest_current_value, compare_value);
1557   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1558     bne_predict_not_taken(flag, failed);
1559   } else {
1560     bne(                  flag, failed);
1561   }
1562   // branch to done  => (flag == ne), (dest_current_value != compare_value)
1563   // fall through    => (flag == eq), (dest_current_value == compare_value)
1564 
1565   if (instruction_type != size) {
1566     xorr(modval, val32, exchange_value);
1567   }
1568 
1569   switch (instruction_type) {
1570     case 4: stwcx_(modval, addr_base); break;
1571     case 2: sthcx_(modval, addr_base); break;
1572     case 1: stbcx_(modval, addr_base); break;
1573     default: ShouldNotReachHere();
1574   }
1575 }
1576 
1577 // CmpxchgX sets condition register to cmpX(current, compare).
1578 void MacroAssembler::cmpxchg_generic(ConditionRegister flag, Register dest_current_value,
1579                                      Register compare_value, Register exchange_value,
1580                                      Register addr_base, Register tmp1, Register tmp2,
1581                                      int semantics, bool cmpxchgx_hint,
1582                                      Register int_flag_success, bool contention_hint, bool weak, int size) {
1583   Label retry;
1584   Label failed;
1585   Label done;
1586 
1587   // Save one branch if result is returned via register and
1588   // result register is different from the other ones.
1589   bool use_result_reg    = (int_flag_success != noreg);
1590   bool preset_result_reg = (int_flag_success != dest_current_value && int_flag_success != compare_value &&
1591                             int_flag_success != exchange_value && int_flag_success != addr_base &&
1592                             int_flag_success != tmp1 && int_flag_success != tmp2);
1593   assert(!weak || flag == CCR0, "weak only supported with CCR0");
1594   assert(size == 1 || size == 2 || size == 4, "unsupported");
1595 
1596   if (use_result_reg && preset_result_reg) {
1597     li(int_flag_success, 0); // preset (assume cas failed)
1598   }
1599 
1600   // Add simple guard in order to reduce risk of starving under high contention (recommended by IBM).
1601   if (contention_hint) { // Don't try to reserve if cmp fails.
1602     switch (size) {
1603       case 1: lbz(dest_current_value, 0, addr_base); extsb(dest_current_value, dest_current_value); break;
1604       case 2: lha(dest_current_value, 0, addr_base); break;
1605       case 4: lwz(dest_current_value, 0, addr_base); break;
1606       default: ShouldNotReachHere();
1607     }
1608     cmpw(flag, dest_current_value, compare_value);
1609     bne(flag, failed);
1610   }
1611 
1612   // release/fence semantics
1613   if (semantics & MemBarRel) {
1614     release();
1615   }
1616 
1617   cmpxchg_loop_body(flag, dest_current_value, compare_value, exchange_value, addr_base, tmp1, tmp2,
1618                     retry, failed, cmpxchgx_hint, size);
1619   if (!weak || use_result_reg) {
1620     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1621       bne_predict_not_taken(CCR0, weak ? failed : retry); // StXcx_ sets CCR0.
1622     } else {
1623       bne(                  CCR0, weak ? failed : retry); // StXcx_ sets CCR0.
1624     }
1625   }
1626   // fall through    => (flag == eq), (dest_current_value == compare_value), (swapped)
1627 
1628   // Result in register (must do this at the end because int_flag_success can be the
1629   // same register as one above).
1630   if (use_result_reg) {
1631     li(int_flag_success, 1);
1632   }
1633 
1634   if (semantics & MemBarFenceAfter) {
1635     fence();
1636   } else if (semantics & MemBarAcq) {
1637     isync();
1638   }
1639 
1640   if (use_result_reg && !preset_result_reg) {
1641     b(done);
1642   }
1643 
1644   bind(failed);
1645   if (use_result_reg && !preset_result_reg) {
1646     li(int_flag_success, 0);
1647   }
1648 
1649   bind(done);
1650   // (flag == ne) => (dest_current_value != compare_value), (!swapped)
1651   // (flag == eq) => (dest_current_value == compare_value), ( swapped)
1652 }
1653 
1654 // Preforms atomic compare exchange:
1655 //   if (compare_value == *addr_base)
1656 //     *addr_base = exchange_value
1657 //     int_flag_success = 1;
1658 //   else
1659 //     int_flag_success = 0;
1660 //
1661 // ConditionRegister flag       = cmp(compare_value, *addr_base)
1662 // Register dest_current_value  = *addr_base
1663 // Register compare_value       Used to compare with value in memory
1664 // Register exchange_value      Written to memory if compare_value == *addr_base
1665 // Register addr_base           The memory location to compareXChange
1666 // Register int_flag_success    Set to 1 if exchange_value was written to *addr_base
1667 //
1668 // To avoid the costly compare exchange the value is tested beforehand.
1669 // Several special cases exist to avoid that unnecessary information is generated.
1670 //
1671 void MacroAssembler::cmpxchgd(ConditionRegister flag,
1672                               Register dest_current_value, RegisterOrConstant compare_value, Register exchange_value,
1673                               Register addr_base, int semantics, bool cmpxchgx_hint,
1674                               Register int_flag_success, Label* failed_ext, bool contention_hint, bool weak) {
1675   Label retry;
1676   Label failed_int;
1677   Label& failed = (failed_ext != NULL) ? *failed_ext : failed_int;
1678   Label done;
1679 
1680   // Save one branch if result is returned via register and result register is different from the other ones.
1681   bool use_result_reg    = (int_flag_success!=noreg);
1682   bool preset_result_reg = (int_flag_success!=dest_current_value && int_flag_success!=compare_value.register_or_noreg() &&
1683                             int_flag_success!=exchange_value && int_flag_success!=addr_base);
1684   assert(!weak || flag == CCR0, "weak only supported with CCR0");
1685   assert(int_flag_success == noreg || failed_ext == NULL, "cannot have both");
1686 
1687   if (use_result_reg && preset_result_reg) {
1688     li(int_flag_success, 0); // preset (assume cas failed)
1689   }
1690 
1691   // Add simple guard in order to reduce risk of starving under high contention (recommended by IBM).
1692   if (contention_hint) { // Don't try to reserve if cmp fails.
1693     ld(dest_current_value, 0, addr_base);
1694     cmpd(flag, compare_value, dest_current_value);
1695     bne(flag, failed);
1696   }
1697 
1698   // release/fence semantics
1699   if (semantics & MemBarRel) {
1700     release();
1701   }
1702 
1703   // atomic emulation loop
1704   bind(retry);
1705 
1706   ldarx(dest_current_value, addr_base, cmpxchgx_hint);
1707   cmpd(flag, compare_value, dest_current_value);
1708   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1709     bne_predict_not_taken(flag, failed);
1710   } else {
1711     bne(                  flag, failed);
1712   }
1713 
1714   stdcx_(exchange_value, addr_base);
1715   if (!weak || use_result_reg || failed_ext) {
1716     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
1717       bne_predict_not_taken(CCR0, weak ? failed : retry); // stXcx_ sets CCR0
1718     } else {
1719       bne(                  CCR0, weak ? failed : retry); // stXcx_ sets CCR0
1720     }
1721   }
1722 
1723   // result in register (must do this at the end because int_flag_success can be the same register as one above)
1724   if (use_result_reg) {
1725     li(int_flag_success, 1);
1726   }
1727 
1728   if (semantics & MemBarFenceAfter) {
1729     fence();
1730   } else if (semantics & MemBarAcq) {
1731     isync();
1732   }
1733 
1734   if (use_result_reg && !preset_result_reg) {
1735     b(done);
1736   }
1737 
1738   bind(failed_int);
1739   if (use_result_reg && !preset_result_reg) {
1740     li(int_flag_success, 0);
1741   }
1742 
1743   bind(done);
1744   // (flag == ne) => (dest_current_value != compare_value), (!swapped)
1745   // (flag == eq) => (dest_current_value == compare_value), ( swapped)
1746 }
1747 
1748 // Look up the method for a megamorphic invokeinterface call.
1749 // The target method is determined by <intf_klass, itable_index>.
1750 // The receiver klass is in recv_klass.
1751 // On success, the result will be in method_result, and execution falls through.
1752 // On failure, execution transfers to the given label.
1753 void MacroAssembler::lookup_interface_method(Register recv_klass,
1754                                              Register intf_klass,
1755                                              RegisterOrConstant itable_index,
1756                                              Register method_result,
1757                                              Register scan_temp,
1758                                              Register temp2,
1759                                              Label& L_no_such_interface,
1760                                              bool return_method) {
1761   assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
1762 
1763   // Compute start of first itableOffsetEntry (which is at the end of the vtable).
1764   int vtable_base = in_bytes(Klass::vtable_start_offset());
1765   int itentry_off = itableMethodEntry::method_offset_in_bytes();
1766   int logMEsize   = exact_log2(itableMethodEntry::size() * wordSize);
1767   int scan_step   = itableOffsetEntry::size() * wordSize;
1768   int log_vte_size= exact_log2(vtableEntry::size_in_bytes());
1769 
1770   lwz(scan_temp, in_bytes(Klass::vtable_length_offset()), recv_klass);
1771   // %%% We should store the aligned, prescaled offset in the klassoop.
1772   // Then the next several instructions would fold away.
1773 
1774   sldi(scan_temp, scan_temp, log_vte_size);
1775   addi(scan_temp, scan_temp, vtable_base);
1776   add(scan_temp, recv_klass, scan_temp);
1777 
1778   // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1779   if (return_method) {
1780     if (itable_index.is_register()) {
1781       Register itable_offset = itable_index.as_register();
1782       sldi(method_result, itable_offset, logMEsize);
1783       if (itentry_off) { addi(method_result, method_result, itentry_off); }
1784       add(method_result, method_result, recv_klass);
1785     } else {
1786       long itable_offset = (long)itable_index.as_constant();
1787       // static address, no relocation
1788       add_const_optimized(method_result, recv_klass, (itable_offset << logMEsize) + itentry_off, temp2);
1789     }
1790   }
1791 
1792   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
1793   //   if (scan->interface() == intf) {
1794   //     result = (klass + scan->offset() + itable_index);
1795   //   }
1796   // }
1797   Label search, found_method;
1798 
1799   for (int peel = 1; peel >= 0; peel--) {
1800     // %%%% Could load both offset and interface in one ldx, if they were
1801     // in the opposite order. This would save a load.
1802     ld(temp2, itableOffsetEntry::interface_offset_in_bytes(), scan_temp);
1803 
1804     // Check that this entry is non-null. A null entry means that
1805     // the receiver class doesn't implement the interface, and wasn't the
1806     // same as when the caller was compiled.
1807     cmpd(CCR0, temp2, intf_klass);
1808 
1809     if (peel) {
1810       beq(CCR0, found_method);
1811     } else {
1812       bne(CCR0, search);
1813       // (invert the test to fall through to found_method...)
1814     }
1815 
1816     if (!peel) break;
1817 
1818     bind(search);
1819 
1820     cmpdi(CCR0, temp2, 0);
1821     beq(CCR0, L_no_such_interface);
1822     addi(scan_temp, scan_temp, scan_step);
1823   }
1824 
1825   bind(found_method);
1826 
1827   // Got a hit.
1828   if (return_method) {
1829     int ito_offset = itableOffsetEntry::offset_offset_in_bytes();
1830     lwz(scan_temp, ito_offset, scan_temp);
1831     ldx(method_result, scan_temp, method_result);
1832   }
1833 }
1834 
1835 // virtual method calling
1836 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1837                                            RegisterOrConstant vtable_index,
1838                                            Register method_result) {
1839 
1840   assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg());
1841 
1842   const int base = in_bytes(Klass::vtable_start_offset());
1843   assert(vtableEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1844 
1845   if (vtable_index.is_register()) {
1846     sldi(vtable_index.as_register(), vtable_index.as_register(), LogBytesPerWord);
1847     add(recv_klass, vtable_index.as_register(), recv_klass);
1848   } else {
1849     addi(recv_klass, recv_klass, vtable_index.as_constant() << LogBytesPerWord);
1850   }
1851   ld(R19_method, base + vtableEntry::method_offset_in_bytes(), recv_klass);
1852 }
1853 
1854 /////////////////////////////////////////// subtype checking ////////////////////////////////////////////
1855 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1856                                                    Register super_klass,
1857                                                    Register temp1_reg,
1858                                                    Register temp2_reg,
1859                                                    Label* L_success,
1860                                                    Label* L_failure,
1861                                                    Label* L_slow_path,
1862                                                    RegisterOrConstant super_check_offset) {
1863 
1864   const Register check_cache_offset = temp1_reg;
1865   const Register cached_super       = temp2_reg;
1866 
1867   assert_different_registers(sub_klass, super_klass, check_cache_offset, cached_super);
1868 
1869   int sco_offset = in_bytes(Klass::super_check_offset_offset());
1870   int sc_offset  = in_bytes(Klass::secondary_super_cache_offset());
1871 
1872   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
1873   bool need_slow_path = (must_load_sco || super_check_offset.constant_or_zero() == sco_offset);
1874 
1875   Label L_fallthrough;
1876   int label_nulls = 0;
1877   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
1878   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
1879   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
1880   assert(label_nulls <= 1 ||
1881          (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
1882          "at most one NULL in the batch, usually");
1883 
1884   // If the pointers are equal, we are done (e.g., String[] elements).
1885   // This self-check enables sharing of secondary supertype arrays among
1886   // non-primary types such as array-of-interface. Otherwise, each such
1887   // type would need its own customized SSA.
1888   // We move this check to the front of the fast path because many
1889   // type checks are in fact trivially successful in this manner,
1890   // so we get a nicely predicted branch right at the start of the check.
1891   cmpd(CCR0, sub_klass, super_klass);
1892   beq(CCR0, *L_success);
1893 
1894   // Check the supertype display:
1895   if (must_load_sco) {
1896     // The super check offset is always positive...
1897     lwz(check_cache_offset, sco_offset, super_klass);
1898     super_check_offset = RegisterOrConstant(check_cache_offset);
1899     // super_check_offset is register.
1900     assert_different_registers(sub_klass, super_klass, cached_super, super_check_offset.as_register());
1901   }
1902   // The loaded value is the offset from KlassOopDesc.
1903 
1904   ld(cached_super, super_check_offset, sub_klass);
1905   cmpd(CCR0, cached_super, super_klass);
1906 
1907   // This check has worked decisively for primary supers.
1908   // Secondary supers are sought in the super_cache ('super_cache_addr').
1909   // (Secondary supers are interfaces and very deeply nested subtypes.)
1910   // This works in the same check above because of a tricky aliasing
1911   // between the super_cache and the primary super display elements.
1912   // (The 'super_check_addr' can address either, as the case requires.)
1913   // Note that the cache is updated below if it does not help us find
1914   // what we need immediately.
1915   // So if it was a primary super, we can just fail immediately.
1916   // Otherwise, it's the slow path for us (no success at this point).
1917 
1918 #define FINAL_JUMP(label) if (&(label) != &L_fallthrough) { b(label); }
1919 
1920   if (super_check_offset.is_register()) {
1921     beq(CCR0, *L_success);
1922     cmpwi(CCR0, super_check_offset.as_register(), sc_offset);
1923     if (L_failure == &L_fallthrough) {
1924       beq(CCR0, *L_slow_path);
1925     } else {
1926       bne(CCR0, *L_failure);
1927       FINAL_JUMP(*L_slow_path);
1928     }
1929   } else {
1930     if (super_check_offset.as_constant() == sc_offset) {
1931       // Need a slow path; fast failure is impossible.
1932       if (L_slow_path == &L_fallthrough) {
1933         beq(CCR0, *L_success);
1934       } else {
1935         bne(CCR0, *L_slow_path);
1936         FINAL_JUMP(*L_success);
1937       }
1938     } else {
1939       // No slow path; it's a fast decision.
1940       if (L_failure == &L_fallthrough) {
1941         beq(CCR0, *L_success);
1942       } else {
1943         bne(CCR0, *L_failure);
1944         FINAL_JUMP(*L_success);
1945       }
1946     }
1947   }
1948 
1949   bind(L_fallthrough);
1950 #undef FINAL_JUMP
1951 }
1952 
1953 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1954                                                    Register super_klass,
1955                                                    Register temp1_reg,
1956                                                    Register temp2_reg,
1957                                                    Label* L_success,
1958                                                    Register result_reg) {
1959   const Register array_ptr = temp1_reg; // current value from cache array
1960   const Register temp      = temp2_reg;
1961 
1962   assert_different_registers(sub_klass, super_klass, array_ptr, temp);
1963 
1964   int source_offset = in_bytes(Klass::secondary_supers_offset());
1965   int target_offset = in_bytes(Klass::secondary_super_cache_offset());
1966 
1967   int length_offset = Array<Klass*>::length_offset_in_bytes();
1968   int base_offset   = Array<Klass*>::base_offset_in_bytes();
1969 
1970   Label hit, loop, failure, fallthru;
1971 
1972   ld(array_ptr, source_offset, sub_klass);
1973 
1974   // TODO: PPC port: assert(4 == arrayOopDesc::length_length_in_bytes(), "precondition violated.");
1975   lwz(temp, length_offset, array_ptr);
1976   cmpwi(CCR0, temp, 0);
1977   beq(CCR0, result_reg!=noreg ? failure : fallthru); // length 0
1978 
1979   mtctr(temp); // load ctr
1980 
1981   bind(loop);
1982   // Oops in table are NO MORE compressed.
1983   ld(temp, base_offset, array_ptr);
1984   cmpd(CCR0, temp, super_klass);
1985   beq(CCR0, hit);
1986   addi(array_ptr, array_ptr, BytesPerWord);
1987   bdnz(loop);
1988 
1989   bind(failure);
1990   if (result_reg!=noreg) li(result_reg, 1); // load non-zero result (indicates a miss)
1991   b(fallthru);
1992 
1993   bind(hit);
1994   std(super_klass, target_offset, sub_klass); // save result to cache
1995   if (result_reg != noreg) { li(result_reg, 0); } // load zero result (indicates a hit)
1996   if (L_success != NULL) { b(*L_success); }
1997   else if (result_reg == noreg) { blr(); } // return with CR0.eq if neither label nor result reg provided
1998 
1999   bind(fallthru);
2000 }
2001 
2002 // Try fast path, then go to slow one if not successful
2003 void MacroAssembler::check_klass_subtype(Register sub_klass,
2004                          Register super_klass,
2005                          Register temp1_reg,
2006                          Register temp2_reg,
2007                          Label& L_success) {
2008   Label L_failure;
2009   check_klass_subtype_fast_path(sub_klass, super_klass, temp1_reg, temp2_reg, &L_success, &L_failure);
2010   check_klass_subtype_slow_path(sub_klass, super_klass, temp1_reg, temp2_reg, &L_success);
2011   bind(L_failure); // Fallthru if not successful.
2012 }
2013 
2014 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
2015   assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
2016 
2017   Label L_fallthrough;
2018   if (L_fast_path == NULL) {
2019     L_fast_path = &L_fallthrough;
2020   } else if (L_slow_path == NULL) {
2021     L_slow_path = &L_fallthrough;
2022   }
2023 
2024   // Fast path check: class is fully initialized
2025   lbz(R0, in_bytes(InstanceKlass::init_state_offset()), klass);
2026   cmpwi(CCR0, R0, InstanceKlass::fully_initialized);
2027   beq(CCR0, *L_fast_path);
2028 
2029   // Fast path check: current thread is initializer thread
2030   ld(R0, in_bytes(InstanceKlass::init_thread_offset()), klass);
2031   cmpd(CCR0, thread, R0);
2032   if (L_slow_path == &L_fallthrough) {
2033     beq(CCR0, *L_fast_path);
2034   } else if (L_fast_path == &L_fallthrough) {
2035     bne(CCR0, *L_slow_path);
2036   } else {
2037     Unimplemented();
2038   }
2039 
2040   bind(L_fallthrough);
2041 }
2042 
2043 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
2044                                               Register temp_reg,
2045                                               Label& wrong_method_type) {
2046   assert_different_registers(mtype_reg, mh_reg, temp_reg);
2047   // Compare method type against that of the receiver.
2048   load_heap_oop(temp_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg), mh_reg,
2049                 noreg, noreg, false, IS_NOT_NULL);
2050   cmpd(CCR0, temp_reg, mtype_reg);
2051   bne(CCR0, wrong_method_type);
2052 }
2053 
2054 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot,
2055                                                    Register temp_reg,
2056                                                    int extra_slot_offset) {
2057   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2058   int stackElementSize = Interpreter::stackElementSize;
2059   int offset = extra_slot_offset * stackElementSize;
2060   if (arg_slot.is_constant()) {
2061     offset += arg_slot.as_constant() * stackElementSize;
2062     return offset;
2063   } else {
2064     assert(temp_reg != noreg, "must specify");
2065     sldi(temp_reg, arg_slot.as_register(), exact_log2(stackElementSize));
2066     if (offset != 0)
2067       addi(temp_reg, temp_reg, offset);
2068     return temp_reg;
2069   }
2070 }
2071 
2072 // Supports temp2_reg = R0.
2073 void MacroAssembler::biased_locking_enter(ConditionRegister cr_reg, Register obj_reg,
2074                                           Register mark_reg, Register temp_reg,
2075                                           Register temp2_reg, Label& done, Label* slow_case) {
2076   assert(UseBiasedLocking, "why call this otherwise?");
2077 
2078 #ifdef ASSERT
2079   assert_different_registers(obj_reg, mark_reg, temp_reg, temp2_reg);
2080 #endif
2081 
2082   Label cas_label;
2083 
2084   // Branch to done if fast path fails and no slow_case provided.
2085   Label *slow_case_int = (slow_case != NULL) ? slow_case : &done;
2086 
2087   // Biased locking
2088   // See whether the lock is currently biased toward our thread and
2089   // whether the epoch is still valid
2090   // Note that the runtime guarantees sufficient alignment of JavaThread
2091   // pointers to allow age to be placed into low bits
2092   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits,
2093          "biased locking makes assumptions about bit layout");
2094 
2095   if (PrintBiasedLockingStatistics) {
2096     load_const(temp2_reg, (address) BiasedLocking::total_entry_count_addr(), temp_reg);
2097     lwzx(temp_reg, temp2_reg);
2098     addi(temp_reg, temp_reg, 1);
2099     stwx(temp_reg, temp2_reg);
2100   }
2101 
2102   andi(temp_reg, mark_reg, markOopDesc::biased_lock_mask_in_place);
2103   cmpwi(cr_reg, temp_reg, markOopDesc::biased_lock_pattern);
2104   bne(cr_reg, cas_label);
2105 
2106   load_klass(temp_reg, obj_reg);
2107 
2108   load_const_optimized(temp2_reg, ~((int) markOopDesc::age_mask_in_place));
2109   ld(temp_reg, in_bytes(Klass::prototype_header_offset()), temp_reg);
2110   orr(temp_reg, R16_thread, temp_reg);
2111   xorr(temp_reg, mark_reg, temp_reg);
2112   andr(temp_reg, temp_reg, temp2_reg);
2113   cmpdi(cr_reg, temp_reg, 0);
2114   if (PrintBiasedLockingStatistics) {
2115     Label l;
2116     bne(cr_reg, l);
2117     load_const(temp2_reg, (address) BiasedLocking::biased_lock_entry_count_addr());
2118     lwzx(mark_reg, temp2_reg);
2119     addi(mark_reg, mark_reg, 1);
2120     stwx(mark_reg, temp2_reg);
2121     // restore mark_reg
2122     ld(mark_reg, oopDesc::mark_offset_in_bytes(), obj_reg);
2123     bind(l);
2124   }
2125   beq(cr_reg, done);
2126 
2127   Label try_revoke_bias;
2128   Label try_rebias;
2129 
2130   // At this point we know that the header has the bias pattern and
2131   // that we are not the bias owner in the current epoch. We need to
2132   // figure out more details about the state of the header in order to
2133   // know what operations can be legally performed on the object's
2134   // header.
2135 
2136   // If the low three bits in the xor result aren't clear, that means
2137   // the prototype header is no longer biased and we have to revoke
2138   // the bias on this object.
2139   andi(temp2_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
2140   cmpwi(cr_reg, temp2_reg, 0);
2141   bne(cr_reg, try_revoke_bias);
2142 
2143   // Biasing is still enabled for this data type. See whether the
2144   // epoch of the current bias is still valid, meaning that the epoch
2145   // bits of the mark word are equal to the epoch bits of the
2146   // prototype header. (Note that the prototype header's epoch bits
2147   // only change at a safepoint.) If not, attempt to rebias the object
2148   // toward the current thread. Note that we must be absolutely sure
2149   // that the current epoch is invalid in order to do this because
2150   // otherwise the manipulations it performs on the mark word are
2151   // illegal.
2152 
2153   int shift_amount = 64 - markOopDesc::epoch_shift;
2154   // rotate epoch bits to right (little) end and set other bits to 0
2155   // [ big part | epoch | little part ] -> [ 0..0 | epoch ]
2156   rldicl_(temp2_reg, temp_reg, shift_amount, 64 - markOopDesc::epoch_bits);
2157   // branch if epoch bits are != 0, i.e. they differ, because the epoch has been incremented
2158   bne(CCR0, try_rebias);
2159 
2160   // The epoch of the current bias is still valid but we know nothing
2161   // about the owner; it might be set or it might be clear. Try to
2162   // acquire the bias of the object using an atomic operation. If this
2163   // fails we will go in to the runtime to revoke the object's bias.
2164   // Note that we first construct the presumed unbiased header so we
2165   // don't accidentally blow away another thread's valid bias.
2166   andi(mark_reg, mark_reg, (markOopDesc::biased_lock_mask_in_place |
2167                                 markOopDesc::age_mask_in_place |
2168                                 markOopDesc::epoch_mask_in_place));
2169   orr(temp_reg, R16_thread, mark_reg);
2170 
2171   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2172 
2173   // CmpxchgX sets cr_reg to cmpX(temp2_reg, mark_reg).
2174   cmpxchgd(/*flag=*/cr_reg, /*current_value=*/temp2_reg,
2175            /*compare_value=*/mark_reg, /*exchange_value=*/temp_reg,
2176            /*where=*/obj_reg,
2177            MacroAssembler::MemBarAcq,
2178            MacroAssembler::cmpxchgx_hint_acquire_lock(),
2179            noreg, slow_case_int); // bail out if failed
2180 
2181   // If the biasing toward our thread failed, this means that
2182   // another thread succeeded in biasing it toward itself and we
2183   // need to revoke that bias. The revocation will occur in the
2184   // interpreter runtime in the slow case.
2185   if (PrintBiasedLockingStatistics) {
2186     load_const(temp2_reg, (address) BiasedLocking::anonymously_biased_lock_entry_count_addr(), temp_reg);
2187     lwzx(temp_reg, temp2_reg);
2188     addi(temp_reg, temp_reg, 1);
2189     stwx(temp_reg, temp2_reg);
2190   }
2191   b(done);
2192 
2193   bind(try_rebias);
2194   // At this point we know the epoch has expired, meaning that the
2195   // current "bias owner", if any, is actually invalid. Under these
2196   // circumstances _only_, we are allowed to use the current header's
2197   // value as the comparison value when doing the cas to acquire the
2198   // bias in the current epoch. In other words, we allow transfer of
2199   // the bias from one thread to another directly in this situation.
2200   load_klass(temp_reg, obj_reg);
2201   andi(temp2_reg, mark_reg, markOopDesc::age_mask_in_place);
2202   orr(temp2_reg, R16_thread, temp2_reg);
2203   ld(temp_reg, in_bytes(Klass::prototype_header_offset()), temp_reg);
2204   orr(temp_reg, temp2_reg, temp_reg);
2205 
2206   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2207 
2208   cmpxchgd(/*flag=*/cr_reg, /*current_value=*/temp2_reg,
2209                  /*compare_value=*/mark_reg, /*exchange_value=*/temp_reg,
2210                  /*where=*/obj_reg,
2211                  MacroAssembler::MemBarAcq,
2212                  MacroAssembler::cmpxchgx_hint_acquire_lock(),
2213                  noreg, slow_case_int); // bail out if failed
2214 
2215   // If the biasing toward our thread failed, this means that
2216   // another thread succeeded in biasing it toward itself and we
2217   // need to revoke that bias. The revocation will occur in the
2218   // interpreter runtime in the slow case.
2219   if (PrintBiasedLockingStatistics) {
2220     load_const(temp2_reg, (address) BiasedLocking::rebiased_lock_entry_count_addr(), temp_reg);
2221     lwzx(temp_reg, temp2_reg);
2222     addi(temp_reg, temp_reg, 1);
2223     stwx(temp_reg, temp2_reg);
2224   }
2225   b(done);
2226 
2227   bind(try_revoke_bias);
2228   // The prototype mark in the klass doesn't have the bias bit set any
2229   // more, indicating that objects of this data type are not supposed
2230   // to be biased any more. We are going to try to reset the mark of
2231   // this object to the prototype value and fall through to the
2232   // CAS-based locking scheme. Note that if our CAS fails, it means
2233   // that another thread raced us for the privilege of revoking the
2234   // bias of this particular object, so it's okay to continue in the
2235   // normal locking code.
2236   load_klass(temp_reg, obj_reg);
2237   ld(temp_reg, in_bytes(Klass::prototype_header_offset()), temp_reg);
2238   andi(temp2_reg, mark_reg, markOopDesc::age_mask_in_place);
2239   orr(temp_reg, temp_reg, temp2_reg);
2240 
2241   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2242 
2243   // CmpxchgX sets cr_reg to cmpX(temp2_reg, mark_reg).
2244   cmpxchgd(/*flag=*/cr_reg, /*current_value=*/temp2_reg,
2245                  /*compare_value=*/mark_reg, /*exchange_value=*/temp_reg,
2246                  /*where=*/obj_reg,
2247                  MacroAssembler::MemBarAcq,
2248                  MacroAssembler::cmpxchgx_hint_acquire_lock());
2249 
2250   // reload markOop in mark_reg before continuing with lightweight locking
2251   ld(mark_reg, oopDesc::mark_offset_in_bytes(), obj_reg);
2252 
2253   // Fall through to the normal CAS-based lock, because no matter what
2254   // the result of the above CAS, some thread must have succeeded in
2255   // removing the bias bit from the object's header.
2256   if (PrintBiasedLockingStatistics) {
2257     Label l;
2258     bne(cr_reg, l);
2259     load_const(temp2_reg, (address) BiasedLocking::revoked_lock_entry_count_addr(), temp_reg);
2260     lwzx(temp_reg, temp2_reg);
2261     addi(temp_reg, temp_reg, 1);
2262     stwx(temp_reg, temp2_reg);
2263     bind(l);
2264   }
2265 
2266   bind(cas_label);
2267 }
2268 
2269 void MacroAssembler::biased_locking_exit (ConditionRegister cr_reg, Register mark_addr, Register temp_reg, Label& done) {
2270   // Check for biased locking unlock case, which is a no-op
2271   // Note: we do not have to check the thread ID for two reasons.
2272   // First, the interpreter checks for IllegalMonitorStateException at
2273   // a higher level. Second, if the bias was revoked while we held the
2274   // lock, the object could not be rebiased toward another thread, so
2275   // the bias bit would be clear.
2276 
2277   ld(temp_reg, 0, mark_addr);
2278   andi(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
2279 
2280   cmpwi(cr_reg, temp_reg, markOopDesc::biased_lock_pattern);
2281   beq(cr_reg, done);
2282 }
2283 
2284 // allocation (for C1)
2285 void MacroAssembler::eden_allocate(
2286   Register obj,                      // result: pointer to object after successful allocation
2287   Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
2288   int      con_size_in_bytes,        // object size in bytes if   known at compile time
2289   Register t1,                       // temp register
2290   Register t2,                       // temp register
2291   Label&   slow_case                 // continuation point if fast allocation fails
2292 ) {
2293   b(slow_case);
2294 }
2295 
2296 void MacroAssembler::tlab_allocate(
2297   Register obj,                      // result: pointer to object after successful allocation
2298   Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
2299   int      con_size_in_bytes,        // object size in bytes if   known at compile time
2300   Register t1,                       // temp register
2301   Label&   slow_case                 // continuation point if fast allocation fails
2302 ) {
2303   // make sure arguments make sense
2304   assert_different_registers(obj, var_size_in_bytes, t1);
2305   assert(0 <= con_size_in_bytes && is_simm16(con_size_in_bytes), "illegal object size");
2306   assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
2307 
2308   const Register new_top = t1;
2309   //verify_tlab(); not implemented
2310 
2311   ld(obj, in_bytes(JavaThread::tlab_top_offset()), R16_thread);
2312   ld(R0, in_bytes(JavaThread::tlab_end_offset()), R16_thread);
2313   if (var_size_in_bytes == noreg) {
2314     addi(new_top, obj, con_size_in_bytes);
2315   } else {
2316     add(new_top, obj, var_size_in_bytes);
2317   }
2318   cmpld(CCR0, new_top, R0);
2319   bc_far_optimized(Assembler::bcondCRbiIs1, bi0(CCR0, Assembler::greater), slow_case);
2320 
2321 #ifdef ASSERT
2322   // make sure new free pointer is properly aligned
2323   {
2324     Label L;
2325     andi_(R0, new_top, MinObjAlignmentInBytesMask);
2326     beq(CCR0, L);
2327     stop("updated TLAB free is not properly aligned", 0x934);
2328     bind(L);
2329   }
2330 #endif // ASSERT
2331 
2332   // update the tlab top pointer
2333   std(new_top, in_bytes(JavaThread::tlab_top_offset()), R16_thread);
2334   //verify_tlab(); not implemented
2335 }
2336 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes, Register t1, Register t2) {
2337   unimplemented("incr_allocated_bytes");
2338 }
2339 
2340 address MacroAssembler::emit_trampoline_stub(int destination_toc_offset,
2341                                              int insts_call_instruction_offset, Register Rtoc) {
2342   // Start the stub.
2343   address stub = start_a_stub(64);
2344   if (stub == NULL) { return NULL; } // CodeCache full: bail out
2345 
2346   // Create a trampoline stub relocation which relates this trampoline stub
2347   // with the call instruction at insts_call_instruction_offset in the
2348   // instructions code-section.
2349   relocate(trampoline_stub_Relocation::spec(code()->insts()->start() + insts_call_instruction_offset));
2350   const int stub_start_offset = offset();
2351 
2352   // For java_to_interp stubs we use R11_scratch1 as scratch register
2353   // and in call trampoline stubs we use R12_scratch2. This way we
2354   // can distinguish them (see is_NativeCallTrampolineStub_at()).
2355   Register reg_scratch = R12_scratch2;
2356 
2357   // Now, create the trampoline stub's code:
2358   // - load the TOC
2359   // - load the call target from the constant pool
2360   // - call
2361   if (Rtoc == noreg) {
2362     calculate_address_from_global_toc(reg_scratch, method_toc());
2363     Rtoc = reg_scratch;
2364   }
2365 
2366   ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, Rtoc, false);
2367   mtctr(reg_scratch);
2368   bctr();
2369 
2370   const address stub_start_addr = addr_at(stub_start_offset);
2371 
2372   // Assert that the encoded destination_toc_offset can be identified and that it is correct.
2373   assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
2374          "encoded offset into the constant pool must match");
2375   // Trampoline_stub_size should be good.
2376   assert((uint)(offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
2377   assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
2378 
2379   // End the stub.
2380   end_a_stub();
2381   return stub;
2382 }
2383 
2384 // TM on PPC64.
2385 void MacroAssembler::atomic_inc_ptr(Register addr, Register result, int simm16) {
2386   Label retry;
2387   bind(retry);
2388   ldarx(result, addr, /*hint*/ false);
2389   addi(result, result, simm16);
2390   stdcx_(result, addr);
2391   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
2392     bne_predict_not_taken(CCR0, retry); // stXcx_ sets CCR0
2393   } else {
2394     bne(                  CCR0, retry); // stXcx_ sets CCR0
2395   }
2396 }
2397 
2398 void MacroAssembler::atomic_ori_int(Register addr, Register result, int uimm16) {
2399   Label retry;
2400   bind(retry);
2401   lwarx(result, addr, /*hint*/ false);
2402   ori(result, result, uimm16);
2403   stwcx_(result, addr);
2404   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
2405     bne_predict_not_taken(CCR0, retry); // stXcx_ sets CCR0
2406   } else {
2407     bne(                  CCR0, retry); // stXcx_ sets CCR0
2408   }
2409 }
2410 
2411 #if INCLUDE_RTM_OPT
2412 
2413 // Update rtm_counters based on abort status
2414 // input: abort_status
2415 //        rtm_counters_Reg (RTMLockingCounters*)
2416 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters_Reg) {
2417   // Mapping to keep PreciseRTMLockingStatistics similar to x86.
2418   // x86 ppc (! means inverted, ? means not the same)
2419   //  0   31  Set if abort caused by XABORT instruction.
2420   //  1  ! 7  If set, the transaction may succeed on a retry. This bit is always clear if bit 0 is set.
2421   //  2   13  Set if another logical processor conflicted with a memory address that was part of the transaction that aborted.
2422   //  3   10  Set if an internal buffer overflowed.
2423   //  4  ?12  Set if a debug breakpoint was hit.
2424   //  5  ?32  Set if an abort occurred during execution of a nested transaction.
2425   const int failure_bit[] = {tm_tabort, // Signal handler will set this too.
2426                              tm_failure_persistent,
2427                              tm_non_trans_cf,
2428                              tm_trans_cf,
2429                              tm_footprint_of,
2430                              tm_failure_code,
2431                              tm_transaction_level};
2432 
2433   const int num_failure_bits = sizeof(failure_bit) / sizeof(int);
2434   const int num_counters = RTMLockingCounters::ABORT_STATUS_LIMIT;
2435 
2436   const int bit2counter_map[][num_counters] =
2437   // 0 = no map; 1 = mapped, no inverted logic; -1 = mapped, inverted logic
2438   // Inverted logic means that if a bit is set don't count it, or vice-versa.
2439   // Care must be taken when mapping bits to counters as bits for a given
2440   // counter must be mutually exclusive. Otherwise, the counter will be
2441   // incremented more than once.
2442   // counters:
2443   // 0        1        2         3         4         5
2444   // abort  , persist, conflict, overflow, debug   , nested         bits:
2445   {{ 1      , 0      , 0       , 0       , 0       , 0      },   // abort
2446    { 0      , -1     , 0       , 0       , 0       , 0      },   // failure_persistent
2447    { 0      , 0      , 1       , 0       , 0       , 0      },   // non_trans_cf
2448    { 0      , 0      , 1       , 0       , 0       , 0      },   // trans_cf
2449    { 0      , 0      , 0       , 1       , 0       , 0      },   // footprint_of
2450    { 0      , 0      , 0       , 0       , -1      , 0      },   // failure_code = 0xD4
2451    { 0      , 0      , 0       , 0       , 0       , 1      }};  // transaction_level > 1
2452   // ...
2453 
2454   // Move abort_status value to R0 and use abort_status register as a
2455   // temporary register because R0 as third operand in ld/std is treated
2456   // as base address zero (value). Likewise, R0 as second operand in addi
2457   // is problematic because it amounts to li.
2458   const Register temp_Reg = abort_status;
2459   const Register abort_status_R0 = R0;
2460   mr(abort_status_R0, abort_status);
2461 
2462   // Increment total abort counter.
2463   int counters_offs = RTMLockingCounters::abort_count_offset();
2464   ld(temp_Reg, counters_offs, rtm_counters_Reg);
2465   addi(temp_Reg, temp_Reg, 1);
2466   std(temp_Reg, counters_offs, rtm_counters_Reg);
2467 
2468   // Increment specific abort counters.
2469   if (PrintPreciseRTMLockingStatistics) {
2470 
2471     // #0 counter offset.
2472     int abortX_offs = RTMLockingCounters::abortX_count_offset();
2473 
2474     for (int nbit = 0; nbit < num_failure_bits; nbit++) {
2475       for (int ncounter = 0; ncounter < num_counters; ncounter++) {
2476         if (bit2counter_map[nbit][ncounter] != 0) {
2477           Label check_abort;
2478           int abort_counter_offs = abortX_offs + (ncounter << 3);
2479 
2480           if (failure_bit[nbit] == tm_transaction_level) {
2481             // Don't check outer transaction, TL = 1 (bit 63). Hence only
2482             // 11 bits in the TL field are checked to find out if failure
2483             // occured in a nested transaction. This check also matches
2484             // the case when nesting_of = 1 (nesting overflow).
2485             rldicr_(temp_Reg, abort_status_R0, failure_bit[nbit], 10);
2486           } else if (failure_bit[nbit] == tm_failure_code) {
2487             // Check failure code for trap or illegal caught in TM.
2488             // Bits 0:7 are tested as bit 7 (persistent) is copied from
2489             // tabort or treclaim source operand.
2490             // On Linux: trap or illegal is TM_CAUSE_SIGNAL (0xD4).
2491             rldicl(temp_Reg, abort_status_R0, 8, 56);
2492             cmpdi(CCR0, temp_Reg, 0xD4);
2493           } else {
2494             rldicr_(temp_Reg, abort_status_R0, failure_bit[nbit], 0);
2495           }
2496 
2497           if (bit2counter_map[nbit][ncounter] == 1) {
2498             beq(CCR0, check_abort);
2499           } else {
2500             bne(CCR0, check_abort);
2501           }
2502 
2503           // We don't increment atomically.
2504           ld(temp_Reg, abort_counter_offs, rtm_counters_Reg);
2505           addi(temp_Reg, temp_Reg, 1);
2506           std(temp_Reg, abort_counter_offs, rtm_counters_Reg);
2507 
2508           bind(check_abort);
2509         }
2510       }
2511     }
2512   }
2513   // Restore abort_status.
2514   mr(abort_status, abort_status_R0);
2515 }
2516 
2517 // Branch if (random & (count-1) != 0), count is 2^n
2518 // tmp and CR0 are killed
2519 void MacroAssembler::branch_on_random_using_tb(Register tmp, int count, Label& brLabel) {
2520   mftb(tmp);
2521   andi_(tmp, tmp, count-1);
2522   bne(CCR0, brLabel);
2523 }
2524 
2525 // Perform abort ratio calculation, set no_rtm bit if high ratio.
2526 // input:  rtm_counters_Reg (RTMLockingCounters* address) - KILLED
2527 void MacroAssembler::rtm_abort_ratio_calculation(Register rtm_counters_Reg,
2528                                                  RTMLockingCounters* rtm_counters,
2529                                                  Metadata* method_data) {
2530   Label L_done, L_check_always_rtm1, L_check_always_rtm2;
2531 
2532   if (RTMLockingCalculationDelay > 0) {
2533     // Delay calculation.
2534     ld(rtm_counters_Reg, (RegisterOrConstant)(intptr_t)RTMLockingCounters::rtm_calculation_flag_addr());
2535     cmpdi(CCR0, rtm_counters_Reg, 0);
2536     beq(CCR0, L_done);
2537     load_const_optimized(rtm_counters_Reg, (address)rtm_counters, R0); // reload
2538   }
2539   // Abort ratio calculation only if abort_count > RTMAbortThreshold.
2540   //   Aborted transactions = abort_count * 100
2541   //   All transactions = total_count *  RTMTotalCountIncrRate
2542   //   Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
2543   ld(R0, RTMLockingCounters::abort_count_offset(), rtm_counters_Reg);
2544   if (is_simm(RTMAbortThreshold, 16)) {   // cmpdi can handle 16bit immediate only.
2545     cmpdi(CCR0, R0, RTMAbortThreshold);
2546     blt(CCR0, L_check_always_rtm2);  // reload of rtm_counters_Reg not necessary
2547   } else {
2548     load_const_optimized(rtm_counters_Reg, RTMAbortThreshold);
2549     cmpd(CCR0, R0, rtm_counters_Reg);
2550     blt(CCR0, L_check_always_rtm1);  // reload of rtm_counters_Reg required
2551   }
2552   mulli(R0, R0, 100);
2553 
2554   const Register tmpReg = rtm_counters_Reg;
2555   ld(tmpReg, RTMLockingCounters::total_count_offset(), rtm_counters_Reg);
2556   mulli(tmpReg, tmpReg, RTMTotalCountIncrRate); // allowable range: int16
2557   mulli(tmpReg, tmpReg, RTMAbortRatio);         // allowable range: int16
2558   cmpd(CCR0, R0, tmpReg);
2559   blt(CCR0, L_check_always_rtm1); // jump to reload
2560   if (method_data != NULL) {
2561     // Set rtm_state to "no rtm" in MDO.
2562     // Not using a metadata relocation. Method and Class Loader are kept alive anyway.
2563     // (See nmethod::metadata_do and CodeBuffer::finalize_oop_references.)
2564     load_const(R0, (address)method_data + MethodData::rtm_state_offset_in_bytes(), tmpReg);
2565     atomic_ori_int(R0, tmpReg, NoRTM);
2566   }
2567   b(L_done);
2568 
2569   bind(L_check_always_rtm1);
2570   load_const_optimized(rtm_counters_Reg, (address)rtm_counters, R0); // reload
2571   bind(L_check_always_rtm2);
2572   ld(tmpReg, RTMLockingCounters::total_count_offset(), rtm_counters_Reg);
2573   int64_t thresholdValue = RTMLockingThreshold / RTMTotalCountIncrRate;
2574   if (is_simm(thresholdValue, 16)) {   // cmpdi can handle 16bit immediate only.
2575     cmpdi(CCR0, tmpReg, thresholdValue);
2576   } else {
2577     load_const_optimized(R0, thresholdValue);
2578     cmpd(CCR0, tmpReg, R0);
2579   }
2580   blt(CCR0, L_done);
2581   if (method_data != NULL) {
2582     // Set rtm_state to "always rtm" in MDO.
2583     // Not using a metadata relocation. See above.
2584     load_const(R0, (address)method_data + MethodData::rtm_state_offset_in_bytes(), tmpReg);
2585     atomic_ori_int(R0, tmpReg, UseRTM);
2586   }
2587   bind(L_done);
2588 }
2589 
2590 // Update counters and perform abort ratio calculation.
2591 // input: abort_status_Reg
2592 void MacroAssembler::rtm_profiling(Register abort_status_Reg, Register temp_Reg,
2593                                    RTMLockingCounters* rtm_counters,
2594                                    Metadata* method_data,
2595                                    bool profile_rtm) {
2596 
2597   assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
2598   // Update rtm counters based on state at abort.
2599   // Reads abort_status_Reg, updates flags.
2600   assert_different_registers(abort_status_Reg, temp_Reg);
2601   load_const_optimized(temp_Reg, (address)rtm_counters, R0);
2602   rtm_counters_update(abort_status_Reg, temp_Reg);
2603   if (profile_rtm) {
2604     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
2605     rtm_abort_ratio_calculation(temp_Reg, rtm_counters, method_data);
2606   }
2607 }
2608 
2609 // Retry on abort if abort's status indicates non-persistent failure.
2610 // inputs: retry_count_Reg
2611 //       : abort_status_Reg
2612 // output: retry_count_Reg decremented by 1
2613 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg,
2614                                              Label& retryLabel, Label* checkRetry) {
2615   Label doneRetry;
2616 
2617   // Don't retry if failure is persistent.
2618   // The persistent bit is set when a (A) Disallowed operation is performed in
2619   // transactional state, like for instance trying to write the TFHAR after a
2620   // transaction is started; or when there is (B) a Nesting Overflow (too many
2621   // nested transactions); or when (C) the Footprint overflows (too many
2622   // addressess touched in TM state so there is no more space in the footprint
2623   // area to track them); or in case of (D) a Self-Induced Conflict, i.e. a
2624   // store is performed to a given address in TM state, then once in suspended
2625   // state the same address is accessed. Failure (A) is very unlikely to occur
2626   // in the JVM. Failure (D) will never occur because Suspended state is never
2627   // used in the JVM. Thus mostly (B) a Nesting Overflow or (C) a Footprint
2628   // Overflow will set the persistent bit.
2629   rldicr_(R0, abort_status_Reg, tm_failure_persistent, 0);
2630   bne(CCR0, doneRetry);
2631 
2632   // Don't retry if transaction was deliberately aborted, i.e. caused by a
2633   // tabort instruction.
2634   rldicr_(R0, abort_status_Reg, tm_tabort, 0);
2635   bne(CCR0, doneRetry);
2636 
2637   // Retry if transaction aborted due to a conflict with another thread.
2638   if (checkRetry) { bind(*checkRetry); }
2639   addic_(retry_count_Reg, retry_count_Reg, -1);
2640   blt(CCR0, doneRetry);
2641   b(retryLabel);
2642   bind(doneRetry);
2643 }
2644 
2645 // Spin and retry if lock is busy.
2646 // inputs: owner_addr_Reg (monitor address)
2647 //       : retry_count_Reg
2648 // output: retry_count_Reg decremented by 1
2649 // CTR is killed
2650 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register owner_addr_Reg, Label& retryLabel) {
2651   Label SpinLoop, doneRetry, doRetry;
2652   addic_(retry_count_Reg, retry_count_Reg, -1);
2653   blt(CCR0, doneRetry);
2654 
2655   if (RTMSpinLoopCount > 1) {
2656     li(R0, RTMSpinLoopCount);
2657     mtctr(R0);
2658   }
2659 
2660   // low thread priority
2661   smt_prio_low();
2662   bind(SpinLoop);
2663 
2664   if (RTMSpinLoopCount > 1) {
2665     bdz(doRetry);
2666     ld(R0, 0, owner_addr_Reg);
2667     cmpdi(CCR0, R0, 0);
2668     bne(CCR0, SpinLoop);
2669   }
2670 
2671   bind(doRetry);
2672 
2673   // restore thread priority to default in userspace
2674 #ifdef LINUX
2675   smt_prio_medium_low();
2676 #else
2677   smt_prio_medium();
2678 #endif
2679 
2680   b(retryLabel);
2681 
2682   bind(doneRetry);
2683 }
2684 
2685 // Use RTM for normal stack locks.
2686 // Input: objReg (object to lock)
2687 void MacroAssembler::rtm_stack_locking(ConditionRegister flag,
2688                                        Register obj, Register mark_word, Register tmp,
2689                                        Register retry_on_abort_count_Reg,
2690                                        RTMLockingCounters* stack_rtm_counters,
2691                                        Metadata* method_data, bool profile_rtm,
2692                                        Label& DONE_LABEL, Label& IsInflated) {
2693   assert(UseRTMForStackLocks, "why call this otherwise?");
2694   assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
2695   Label L_rtm_retry, L_decrement_retry, L_on_abort;
2696 
2697   if (RTMRetryCount > 0) {
2698     load_const_optimized(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
2699     bind(L_rtm_retry);
2700   }
2701   andi_(R0, mark_word, markOopDesc::monitor_value);  // inflated vs stack-locked|neutral|biased
2702   bne(CCR0, IsInflated);
2703 
2704   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
2705     Label L_noincrement;
2706     if (RTMTotalCountIncrRate > 1) {
2707       branch_on_random_using_tb(tmp, RTMTotalCountIncrRate, L_noincrement);
2708     }
2709     assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
2710     load_const_optimized(tmp, (address)stack_rtm_counters->total_count_addr(), R0);
2711     //atomic_inc_ptr(tmp, /*temp, will be reloaded*/mark_word); We don't increment atomically
2712     ldx(mark_word, tmp);
2713     addi(mark_word, mark_word, 1);
2714     stdx(mark_word, tmp);
2715     bind(L_noincrement);
2716   }
2717   tbegin_();
2718   beq(CCR0, L_on_abort);
2719   ld(mark_word, oopDesc::mark_offset_in_bytes(), obj);         // Reload in transaction, conflicts need to be tracked.
2720   andi(R0, mark_word, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2721   cmpwi(flag, R0, markOopDesc::unlocked_value);                // bits = 001 unlocked
2722   beq(flag, DONE_LABEL);                                       // all done if unlocked
2723 
2724   if (UseRTMXendForLockBusy) {
2725     tend_();
2726     b(L_decrement_retry);
2727   } else {
2728     tabort_();
2729   }
2730   bind(L_on_abort);
2731   const Register abort_status_Reg = tmp;
2732   mftexasr(abort_status_Reg);
2733   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
2734     rtm_profiling(abort_status_Reg, /*temp*/mark_word, stack_rtm_counters, method_data, profile_rtm);
2735   }
2736   ld(mark_word, oopDesc::mark_offset_in_bytes(), obj); // reload
2737   if (RTMRetryCount > 0) {
2738     // Retry on lock abort if abort status is not permanent.
2739     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry, &L_decrement_retry);
2740   } else {
2741     bind(L_decrement_retry);
2742   }
2743 }
2744 
2745 // Use RTM for inflating locks
2746 // inputs: obj       (object to lock)
2747 //         mark_word (current header - KILLED)
2748 //         boxReg    (on-stack box address (displaced header location) - KILLED)
2749 void MacroAssembler::rtm_inflated_locking(ConditionRegister flag,
2750                                           Register obj, Register mark_word, Register boxReg,
2751                                           Register retry_on_busy_count_Reg, Register retry_on_abort_count_Reg,
2752                                           RTMLockingCounters* rtm_counters,
2753                                           Metadata* method_data, bool profile_rtm,
2754                                           Label& DONE_LABEL) {
2755   assert(UseRTMLocking, "why call this otherwise?");
2756   Label L_rtm_retry, L_decrement_retry, L_on_abort;
2757   // Clean monitor_value bit to get valid pointer.
2758   int owner_offset = ObjectMonitor::owner_offset_in_bytes() - markOopDesc::monitor_value;
2759 
2760   // Store non-null, using boxReg instead of (intptr_t)markOopDesc::unused_mark().
2761   std(boxReg, BasicLock::displaced_header_offset_in_bytes(), boxReg);
2762   const Register tmpReg = boxReg;
2763   const Register owner_addr_Reg = mark_word;
2764   addi(owner_addr_Reg, mark_word, owner_offset);
2765 
2766   if (RTMRetryCount > 0) {
2767     load_const_optimized(retry_on_busy_count_Reg, RTMRetryCount);  // Retry on lock busy.
2768     load_const_optimized(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort.
2769     bind(L_rtm_retry);
2770   }
2771   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
2772     Label L_noincrement;
2773     if (RTMTotalCountIncrRate > 1) {
2774       branch_on_random_using_tb(R0, RTMTotalCountIncrRate, L_noincrement);
2775     }
2776     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
2777     load_const(R0, (address)rtm_counters->total_count_addr(), tmpReg);
2778     //atomic_inc_ptr(R0, tmpReg); We don't increment atomically
2779     ldx(tmpReg, R0);
2780     addi(tmpReg, tmpReg, 1);
2781     stdx(tmpReg, R0);
2782     bind(L_noincrement);
2783   }
2784   tbegin_();
2785   beq(CCR0, L_on_abort);
2786   // We don't reload mark word. Will only be reset at safepoint.
2787   ld(R0, 0, owner_addr_Reg); // Load in transaction, conflicts need to be tracked.
2788   cmpdi(flag, R0, 0);
2789   beq(flag, DONE_LABEL);
2790 
2791   if (UseRTMXendForLockBusy) {
2792     tend_();
2793     b(L_decrement_retry);
2794   } else {
2795     tabort_();
2796   }
2797   bind(L_on_abort);
2798   const Register abort_status_Reg = tmpReg;
2799   mftexasr(abort_status_Reg);
2800   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
2801     rtm_profiling(abort_status_Reg, /*temp*/ owner_addr_Reg, rtm_counters, method_data, profile_rtm);
2802     // Restore owner_addr_Reg
2803     ld(mark_word, oopDesc::mark_offset_in_bytes(), obj);
2804 #ifdef ASSERT
2805     andi_(R0, mark_word, markOopDesc::monitor_value);
2806     asm_assert_ne("must be inflated", 0xa754); // Deflating only allowed at safepoint.
2807 #endif
2808     addi(owner_addr_Reg, mark_word, owner_offset);
2809   }
2810   if (RTMRetryCount > 0) {
2811     // Retry on lock abort if abort status is not permanent.
2812     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
2813   }
2814 
2815   // Appears unlocked - try to swing _owner from null to non-null.
2816   cmpxchgd(flag, /*current val*/ R0, (intptr_t)0, /*new val*/ R16_thread, owner_addr_Reg,
2817            MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq,
2818            MacroAssembler::cmpxchgx_hint_acquire_lock(), noreg, &L_decrement_retry, true);
2819 
2820   if (RTMRetryCount > 0) {
2821     // success done else retry
2822     b(DONE_LABEL);
2823     bind(L_decrement_retry);
2824     // Spin and retry if lock is busy.
2825     rtm_retry_lock_on_busy(retry_on_busy_count_Reg, owner_addr_Reg, L_rtm_retry);
2826   } else {
2827     bind(L_decrement_retry);
2828   }
2829 }
2830 
2831 #endif //  INCLUDE_RTM_OPT
2832 
2833 // "The box" is the space on the stack where we copy the object mark.
2834 void MacroAssembler::compiler_fast_lock_object(ConditionRegister flag, Register oop, Register box,
2835                                                Register temp, Register displaced_header, Register current_header,
2836                                                bool try_bias,
2837                                                RTMLockingCounters* rtm_counters,
2838                                                RTMLockingCounters* stack_rtm_counters,
2839                                                Metadata* method_data,
2840                                                bool use_rtm, bool profile_rtm) {
2841   assert_different_registers(oop, box, temp, displaced_header, current_header);
2842   assert(flag != CCR0, "bad condition register");
2843   Label cont;
2844   Label object_has_monitor;
2845   Label cas_failed;
2846 
2847   // Load markOop from object into displaced_header.
2848   ld(displaced_header, oopDesc::mark_offset_in_bytes(), oop);
2849 
2850 
2851   if (try_bias) {
2852     biased_locking_enter(flag, oop, displaced_header, temp, current_header, cont);
2853   }
2854 
2855 #if INCLUDE_RTM_OPT
2856   if (UseRTMForStackLocks && use_rtm) {
2857     rtm_stack_locking(flag, oop, displaced_header, temp, /*temp*/ current_header,
2858                       stack_rtm_counters, method_data, profile_rtm,
2859                       cont, object_has_monitor);
2860   }
2861 #endif // INCLUDE_RTM_OPT
2862 
2863   // Handle existing monitor.
2864   // The object has an existing monitor iff (mark & monitor_value) != 0.
2865   andi_(temp, displaced_header, markOopDesc::monitor_value);
2866   bne(CCR0, object_has_monitor);
2867 
2868   // Set displaced_header to be (markOop of object | UNLOCK_VALUE).
2869   ori(displaced_header, displaced_header, markOopDesc::unlocked_value);
2870 
2871   // Load Compare Value application register.
2872 
2873   // Initialize the box. (Must happen before we update the object mark!)
2874   std(displaced_header, BasicLock::displaced_header_offset_in_bytes(), box);
2875 
2876   // Must fence, otherwise, preceding store(s) may float below cmpxchg.
2877   // Compare object markOop with mark and if equal exchange scratch1 with object markOop.
2878   cmpxchgd(/*flag=*/flag,
2879            /*current_value=*/current_header,
2880            /*compare_value=*/displaced_header,
2881            /*exchange_value=*/box,
2882            /*where=*/oop,
2883            MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq,
2884            MacroAssembler::cmpxchgx_hint_acquire_lock(),
2885            noreg,
2886            &cas_failed,
2887            /*check without membar and ldarx first*/true);
2888   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
2889 
2890   // If the compare-and-exchange succeeded, then we found an unlocked
2891   // object and we have now locked it.
2892   b(cont);
2893 
2894   bind(cas_failed);
2895   // We did not see an unlocked object so try the fast recursive case.
2896 
2897   // Check if the owner is self by comparing the value in the markOop of object
2898   // (current_header) with the stack pointer.
2899   sub(current_header, current_header, R1_SP);
2900   load_const_optimized(temp, ~(os::vm_page_size()-1) | markOopDesc::lock_mask_in_place);
2901 
2902   and_(R0/*==0?*/, current_header, temp);
2903   // If condition is true we are cont and hence we can store 0 as the
2904   // displaced header in the box, which indicates that it is a recursive lock.
2905   mcrf(flag,CCR0);
2906   std(R0/*==0, perhaps*/, BasicLock::displaced_header_offset_in_bytes(), box);
2907 
2908   // Handle existing monitor.
2909   b(cont);
2910 
2911   bind(object_has_monitor);
2912   // The object's monitor m is unlocked iff m->owner == NULL,
2913   // otherwise m->owner may contain a thread or a stack address.
2914 
2915 #if INCLUDE_RTM_OPT
2916   // Use the same RTM locking code in 32- and 64-bit VM.
2917   if (use_rtm) {
2918     rtm_inflated_locking(flag, oop, displaced_header, box, temp, /*temp*/ current_header,
2919                          rtm_counters, method_data, profile_rtm, cont);
2920   } else {
2921 #endif // INCLUDE_RTM_OPT
2922 
2923   // Try to CAS m->owner from NULL to current thread.
2924   addi(temp, displaced_header, ObjectMonitor::owner_offset_in_bytes()-markOopDesc::monitor_value);
2925   cmpxchgd(/*flag=*/flag,
2926            /*current_value=*/current_header,
2927            /*compare_value=*/(intptr_t)0,
2928            /*exchange_value=*/R16_thread,
2929            /*where=*/temp,
2930            MacroAssembler::MemBarRel | MacroAssembler::MemBarAcq,
2931            MacroAssembler::cmpxchgx_hint_acquire_lock());
2932 
2933   // Store a non-null value into the box.
2934   std(box, BasicLock::displaced_header_offset_in_bytes(), box);
2935 
2936 # ifdef ASSERT
2937   bne(flag, cont);
2938   // We have acquired the monitor, check some invariants.
2939   addi(/*monitor=*/temp, temp, -ObjectMonitor::owner_offset_in_bytes());
2940   // Invariant 1: _recursions should be 0.
2941   //assert(ObjectMonitor::recursions_size_in_bytes() == 8, "unexpected size");
2942   asm_assert_mem8_is_zero(ObjectMonitor::recursions_offset_in_bytes(), temp,
2943                             "monitor->_recursions should be 0", -1);
2944 # endif
2945 
2946 #if INCLUDE_RTM_OPT
2947   } // use_rtm()
2948 #endif
2949 
2950   bind(cont);
2951   // flag == EQ indicates success
2952   // flag == NE indicates failure
2953 }
2954 
2955 void MacroAssembler::compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box,
2956                                                  Register temp, Register displaced_header, Register current_header,
2957                                                  bool try_bias, bool use_rtm) {
2958   assert_different_registers(oop, box, temp, displaced_header, current_header);
2959   assert(flag != CCR0, "bad condition register");
2960   Label cont;
2961   Label object_has_monitor;
2962 
2963   if (try_bias) {
2964     biased_locking_exit(flag, oop, current_header, cont);
2965   }
2966 
2967 #if INCLUDE_RTM_OPT
2968   if (UseRTMForStackLocks && use_rtm) {
2969     assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
2970     Label L_regular_unlock;
2971     ld(current_header, oopDesc::mark_offset_in_bytes(), oop);         // fetch markword
2972     andi(R0, current_header, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2973     cmpwi(flag, R0, markOopDesc::unlocked_value);                     // bits = 001 unlocked
2974     bne(flag, L_regular_unlock);                                      // else RegularLock
2975     tend_();                                                          // otherwise end...
2976     b(cont);                                                          // ... and we're done
2977     bind(L_regular_unlock);
2978   }
2979 #endif
2980 
2981   // Find the lock address and load the displaced header from the stack.
2982   ld(displaced_header, BasicLock::displaced_header_offset_in_bytes(), box);
2983 
2984   // If the displaced header is 0, we have a recursive unlock.
2985   cmpdi(flag, displaced_header, 0);
2986   beq(flag, cont);
2987 
2988   // Handle existing monitor.
2989   // The object has an existing monitor iff (mark & monitor_value) != 0.
2990   RTM_OPT_ONLY( if (!(UseRTMForStackLocks && use_rtm)) ) // skip load if already done
2991   ld(current_header, oopDesc::mark_offset_in_bytes(), oop);
2992   andi_(R0, current_header, markOopDesc::monitor_value);
2993   bne(CCR0, object_has_monitor);
2994 
2995   // Check if it is still a light weight lock, this is is true if we see
2996   // the stack address of the basicLock in the markOop of the object.
2997   // Cmpxchg sets flag to cmpd(current_header, box).
2998   cmpxchgd(/*flag=*/flag,
2999            /*current_value=*/current_header,
3000            /*compare_value=*/box,
3001            /*exchange_value=*/displaced_header,
3002            /*where=*/oop,
3003            MacroAssembler::MemBarRel,
3004            MacroAssembler::cmpxchgx_hint_release_lock(),
3005            noreg,
3006            &cont);
3007 
3008   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
3009 
3010   // Handle existing monitor.
3011   b(cont);
3012 
3013   bind(object_has_monitor);
3014   addi(current_header, current_header, -markOopDesc::monitor_value); // monitor
3015   ld(temp,             ObjectMonitor::owner_offset_in_bytes(), current_header);
3016 
3017     // It's inflated.
3018 #if INCLUDE_RTM_OPT
3019   if (use_rtm) {
3020     Label L_regular_inflated_unlock;
3021     // Clean monitor_value bit to get valid pointer
3022     cmpdi(flag, temp, 0);
3023     bne(flag, L_regular_inflated_unlock);
3024     tend_();
3025     b(cont);
3026     bind(L_regular_inflated_unlock);
3027   }
3028 #endif
3029 
3030   ld(displaced_header, ObjectMonitor::recursions_offset_in_bytes(), current_header);
3031   xorr(temp, R16_thread, temp);      // Will be 0 if we are the owner.
3032   orr(temp, temp, displaced_header); // Will be 0 if there are 0 recursions.
3033   cmpdi(flag, temp, 0);
3034   bne(flag, cont);
3035 
3036   ld(temp,             ObjectMonitor::EntryList_offset_in_bytes(), current_header);
3037   ld(displaced_header, ObjectMonitor::cxq_offset_in_bytes(), current_header);
3038   orr(temp, temp, displaced_header); // Will be 0 if both are 0.
3039   cmpdi(flag, temp, 0);
3040   bne(flag, cont);
3041   release();
3042   std(temp, ObjectMonitor::owner_offset_in_bytes(), current_header);
3043 
3044   bind(cont);
3045   // flag == EQ indicates success
3046   // flag == NE indicates failure
3047 }
3048 
3049 void MacroAssembler::safepoint_poll(Label& slow_path, Register temp_reg) {
3050   if (SafepointMechanism::uses_thread_local_poll()) {
3051     ld(temp_reg, in_bytes(Thread::polling_page_offset()), R16_thread);
3052     // Armed page has poll_bit set.
3053     andi_(temp_reg, temp_reg, SafepointMechanism::poll_bit());
3054   } else {
3055     lwz(temp_reg, (RegisterOrConstant)(intptr_t)SafepointSynchronize::address_of_state());
3056     cmpwi(CCR0, temp_reg, SafepointSynchronize::_not_synchronized);
3057   }
3058   bne(CCR0, slow_path);
3059 }
3060 
3061 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2, bool needs_frame) {
3062   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3063   bs->resolve_jobject(this, value, tmp1, tmp2, needs_frame);
3064 }
3065 
3066 // Values for last_Java_pc, and last_Java_sp must comply to the rules
3067 // in frame_ppc.hpp.
3068 void MacroAssembler::set_last_Java_frame(Register last_Java_sp, Register last_Java_pc) {
3069   // Always set last_Java_pc and flags first because once last_Java_sp
3070   // is visible has_last_Java_frame is true and users will look at the
3071   // rest of the fields. (Note: flags should always be zero before we
3072   // get here so doesn't need to be set.)
3073 
3074   // Verify that last_Java_pc was zeroed on return to Java
3075   asm_assert_mem8_is_zero(in_bytes(JavaThread::last_Java_pc_offset()), R16_thread,
3076                           "last_Java_pc not zeroed before leaving Java", 0x200);
3077 
3078   // When returning from calling out from Java mode the frame anchor's
3079   // last_Java_pc will always be set to NULL. It is set here so that
3080   // if we are doing a call to native (not VM) that we capture the
3081   // known pc and don't have to rely on the native call having a
3082   // standard frame linkage where we can find the pc.
3083   if (last_Java_pc != noreg)
3084     std(last_Java_pc, in_bytes(JavaThread::last_Java_pc_offset()), R16_thread);
3085 
3086   // Set last_Java_sp last.
3087   std(last_Java_sp, in_bytes(JavaThread::last_Java_sp_offset()), R16_thread);
3088 }
3089 
3090 void MacroAssembler::reset_last_Java_frame(void) {
3091   asm_assert_mem8_isnot_zero(in_bytes(JavaThread::last_Java_sp_offset()),
3092                              R16_thread, "SP was not set, still zero", 0x202);
3093 
3094   BLOCK_COMMENT("reset_last_Java_frame {");
3095   li(R0, 0);
3096 
3097   // _last_Java_sp = 0
3098   std(R0, in_bytes(JavaThread::last_Java_sp_offset()), R16_thread);
3099 
3100   // _last_Java_pc = 0
3101   std(R0, in_bytes(JavaThread::last_Java_pc_offset()), R16_thread);
3102   BLOCK_COMMENT("} reset_last_Java_frame");
3103 }
3104 
3105 void MacroAssembler::set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1) {
3106   assert_different_registers(sp, tmp1);
3107 
3108   // sp points to a TOP_IJAVA_FRAME, retrieve frame's PC via
3109   // TOP_IJAVA_FRAME_ABI.
3110   // FIXME: assert that we really have a TOP_IJAVA_FRAME here!
3111   address entry = pc();
3112   load_const_optimized(tmp1, entry);
3113 
3114   set_last_Java_frame(/*sp=*/sp, /*pc=*/tmp1);
3115 }
3116 
3117 void MacroAssembler::get_vm_result(Register oop_result) {
3118   // Read:
3119   //   R16_thread
3120   //   R16_thread->in_bytes(JavaThread::vm_result_offset())
3121   //
3122   // Updated:
3123   //   oop_result
3124   //   R16_thread->in_bytes(JavaThread::vm_result_offset())
3125 
3126   verify_thread();
3127 
3128   ld(oop_result, in_bytes(JavaThread::vm_result_offset()), R16_thread);
3129   li(R0, 0);
3130   std(R0, in_bytes(JavaThread::vm_result_offset()), R16_thread);
3131 
3132   verify_oop(oop_result);
3133 }
3134 
3135 void MacroAssembler::get_vm_result_2(Register metadata_result) {
3136   // Read:
3137   //   R16_thread
3138   //   R16_thread->in_bytes(JavaThread::vm_result_2_offset())
3139   //
3140   // Updated:
3141   //   metadata_result
3142   //   R16_thread->in_bytes(JavaThread::vm_result_2_offset())
3143 
3144   ld(metadata_result, in_bytes(JavaThread::vm_result_2_offset()), R16_thread);
3145   li(R0, 0);
3146   std(R0, in_bytes(JavaThread::vm_result_2_offset()), R16_thread);
3147 }
3148 
3149 Register MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3150   Register current = (src != noreg) ? src : dst; // Klass is in dst if no src provided.
3151   if (CompressedKlassPointers::base() != 0) {
3152     // Use dst as temp if it is free.
3153     sub_const_optimized(dst, current, CompressedKlassPointers::base(), R0);
3154     current = dst;
3155   }
3156   if (CompressedKlassPointers::shift() != 0) {
3157     srdi(dst, current, CompressedKlassPointers::shift());
3158     current = dst;
3159   }
3160   return current;
3161 }
3162 
3163 void MacroAssembler::store_klass(Register dst_oop, Register klass, Register ck) {
3164   if (UseCompressedClassPointers) {
3165     Register compressedKlass = encode_klass_not_null(ck, klass);
3166     stw(compressedKlass, oopDesc::klass_offset_in_bytes(), dst_oop);
3167   } else {
3168     std(klass, oopDesc::klass_offset_in_bytes(), dst_oop);
3169   }
3170 }
3171 
3172 void MacroAssembler::store_klass_gap(Register dst_oop, Register val) {
3173   if (UseCompressedClassPointers) {
3174     if (val == noreg) {
3175       val = R0;
3176       li(val, 0);
3177     }
3178     stw(val, oopDesc::klass_gap_offset_in_bytes(), dst_oop); // klass gap if compressed
3179   }
3180 }
3181 
3182 int MacroAssembler::instr_size_for_decode_klass_not_null() {
3183   if (!UseCompressedClassPointers) return 0;
3184   int num_instrs = 1;  // shift or move
3185   if (CompressedKlassPointers::base() != 0) num_instrs = 7;  // shift + load const + add
3186   return num_instrs * BytesPerInstWord;
3187 }
3188 
3189 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3190   assert(dst != R0, "Dst reg may not be R0, as R0 is used here.");
3191   if (src == noreg) src = dst;
3192   Register shifted_src = src;
3193   if (CompressedKlassPointers::shift() != 0 ||
3194       CompressedKlassPointers::base() == 0 && src != dst) {  // Move required.
3195     shifted_src = dst;
3196     sldi(shifted_src, src, CompressedKlassPointers::shift());
3197   }
3198   if (CompressedKlassPointers::base() != 0) {
3199     add_const_optimized(dst, shifted_src, CompressedKlassPointers::base(), R0);
3200   }
3201 }
3202 
3203 void MacroAssembler::load_klass(Register dst, Register src) {
3204   if (UseCompressedClassPointers) {
3205     lwz(dst, oopDesc::klass_offset_in_bytes(), src);
3206     // Attention: no null check here!
3207     decode_klass_not_null(dst, dst);
3208   } else {
3209     ld(dst, oopDesc::klass_offset_in_bytes(), src);
3210   }
3211 }
3212 
3213 // ((OopHandle)result).resolve();
3214 void MacroAssembler::resolve_oop_handle(Register result) {
3215   // OopHandle::resolve is an indirection.
3216   ld(result, 0, result);
3217 }
3218 
3219 void MacroAssembler::load_mirror_from_const_method(Register mirror, Register const_method) {
3220   ld(mirror, in_bytes(ConstMethod::constants_offset()), const_method);
3221   ld(mirror, ConstantPool::pool_holder_offset_in_bytes(), mirror);
3222   ld(mirror, in_bytes(Klass::java_mirror_offset()), mirror);
3223   resolve_oop_handle(mirror);
3224 }
3225 
3226 void MacroAssembler::load_method_holder(Register holder, Register method) {
3227   ld(holder, in_bytes(Method::const_offset()), method);
3228   ld(holder, in_bytes(ConstMethod::constants_offset()), holder);
3229   ld(holder, ConstantPool::pool_holder_offset_in_bytes(), holder);
3230 }
3231 
3232 // Clear Array
3233 // For very short arrays. tmp == R0 is allowed.
3234 void MacroAssembler::clear_memory_unrolled(Register base_ptr, int cnt_dwords, Register tmp, int offset) {
3235   if (cnt_dwords > 0) { li(tmp, 0); }
3236   for (int i = 0; i < cnt_dwords; ++i) { std(tmp, offset + i * 8, base_ptr); }
3237 }
3238 
3239 // Version for constant short array length. Kills base_ptr. tmp == R0 is allowed.
3240 void MacroAssembler::clear_memory_constlen(Register base_ptr, int cnt_dwords, Register tmp) {
3241   if (cnt_dwords < 8) {
3242     clear_memory_unrolled(base_ptr, cnt_dwords, tmp);
3243     return;
3244   }
3245 
3246   Label loop;
3247   const long loopcnt   = cnt_dwords >> 1,
3248              remainder = cnt_dwords & 1;
3249 
3250   li(tmp, loopcnt);
3251   mtctr(tmp);
3252   li(tmp, 0);
3253   bind(loop);
3254     std(tmp, 0, base_ptr);
3255     std(tmp, 8, base_ptr);
3256     addi(base_ptr, base_ptr, 16);
3257     bdnz(loop);
3258   if (remainder) { std(tmp, 0, base_ptr); }
3259 }
3260 
3261 // Kills both input registers. tmp == R0 is allowed.
3262 void MacroAssembler::clear_memory_doubleword(Register base_ptr, Register cnt_dwords, Register tmp, long const_cnt) {
3263   // Procedure for large arrays (uses data cache block zero instruction).
3264     Label startloop, fast, fastloop, small_rest, restloop, done;
3265     const int cl_size         = VM_Version::L1_data_cache_line_size(),
3266               cl_dwords       = cl_size >> 3,
3267               cl_dw_addr_bits = exact_log2(cl_dwords),
3268               dcbz_min        = 1,  // Min count of dcbz executions, needs to be >0.
3269               min_cnt         = ((dcbz_min + 1) << cl_dw_addr_bits) - 1;
3270 
3271   if (const_cnt >= 0) {
3272     // Constant case.
3273     if (const_cnt < min_cnt) {
3274       clear_memory_constlen(base_ptr, const_cnt, tmp);
3275       return;
3276     }
3277     load_const_optimized(cnt_dwords, const_cnt, tmp);
3278   } else {
3279     // cnt_dwords already loaded in register. Need to check size.
3280     cmpdi(CCR1, cnt_dwords, min_cnt); // Big enough? (ensure >= dcbz_min lines included).
3281     blt(CCR1, small_rest);
3282   }
3283     rldicl_(tmp, base_ptr, 64-3, 64-cl_dw_addr_bits); // Extract dword offset within first cache line.
3284     beq(CCR0, fast);                                  // Already 128byte aligned.
3285 
3286     subfic(tmp, tmp, cl_dwords);
3287     mtctr(tmp);                        // Set ctr to hit 128byte boundary (0<ctr<cl_dwords).
3288     subf(cnt_dwords, tmp, cnt_dwords); // rest.
3289     li(tmp, 0);
3290 
3291   bind(startloop);                     // Clear at the beginning to reach 128byte boundary.
3292     std(tmp, 0, base_ptr);             // Clear 8byte aligned block.
3293     addi(base_ptr, base_ptr, 8);
3294     bdnz(startloop);
3295 
3296   bind(fast);                                  // Clear 128byte blocks.
3297     srdi(tmp, cnt_dwords, cl_dw_addr_bits);    // Loop count for 128byte loop (>0).
3298     andi(cnt_dwords, cnt_dwords, cl_dwords-1); // Rest in dwords.
3299     mtctr(tmp);                                // Load counter.
3300 
3301   bind(fastloop);
3302     dcbz(base_ptr);                    // Clear 128byte aligned block.
3303     addi(base_ptr, base_ptr, cl_size);
3304     bdnz(fastloop);
3305 
3306   bind(small_rest);
3307     cmpdi(CCR0, cnt_dwords, 0);        // size 0?
3308     beq(CCR0, done);                   // rest == 0
3309     li(tmp, 0);
3310     mtctr(cnt_dwords);                 // Load counter.
3311 
3312   bind(restloop);                      // Clear rest.
3313     std(tmp, 0, base_ptr);             // Clear 8byte aligned block.
3314     addi(base_ptr, base_ptr, 8);
3315     bdnz(restloop);
3316 
3317   bind(done);
3318 }
3319 
3320 /////////////////////////////////////////// String intrinsics ////////////////////////////////////////////
3321 
3322 #ifdef COMPILER2
3323 // Intrinsics for CompactStrings
3324 
3325 // Compress char[] to byte[] by compressing 16 bytes at once.
3326 void MacroAssembler::string_compress_16(Register src, Register dst, Register cnt,
3327                                         Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
3328                                         Label& Lfailure) {
3329 
3330   const Register tmp0 = R0;
3331   assert_different_registers(src, dst, cnt, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
3332   Label Lloop, Lslow;
3333 
3334   // Check if cnt >= 8 (= 16 bytes)
3335   lis(tmp1, 0xFF);                // tmp1 = 0x00FF00FF00FF00FF
3336   srwi_(tmp2, cnt, 3);
3337   beq(CCR0, Lslow);
3338   ori(tmp1, tmp1, 0xFF);
3339   rldimi(tmp1, tmp1, 32, 0);
3340   mtctr(tmp2);
3341 
3342   // 2x unrolled loop
3343   bind(Lloop);
3344   ld(tmp2, 0, src);               // _0_1_2_3 (Big Endian)
3345   ld(tmp4, 8, src);               // _4_5_6_7
3346 
3347   orr(tmp0, tmp2, tmp4);
3348   rldicl(tmp3, tmp2, 6*8, 64-24); // _____1_2
3349   rldimi(tmp2, tmp2, 2*8, 2*8);   // _0_2_3_3
3350   rldicl(tmp5, tmp4, 6*8, 64-24); // _____5_6
3351   rldimi(tmp4, tmp4, 2*8, 2*8);   // _4_6_7_7
3352 
3353   andc_(tmp0, tmp0, tmp1);
3354   bne(CCR0, Lfailure);            // Not latin1.
3355   addi(src, src, 16);
3356 
3357   rlwimi(tmp3, tmp2, 0*8, 24, 31);// _____1_3
3358   srdi(tmp2, tmp2, 3*8);          // ____0_2_
3359   rlwimi(tmp5, tmp4, 0*8, 24, 31);// _____5_7
3360   srdi(tmp4, tmp4, 3*8);          // ____4_6_
3361 
3362   orr(tmp2, tmp2, tmp3);          // ____0123
3363   orr(tmp4, tmp4, tmp5);          // ____4567
3364 
3365   stw(tmp2, 0, dst);
3366   stw(tmp4, 4, dst);
3367   addi(dst, dst, 8);
3368   bdnz(Lloop);
3369 
3370   bind(Lslow);                    // Fallback to slow version
3371 }
3372 
3373 // Compress char[] to byte[]. cnt must be positive int.
3374 void MacroAssembler::string_compress(Register src, Register dst, Register cnt, Register tmp, Label& Lfailure) {
3375   Label Lloop;
3376   mtctr(cnt);
3377 
3378   bind(Lloop);
3379   lhz(tmp, 0, src);
3380   cmplwi(CCR0, tmp, 0xff);
3381   bgt(CCR0, Lfailure);            // Not latin1.
3382   addi(src, src, 2);
3383   stb(tmp, 0, dst);
3384   addi(dst, dst, 1);
3385   bdnz(Lloop);
3386 }
3387 
3388 // Inflate byte[] to char[] by inflating 16 bytes at once.
3389 void MacroAssembler::string_inflate_16(Register src, Register dst, Register cnt,
3390                                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
3391   const Register tmp0 = R0;
3392   assert_different_registers(src, dst, cnt, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
3393   Label Lloop, Lslow;
3394 
3395   // Check if cnt >= 8
3396   srwi_(tmp2, cnt, 3);
3397   beq(CCR0, Lslow);
3398   lis(tmp1, 0xFF);                // tmp1 = 0x00FF00FF
3399   ori(tmp1, tmp1, 0xFF);
3400   mtctr(tmp2);
3401 
3402   // 2x unrolled loop
3403   bind(Lloop);
3404   lwz(tmp2, 0, src);              // ____0123 (Big Endian)
3405   lwz(tmp4, 4, src);              // ____4567
3406   addi(src, src, 8);
3407 
3408   rldicl(tmp3, tmp2, 7*8, 64-8);  // _______2
3409   rlwimi(tmp2, tmp2, 3*8, 16, 23);// ____0113
3410   rldicl(tmp5, tmp4, 7*8, 64-8);  // _______6
3411   rlwimi(tmp4, tmp4, 3*8, 16, 23);// ____4557
3412 
3413   andc(tmp0, tmp2, tmp1);         // ____0_1_
3414   rlwimi(tmp2, tmp3, 2*8, 0, 23); // _____2_3
3415   andc(tmp3, tmp4, tmp1);         // ____4_5_
3416   rlwimi(tmp4, tmp5, 2*8, 0, 23); // _____6_7
3417 
3418   rldimi(tmp2, tmp0, 3*8, 0*8);   // _0_1_2_3
3419   rldimi(tmp4, tmp3, 3*8, 0*8);   // _4_5_6_7
3420 
3421   std(tmp2, 0, dst);
3422   std(tmp4, 8, dst);
3423   addi(dst, dst, 16);
3424   bdnz(Lloop);
3425 
3426   bind(Lslow);                    // Fallback to slow version
3427 }
3428 
3429 // Inflate byte[] to char[]. cnt must be positive int.
3430 void MacroAssembler::string_inflate(Register src, Register dst, Register cnt, Register tmp) {
3431   Label Lloop;
3432   mtctr(cnt);
3433 
3434   bind(Lloop);
3435   lbz(tmp, 0, src);
3436   addi(src, src, 1);
3437   sth(tmp, 0, dst);
3438   addi(dst, dst, 2);
3439   bdnz(Lloop);
3440 }
3441 
3442 void MacroAssembler::string_compare(Register str1, Register str2,
3443                                     Register cnt1, Register cnt2,
3444                                     Register tmp1, Register result, int ae) {
3445   const Register tmp0 = R0,
3446                  diff = tmp1;
3447 
3448   assert_different_registers(str1, str2, cnt1, cnt2, tmp0, tmp1, result);
3449   Label Ldone, Lslow, Lloop, Lreturn_diff;
3450 
3451   // Note: Making use of the fact that compareTo(a, b) == -compareTo(b, a)
3452   // we interchange str1 and str2 in the UL case and negate the result.
3453   // Like this, str1 is always latin1 encoded, except for the UU case.
3454   // In addition, we need 0 (or sign which is 0) extend.
3455 
3456   if (ae == StrIntrinsicNode::UU) {
3457     srwi(cnt1, cnt1, 1);
3458   } else {
3459     clrldi(cnt1, cnt1, 32);
3460   }
3461 
3462   if (ae != StrIntrinsicNode::LL) {
3463     srwi(cnt2, cnt2, 1);
3464   } else {
3465     clrldi(cnt2, cnt2, 32);
3466   }
3467 
3468   // See if the lengths are different, and calculate min in cnt1.
3469   // Save diff in case we need it for a tie-breaker.
3470   subf_(diff, cnt2, cnt1); // diff = cnt1 - cnt2
3471   // if (diff > 0) { cnt1 = cnt2; }
3472   if (VM_Version::has_isel()) {
3473     isel(cnt1, CCR0, Assembler::greater, /*invert*/ false, cnt2);
3474   } else {
3475     Label Lskip;
3476     blt(CCR0, Lskip);
3477     mr(cnt1, cnt2);
3478     bind(Lskip);
3479   }
3480 
3481   // Rename registers
3482   Register chr1 = result;
3483   Register chr2 = tmp0;
3484 
3485   // Compare multiple characters in fast loop (only implemented for same encoding).
3486   int stride1 = 8, stride2 = 8;
3487   if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
3488     int log2_chars_per_iter = (ae == StrIntrinsicNode::LL) ? 3 : 2;
3489     Label Lfastloop, Lskipfast;
3490 
3491     srwi_(tmp0, cnt1, log2_chars_per_iter);
3492     beq(CCR0, Lskipfast);
3493     rldicl(cnt2, cnt1, 0, 64 - log2_chars_per_iter); // Remaining characters.
3494     li(cnt1, 1 << log2_chars_per_iter); // Initialize for failure case: Rescan characters from current iteration.
3495     mtctr(tmp0);
3496 
3497     bind(Lfastloop);
3498     ld(chr1, 0, str1);
3499     ld(chr2, 0, str2);
3500     cmpd(CCR0, chr1, chr2);
3501     bne(CCR0, Lslow);
3502     addi(str1, str1, stride1);
3503     addi(str2, str2, stride2);
3504     bdnz(Lfastloop);
3505     mr(cnt1, cnt2); // Remaining characters.
3506     bind(Lskipfast);
3507   }
3508 
3509   // Loop which searches the first difference character by character.
3510   cmpwi(CCR0, cnt1, 0);
3511   beq(CCR0, Lreturn_diff);
3512   bind(Lslow);
3513   mtctr(cnt1);
3514 
3515   switch (ae) {
3516     case StrIntrinsicNode::LL: stride1 = 1; stride2 = 1; break;
3517     case StrIntrinsicNode::UL: // fallthru (see comment above)
3518     case StrIntrinsicNode::LU: stride1 = 1; stride2 = 2; break;
3519     case StrIntrinsicNode::UU: stride1 = 2; stride2 = 2; break;
3520     default: ShouldNotReachHere(); break;
3521   }
3522 
3523   bind(Lloop);
3524   if (stride1 == 1) { lbz(chr1, 0, str1); } else { lhz(chr1, 0, str1); }
3525   if (stride2 == 1) { lbz(chr2, 0, str2); } else { lhz(chr2, 0, str2); }
3526   subf_(result, chr2, chr1); // result = chr1 - chr2
3527   bne(CCR0, Ldone);
3528   addi(str1, str1, stride1);
3529   addi(str2, str2, stride2);
3530   bdnz(Lloop);
3531 
3532   // If strings are equal up to min length, return the length difference.
3533   bind(Lreturn_diff);
3534   mr(result, diff);
3535 
3536   // Otherwise, return the difference between the first mismatched chars.
3537   bind(Ldone);
3538   if (ae == StrIntrinsicNode::UL) {
3539     neg(result, result); // Negate result (see note above).
3540   }
3541 }
3542 
3543 void MacroAssembler::array_equals(bool is_array_equ, Register ary1, Register ary2,
3544                                   Register limit, Register tmp1, Register result, bool is_byte) {
3545   const Register tmp0 = R0;
3546   assert_different_registers(ary1, ary2, limit, tmp0, tmp1, result);
3547   Label Ldone, Lskiploop, Lloop, Lfastloop, Lskipfast;
3548   bool limit_needs_shift = false;
3549 
3550   if (is_array_equ) {
3551     const int length_offset = arrayOopDesc::length_offset_in_bytes();
3552     const int base_offset   = arrayOopDesc::base_offset_in_bytes(is_byte ? T_BYTE : T_CHAR);
3553 
3554     // Return true if the same array.
3555     cmpd(CCR0, ary1, ary2);
3556     beq(CCR0, Lskiploop);
3557 
3558     // Return false if one of them is NULL.
3559     cmpdi(CCR0, ary1, 0);
3560     cmpdi(CCR1, ary2, 0);
3561     li(result, 0);
3562     cror(CCR0, Assembler::equal, CCR1, Assembler::equal);
3563     beq(CCR0, Ldone);
3564 
3565     // Load the lengths of arrays.
3566     lwz(limit, length_offset, ary1);
3567     lwz(tmp0, length_offset, ary2);
3568 
3569     // Return false if the two arrays are not equal length.
3570     cmpw(CCR0, limit, tmp0);
3571     bne(CCR0, Ldone);
3572 
3573     // Load array addresses.
3574     addi(ary1, ary1, base_offset);
3575     addi(ary2, ary2, base_offset);
3576   } else {
3577     limit_needs_shift = !is_byte;
3578     li(result, 0); // Assume not equal.
3579   }
3580 
3581   // Rename registers
3582   Register chr1 = tmp0;
3583   Register chr2 = tmp1;
3584 
3585   // Compare 8 bytes per iteration in fast loop.
3586   const int log2_chars_per_iter = is_byte ? 3 : 2;
3587 
3588   srwi_(tmp0, limit, log2_chars_per_iter + (limit_needs_shift ? 1 : 0));
3589   beq(CCR0, Lskipfast);
3590   mtctr(tmp0);
3591 
3592   bind(Lfastloop);
3593   ld(chr1, 0, ary1);
3594   ld(chr2, 0, ary2);
3595   addi(ary1, ary1, 8);
3596   addi(ary2, ary2, 8);
3597   cmpd(CCR0, chr1, chr2);
3598   bne(CCR0, Ldone);
3599   bdnz(Lfastloop);
3600 
3601   bind(Lskipfast);
3602   rldicl_(limit, limit, limit_needs_shift ? 64 - 1 : 0, 64 - log2_chars_per_iter); // Remaining characters.
3603   beq(CCR0, Lskiploop);
3604   mtctr(limit);
3605 
3606   // Character by character.
3607   bind(Lloop);
3608   if (is_byte) {
3609     lbz(chr1, 0, ary1);
3610     lbz(chr2, 0, ary2);
3611     addi(ary1, ary1, 1);
3612     addi(ary2, ary2, 1);
3613   } else {
3614     lhz(chr1, 0, ary1);
3615     lhz(chr2, 0, ary2);
3616     addi(ary1, ary1, 2);
3617     addi(ary2, ary2, 2);
3618   }
3619   cmpw(CCR0, chr1, chr2);
3620   bne(CCR0, Ldone);
3621   bdnz(Lloop);
3622 
3623   bind(Lskiploop);
3624   li(result, 1); // All characters are equal.
3625   bind(Ldone);
3626 }
3627 
3628 void MacroAssembler::string_indexof(Register result, Register haystack, Register haycnt,
3629                                     Register needle, ciTypeArray* needle_values, Register needlecnt, int needlecntval,
3630                                     Register tmp1, Register tmp2, Register tmp3, Register tmp4, int ae) {
3631 
3632   // Ensure 0<needlecnt<=haycnt in ideal graph as prerequisite!
3633   Label L_TooShort, L_Found, L_NotFound, L_End;
3634   Register last_addr = haycnt, // Kill haycnt at the beginning.
3635   addr      = tmp1,
3636   n_start   = tmp2,
3637   ch1       = tmp3,
3638   ch2       = R0;
3639 
3640   assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
3641   const int h_csize = (ae == StrIntrinsicNode::LL) ? 1 : 2;
3642   const int n_csize = (ae == StrIntrinsicNode::UU) ? 2 : 1;
3643 
3644   // **************************************************************************************************
3645   // Prepare for main loop: optimized for needle count >=2, bail out otherwise.
3646   // **************************************************************************************************
3647 
3648   // Compute last haystack addr to use if no match gets found.
3649   clrldi(haycnt, haycnt, 32);         // Ensure positive int is valid as 64 bit value.
3650   addi(addr, haystack, -h_csize);     // Accesses use pre-increment.
3651   if (needlecntval == 0) { // variable needlecnt
3652    cmpwi(CCR6, needlecnt, 2);
3653    clrldi(needlecnt, needlecnt, 32);  // Ensure positive int is valid as 64 bit value.
3654    blt(CCR6, L_TooShort);             // Variable needlecnt: handle short needle separately.
3655   }
3656 
3657   if (n_csize == 2) { lwz(n_start, 0, needle); } else { lhz(n_start, 0, needle); } // Load first 2 characters of needle.
3658 
3659   if (needlecntval == 0) { // variable needlecnt
3660    subf(ch1, needlecnt, haycnt);      // Last character index to compare is haycnt-needlecnt.
3661    addi(needlecnt, needlecnt, -2);    // Rest of needle.
3662   } else { // constant needlecnt
3663   guarantee(needlecntval != 1, "IndexOf with single-character needle must be handled separately");
3664   assert((needlecntval & 0x7fff) == needlecntval, "wrong immediate");
3665    addi(ch1, haycnt, -needlecntval);  // Last character index to compare is haycnt-needlecnt.
3666    if (needlecntval > 3) { li(needlecnt, needlecntval - 2); } // Rest of needle.
3667   }
3668 
3669   if (h_csize == 2) { slwi(ch1, ch1, 1); } // Scale to number of bytes.
3670 
3671   if (ae ==StrIntrinsicNode::UL) {
3672    srwi(tmp4, n_start, 1*8);          // ___0
3673    rlwimi(n_start, tmp4, 2*8, 0, 23); // _0_1
3674   }
3675 
3676   add(last_addr, haystack, ch1);      // Point to last address to compare (haystack+2*(haycnt-needlecnt)).
3677 
3678   // Main Loop (now we have at least 2 characters).
3679   Label L_OuterLoop, L_InnerLoop, L_FinalCheck, L_Comp1, L_Comp2;
3680   bind(L_OuterLoop); // Search for 1st 2 characters.
3681   Register addr_diff = tmp4;
3682    subf(addr_diff, addr, last_addr);  // Difference between already checked address and last address to check.
3683    addi(addr, addr, h_csize);         // This is the new address we want to use for comparing.
3684    srdi_(ch2, addr_diff, h_csize);
3685    beq(CCR0, L_FinalCheck);           // 2 characters left?
3686    mtctr(ch2);                        // num of characters / 2
3687   bind(L_InnerLoop);                  // Main work horse (2x unrolled search loop)
3688    if (h_csize == 2) {                // Load 2 characters of haystack (ignore alignment).
3689     lwz(ch1, 0, addr);
3690     lwz(ch2, 2, addr);
3691    } else {
3692     lhz(ch1, 0, addr);
3693     lhz(ch2, 1, addr);
3694    }
3695    cmpw(CCR0, ch1, n_start);          // Compare 2 characters (1 would be sufficient but try to reduce branches to CompLoop).
3696    cmpw(CCR1, ch2, n_start);
3697    beq(CCR0, L_Comp1);                // Did we find the needle start?
3698    beq(CCR1, L_Comp2);
3699    addi(addr, addr, 2 * h_csize);
3700    bdnz(L_InnerLoop);
3701   bind(L_FinalCheck);
3702    andi_(addr_diff, addr_diff, h_csize); // Remaining characters not covered by InnerLoop: (num of characters) & 1.
3703    beq(CCR0, L_NotFound);
3704    if (h_csize == 2) { lwz(ch1, 0, addr); } else { lhz(ch1, 0, addr); } // One position left at which we have to compare.
3705    cmpw(CCR1, ch1, n_start);
3706    beq(CCR1, L_Comp1);
3707   bind(L_NotFound);
3708    li(result, -1);                    // not found
3709    b(L_End);
3710 
3711    // **************************************************************************************************
3712    // Special Case: unfortunately, the variable needle case can be called with needlecnt<2
3713    // **************************************************************************************************
3714   if (needlecntval == 0) {           // We have to handle these cases separately.
3715   Label L_OneCharLoop;
3716   bind(L_TooShort);
3717    mtctr(haycnt);
3718    if (n_csize == 2) { lhz(n_start, 0, needle); } else { lbz(n_start, 0, needle); } // First character of needle
3719   bind(L_OneCharLoop);
3720    if (h_csize == 2) { lhzu(ch1, 2, addr); } else { lbzu(ch1, 1, addr); }
3721    cmpw(CCR1, ch1, n_start);
3722    beq(CCR1, L_Found);               // Did we find the one character needle?
3723    bdnz(L_OneCharLoop);
3724    li(result, -1);                   // Not found.
3725    b(L_End);
3726   }
3727 
3728   // **************************************************************************************************
3729   // Regular Case Part II: compare rest of needle (first 2 characters have been compared already)
3730   // **************************************************************************************************
3731 
3732   // Compare the rest
3733   bind(L_Comp2);
3734    addi(addr, addr, h_csize);        // First comparison has failed, 2nd one hit.
3735   bind(L_Comp1);                     // Addr points to possible needle start.
3736   if (needlecntval != 2) {           // Const needlecnt==2?
3737    if (needlecntval != 3) {
3738     if (needlecntval == 0) { beq(CCR6, L_Found); } // Variable needlecnt==2?
3739     Register n_ind = tmp4,
3740              h_ind = n_ind;
3741     li(n_ind, 2 * n_csize);          // First 2 characters are already compared, use index 2.
3742     mtctr(needlecnt);                // Decremented by 2, still > 0.
3743    Label L_CompLoop;
3744    bind(L_CompLoop);
3745     if (ae ==StrIntrinsicNode::UL) {
3746       h_ind = ch1;
3747       sldi(h_ind, n_ind, 1);
3748     }
3749     if (n_csize == 2) { lhzx(ch2, needle, n_ind); } else { lbzx(ch2, needle, n_ind); }
3750     if (h_csize == 2) { lhzx(ch1, addr, h_ind); } else { lbzx(ch1, addr, h_ind); }
3751     cmpw(CCR1, ch1, ch2);
3752     bne(CCR1, L_OuterLoop);
3753     addi(n_ind, n_ind, n_csize);
3754     bdnz(L_CompLoop);
3755    } else { // No loop required if there's only one needle character left.
3756     if (n_csize == 2) { lhz(ch2, 2 * 2, needle); } else { lbz(ch2, 2 * 1, needle); }
3757     if (h_csize == 2) { lhz(ch1, 2 * 2, addr); } else { lbz(ch1, 2 * 1, addr); }
3758     cmpw(CCR1, ch1, ch2);
3759     bne(CCR1, L_OuterLoop);
3760    }
3761   }
3762   // Return index ...
3763   bind(L_Found);
3764    subf(result, haystack, addr);     // relative to haystack, ...
3765    if (h_csize == 2) { srdi(result, result, 1); } // in characters.
3766   bind(L_End);
3767 } // string_indexof
3768 
3769 void MacroAssembler::string_indexof_char(Register result, Register haystack, Register haycnt,
3770                                          Register needle, jchar needleChar, Register tmp1, Register tmp2, bool is_byte) {
3771   assert_different_registers(haystack, haycnt, needle, tmp1, tmp2);
3772 
3773   Label L_InnerLoop, L_FinalCheck, L_Found1, L_Found2, L_NotFound, L_End;
3774   Register addr = tmp1,
3775            ch1 = tmp2,
3776            ch2 = R0;
3777 
3778   const int h_csize = is_byte ? 1 : 2;
3779 
3780 //4:
3781    srwi_(tmp2, haycnt, 1);   // Shift right by exact_log2(UNROLL_FACTOR).
3782    mr(addr, haystack);
3783    beq(CCR0, L_FinalCheck);
3784    mtctr(tmp2);              // Move to count register.
3785 //8:
3786   bind(L_InnerLoop);         // Main work horse (2x unrolled search loop).
3787    if (!is_byte) {
3788     lhz(ch1, 0, addr);
3789     lhz(ch2, 2, addr);
3790    } else {
3791     lbz(ch1, 0, addr);
3792     lbz(ch2, 1, addr);
3793    }
3794    (needle != R0) ? cmpw(CCR0, ch1, needle) : cmplwi(CCR0, ch1, (unsigned int)needleChar);
3795    (needle != R0) ? cmpw(CCR1, ch2, needle) : cmplwi(CCR1, ch2, (unsigned int)needleChar);
3796    beq(CCR0, L_Found1);      // Did we find the needle?
3797    beq(CCR1, L_Found2);
3798    addi(addr, addr, 2 * h_csize);
3799    bdnz(L_InnerLoop);
3800 //16:
3801   bind(L_FinalCheck);
3802    andi_(R0, haycnt, 1);
3803    beq(CCR0, L_NotFound);
3804    if (!is_byte) { lhz(ch1, 0, addr); } else { lbz(ch1, 0, addr); } // One position left at which we have to compare.
3805    (needle != R0) ? cmpw(CCR1, ch1, needle) : cmplwi(CCR1, ch1, (unsigned int)needleChar);
3806    beq(CCR1, L_Found1);
3807 //21:
3808   bind(L_NotFound);
3809    li(result, -1);           // Not found.
3810    b(L_End);
3811 
3812   bind(L_Found2);
3813    addi(addr, addr, h_csize);
3814 //24:
3815   bind(L_Found1);            // Return index ...
3816    subf(result, haystack, addr); // relative to haystack, ...
3817    if (!is_byte) { srdi(result, result, 1); } // in characters.
3818   bind(L_End);
3819 } // string_indexof_char
3820 
3821 
3822 void MacroAssembler::has_negatives(Register src, Register cnt, Register result,
3823                                    Register tmp1, Register tmp2) {
3824   const Register tmp0 = R0;
3825   assert_different_registers(src, result, cnt, tmp0, tmp1, tmp2);
3826   Label Lfastloop, Lslow, Lloop, Lnoneg, Ldone;
3827 
3828   // Check if cnt >= 8 (= 16 bytes)
3829   lis(tmp1, (int)(short)0x8080);  // tmp1 = 0x8080808080808080
3830   srwi_(tmp2, cnt, 4);
3831   li(result, 1);                  // Assume there's a negative byte.
3832   beq(CCR0, Lslow);
3833   ori(tmp1, tmp1, 0x8080);
3834   rldimi(tmp1, tmp1, 32, 0);
3835   mtctr(tmp2);
3836 
3837   // 2x unrolled loop
3838   bind(Lfastloop);
3839   ld(tmp2, 0, src);
3840   ld(tmp0, 8, src);
3841 
3842   orr(tmp0, tmp2, tmp0);
3843 
3844   and_(tmp0, tmp0, tmp1);
3845   bne(CCR0, Ldone);               // Found negative byte.
3846   addi(src, src, 16);
3847 
3848   bdnz(Lfastloop);
3849 
3850   bind(Lslow);                    // Fallback to slow version
3851   rldicl_(tmp0, cnt, 0, 64-4);
3852   beq(CCR0, Lnoneg);
3853   mtctr(tmp0);
3854   bind(Lloop);
3855   lbz(tmp0, 0, src);
3856   addi(src, src, 1);
3857   andi_(tmp0, tmp0, 0x80);
3858   bne(CCR0, Ldone);               // Found negative byte.
3859   bdnz(Lloop);
3860   bind(Lnoneg);
3861   li(result, 0);
3862 
3863   bind(Ldone);
3864 }
3865 
3866 #endif // Compiler2
3867 
3868 // Helpers for Intrinsic Emitters
3869 //
3870 // Revert the byte order of a 32bit value in a register
3871 //   src: 0x44556677
3872 //   dst: 0x77665544
3873 // Three steps to obtain the result:
3874 //  1) Rotate src (as doubleword) left 5 bytes. That puts the leftmost byte of the src word
3875 //     into the rightmost byte position. Afterwards, everything left of the rightmost byte is cleared.
3876 //     This value initializes dst.
3877 //  2) Rotate src (as word) left 3 bytes. That puts the rightmost byte of the src word into the leftmost
3878 //     byte position. Furthermore, byte 5 is rotated into byte 6 position where it is supposed to go.
3879 //     This value is mask inserted into dst with a [0..23] mask of 1s.
3880 //  3) Rotate src (as word) left 1 byte. That puts byte 6 into byte 5 position.
3881 //     This value is mask inserted into dst with a [8..15] mask of 1s.
3882 void MacroAssembler::load_reverse_32(Register dst, Register src) {
3883   assert_different_registers(dst, src);
3884 
3885   rldicl(dst, src, (4+1)*8, 56);       // Rotate byte 4 into position 7 (rightmost), clear all to the left.
3886   rlwimi(dst, src,     3*8,  0, 23);   // Insert byte 5 into position 6, 7 into 4, leave pos 7 alone.
3887   rlwimi(dst, src,     1*8,  8, 15);   // Insert byte 6 into position 5, leave the rest alone.
3888 }
3889 
3890 // Calculate the column addresses of the crc32 lookup table into distinct registers.
3891 // This loop-invariant calculation is moved out of the loop body, reducing the loop
3892 // body size from 20 to 16 instructions.
3893 // Returns the offset that was used to calculate the address of column tc3.
3894 // Due to register shortage, setting tc3 may overwrite table. With the return offset
3895 // at hand, the original table address can be easily reconstructed.
3896 int MacroAssembler::crc32_table_columns(Register table, Register tc0, Register tc1, Register tc2, Register tc3) {
3897   assert(!VM_Version::has_vpmsumb(), "Vector version should be used instead!");
3898 
3899   // Point to 4 byte folding tables (byte-reversed version for Big Endian)
3900   // Layout: See StubRoutines::generate_crc_constants.
3901 #ifdef VM_LITTLE_ENDIAN
3902   const int ix0 = 3 * CRC32_TABLE_SIZE;
3903   const int ix1 = 2 * CRC32_TABLE_SIZE;
3904   const int ix2 = 1 * CRC32_TABLE_SIZE;
3905   const int ix3 = 0 * CRC32_TABLE_SIZE;
3906 #else
3907   const int ix0 = 1 * CRC32_TABLE_SIZE;
3908   const int ix1 = 2 * CRC32_TABLE_SIZE;
3909   const int ix2 = 3 * CRC32_TABLE_SIZE;
3910   const int ix3 = 4 * CRC32_TABLE_SIZE;
3911 #endif
3912   assert_different_registers(table, tc0, tc1, tc2);
3913   assert(table == tc3, "must be!");
3914 
3915   addi(tc0, table, ix0);
3916   addi(tc1, table, ix1);
3917   addi(tc2, table, ix2);
3918   if (ix3 != 0) addi(tc3, table, ix3);
3919 
3920   return ix3;
3921 }
3922 
3923 /**
3924  * uint32_t crc;
3925  * table[crc & 0xFF] ^ (crc >> 8);
3926  */
3927 void MacroAssembler::fold_byte_crc32(Register crc, Register val, Register table, Register tmp) {
3928   assert_different_registers(crc, table, tmp);
3929   assert_different_registers(val, table);
3930 
3931   if (crc == val) {                   // Must rotate first to use the unmodified value.
3932     rlwinm(tmp, val, 2, 24-2, 31-2);  // Insert (rightmost) byte 7 of val, shifted left by 2, into byte 6..7 of tmp, clear the rest.
3933                                       // As we use a word (4-byte) instruction, we have to adapt the mask bit positions.
3934     srwi(crc, crc, 8);                // Unsigned shift, clear leftmost 8 bits.
3935   } else {
3936     srwi(crc, crc, 8);                // Unsigned shift, clear leftmost 8 bits.
3937     rlwinm(tmp, val, 2, 24-2, 31-2);  // Insert (rightmost) byte 7 of val, shifted left by 2, into byte 6..7 of tmp, clear the rest.
3938   }
3939   lwzx(tmp, table, tmp);
3940   xorr(crc, crc, tmp);
3941 }
3942 
3943 /**
3944  * Emits code to update CRC-32 with a byte value according to constants in table.
3945  *
3946  * @param [in,out]crc   Register containing the crc.
3947  * @param [in]val       Register containing the byte to fold into the CRC.
3948  * @param [in]table     Register containing the table of crc constants.
3949  *
3950  * uint32_t crc;
3951  * val = crc_table[(val ^ crc) & 0xFF];
3952  * crc = val ^ (crc >> 8);
3953  */
3954 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
3955   BLOCK_COMMENT("update_byte_crc32:");
3956   xorr(val, val, crc);
3957   fold_byte_crc32(crc, val, table, val);
3958 }
3959 
3960 /**
3961  * @param crc   register containing existing CRC (32-bit)
3962  * @param buf   register pointing to input byte buffer (byte*)
3963  * @param len   register containing number of bytes
3964  * @param table register pointing to CRC table
3965  */
3966 void MacroAssembler::update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
3967                                            Register data, bool loopAlignment) {
3968   assert_different_registers(crc, buf, len, table, data);
3969 
3970   Label L_mainLoop, L_done;
3971   const int mainLoop_stepping  = 1;
3972   const int mainLoop_alignment = loopAlignment ? 32 : 4; // (InputForNewCode > 4 ? InputForNewCode : 32) : 4;
3973 
3974   // Process all bytes in a single-byte loop.
3975   clrldi_(len, len, 32);                         // Enforce 32 bit. Anything to do?
3976   beq(CCR0, L_done);
3977 
3978   mtctr(len);
3979   align(mainLoop_alignment);
3980   BIND(L_mainLoop);
3981     lbz(data, 0, buf);                           // Byte from buffer, zero-extended.
3982     addi(buf, buf, mainLoop_stepping);           // Advance buffer position.
3983     update_byte_crc32(crc, data, table);
3984     bdnz(L_mainLoop);                            // Iterate.
3985 
3986   bind(L_done);
3987 }
3988 
3989 /**
3990  * Emits code to update CRC-32 with a 4-byte value according to constants in table
3991  * Implementation according to jdk/src/share/native/java/util/zip/zlib-1.2.8/crc32.c
3992  */
3993 // A note on the lookup table address(es):
3994 // The implementation uses 4 table columns (byte-reversed versions for Big Endian).
3995 // To save the effort of adding the column offset to the table address each time
3996 // a table element is looked up, it is possible to pass the pre-calculated
3997 // column addresses.
3998 // Uses R9..R12 as work register. Must be saved/restored by caller, if necessary.
3999 void MacroAssembler::update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
4000                                         Register t0,  Register t1,  Register t2,  Register t3,
4001                                         Register tc0, Register tc1, Register tc2, Register tc3) {
4002   assert_different_registers(crc, t3);
4003 
4004   // XOR crc with next four bytes of buffer.
4005   lwz(t3, bufDisp, buf);
4006   if (bufInc != 0) {
4007     addi(buf, buf, bufInc);
4008   }
4009   xorr(t3, t3, crc);
4010 
4011   // Chop crc into 4 single-byte pieces, shifted left 2 bits, to form the table indices.
4012   rlwinm(t0, t3,  2,         24-2, 31-2);  // ((t1 >>  0) & 0xff) << 2
4013   rlwinm(t1, t3,  32+(2- 8), 24-2, 31-2);  // ((t1 >>  8) & 0xff) << 2
4014   rlwinm(t2, t3,  32+(2-16), 24-2, 31-2);  // ((t1 >> 16) & 0xff) << 2
4015   rlwinm(t3, t3,  32+(2-24), 24-2, 31-2);  // ((t1 >> 24) & 0xff) << 2
4016 
4017   // Use the pre-calculated column addresses.
4018   // Load pre-calculated table values.
4019   lwzx(t0, tc0, t0);
4020   lwzx(t1, tc1, t1);
4021   lwzx(t2, tc2, t2);
4022   lwzx(t3, tc3, t3);
4023 
4024   // Calculate new crc from table values.
4025   xorr(t0,  t0, t1);
4026   xorr(t2,  t2, t3);
4027   xorr(crc, t0, t2);  // Now crc contains the final checksum value.
4028 }
4029 
4030 /**
4031  * @param crc   register containing existing CRC (32-bit)
4032  * @param buf   register pointing to input byte buffer (byte*)
4033  * @param len   register containing number of bytes
4034  * @param table register pointing to CRC table
4035  *
4036  * uses R9..R12 as work register. Must be saved/restored by caller!
4037  */
4038 void MacroAssembler::kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
4039                                         Register t0,  Register t1,  Register t2,  Register t3,
4040                                         Register tc0, Register tc1, Register tc2, Register tc3,
4041                                         bool invertCRC) {
4042   assert_different_registers(crc, buf, len, table);
4043 
4044   Label L_mainLoop, L_tail;
4045   Register  tmp          = t0;
4046   Register  data         = t0;
4047   Register  tmp2         = t1;
4048   const int mainLoop_stepping  = 4;
4049   const int tailLoop_stepping  = 1;
4050   const int log_stepping       = exact_log2(mainLoop_stepping);
4051   const int mainLoop_alignment = 32; // InputForNewCode > 4 ? InputForNewCode : 32;
4052   const int complexThreshold   = 2*mainLoop_stepping;
4053 
4054   // Don't test for len <= 0 here. This pathological case should not occur anyway.
4055   // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles
4056   // for all well-behaved cases. The situation itself is detected and handled correctly
4057   // within update_byteLoop_crc32.
4058   assert(tailLoop_stepping == 1, "check tailLoop_stepping!");
4059 
4060   BLOCK_COMMENT("kernel_crc32_1word {");
4061 
4062   if (invertCRC) {
4063     nand(crc, crc, crc);                      // 1s complement of crc
4064   }
4065 
4066   // Check for short (<mainLoop_stepping) buffer.
4067   cmpdi(CCR0, len, complexThreshold);
4068   blt(CCR0, L_tail);
4069 
4070   // Pre-mainLoop alignment did show a slight (1%) positive effect on performance.
4071   // We leave the code in for reference. Maybe we need alignment when we exploit vector instructions.
4072   {
4073     // Align buf addr to mainLoop_stepping boundary.
4074     neg(tmp2, buf);                              // Calculate # preLoop iterations for alignment.
4075     rldicl(tmp2, tmp2, 0, 64-log_stepping);      // Rotate tmp2 0 bits, insert into tmp2, anding with mask with 1s from 62..63.
4076 
4077     if (complexThreshold > mainLoop_stepping) {
4078       sub(len, len, tmp2);                       // Remaining bytes for main loop (>=mainLoop_stepping is guaranteed).
4079     } else {
4080       sub(tmp, len, tmp2);                       // Remaining bytes for main loop.
4081       cmpdi(CCR0, tmp, mainLoop_stepping);
4082       blt(CCR0, L_tail);                         // For less than one mainloop_stepping left, do only tail processing
4083       mr(len, tmp);                              // remaining bytes for main loop (>=mainLoop_stepping is guaranteed).
4084     }
4085     update_byteLoop_crc32(crc, buf, tmp2, table, data, false);
4086   }
4087 
4088   srdi(tmp2, len, log_stepping);                 // #iterations for mainLoop
4089   andi(len, len, mainLoop_stepping-1);           // remaining bytes for tailLoop
4090   mtctr(tmp2);
4091 
4092 #ifdef VM_LITTLE_ENDIAN
4093   Register crc_rv = crc;
4094 #else
4095   Register crc_rv = tmp;                         // Load_reverse needs separate registers to work on.
4096                                                  // Occupies tmp, but frees up crc.
4097   load_reverse_32(crc_rv, crc);                  // Revert byte order because we are dealing with big-endian data.
4098   tmp = crc;
4099 #endif
4100 
4101   int reconstructTableOffset = crc32_table_columns(table, tc0, tc1, tc2, tc3);
4102 
4103   align(mainLoop_alignment);                     // Octoword-aligned loop address. Shows 2% improvement.
4104   BIND(L_mainLoop);
4105     update_1word_crc32(crc_rv, buf, table, 0, mainLoop_stepping, crc_rv, t1, t2, t3, tc0, tc1, tc2, tc3);
4106     bdnz(L_mainLoop);
4107 
4108 #ifndef VM_LITTLE_ENDIAN
4109   load_reverse_32(crc, crc_rv);                  // Revert byte order because we are dealing with big-endian data.
4110   tmp = crc_rv;                                  // Tmp uses it's original register again.
4111 #endif
4112 
4113   // Restore original table address for tailLoop.
4114   if (reconstructTableOffset != 0) {
4115     addi(table, table, -reconstructTableOffset);
4116   }
4117 
4118   // Process last few (<complexThreshold) bytes of buffer.
4119   BIND(L_tail);
4120   update_byteLoop_crc32(crc, buf, len, table, data, false);
4121 
4122   if (invertCRC) {
4123     nand(crc, crc, crc);                      // 1s complement of crc
4124   }
4125   BLOCK_COMMENT("} kernel_crc32_1word");
4126 }
4127 
4128 /**
4129  * @param crc             register containing existing CRC (32-bit)
4130  * @param buf             register pointing to input byte buffer (byte*)
4131  * @param len             register containing number of bytes
4132  * @param constants       register pointing to precomputed constants
4133  * @param t0-t6           temp registers
4134  */
4135 void MacroAssembler::kernel_crc32_vpmsum(Register crc, Register buf, Register len, Register constants,
4136                                          Register t0, Register t1, Register t2, Register t3,
4137                                          Register t4, Register t5, Register t6, bool invertCRC) {
4138   assert_different_registers(crc, buf, len, constants);
4139 
4140   Label L_tail;
4141 
4142   BLOCK_COMMENT("kernel_crc32_vpmsum {");
4143 
4144   if (invertCRC) {
4145     nand(crc, crc, crc);                      // 1s complement of crc
4146   }
4147 
4148   // Enforce 32 bit.
4149   clrldi(len, len, 32);
4150 
4151   // Align if we have enough bytes for the fast version.
4152   const int alignment = 16,
4153             threshold = 32;
4154   Register prealign = t0;
4155 
4156   neg(prealign, buf);
4157   addi(t1, len, -threshold);
4158   andi(prealign, prealign, alignment - 1);
4159   cmpw(CCR0, t1, prealign);
4160   blt(CCR0, L_tail); // len - prealign < threshold?
4161 
4162   subf(len, prealign, len);
4163   update_byteLoop_crc32(crc, buf, prealign, constants, t2, false);
4164 
4165   // Calculate from first aligned address as far as possible.
4166   addi(constants, constants, CRC32_TABLE_SIZE); // Point to vector constants.
4167   kernel_crc32_vpmsum_aligned(crc, buf, len, constants, t0, t1, t2, t3, t4, t5, t6);
4168   addi(constants, constants, -CRC32_TABLE_SIZE); // Point to table again.
4169 
4170   // Remaining bytes.
4171   BIND(L_tail);
4172   update_byteLoop_crc32(crc, buf, len, constants, t2, false);
4173 
4174   if (invertCRC) {
4175     nand(crc, crc, crc);                      // 1s complement of crc
4176   }
4177 
4178   BLOCK_COMMENT("} kernel_crc32_vpmsum");
4179 }
4180 
4181 /**
4182  * @param crc             register containing existing CRC (32-bit)
4183  * @param buf             register pointing to input byte buffer (byte*)
4184  * @param len             register containing number of bytes (will get updated to remaining bytes)
4185  * @param constants       register pointing to CRC table for 128-bit aligned memory
4186  * @param t0-t6           temp registers
4187  */
4188 void MacroAssembler::kernel_crc32_vpmsum_aligned(Register crc, Register buf, Register len, Register constants,
4189     Register t0, Register t1, Register t2, Register t3, Register t4, Register t5, Register t6) {
4190 
4191   // Save non-volatile vector registers (frameless).
4192   Register offset = t1;
4193   int offsetInt = 0;
4194   offsetInt -= 16; li(offset, offsetInt); stvx(VR20, offset, R1_SP);
4195   offsetInt -= 16; li(offset, offsetInt); stvx(VR21, offset, R1_SP);
4196   offsetInt -= 16; li(offset, offsetInt); stvx(VR22, offset, R1_SP);
4197   offsetInt -= 16; li(offset, offsetInt); stvx(VR23, offset, R1_SP);
4198   offsetInt -= 16; li(offset, offsetInt); stvx(VR24, offset, R1_SP);
4199   offsetInt -= 16; li(offset, offsetInt); stvx(VR25, offset, R1_SP);
4200 #ifndef VM_LITTLE_ENDIAN
4201   offsetInt -= 16; li(offset, offsetInt); stvx(VR26, offset, R1_SP);
4202 #endif
4203   offsetInt -= 8; std(R14, offsetInt, R1_SP);
4204   offsetInt -= 8; std(R15, offsetInt, R1_SP);
4205 
4206   // Implementation uses an inner loop which uses between 256 and 16 * unroll_factor
4207   // bytes per iteration. The basic scheme is:
4208   // lvx: load vector (Big Endian needs reversal)
4209   // vpmsumw: carry-less 32 bit multiplications with constant representing a large CRC shift
4210   // vxor: xor partial results together to get unroll_factor2 vectors
4211 
4212   // Outer loop performs the CRC shifts needed to combine the unroll_factor2 vectors.
4213 
4214   // Using 16 * unroll_factor / unroll_factor_2 bytes for constants.
4215   const int unroll_factor = CRC32_UNROLL_FACTOR,
4216             unroll_factor2 = CRC32_UNROLL_FACTOR2;
4217 
4218   const int outer_consts_size = (unroll_factor2 - 1) * 16,
4219             inner_consts_size = (unroll_factor / unroll_factor2) * 16;
4220 
4221   // Support registers.
4222   Register offs[] = { noreg, t0, t1, t2, t3, t4, t5, t6 };
4223   Register num_bytes = R14,
4224            loop_count = R15,
4225            cur_const = crc; // will live in VCRC
4226   // Constant array for outer loop: unroll_factor2 - 1 registers,
4227   // Constant array for inner loop: unroll_factor / unroll_factor2 registers.
4228   VectorRegister consts0[] = { VR16, VR17, VR18, VR19, VR20, VR21, VR22 },
4229                  consts1[] = { VR23, VR24 };
4230   // Data register arrays: 2 arrays with unroll_factor2 registers.
4231   VectorRegister data0[] = { VR0, VR1, VR2, VR3, VR4, VR5, VR6, VR7 },
4232                  data1[] = { VR8, VR9, VR10, VR11, VR12, VR13, VR14, VR15 };
4233 
4234   VectorRegister VCRC = data0[0];
4235   VectorRegister Vc = VR25;
4236   VectorRegister swap_bytes = VR26; // Only for Big Endian.
4237 
4238   // We have at least 1 iteration (ensured by caller).
4239   Label L_outer_loop, L_inner_loop, L_last;
4240 
4241   // If supported set DSCR pre-fetch to deepest.
4242   if (VM_Version::has_mfdscr()) {
4243     load_const_optimized(t0, VM_Version::_dscr_val | 7);
4244     mtdscr(t0);
4245   }
4246 
4247   mtvrwz(VCRC, crc); // crc lives in VCRC, now
4248 
4249   for (int i = 1; i < unroll_factor2; ++i) {
4250     li(offs[i], 16 * i);
4251   }
4252 
4253   // Load consts for outer loop
4254   lvx(consts0[0], constants);
4255   for (int i = 1; i < unroll_factor2 - 1; ++i) {
4256     lvx(consts0[i], offs[i], constants);
4257   }
4258 
4259   load_const_optimized(num_bytes, 16 * unroll_factor);
4260 
4261   // Reuse data registers outside of the loop.
4262   VectorRegister Vtmp = data1[0];
4263   VectorRegister Vtmp2 = data1[1];
4264   VectorRegister zeroes = data1[2];
4265 
4266   vspltisb(Vtmp, 0);
4267   vsldoi(VCRC, Vtmp, VCRC, 8); // 96 bit zeroes, 32 bit CRC.
4268 
4269   // Load vector for vpermxor (to xor both 64 bit parts together)
4270   lvsl(Vtmp, buf);   // 000102030405060708090a0b0c0d0e0f
4271   vspltisb(Vc, 4);
4272   vsl(Vc, Vtmp, Vc); // 00102030405060708090a0b0c0d0e0f0
4273   xxspltd(Vc->to_vsr(), Vc->to_vsr(), 0);
4274   vor(Vc, Vtmp, Vc); // 001122334455667708192a3b4c5d6e7f
4275 
4276 #ifdef VM_LITTLE_ENDIAN
4277 #define BE_swap_bytes(x)
4278 #else
4279   vspltisb(Vtmp2, 0xf);
4280   vxor(swap_bytes, Vtmp, Vtmp2);
4281 #define BE_swap_bytes(x) vperm(x, x, x, swap_bytes)
4282 #endif
4283 
4284   cmpd(CCR0, len, num_bytes);
4285   blt(CCR0, L_last);
4286 
4287   addi(cur_const, constants, outer_consts_size); // Point to consts for inner loop
4288   load_const_optimized(loop_count, unroll_factor / (2 * unroll_factor2) - 1); // One double-iteration peeled off.
4289 
4290   // ********** Main loop start **********
4291   align(32);
4292   bind(L_outer_loop);
4293 
4294   // Begin of unrolled first iteration (no xor).
4295   lvx(data1[0], buf);
4296   for (int i = 1; i < unroll_factor2 / 2; ++i) {
4297     lvx(data1[i], offs[i], buf);
4298   }
4299   vpermxor(VCRC, VCRC, VCRC, Vc); // xor both halves to 64 bit result.
4300   lvx(consts1[0], cur_const);
4301   mtctr(loop_count);
4302   for (int i = 0; i < unroll_factor2 / 2; ++i) {
4303     BE_swap_bytes(data1[i]);
4304     if (i == 0) { vxor(data1[0], data1[0], VCRC); } // xor in previous CRC.
4305     lvx(data1[i + unroll_factor2 / 2], offs[i + unroll_factor2 / 2], buf);
4306     vpmsumw(data0[i], data1[i], consts1[0]);
4307   }
4308   addi(buf, buf, 16 * unroll_factor2);
4309   subf(len, num_bytes, len);
4310   lvx(consts1[1], offs[1], cur_const);
4311   addi(cur_const, cur_const, 32);
4312   // Begin of unrolled second iteration (head).
4313   for (int i = 0; i < unroll_factor2 / 2; ++i) {
4314     BE_swap_bytes(data1[i + unroll_factor2 / 2]);
4315     if (i == 0) { lvx(data1[0], buf); } else { lvx(data1[i], offs[i], buf); }
4316     vpmsumw(data0[i + unroll_factor2 / 2], data1[i + unroll_factor2 / 2], consts1[0]);
4317   }
4318   for (int i = 0; i < unroll_factor2 / 2; ++i) {
4319     BE_swap_bytes(data1[i]);
4320     lvx(data1[i + unroll_factor2 / 2], offs[i + unroll_factor2 / 2], buf);
4321     vpmsumw(data1[i], data1[i], consts1[1]);
4322   }
4323   addi(buf, buf, 16 * unroll_factor2);
4324 
4325   // Generate most performance relevant code. Loads + half of the vpmsumw have been generated.
4326   // Double-iteration allows using the 2 constant registers alternatingly.
4327   align(32);
4328   bind(L_inner_loop);
4329   for (int j = 1; j < 3; ++j) { // j < unroll_factor / unroll_factor2 - 1 for complete unrolling.
4330     if (j & 1) {
4331       lvx(consts1[0], cur_const);
4332     } else {
4333       lvx(consts1[1], offs[1], cur_const);
4334       addi(cur_const, cur_const, 32);
4335     }
4336     for (int i = 0; i < unroll_factor2; ++i) {
4337       int idx = i + unroll_factor2 / 2, inc = 0; // For modulo-scheduled input.
4338       if (idx >= unroll_factor2) { idx -= unroll_factor2; inc = 1; }
4339       BE_swap_bytes(data1[idx]);
4340       vxor(data0[i], data0[i], data1[i]);
4341       if (i == 0) lvx(data1[0], buf); else lvx(data1[i], offs[i], buf);
4342       vpmsumw(data1[idx], data1[idx], consts1[(j + inc) & 1]);
4343     }
4344     addi(buf, buf, 16 * unroll_factor2);
4345   }
4346   bdnz(L_inner_loop);
4347 
4348   addi(cur_const, constants, outer_consts_size); // Reset
4349 
4350   // Tail of last iteration (no loads).
4351   for (int i = 0; i < unroll_factor2 / 2; ++i) {
4352     BE_swap_bytes(data1[i + unroll_factor2 / 2]);
4353     vxor(data0[i], data0[i], data1[i]);
4354     vpmsumw(data1[i + unroll_factor2 / 2], data1[i + unroll_factor2 / 2], consts1[1]);
4355   }
4356   for (int i = 0; i < unroll_factor2 / 2; ++i) {
4357     vpmsumw(data0[i], data0[i], consts0[unroll_factor2 - 2 - i]); // First half of fixup shifts.
4358     vxor(data0[i + unroll_factor2 / 2], data0[i + unroll_factor2 / 2], data1[i + unroll_factor2 / 2]);
4359   }
4360 
4361   // Last data register is ok, other ones need fixup shift.
4362   for (int i = unroll_factor2 / 2; i < unroll_factor2 - 1; ++i) {
4363     vpmsumw(data0[i], data0[i], consts0[unroll_factor2 - 2 - i]);
4364   }
4365 
4366   // Combine to 128 bit result vector VCRC = data0[0].
4367   for (int i = 1; i < unroll_factor2; i<<=1) {
4368     for (int j = 0; j <= unroll_factor2 - 2*i; j+=2*i) {
4369       vxor(data0[j], data0[j], data0[j+i]);
4370     }
4371   }
4372   cmpd(CCR0, len, num_bytes);
4373   bge(CCR0, L_outer_loop);
4374 
4375   // Last chance with lower num_bytes.
4376   bind(L_last);
4377   srdi(loop_count, len, exact_log2(16 * 2 * unroll_factor2)); // Use double-iterations.
4378   // Point behind last const for inner loop.
4379   add_const_optimized(cur_const, constants, outer_consts_size + inner_consts_size);
4380   sldi(R0, loop_count, exact_log2(16 * 2)); // Bytes of constants to be used.
4381   clrrdi(num_bytes, len, exact_log2(16 * 2 * unroll_factor2));
4382   subf(cur_const, R0, cur_const); // Point to constant to be used first.
4383 
4384   addic_(loop_count, loop_count, -1); // One double-iteration peeled off.
4385   bgt(CCR0, L_outer_loop);
4386   // ********** Main loop end **********
4387 
4388   // Restore DSCR pre-fetch value.
4389   if (VM_Version::has_mfdscr()) {
4390     load_const_optimized(t0, VM_Version::_dscr_val);
4391     mtdscr(t0);
4392   }
4393 
4394   // ********** Simple loop for remaining 16 byte blocks **********
4395   {
4396     Label L_loop, L_done;
4397 
4398     srdi_(t0, len, 4); // 16 bytes per iteration
4399     clrldi(len, len, 64-4);
4400     beq(CCR0, L_done);
4401 
4402     // Point to const (same as last const for inner loop).
4403     add_const_optimized(cur_const, constants, outer_consts_size + inner_consts_size - 16);
4404     mtctr(t0);
4405     lvx(Vtmp2, cur_const);
4406 
4407     align(32);
4408     bind(L_loop);
4409 
4410     lvx(Vtmp, buf);
4411     addi(buf, buf, 16);
4412     vpermxor(VCRC, VCRC, VCRC, Vc); // xor both halves to 64 bit result.
4413     BE_swap_bytes(Vtmp);
4414     vxor(VCRC, VCRC, Vtmp);
4415     vpmsumw(VCRC, VCRC, Vtmp2);
4416     bdnz(L_loop);
4417 
4418     bind(L_done);
4419   }
4420   // ********** Simple loop end **********
4421 #undef BE_swap_bytes
4422 
4423   // Point to Barrett constants
4424   add_const_optimized(cur_const, constants, outer_consts_size + inner_consts_size);
4425 
4426   vspltisb(zeroes, 0);
4427 
4428   // Combine to 64 bit result.
4429   vpermxor(VCRC, VCRC, VCRC, Vc); // xor both halves to 64 bit result.
4430 
4431   // Reduce to 32 bit CRC: Remainder by multiply-high.
4432   lvx(Vtmp, cur_const);
4433   vsldoi(Vtmp2, zeroes, VCRC, 12);  // Extract high 32 bit.
4434   vpmsumd(Vtmp2, Vtmp2, Vtmp);      // Multiply by inverse long poly.
4435   vsldoi(Vtmp2, zeroes, Vtmp2, 12); // Extract high 32 bit.
4436   vsldoi(Vtmp, zeroes, Vtmp, 8);
4437   vpmsumd(Vtmp2, Vtmp2, Vtmp);      // Multiply quotient by long poly.
4438   vxor(VCRC, VCRC, Vtmp2);          // Remainder fits into 32 bit.
4439 
4440   // Move result. len is already updated.
4441   vsldoi(VCRC, VCRC, zeroes, 8);
4442   mfvrd(crc, VCRC);
4443 
4444   // Restore non-volatile Vector registers (frameless).
4445   offsetInt = 0;
4446   offsetInt -= 16; li(offset, offsetInt); lvx(VR20, offset, R1_SP);
4447   offsetInt -= 16; li(offset, offsetInt); lvx(VR21, offset, R1_SP);
4448   offsetInt -= 16; li(offset, offsetInt); lvx(VR22, offset, R1_SP);
4449   offsetInt -= 16; li(offset, offsetInt); lvx(VR23, offset, R1_SP);
4450   offsetInt -= 16; li(offset, offsetInt); lvx(VR24, offset, R1_SP);
4451   offsetInt -= 16; li(offset, offsetInt); lvx(VR25, offset, R1_SP);
4452 #ifndef VM_LITTLE_ENDIAN
4453   offsetInt -= 16; li(offset, offsetInt); lvx(VR26, offset, R1_SP);
4454 #endif
4455   offsetInt -= 8;  ld(R14, offsetInt, R1_SP);
4456   offsetInt -= 8;  ld(R15, offsetInt, R1_SP);
4457 }
4458 
4459 void MacroAssembler::crc32(Register crc, Register buf, Register len, Register t0, Register t1, Register t2,
4460                            Register t3, Register t4, Register t5, Register t6, Register t7, bool is_crc32c) {
4461   load_const_optimized(t0, is_crc32c ? StubRoutines::crc32c_table_addr()
4462                                      : StubRoutines::crc_table_addr()   , R0);
4463 
4464   if (VM_Version::has_vpmsumb()) {
4465     kernel_crc32_vpmsum(crc, buf, len, t0, t1, t2, t3, t4, t5, t6, t7, !is_crc32c);
4466   } else {
4467     kernel_crc32_1word(crc, buf, len, t0, t1, t2, t3, t4, t5, t6, t7, t0, !is_crc32c);
4468   }
4469 }
4470 
4471 void MacroAssembler::kernel_crc32_singleByteReg(Register crc, Register val, Register table, bool invertCRC) {
4472   assert_different_registers(crc, val, table);
4473 
4474   BLOCK_COMMENT("kernel_crc32_singleByteReg:");
4475   if (invertCRC) {
4476     nand(crc, crc, crc);                // 1s complement of crc
4477   }
4478 
4479   update_byte_crc32(crc, val, table);
4480 
4481   if (invertCRC) {
4482     nand(crc, crc, crc);                // 1s complement of crc
4483   }
4484 }
4485 
4486 // dest_lo += src1 + src2
4487 // dest_hi += carry1 + carry2
4488 void MacroAssembler::add2_with_carry(Register dest_hi,
4489                                      Register dest_lo,
4490                                      Register src1, Register src2) {
4491   li(R0, 0);
4492   addc(dest_lo, dest_lo, src1);
4493   adde(dest_hi, dest_hi, R0);
4494   addc(dest_lo, dest_lo, src2);
4495   adde(dest_hi, dest_hi, R0);
4496 }
4497 
4498 // Multiply 64 bit by 64 bit first loop.
4499 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart,
4500                                            Register x_xstart,
4501                                            Register y, Register y_idx,
4502                                            Register z,
4503                                            Register carry,
4504                                            Register product_high, Register product,
4505                                            Register idx, Register kdx,
4506                                            Register tmp) {
4507   //  jlong carry, x[], y[], z[];
4508   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx--, kdx--) {
4509   //    huge_128 product = y[idx] * x[xstart] + carry;
4510   //    z[kdx] = (jlong)product;
4511   //    carry  = (jlong)(product >>> 64);
4512   //  }
4513   //  z[xstart] = carry;
4514 
4515   Label L_first_loop, L_first_loop_exit;
4516   Label L_one_x, L_one_y, L_multiply;
4517 
4518   addic_(xstart, xstart, -1);
4519   blt(CCR0, L_one_x);   // Special case: length of x is 1.
4520 
4521   // Load next two integers of x.
4522   sldi(tmp, xstart, LogBytesPerInt);
4523   ldx(x_xstart, x, tmp);
4524 #ifdef VM_LITTLE_ENDIAN
4525   rldicl(x_xstart, x_xstart, 32, 0);
4526 #endif
4527 
4528   align(32, 16);
4529   bind(L_first_loop);
4530 
4531   cmpdi(CCR0, idx, 1);
4532   blt(CCR0, L_first_loop_exit);
4533   addi(idx, idx, -2);
4534   beq(CCR0, L_one_y);
4535 
4536   // Load next two integers of y.
4537   sldi(tmp, idx, LogBytesPerInt);
4538   ldx(y_idx, y, tmp);
4539 #ifdef VM_LITTLE_ENDIAN
4540   rldicl(y_idx, y_idx, 32, 0);
4541 #endif
4542 
4543 
4544   bind(L_multiply);
4545   multiply64(product_high, product, x_xstart, y_idx);
4546 
4547   li(tmp, 0);
4548   addc(product, product, carry);         // Add carry to result.
4549   adde(product_high, product_high, tmp); // Add carry of the last addition.
4550   addi(kdx, kdx, -2);
4551 
4552   // Store result.
4553 #ifdef VM_LITTLE_ENDIAN
4554   rldicl(product, product, 32, 0);
4555 #endif
4556   sldi(tmp, kdx, LogBytesPerInt);
4557   stdx(product, z, tmp);
4558   mr_if_needed(carry, product_high);
4559   b(L_first_loop);
4560 
4561 
4562   bind(L_one_y); // Load one 32 bit portion of y as (0,value).
4563 
4564   lwz(y_idx, 0, y);
4565   b(L_multiply);
4566 
4567 
4568   bind(L_one_x); // Load one 32 bit portion of x as (0,value).
4569 
4570   lwz(x_xstart, 0, x);
4571   b(L_first_loop);
4572 
4573   bind(L_first_loop_exit);
4574 }
4575 
4576 // Multiply 64 bit by 64 bit and add 128 bit.
4577 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y,
4578                                             Register z, Register yz_idx,
4579                                             Register idx, Register carry,
4580                                             Register product_high, Register product,
4581                                             Register tmp, int offset) {
4582 
4583   //  huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
4584   //  z[kdx] = (jlong)product;
4585 
4586   sldi(tmp, idx, LogBytesPerInt);
4587   if (offset) {
4588     addi(tmp, tmp, offset);
4589   }
4590   ldx(yz_idx, y, tmp);
4591 #ifdef VM_LITTLE_ENDIAN
4592   rldicl(yz_idx, yz_idx, 32, 0);
4593 #endif
4594 
4595   multiply64(product_high, product, x_xstart, yz_idx);
4596   ldx(yz_idx, z, tmp);
4597 #ifdef VM_LITTLE_ENDIAN
4598   rldicl(yz_idx, yz_idx, 32, 0);
4599 #endif
4600 
4601   add2_with_carry(product_high, product, carry, yz_idx);
4602 
4603   sldi(tmp, idx, LogBytesPerInt);
4604   if (offset) {
4605     addi(tmp, tmp, offset);
4606   }
4607 #ifdef VM_LITTLE_ENDIAN
4608   rldicl(product, product, 32, 0);
4609 #endif
4610   stdx(product, z, tmp);
4611 }
4612 
4613 // Multiply 128 bit by 128 bit. Unrolled inner loop.
4614 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart,
4615                                              Register y, Register z,
4616                                              Register yz_idx, Register idx, Register carry,
4617                                              Register product_high, Register product,
4618                                              Register carry2, Register tmp) {
4619 
4620   //  jlong carry, x[], y[], z[];
4621   //  int kdx = ystart+1;
4622   //  for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
4623   //    huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
4624   //    z[kdx+idx+1] = (jlong)product;
4625   //    jlong carry2 = (jlong)(product >>> 64);
4626   //    product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
4627   //    z[kdx+idx] = (jlong)product;
4628   //    carry = (jlong)(product >>> 64);
4629   //  }
4630   //  idx += 2;
4631   //  if (idx > 0) {
4632   //    product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
4633   //    z[kdx+idx] = (jlong)product;
4634   //    carry = (jlong)(product >>> 64);
4635   //  }
4636 
4637   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
4638   const Register jdx = R0;
4639 
4640   // Scale the index.
4641   srdi_(jdx, idx, 2);
4642   beq(CCR0, L_third_loop_exit);
4643   mtctr(jdx);
4644 
4645   align(32, 16);
4646   bind(L_third_loop);
4647 
4648   addi(idx, idx, -4);
4649 
4650   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product_high, product, tmp, 8);
4651   mr_if_needed(carry2, product_high);
4652 
4653   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product_high, product, tmp, 0);
4654   mr_if_needed(carry, product_high);
4655   bdnz(L_third_loop);
4656 
4657   bind(L_third_loop_exit);  // Handle any left-over operand parts.
4658 
4659   andi_(idx, idx, 0x3);
4660   beq(CCR0, L_post_third_loop_done);
4661 
4662   Label L_check_1;
4663 
4664   addic_(idx, idx, -2);
4665   blt(CCR0, L_check_1);
4666 
4667   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product_high, product, tmp, 0);
4668   mr_if_needed(carry, product_high);
4669 
4670   bind(L_check_1);
4671 
4672   addi(idx, idx, 0x2);
4673   andi_(idx, idx, 0x1);
4674   addic_(idx, idx, -1);
4675   blt(CCR0, L_post_third_loop_done);
4676 
4677   sldi(tmp, idx, LogBytesPerInt);
4678   lwzx(yz_idx, y, tmp);
4679   multiply64(product_high, product, x_xstart, yz_idx);
4680   lwzx(yz_idx, z, tmp);
4681 
4682   add2_with_carry(product_high, product, yz_idx, carry);
4683 
4684   sldi(tmp, idx, LogBytesPerInt);
4685   stwx(product, z, tmp);
4686   srdi(product, product, 32);
4687 
4688   sldi(product_high, product_high, 32);
4689   orr(product, product, product_high);
4690   mr_if_needed(carry, product);
4691 
4692   bind(L_post_third_loop_done);
4693 }   // multiply_128_x_128_loop
4694 
4695 void MacroAssembler::muladd(Register out, Register in,
4696                             Register offset, Register len, Register k,
4697                             Register tmp1, Register tmp2, Register carry) {
4698 
4699   // Labels
4700   Label LOOP, SKIP;
4701 
4702   // Make sure length is positive.
4703   cmpdi  (CCR0,    len,     0);
4704 
4705   // Prepare variables
4706   subi   (offset,  offset,  4);
4707   li     (carry,   0);
4708   ble    (CCR0,    SKIP);
4709 
4710   mtctr  (len);
4711   subi   (len,     len,     1    );
4712   sldi   (len,     len,     2    );
4713 
4714   // Main loop
4715   bind(LOOP);
4716   lwzx   (tmp1,    len,     in   );
4717   lwzx   (tmp2,    offset,  out  );
4718   mulld  (tmp1,    tmp1,    k    );
4719   add    (tmp2,    carry,   tmp2 );
4720   add    (tmp2,    tmp1,    tmp2 );
4721   stwx   (tmp2,    offset,  out  );
4722   srdi   (carry,   tmp2,    32   );
4723   subi   (offset,  offset,  4    );
4724   subi   (len,     len,     4    );
4725   bdnz   (LOOP);
4726   bind(SKIP);
4727 }
4728 
4729 void MacroAssembler::multiply_to_len(Register x, Register xlen,
4730                                      Register y, Register ylen,
4731                                      Register z, Register zlen,
4732                                      Register tmp1, Register tmp2,
4733                                      Register tmp3, Register tmp4,
4734                                      Register tmp5, Register tmp6,
4735                                      Register tmp7, Register tmp8,
4736                                      Register tmp9, Register tmp10,
4737                                      Register tmp11, Register tmp12,
4738                                      Register tmp13) {
4739 
4740   ShortBranchVerifier sbv(this);
4741 
4742   assert_different_registers(x, xlen, y, ylen, z, zlen,
4743                              tmp1, tmp2, tmp3, tmp4, tmp5, tmp6);
4744   assert_different_registers(x, xlen, y, ylen, z, zlen,
4745                              tmp1, tmp2, tmp3, tmp4, tmp5, tmp7);
4746   assert_different_registers(x, xlen, y, ylen, z, zlen,
4747                              tmp1, tmp2, tmp3, tmp4, tmp5, tmp8);
4748 
4749   const Register idx = tmp1;
4750   const Register kdx = tmp2;
4751   const Register xstart = tmp3;
4752 
4753   const Register y_idx = tmp4;
4754   const Register carry = tmp5;
4755   const Register product = tmp6;
4756   const Register product_high = tmp7;
4757   const Register x_xstart = tmp8;
4758   const Register tmp = tmp9;
4759 
4760   // First Loop.
4761   //
4762   //  final static long LONG_MASK = 0xffffffffL;
4763   //  int xstart = xlen - 1;
4764   //  int ystart = ylen - 1;
4765   //  long carry = 0;
4766   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4767   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4768   //    z[kdx] = (int)product;
4769   //    carry = product >>> 32;
4770   //  }
4771   //  z[xstart] = (int)carry;
4772 
4773   mr_if_needed(idx, ylen);        // idx = ylen
4774   mr_if_needed(kdx, zlen);        // kdx = xlen + ylen
4775   li(carry, 0);                   // carry = 0
4776 
4777   Label L_done;
4778 
4779   addic_(xstart, xlen, -1);
4780   blt(CCR0, L_done);
4781 
4782   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z,
4783                         carry, product_high, product, idx, kdx, tmp);
4784 
4785   Label L_second_loop;
4786 
4787   cmpdi(CCR0, kdx, 0);
4788   beq(CCR0, L_second_loop);
4789 
4790   Label L_carry;
4791 
4792   addic_(kdx, kdx, -1);
4793   beq(CCR0, L_carry);
4794 
4795   // Store lower 32 bits of carry.
4796   sldi(tmp, kdx, LogBytesPerInt);
4797   stwx(carry, z, tmp);
4798   srdi(carry, carry, 32);
4799   addi(kdx, kdx, -1);
4800 
4801 
4802   bind(L_carry);
4803 
4804   // Store upper 32 bits of carry.
4805   sldi(tmp, kdx, LogBytesPerInt);
4806   stwx(carry, z, tmp);
4807 
4808   // Second and third (nested) loops.
4809   //
4810   //  for (int i = xstart-1; i >= 0; i--) { // Second loop
4811   //    carry = 0;
4812   //    for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4813   //      long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4814   //                     (z[k] & LONG_MASK) + carry;
4815   //      z[k] = (int)product;
4816   //      carry = product >>> 32;
4817   //    }
4818   //    z[i] = (int)carry;
4819   //  }
4820   //
4821   //  i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
4822 
4823   bind(L_second_loop);
4824 
4825   li(carry, 0);                   // carry = 0;
4826 
4827   addic_(xstart, xstart, -1);     // i = xstart-1;
4828   blt(CCR0, L_done);
4829 
4830   Register zsave = tmp10;
4831 
4832   mr(zsave, z);
4833 
4834 
4835   Label L_last_x;
4836 
4837   sldi(tmp, xstart, LogBytesPerInt);
4838   add(z, z, tmp);                 // z = z + k - j
4839   addi(z, z, 4);
4840   addic_(xstart, xstart, -1);     // i = xstart-1;
4841   blt(CCR0, L_last_x);
4842 
4843   sldi(tmp, xstart, LogBytesPerInt);
4844   ldx(x_xstart, x, tmp);
4845 #ifdef VM_LITTLE_ENDIAN
4846   rldicl(x_xstart, x_xstart, 32, 0);
4847 #endif
4848 
4849 
4850   Label L_third_loop_prologue;
4851 
4852   bind(L_third_loop_prologue);
4853 
4854   Register xsave = tmp11;
4855   Register xlensave = tmp12;
4856   Register ylensave = tmp13;
4857 
4858   mr(xsave, x);
4859   mr(xlensave, xstart);
4860   mr(ylensave, ylen);
4861 
4862 
4863   multiply_128_x_128_loop(x_xstart, y, z, y_idx, ylen,
4864                           carry, product_high, product, x, tmp);
4865 
4866   mr(z, zsave);
4867   mr(x, xsave);
4868   mr(xlen, xlensave);   // This is the decrement of the loop counter!
4869   mr(ylen, ylensave);
4870 
4871   addi(tmp3, xlen, 1);
4872   sldi(tmp, tmp3, LogBytesPerInt);
4873   stwx(carry, z, tmp);
4874   addic_(tmp3, tmp3, -1);
4875   blt(CCR0, L_done);
4876 
4877   srdi(carry, carry, 32);
4878   sldi(tmp, tmp3, LogBytesPerInt);
4879   stwx(carry, z, tmp);
4880   b(L_second_loop);
4881 
4882   // Next infrequent code is moved outside loops.
4883   bind(L_last_x);
4884 
4885   lwz(x_xstart, 0, x);
4886   b(L_third_loop_prologue);
4887 
4888   bind(L_done);
4889 }   // multiply_to_len
4890 
4891 void MacroAssembler::asm_assert(bool check_equal, const char *msg, int id) {
4892 #ifdef ASSERT
4893   Label ok;
4894   if (check_equal) {
4895     beq(CCR0, ok);
4896   } else {
4897     bne(CCR0, ok);
4898   }
4899   stop(msg, id);
4900   bind(ok);
4901 #endif
4902 }
4903 
4904 void MacroAssembler::asm_assert_mems_zero(bool check_equal, int size, int mem_offset,
4905                                           Register mem_base, const char* msg, int id) {
4906 #ifdef ASSERT
4907   switch (size) {
4908     case 4:
4909       lwz(R0, mem_offset, mem_base);
4910       cmpwi(CCR0, R0, 0);
4911       break;
4912     case 8:
4913       ld(R0, mem_offset, mem_base);
4914       cmpdi(CCR0, R0, 0);
4915       break;
4916     default:
4917       ShouldNotReachHere();
4918   }
4919   asm_assert(check_equal, msg, id);
4920 #endif // ASSERT
4921 }
4922 
4923 void MacroAssembler::verify_thread() {
4924   if (VerifyThread) {
4925     unimplemented("'VerifyThread' currently not implemented on PPC");
4926   }
4927 }
4928 
4929 // READ: oop. KILL: R0. Volatile floats perhaps.
4930 void MacroAssembler::verify_oop(Register oop, const char* msg) {
4931   if (!VerifyOops) {
4932     return;
4933   }
4934 
4935   address/* FunctionDescriptor** */fd = StubRoutines::verify_oop_subroutine_entry_address();
4936   const Register tmp = R11; // Will be preserved.
4937   const int nbytes_save = MacroAssembler::num_volatile_regs * 8;
4938   save_volatile_gprs(R1_SP, -nbytes_save); // except R0
4939 
4940   mr_if_needed(R4_ARG2, oop);
4941   save_LR_CR(tmp); // save in old frame
4942   push_frame_reg_args(nbytes_save, tmp);
4943   // load FunctionDescriptor** / entry_address *
4944   load_const_optimized(tmp, fd, R0);
4945   // load FunctionDescriptor* / entry_address
4946   ld(tmp, 0, tmp);
4947   load_const_optimized(R3_ARG1, (address)msg, R0);
4948   // Call destination for its side effect.
4949   call_c(tmp);
4950 
4951   pop_frame();
4952   restore_LR_CR(tmp);
4953   restore_volatile_gprs(R1_SP, -nbytes_save); // except R0
4954 }
4955 
4956 void MacroAssembler::verify_oop_addr(RegisterOrConstant offs, Register base, const char* msg) {
4957   if (!VerifyOops) {
4958     return;
4959   }
4960 
4961   address/* FunctionDescriptor** */fd = StubRoutines::verify_oop_subroutine_entry_address();
4962   const Register tmp = R11; // Will be preserved.
4963   const int nbytes_save = MacroAssembler::num_volatile_regs * 8;
4964   save_volatile_gprs(R1_SP, -nbytes_save); // except R0
4965 
4966   ld(R4_ARG2, offs, base);
4967   save_LR_CR(tmp); // save in old frame
4968   push_frame_reg_args(nbytes_save, tmp);
4969   // load FunctionDescriptor** / entry_address *
4970   load_const_optimized(tmp, fd, R0);
4971   // load FunctionDescriptor* / entry_address
4972   ld(tmp, 0, tmp);
4973   load_const_optimized(R3_ARG1, (address)msg, R0);
4974   // Call destination for its side effect.
4975   call_c(tmp);
4976 
4977   pop_frame();
4978   restore_LR_CR(tmp);
4979   restore_volatile_gprs(R1_SP, -nbytes_save); // except R0
4980 }
4981 
4982 const char* stop_types[] = {
4983   "stop",
4984   "untested",
4985   "unimplemented",
4986   "shouldnotreachhere"
4987 };
4988 
4989 static void stop_on_request(int tp, const char* msg) {
4990   tty->print("PPC assembly code requires stop: (%s) %s\n", stop_types[tp%/*stop_end*/4], msg);
4991   guarantee(false, "PPC assembly code requires stop: %s", msg);
4992 }
4993 
4994 // Call a C-function that prints output.
4995 void MacroAssembler::stop(int type, const char* msg, int id) {
4996 #ifndef PRODUCT
4997   block_comment(err_msg("stop: %s %s {", stop_types[type%stop_end], msg));
4998 #else
4999   block_comment("stop {");
5000 #endif
5001 
5002   // setup arguments
5003   load_const_optimized(R3_ARG1, type);
5004   load_const_optimized(R4_ARG2, (void *)msg, /*tmp=*/R0);
5005   call_VM_leaf(CAST_FROM_FN_PTR(address, stop_on_request), R3_ARG1, R4_ARG2);
5006   illtrap();
5007   emit_int32(id);
5008   block_comment("} stop;");
5009 }
5010 
5011 #ifndef PRODUCT
5012 // Write pattern 0x0101010101010101 in memory region [low-before, high+after].
5013 // Val, addr are temp registers.
5014 // If low == addr, addr is killed.
5015 // High is preserved.
5016 void MacroAssembler::zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) {
5017   if (!ZapMemory) return;
5018 
5019   assert_different_registers(low, val);
5020 
5021   BLOCK_COMMENT("zap memory region {");
5022   load_const_optimized(val, 0x0101010101010101);
5023   int size = before + after;
5024   if (low == high && size < 5 && size > 0) {
5025     int offset = -before*BytesPerWord;
5026     for (int i = 0; i < size; ++i) {
5027       std(val, offset, low);
5028       offset += (1*BytesPerWord);
5029     }
5030   } else {
5031     addi(addr, low, -before*BytesPerWord);
5032     assert_different_registers(high, val);
5033     if (after) addi(high, high, after * BytesPerWord);
5034     Label loop;
5035     bind(loop);
5036     std(val, 0, addr);
5037     addi(addr, addr, 8);
5038     cmpd(CCR6, addr, high);
5039     ble(CCR6, loop);
5040     if (after) addi(high, high, -after * BytesPerWord);  // Correct back to old value.
5041   }
5042   BLOCK_COMMENT("} zap memory region");
5043 }
5044 
5045 #endif // !PRODUCT
5046 
5047 void SkipIfEqualZero::skip_to_label_if_equal_zero(MacroAssembler* masm, Register temp,
5048                                                   const bool* flag_addr, Label& label) {
5049   int simm16_offset = masm->load_const_optimized(temp, (address)flag_addr, R0, true);
5050   assert(sizeof(bool) == 1, "PowerPC ABI");
5051   masm->lbz(temp, simm16_offset, temp);
5052   masm->cmpwi(CCR0, temp, 0);
5053   masm->beq(CCR0, label);
5054 }
5055 
5056 SkipIfEqualZero::SkipIfEqualZero(MacroAssembler* masm, Register temp, const bool* flag_addr) : _masm(masm), _label() {
5057   skip_to_label_if_equal_zero(masm, temp, flag_addr, _label);
5058 }
5059 
5060 SkipIfEqualZero::~SkipIfEqualZero() {
5061   _masm->bind(_label);
5062 }