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src/hotspot/cpu/ppc/ppc.ad

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*** 1,8 **** // ! // Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved. ! // Copyright (c) 2012, 2019 SAP SE. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License version 2 only, as // published by the Free Software Foundation. --- 1,8 ---- // ! // Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. ! // Copyright (c) 2012, 2018 SAP SE. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License version 2 only, as // published by the Free Software Foundation.
*** 1398,1425 **** } else { // Get return pc. ___(mflr) mflr(return_pc); } - if (C->clinit_barrier_on_entry()) { - assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started"); - - Label L_skip_barrier; - Register klass = toc_temp; - - // Notify OOP recorder (don't need the relocation) - AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding()); - __ load_const_optimized(klass, md.value(), R0); - __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/); - - __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0); - __ mtctr(klass); - __ bctr(); - - __ bind(L_skip_barrier); - } - // Calls to C2R adapters often do not accept exceptional returns. // We require that their callers must bang for them. But be // careful, because some VM calls (such as call site linkage) can // use several kilobytes of stack. But the stack safety zone should // account for that. See bugs 4446381, 4468289, 4497237. --- 1398,1407 ----
*** 4647,4666 **** op_cost(40); format %{ %} interface(CONST_INTER); %} - // Double Immediate: +0.0d. - operand immD_0() %{ - predicate(jlong_cast(n->getd()) == 0); - match(ConD); - - op_cost(0); - format %{ %} - interface(CONST_INTER); - %} - // Integer Register Operands // Integer Destination Register // See definition of reg_class bits32_reg_rw. operand iRegIdst() %{ constraint(ALLOC_IN_RC(bits32_reg_rw)); --- 4629,4638 ----
*** 14035,14045 **** %} instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ match(Set dst (ReplicateS zero)); predicate(n->as_Vector()->length() == 4); ! format %{ "LI $dst, #0 \t// replicate4S" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); %} --- 14007,14017 ---- %} instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ match(Set dst (ReplicateS zero)); predicate(n->as_Vector()->length() == 4); ! format %{ "LI $dst, #0 \t// replicate4C" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); %}
*** 14047,14057 **** %} instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ match(Set dst (ReplicateS src)); predicate(n->as_Vector()->length() == 4); ! format %{ "LI $dst, -1 \t// replicate4S" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); %} --- 14019,14029 ---- %} instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ match(Set dst (ReplicateS src)); predicate(n->as_Vector()->length() == 4); ! format %{ "LI $dst, -1 \t// replicate4C" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); %}
*** 14088,14098 **** instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{ match(Set dst (ReplicateS src)); predicate(n->as_Vector()->length() == 8); ! format %{ "XXLEQV $dst, $src \t// replicate8S" %} size(4); ins_encode %{ __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister); %} ins_pipe(pipe_class_default); --- 14060,14070 ---- instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{ match(Set dst (ReplicateS src)); predicate(n->as_Vector()->length() == 8); ! format %{ "XXLEQV $dst, $src \t// replicate16B" %} size(4); ins_encode %{ __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister); %} ins_pipe(pipe_class_default);
*** 14109,14119 **** %} instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ match(Set dst (ReplicateI zero)); predicate(n->as_Vector()->length() == 2); ! format %{ "LI $dst, #0 \t// replicate2I" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); %} --- 14081,14091 ---- %} instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ match(Set dst (ReplicateI zero)); predicate(n->as_Vector()->length() == 2); ! format %{ "LI $dst, #0 \t// replicate4C" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); %}
*** 14121,14131 **** %} instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ match(Set dst (ReplicateI src)); predicate(n->as_Vector()->length() == 2); ! format %{ "LI $dst, -1 \t// replicate2I" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); %} --- 14093,14103 ---- %} instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ match(Set dst (ReplicateI src)); predicate(n->as_Vector()->length() == 2); ! format %{ "LI $dst, -1 \t// replicate4C" %} size(4); ins_encode %{ // TODO: PPC port $archOpcode(ppc64Opcode_addi); __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); %}
*** 14695,14705 **** __ xxpermdi($dst$$VectorSRegister, $src$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr(), 0); %} ins_pipe(pipe_class_default); %} ! instruct repl2D_immD0(vecX dst, immD_0 zero) %{ match(Set dst (ReplicateD zero)); predicate(n->as_Vector()->length() == 2); format %{ "XXLXOR $dst, $zero \t// replicate2D" %} size(4); --- 14667,14677 ---- __ xxpermdi($dst$$VectorSRegister, $src$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr(), 0); %} ins_pipe(pipe_class_default); %} ! instruct repl2D_immI0(vecX dst, immI_0 zero) %{ match(Set dst (ReplicateD zero)); predicate(n->as_Vector()->length() == 2); format %{ "XXLXOR $dst, $zero \t// replicate2D" %} size(4);
*** 14707,14716 **** --- 14679,14700 ---- __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister); %} ins_pipe(pipe_class_default); %} + instruct repl2D_immIminus1(vecX dst, immI_minus1 src) %{ + match(Set dst (ReplicateD src)); + predicate(n->as_Vector()->length() == 2); + + format %{ "XXLEQV $dst, $src \t// replicate16B" %} + size(4); + ins_encode %{ + __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister); + %} + ins_pipe(pipe_class_default); + %} + instruct mtvsrd(vecX dst, iRegLsrc src) %{ predicate(false); effect(DEF dst, USE src); format %{ "MTVSRD $dst, $src \t// Move to 16-byte register" %}
*** 14768,14778 **** instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{ match(Set dst (ReplicateL src)); predicate(n->as_Vector()->length() == 2); ! format %{ "XXLEQV $dst, $src \t// replicate2L" %} size(4); ins_encode %{ __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister); %} ins_pipe(pipe_class_default); --- 14752,14762 ---- instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{ match(Set dst (ReplicateL src)); predicate(n->as_Vector()->length() == 2); ! format %{ "XXLEQV $dst, $src \t// replicate16B" %} size(4); ins_encode %{ __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister); %} ins_pipe(pipe_class_default);
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