< prev index next >

src/hotspot/cpu/ppc/ppc.ad

Print this page


   1 //
   2 // Copyright (c) 2011, 2019, Oracle and/or its affiliates. All rights reserved.
   3 // Copyright (c) 2012, 2019 SAP SE. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
  18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //


1383   assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1384 
1385   const bool method_is_frameless      = false /* TODO: PPC port C->is_frameless_method()*/;
1386 
1387   const Register return_pc            = R20; // Must match return_addr() in frame section.
1388   const Register callers_sp           = R21;
1389   const Register push_frame_temp      = R22;
1390   const Register toc_temp             = R23;
1391   assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1392 
1393   if (method_is_frameless) {
1394     // Add nop at beginning of all frameless methods to prevent any
1395     // oop instructions from getting overwritten by make_not_entrant
1396     // (patching attempt would fail).
1397     ___(nop) nop();
1398   } else {
1399     // Get return pc.
1400     ___(mflr) mflr(return_pc);
1401   }
1402 
1403   if (C->clinit_barrier_on_entry()) {
1404     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1405 
1406     Label L_skip_barrier;
1407     Register klass = toc_temp;
1408 
1409     // Notify OOP recorder (don't need the relocation)
1410     AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding());
1411     __ load_const_optimized(klass, md.value(), R0);
1412     __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
1413 
1414     __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
1415     __ mtctr(klass);
1416     __ bctr();
1417 
1418     __ bind(L_skip_barrier);
1419   }
1420 
1421   // Calls to C2R adapters often do not accept exceptional returns.
1422   // We require that their callers must bang for them. But be
1423   // careful, because some VM calls (such as call site linkage) can
1424   // use several kilobytes of stack. But the stack safety zone should
1425   // account for that. See bugs 4446381, 4468289, 4497237.
1426 
1427   int bangsize = C->bang_size_in_bytes();
1428   assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1429   if (C->need_stack_bang(bangsize) && UseStackBanging) {
1430     // Unfortunately we cannot use the function provided in
1431     // assembler.cpp as we have to emulate the pipes. So I had to
1432     // insert the code of generate_stack_overflow_check(), see
1433     // assembler.cpp for some illuminative comments.
1434     const int page_size = os::vm_page_size();
1435     int bang_end = JavaThread::stack_shadow_zone_size();
1436 
1437     // This is how far the previous frame's stack banging extended.
1438     const int bang_end_safe = bang_end;
1439 
1440     if (bangsize > page_size) {


4632 %}
4633 
4634 // Float Immediate: +0.0f.
4635 operand immF_0() %{
4636   predicate(jint_cast(n->getf()) == 0);
4637   match(ConF);
4638 
4639   op_cost(0);
4640   format %{ %}
4641   interface(CONST_INTER);
4642 %}
4643 
4644 // Double Immediate
4645 operand immD() %{
4646   match(ConD);
4647   op_cost(40);
4648   format %{ %}
4649   interface(CONST_INTER);
4650 %}
4651 
4652 // Double Immediate: +0.0d.
4653 operand immD_0() %{
4654   predicate(jlong_cast(n->getd()) == 0);
4655   match(ConD);
4656 
4657   op_cost(0);
4658   format %{ %}
4659   interface(CONST_INTER);
4660 %}
4661 
4662 // Integer Register Operands
4663 // Integer Destination Register
4664 // See definition of reg_class bits32_reg_rw.
4665 operand iRegIdst() %{
4666   constraint(ALLOC_IN_RC(bits32_reg_rw));
4667   match(RegI);
4668   match(rscratch1RegI);
4669   match(rscratch2RegI);
4670   match(rarg1RegI);
4671   match(rarg2RegI);
4672   match(rarg3RegI);
4673   match(rarg4RegI);
4674   format %{ %}
4675   interface(REG_INTER);
4676 %}
4677 
4678 // Integer Source Register
4679 // See definition of reg_class bits32_reg_ro.
4680 operand iRegIsrc() %{
4681   constraint(ALLOC_IN_RC(bits32_reg_ro));


14020   size(4);
14021   ins_encode %{
14022     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14023   %}
14024   ins_pipe(pipe_class_default);
14025 %}
14026 
14027 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
14028   match(Set dst (ReplicateS src));
14029   predicate(n->as_Vector()->length() == 4);
14030   expand %{
14031     moveReg(dst, src);
14032     repl48(dst);
14033     repl32(dst);
14034   %}
14035 %}
14036 
14037 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
14038   match(Set dst (ReplicateS zero));
14039   predicate(n->as_Vector()->length() == 4);
14040   format %{ "LI      $dst, #0 \t// replicate4S" %}
14041   size(4);
14042   ins_encode %{
14043     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14044     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
14045   %}
14046   ins_pipe(pipe_class_default);
14047 %}
14048 
14049 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
14050   match(Set dst (ReplicateS src));
14051   predicate(n->as_Vector()->length() == 4);
14052   format %{ "LI      $dst, -1 \t// replicate4S" %}
14053   size(4);
14054   ins_encode %{
14055     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14056     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
14057   %}
14058   ins_pipe(pipe_class_default);
14059 %}
14060 
14061 instruct repl8S_reg_Ex(vecX dst, iRegIsrc src) %{
14062   match(Set dst (ReplicateS src));
14063   predicate(n->as_Vector()->length() == 8);
14064 
14065   expand %{
14066     iRegLdst tmpL;
14067     vecX tmpV;
14068     immI8  zero %{ (int)  0 %}
14069     moveReg(tmpL, src);
14070     repl48(tmpL);
14071     repl32(tmpL);
14072     mtvsrd(tmpV, tmpL);
14073     xxpermdi(dst, tmpV, tmpV, zero);
14074   %}
14075 %}
14076 
14077 instruct repl8S_immI0(vecX dst, immI_0 zero) %{
14078   match(Set dst (ReplicateS zero));
14079   predicate(n->as_Vector()->length() == 8);
14080 
14081   format %{ "XXLXOR      $dst, $zero \t// replicate8S" %}
14082   size(4);
14083   ins_encode %{
14084     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14085   %}
14086   ins_pipe(pipe_class_default);
14087 %}
14088 
14089 instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{
14090   match(Set dst (ReplicateS src));
14091   predicate(n->as_Vector()->length() == 8);
14092 
14093   format %{ "XXLEQV      $dst, $src \t// replicate8S" %}
14094   size(4);
14095   ins_encode %{
14096     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14097   %}
14098   ins_pipe(pipe_class_default);
14099 %}
14100 
14101 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
14102   match(Set dst (ReplicateI src));
14103   predicate(n->as_Vector()->length() == 2);
14104   ins_cost(2 * DEFAULT_COST);
14105   expand %{
14106     moveReg(dst, src);
14107     repl32(dst);
14108   %}
14109 %}
14110 
14111 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
14112   match(Set dst (ReplicateI zero));
14113   predicate(n->as_Vector()->length() == 2);
14114   format %{ "LI      $dst, #0 \t// replicate2I" %}
14115   size(4);
14116   ins_encode %{
14117     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14118     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
14119   %}
14120   ins_pipe(pipe_class_default);
14121 %}
14122 
14123 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
14124   match(Set dst (ReplicateI src));
14125   predicate(n->as_Vector()->length() == 2);
14126   format %{ "LI      $dst, -1 \t// replicate2I" %}
14127   size(4);
14128   ins_encode %{
14129     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14130     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
14131   %}
14132   ins_pipe(pipe_class_default);
14133 %}
14134 
14135 instruct repl4I_reg_Ex(vecX dst, iRegIsrc src) %{
14136   match(Set dst (ReplicateI src));
14137   predicate(n->as_Vector()->length() == 4);
14138   ins_cost(2 * DEFAULT_COST);
14139 
14140   expand %{
14141     iRegLdst tmpL;
14142     vecX tmpV;
14143     immI8  zero %{ (int)  0 %}
14144     moveReg(tmpL, src);
14145     repl32(tmpL);
14146     mtvsrd(tmpV, tmpL);


14680 
14681   format %{ "XXLXOR      $dst, $zero \t// replicate4F" %}
14682   ins_encode %{
14683     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14684   %}
14685   ins_pipe(pipe_class_default);
14686 %}
14687 
14688 instruct repl2D_reg_Ex(vecX dst, regD src) %{
14689   match(Set dst (ReplicateD src));
14690   predicate(n->as_Vector()->length() == 2);
14691 
14692   format %{ "XXPERMDI      $dst, $src, $src, 0 \t// Splat doubleword" %}
14693   size(4);
14694   ins_encode %{
14695     __ xxpermdi($dst$$VectorSRegister, $src$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr(), 0);
14696   %}
14697   ins_pipe(pipe_class_default);
14698 %}
14699 
14700 instruct repl2D_immD0(vecX dst, immD_0 zero) %{
14701   match(Set dst (ReplicateD zero));
14702   predicate(n->as_Vector()->length() == 2);
14703 
14704   format %{ "XXLXOR      $dst, $zero \t// replicate2D" %}
14705   size(4);
14706   ins_encode %{
14707     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14708   %}
14709   ins_pipe(pipe_class_default);
14710 %}
14711 












14712 instruct mtvsrd(vecX dst, iRegLsrc src) %{
14713   predicate(false);
14714   effect(DEF dst, USE src);
14715 
14716   format %{ "MTVSRD      $dst, $src \t// Move to 16-byte register" %}
14717   size(4);
14718   ins_encode %{
14719     __ mtvsrd($dst$$VectorSRegister, $src$$Register);
14720   %}
14721   ins_pipe(pipe_class_default);
14722 %}
14723 
14724 instruct xxspltd(vecX dst, vecX src, immI8 zero) %{
14725   effect(DEF dst, USE src, USE zero);
14726 
14727   format %{ "XXSPLATD      $dst, $src, $zero \t// Splat doubleword" %}
14728   size(4);
14729   ins_encode %{
14730     __ xxpermdi($dst$$VectorSRegister, $src$$VectorSRegister, $src$$VectorSRegister, $zero$$constant);
14731   %}


14753     xxpermdi(dst, tmpV, tmpV, zero);
14754   %}
14755 %}
14756 
14757 instruct repl2L_immI0(vecX dst, immI_0 zero) %{
14758   match(Set dst (ReplicateL zero));
14759   predicate(n->as_Vector()->length() == 2);
14760 
14761   format %{ "XXLXOR      $dst, $zero \t// replicate2L" %}
14762   size(4);
14763   ins_encode %{
14764     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14765   %}
14766   ins_pipe(pipe_class_default);
14767 %}
14768 
14769 instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{
14770   match(Set dst (ReplicateL src));
14771   predicate(n->as_Vector()->length() == 2);
14772 
14773   format %{ "XXLEQV      $dst, $src \t// replicate2L" %}
14774   size(4);
14775   ins_encode %{
14776     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14777   %}
14778   ins_pipe(pipe_class_default);
14779 %}
14780 
14781 // ============================================================================
14782 // Safepoint Instruction
14783 
14784 instruct safePoint_poll(iRegPdst poll) %{
14785   match(SafePoint poll);
14786 
14787   // It caused problems to add the effect that r0 is killed, but this
14788   // effect no longer needs to be mentioned, since r0 is not contained
14789   // in a reg_class.
14790 
14791   format %{ "LD      R0, #0, $poll \t// Safepoint poll for GC" %}
14792   size(4);
14793   ins_encode( enc_poll(0x0, poll) );


   1 //
   2 // Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved.
   3 // Copyright (c) 2012, 2018 SAP SE. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
  18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //


1383   assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1384 
1385   const bool method_is_frameless      = false /* TODO: PPC port C->is_frameless_method()*/;
1386 
1387   const Register return_pc            = R20; // Must match return_addr() in frame section.
1388   const Register callers_sp           = R21;
1389   const Register push_frame_temp      = R22;
1390   const Register toc_temp             = R23;
1391   assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1392 
1393   if (method_is_frameless) {
1394     // Add nop at beginning of all frameless methods to prevent any
1395     // oop instructions from getting overwritten by make_not_entrant
1396     // (patching attempt would fail).
1397     ___(nop) nop();
1398   } else {
1399     // Get return pc.
1400     ___(mflr) mflr(return_pc);
1401   }
1402 


















1403   // Calls to C2R adapters often do not accept exceptional returns.
1404   // We require that their callers must bang for them. But be
1405   // careful, because some VM calls (such as call site linkage) can
1406   // use several kilobytes of stack. But the stack safety zone should
1407   // account for that. See bugs 4446381, 4468289, 4497237.
1408 
1409   int bangsize = C->bang_size_in_bytes();
1410   assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1411   if (C->need_stack_bang(bangsize) && UseStackBanging) {
1412     // Unfortunately we cannot use the function provided in
1413     // assembler.cpp as we have to emulate the pipes. So I had to
1414     // insert the code of generate_stack_overflow_check(), see
1415     // assembler.cpp for some illuminative comments.
1416     const int page_size = os::vm_page_size();
1417     int bang_end = JavaThread::stack_shadow_zone_size();
1418 
1419     // This is how far the previous frame's stack banging extended.
1420     const int bang_end_safe = bang_end;
1421 
1422     if (bangsize > page_size) {


4614 %}
4615 
4616 // Float Immediate: +0.0f.
4617 operand immF_0() %{
4618   predicate(jint_cast(n->getf()) == 0);
4619   match(ConF);
4620 
4621   op_cost(0);
4622   format %{ %}
4623   interface(CONST_INTER);
4624 %}
4625 
4626 // Double Immediate
4627 operand immD() %{
4628   match(ConD);
4629   op_cost(40);
4630   format %{ %}
4631   interface(CONST_INTER);
4632 %}
4633 










4634 // Integer Register Operands
4635 // Integer Destination Register
4636 // See definition of reg_class bits32_reg_rw.
4637 operand iRegIdst() %{
4638   constraint(ALLOC_IN_RC(bits32_reg_rw));
4639   match(RegI);
4640   match(rscratch1RegI);
4641   match(rscratch2RegI);
4642   match(rarg1RegI);
4643   match(rarg2RegI);
4644   match(rarg3RegI);
4645   match(rarg4RegI);
4646   format %{ %}
4647   interface(REG_INTER);
4648 %}
4649 
4650 // Integer Source Register
4651 // See definition of reg_class bits32_reg_ro.
4652 operand iRegIsrc() %{
4653   constraint(ALLOC_IN_RC(bits32_reg_ro));


13992   size(4);
13993   ins_encode %{
13994     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
13995   %}
13996   ins_pipe(pipe_class_default);
13997 %}
13998 
13999 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
14000   match(Set dst (ReplicateS src));
14001   predicate(n->as_Vector()->length() == 4);
14002   expand %{
14003     moveReg(dst, src);
14004     repl48(dst);
14005     repl32(dst);
14006   %}
14007 %}
14008 
14009 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
14010   match(Set dst (ReplicateS zero));
14011   predicate(n->as_Vector()->length() == 4);
14012   format %{ "LI      $dst, #0 \t// replicate4C" %}
14013   size(4);
14014   ins_encode %{
14015     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14016     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
14017   %}
14018   ins_pipe(pipe_class_default);
14019 %}
14020 
14021 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
14022   match(Set dst (ReplicateS src));
14023   predicate(n->as_Vector()->length() == 4);
14024   format %{ "LI      $dst, -1 \t// replicate4C" %}
14025   size(4);
14026   ins_encode %{
14027     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14028     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
14029   %}
14030   ins_pipe(pipe_class_default);
14031 %}
14032 
14033 instruct repl8S_reg_Ex(vecX dst, iRegIsrc src) %{
14034   match(Set dst (ReplicateS src));
14035   predicate(n->as_Vector()->length() == 8);
14036 
14037   expand %{
14038     iRegLdst tmpL;
14039     vecX tmpV;
14040     immI8  zero %{ (int)  0 %}
14041     moveReg(tmpL, src);
14042     repl48(tmpL);
14043     repl32(tmpL);
14044     mtvsrd(tmpV, tmpL);
14045     xxpermdi(dst, tmpV, tmpV, zero);
14046   %}
14047 %}
14048 
14049 instruct repl8S_immI0(vecX dst, immI_0 zero) %{
14050   match(Set dst (ReplicateS zero));
14051   predicate(n->as_Vector()->length() == 8);
14052 
14053   format %{ "XXLXOR      $dst, $zero \t// replicate8S" %}
14054   size(4);
14055   ins_encode %{
14056     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14057   %}
14058   ins_pipe(pipe_class_default);
14059 %}
14060 
14061 instruct repl8S_immIminus1(vecX dst, immI_minus1 src) %{
14062   match(Set dst (ReplicateS src));
14063   predicate(n->as_Vector()->length() == 8);
14064 
14065   format %{ "XXLEQV      $dst, $src \t// replicate16B" %}
14066   size(4);
14067   ins_encode %{
14068     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14069   %}
14070   ins_pipe(pipe_class_default);
14071 %}
14072 
14073 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
14074   match(Set dst (ReplicateI src));
14075   predicate(n->as_Vector()->length() == 2);
14076   ins_cost(2 * DEFAULT_COST);
14077   expand %{
14078     moveReg(dst, src);
14079     repl32(dst);
14080   %}
14081 %}
14082 
14083 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
14084   match(Set dst (ReplicateI zero));
14085   predicate(n->as_Vector()->length() == 2);
14086   format %{ "LI      $dst, #0 \t// replicate4C" %}
14087   size(4);
14088   ins_encode %{
14089     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14090     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
14091   %}
14092   ins_pipe(pipe_class_default);
14093 %}
14094 
14095 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
14096   match(Set dst (ReplicateI src));
14097   predicate(n->as_Vector()->length() == 2);
14098   format %{ "LI      $dst, -1 \t// replicate4C" %}
14099   size(4);
14100   ins_encode %{
14101     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
14102     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
14103   %}
14104   ins_pipe(pipe_class_default);
14105 %}
14106 
14107 instruct repl4I_reg_Ex(vecX dst, iRegIsrc src) %{
14108   match(Set dst (ReplicateI src));
14109   predicate(n->as_Vector()->length() == 4);
14110   ins_cost(2 * DEFAULT_COST);
14111 
14112   expand %{
14113     iRegLdst tmpL;
14114     vecX tmpV;
14115     immI8  zero %{ (int)  0 %}
14116     moveReg(tmpL, src);
14117     repl32(tmpL);
14118     mtvsrd(tmpV, tmpL);


14652 
14653   format %{ "XXLXOR      $dst, $zero \t// replicate4F" %}
14654   ins_encode %{
14655     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14656   %}
14657   ins_pipe(pipe_class_default);
14658 %}
14659 
14660 instruct repl2D_reg_Ex(vecX dst, regD src) %{
14661   match(Set dst (ReplicateD src));
14662   predicate(n->as_Vector()->length() == 2);
14663 
14664   format %{ "XXPERMDI      $dst, $src, $src, 0 \t// Splat doubleword" %}
14665   size(4);
14666   ins_encode %{
14667     __ xxpermdi($dst$$VectorSRegister, $src$$FloatRegister->to_vsr(), $src$$FloatRegister->to_vsr(), 0);
14668   %}
14669   ins_pipe(pipe_class_default);
14670 %}
14671 
14672 instruct repl2D_immI0(vecX dst, immI_0 zero) %{
14673   match(Set dst (ReplicateD zero));
14674   predicate(n->as_Vector()->length() == 2);
14675 
14676   format %{ "XXLXOR      $dst, $zero \t// replicate2D" %}
14677   size(4);
14678   ins_encode %{
14679     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14680   %}
14681   ins_pipe(pipe_class_default);
14682 %}
14683 
14684 instruct repl2D_immIminus1(vecX dst, immI_minus1 src) %{
14685   match(Set dst (ReplicateD src));
14686   predicate(n->as_Vector()->length() == 2);
14687 
14688   format %{ "XXLEQV      $dst, $src \t// replicate16B" %}
14689   size(4);
14690   ins_encode %{
14691     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14692   %}
14693   ins_pipe(pipe_class_default);
14694 %}
14695 
14696 instruct mtvsrd(vecX dst, iRegLsrc src) %{
14697   predicate(false);
14698   effect(DEF dst, USE src);
14699 
14700   format %{ "MTVSRD      $dst, $src \t// Move to 16-byte register" %}
14701   size(4);
14702   ins_encode %{
14703     __ mtvsrd($dst$$VectorSRegister, $src$$Register);
14704   %}
14705   ins_pipe(pipe_class_default);
14706 %}
14707 
14708 instruct xxspltd(vecX dst, vecX src, immI8 zero) %{
14709   effect(DEF dst, USE src, USE zero);
14710 
14711   format %{ "XXSPLATD      $dst, $src, $zero \t// Splat doubleword" %}
14712   size(4);
14713   ins_encode %{
14714     __ xxpermdi($dst$$VectorSRegister, $src$$VectorSRegister, $src$$VectorSRegister, $zero$$constant);
14715   %}


14737     xxpermdi(dst, tmpV, tmpV, zero);
14738   %}
14739 %}
14740 
14741 instruct repl2L_immI0(vecX dst, immI_0 zero) %{
14742   match(Set dst (ReplicateL zero));
14743   predicate(n->as_Vector()->length() == 2);
14744 
14745   format %{ "XXLXOR      $dst, $zero \t// replicate2L" %}
14746   size(4);
14747   ins_encode %{
14748     __ xxlxor($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14749   %}
14750   ins_pipe(pipe_class_default);
14751 %}
14752 
14753 instruct repl2L_immIminus1(vecX dst, immI_minus1 src) %{
14754   match(Set dst (ReplicateL src));
14755   predicate(n->as_Vector()->length() == 2);
14756 
14757   format %{ "XXLEQV      $dst, $src \t// replicate16B" %}
14758   size(4);
14759   ins_encode %{
14760     __ xxleqv($dst$$VectorSRegister, $dst$$VectorSRegister, $dst$$VectorSRegister);
14761   %}
14762   ins_pipe(pipe_class_default);
14763 %}
14764 
14765 // ============================================================================
14766 // Safepoint Instruction
14767 
14768 instruct safePoint_poll(iRegPdst poll) %{
14769   match(SafePoint poll);
14770 
14771   // It caused problems to add the effect that r0 is killed, but this
14772   // effect no longer needs to be mentioned, since r0 is not contained
14773   // in a reg_class.
14774 
14775   format %{ "LD      R0, #0, $poll \t// Safepoint poll for GC" %}
14776   size(4);
14777   ins_encode( enc_poll(0x0, poll) );


< prev index next >