1 //
   2 // Copyright (c) 2017, 2019, Oracle and/or its affiliates. All rights reserved.
   3 // Copyright (c) 2017, 2019 SAP SE. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
  18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //
  24 
  25 // z/Architecture Architecture Description File
  26 
  27 // Major contributions by AS, JL, LS.
  28 
  29 //
  30 // Following information is derived from private mail communication
  31 // (Oct. 2011).
  32 //
  33 // General branch target alignment considerations
  34 //
  35 // z/Architecture does not imply a general branch target alignment requirement.
  36 // There are side effects and side considerations, though, which may
  37 // provide some performance benefit. These are:
  38 //  - Align branch target on octoword (32-byte) boundary
  39 //    On more recent models (from z9 on), I-fetch is done on a Octoword
  40 //    (32 bytes at a time) basis. To avoid I-fetching unnecessary
  41 //    instructions, branch targets should be 32-byte aligend. If this
  42 //    exact alingment cannot be achieved, having the branch target in
  43 //    the first doubleword still provides some benefit.
  44 //  - Avoid branch targets at the end of cache lines (> 64 bytes distance).
  45 //    Sequential instruction prefetching after the branch target starts
  46 //    immediately after having fetched the octoword containing the
  47 //    branch target. When I-fetching crosses a cache line, there may be
  48 //    a small stall. The worst case: the branch target (at the end of
  49 //    a cache line) is a L1 I-cache miss and the next line as well.
  50 //    Then, the entire target line must be filled first (to contine at the
  51 //    branch target). Only then can the next sequential line be filled.
  52 //  - Avoid multiple poorly predicted branches in a row.
  53 //
  54 
  55 //----------REGISTER DEFINITION BLOCK------------------------------------------
  56 // This information is used by the matcher and the register allocator to
  57 // describe individual registers and classes of registers within the target
  58 // architecture.
  59 
  60 register %{
  61 
  62 //----------Architecture Description Register Definitions----------------------
  63 // General Registers
  64 // "reg_def" name (register save type, C convention save type,
  65 //                   ideal register type, encoding);
  66 //
  67 // Register Save Types:
  68 //
  69 //   NS  = No-Save:     The register allocator assumes that these registers
  70 //                      can be used without saving upon entry to the method, &
  71 //                      that they do not need to be saved at call sites.
  72 //
  73 //   SOC = Save-On-Call: The register allocator assumes that these registers
  74 //                      can be used without saving upon entry to the method,
  75 //                      but that they must be saved at call sites.
  76 //
  77 //   SOE = Save-On-Entry: The register allocator assumes that these registers
  78 //                      must be saved before using them upon entry to the
  79 //                      method, but they do not need to be saved at call sites.
  80 //
  81 //   AS  = Always-Save: The register allocator assumes that these registers
  82 //                      must be saved before using them upon entry to the
  83 //                      method, & that they must be saved at call sites.
  84 //
  85 // Ideal Register Type is used to determine how to save & restore a
  86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
  88 //
  89 // The encoding number is the actual bit-pattern placed into the opcodes.
  90 
  91 // z/Architecture register definitions, based on the z/Architecture Principles
  92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
  93 // 5th Edition, March 2001.
  94 //
  95 // For each 64-bit register we must define two registers: the register
  96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
  97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
  98 // for stores, loads, etc.
  99 
 100   // Integer/Long Registers
 101   // ----------------------------
 102 
 103   // z/Architecture has 16 64-bit integer registers.
 104 
 105   // types: v = volatile, nv = non-volatile, s = system
 106   reg_def Z_R0   (SOC, SOC, Op_RegI,  0, Z_R0->as_VMReg());   // v   scratch1
 107   reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
 108   reg_def Z_R1   (SOC, SOC, Op_RegI,  1, Z_R1->as_VMReg());   // v   scratch2
 109   reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
 110   reg_def Z_R2   (SOC, SOC, Op_RegI,  2, Z_R2->as_VMReg());   // v   iarg1 & iret
 111   reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
 112   reg_def Z_R3   (SOC, SOC, Op_RegI,  3, Z_R3->as_VMReg());   // v   iarg2
 113   reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
 114   reg_def Z_R4   (SOC, SOC, Op_RegI,  4, Z_R4->as_VMReg());   // v   iarg3
 115   reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
 116   reg_def Z_R5   (SOC, SOC, Op_RegI,  5, Z_R5->as_VMReg());   // v   iarg4
 117   reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
 118   reg_def Z_R6   (SOC, SOE, Op_RegI,  6, Z_R6->as_VMReg());   // v   iarg5
 119   reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
 120   reg_def Z_R7   (SOC, SOE, Op_RegI,  7, Z_R7->as_VMReg());
 121   reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
 122   reg_def Z_R8   (SOC, SOE, Op_RegI,  8, Z_R8->as_VMReg());
 123   reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
 124   reg_def Z_R9   (SOC, SOE, Op_RegI,  9, Z_R9->as_VMReg());
 125   reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
 126   reg_def Z_R10  (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
 127   reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
 128   reg_def Z_R11  (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
 129   reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
 130   reg_def Z_R12  (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
 131   reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
 132   reg_def Z_R13  (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
 133   reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
 134   reg_def Z_R14  (NS,  NS,  Op_RegI, 14, Z_R14->as_VMReg());   // s  return_pc
 135   reg_def Z_R14_H(NS,  NS,  Op_RegI, 99, Z_R14->as_VMReg()->next());
 136   reg_def Z_R15  (NS,  NS,  Op_RegI, 15, Z_R15->as_VMReg());   // s  SP
 137   reg_def Z_R15_H(NS,  NS,  Op_RegI, 99, Z_R15->as_VMReg()->next());
 138 
 139   // Float/Double Registers
 140 
 141   // The rules of ADL require that double registers be defined in pairs.
 142   // Each pair must be two 32-bit values, but not necessarily a pair of
 143   // single float registers. In each pair, ADLC-assigned register numbers
 144   // must be adjacent, with the lower number even. Finally, when the
 145   // CPU stores such a register pair to memory, the word associated with
 146   // the lower ADLC-assigned number must be stored to the lower address.
 147 
 148   // z/Architecture has 16 64-bit floating-point registers. Each can store a single
 149   // or double precision floating-point value.
 150 
 151   // types: v = volatile, nv = non-volatile, s = system
 152   reg_def Z_F0   (SOC, SOC, Op_RegF,  0, Z_F0->as_VMReg());   // v   farg1 & fret
 153   reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
 154   reg_def Z_F1   (SOC, SOC, Op_RegF,  1, Z_F1->as_VMReg());
 155   reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
 156   reg_def Z_F2   (SOC, SOC, Op_RegF,  2, Z_F2->as_VMReg());   // v   farg2
 157   reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
 158   reg_def Z_F3   (SOC, SOC, Op_RegF,  3, Z_F3->as_VMReg());
 159   reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
 160   reg_def Z_F4   (SOC, SOC, Op_RegF,  4, Z_F4->as_VMReg());   // v   farg3
 161   reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
 162   reg_def Z_F5   (SOC, SOC, Op_RegF,  5, Z_F5->as_VMReg());
 163   reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
 164   reg_def Z_F6   (SOC, SOC, Op_RegF,  6, Z_F6->as_VMReg());
 165   reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
 166   reg_def Z_F7   (SOC, SOC, Op_RegF,  7, Z_F7->as_VMReg());
 167   reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
 168   reg_def Z_F8   (SOC, SOE, Op_RegF,  8, Z_F8->as_VMReg());
 169   reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
 170   reg_def Z_F9   (SOC, SOE, Op_RegF,  9, Z_F9->as_VMReg());
 171   reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
 172   reg_def Z_F10  (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
 173   reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
 174   reg_def Z_F11  (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
 175   reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
 176   reg_def Z_F12  (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
 177   reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
 178   reg_def Z_F13  (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
 179   reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
 180   reg_def Z_F14  (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
 181   reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
 182   reg_def Z_F15  (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
 183   reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
 184 
 185 
 186   // Special Registers
 187 
 188   // Condition Codes Flag Registers
 189 
 190   // z/Architecture has the PSW (program status word) that contains
 191   // (among other information) the condition code. We treat this
 192   // part of the PSW as a condition register CR. It consists of 4
 193   // bits. Floating point instructions influence the same condition register CR.
 194 
 195   reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg());   // volatile
 196 
 197 
 198 // Specify priority of register selection within phases of register
 199 // allocation. Highest priority is first. A useful heuristic is to
 200 // give registers a low priority when they are required by machine
 201 // instructions, and choose no-save registers before save-on-call, and
 202 // save-on-call before save-on-entry. Registers which participate in
 203 // fix calling sequences should come last. Registers which are used
 204 // as pairs must fall on an even boundary.
 205 
 206 // It's worth about 1% on SPEC geomean to get this right.
 207 
 208 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
 209 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
 210 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
 211 // the same as Z_R3->encoding()! Furthermore, we cannot make any
 212 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
 213 // Additionally, the function
 214 //   static enum RC rc_class(OptoReg::Name reg)
 215 // maps a given <register>_num value to its chunk type (except for flags)
 216 // and its current implementation relies on chunk0 and chunk1 having a
 217 // size of 64 each.
 218 
 219 alloc_class chunk0(
 220   // chunk0 contains *all* 32 integer registers halves.
 221 
 222   // potential SOE regs
 223   Z_R13,Z_R13_H,
 224   Z_R12,Z_R12_H,
 225   Z_R11,Z_R11_H,
 226   Z_R10,Z_R10_H,
 227 
 228   Z_R9,Z_R9_H,
 229   Z_R8,Z_R8_H,
 230   Z_R7,Z_R7_H,
 231 
 232   Z_R1,Z_R1_H,
 233   Z_R0,Z_R0_H,
 234 
 235   // argument registers
 236   Z_R6,Z_R6_H,
 237   Z_R5,Z_R5_H,
 238   Z_R4,Z_R4_H,
 239   Z_R3,Z_R3_H,
 240   Z_R2,Z_R2_H,
 241 
 242   // special registers
 243   Z_R14,Z_R14_H,
 244   Z_R15,Z_R15_H
 245 );
 246 
 247 alloc_class chunk1(
 248   // Chunk1 contains *all* 64 floating-point registers halves.
 249 
 250   Z_F15,Z_F15_H,
 251   Z_F14,Z_F14_H,
 252   Z_F13,Z_F13_H,
 253   Z_F12,Z_F12_H,
 254   Z_F11,Z_F11_H,
 255   Z_F10,Z_F10_H,
 256   Z_F9,Z_F9_H,
 257   Z_F8,Z_F8_H,
 258   // scratch register
 259   Z_F7,Z_F7_H,
 260   Z_F5,Z_F5_H,
 261   Z_F3,Z_F3_H,
 262   Z_F1,Z_F1_H,
 263   // argument registers
 264   Z_F6,Z_F6_H,
 265   Z_F4,Z_F4_H,
 266   Z_F2,Z_F2_H,
 267   Z_F0,Z_F0_H
 268 );
 269 
 270 alloc_class chunk2(
 271   Z_CR
 272 );
 273 
 274 
 275 //-------Architecture Description Register Classes-----------------------
 276 
 277 // Several register classes are automatically defined based upon
 278 // information in this architecture description.
 279 
 280 // 1) reg_class inline_cache_reg           (as defined in frame section)
 281 // 2) reg_class compiler_method_oop_reg    (as defined in frame section)
 282 // 2) reg_class interpreter_method_oop_reg (as defined in frame section)
 283 // 3) reg_class stack_slots(/* one chunk of stack-based "registers" */)
 284 
 285 // Integer Register Classes
 286 reg_class z_int_reg(
 287 /*Z_R0*/              // R0
 288 /*Z_R1*/
 289   Z_R2,
 290   Z_R3,
 291   Z_R4,
 292   Z_R5,
 293   Z_R6,
 294   Z_R7,
 295 /*Z_R8,*/             // Z_thread
 296   Z_R9,
 297   Z_R10,
 298   Z_R11,
 299   Z_R12,
 300   Z_R13
 301 /*Z_R14*/             // return_pc
 302 /*Z_R15*/             // SP
 303 );
 304 
 305 reg_class z_no_odd_int_reg(
 306 /*Z_R0*/              // R0
 307 /*Z_R1*/
 308   Z_R2,
 309   Z_R3,
 310   Z_R4,
 311 /*Z_R5,*/             // odd part of fix register pair
 312   Z_R6,
 313   Z_R7,
 314 /*Z_R8,*/             // Z_thread
 315   Z_R9,
 316   Z_R10,
 317   Z_R11,
 318   Z_R12,
 319   Z_R13
 320 /*Z_R14*/             // return_pc
 321 /*Z_R15*/             // SP
 322 );
 323 
 324 reg_class z_no_arg_int_reg(
 325 /*Z_R0*/              // R0
 326 /*Z_R1*/              // scratch
 327 /*Z_R2*/
 328 /*Z_R3*/
 329 /*Z_R4*/
 330 /*Z_R5*/
 331 /*Z_R6*/
 332   Z_R7,
 333 /*Z_R8*/              // Z_thread
 334   Z_R9,
 335   Z_R10,
 336   Z_R11,
 337   Z_R12,
 338   Z_R13
 339 /*Z_R14*/             // return_pc
 340 /*Z_R15*/             // SP
 341 );
 342 
 343 reg_class z_rarg1_int_reg(Z_R2);
 344 reg_class z_rarg2_int_reg(Z_R3);
 345 reg_class z_rarg3_int_reg(Z_R4);
 346 reg_class z_rarg4_int_reg(Z_R5);
 347 reg_class z_rarg5_int_reg(Z_R6);
 348 
 349 // Pointer Register Classes
 350 
 351 // 64-bit build means 64-bit pointers means hi/lo pairs.
 352 
 353 reg_class z_rarg5_ptrN_reg(Z_R6);
 354 
 355 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
 356 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
 357 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
 358 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
 359 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
 360 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
 361 
 362 reg_class z_ptr_reg(
 363 /*Z_R0_H,Z_R0*/     // R0
 364 /*Z_R1_H,Z_R1*/
 365   Z_R2_H,Z_R2,
 366   Z_R3_H,Z_R3,
 367   Z_R4_H,Z_R4,
 368   Z_R5_H,Z_R5,
 369   Z_R6_H,Z_R6,
 370   Z_R7_H,Z_R7,
 371 /*Z_R8_H,Z_R8,*/    // Z_thread
 372   Z_R9_H,Z_R9,
 373   Z_R10_H,Z_R10,
 374   Z_R11_H,Z_R11,
 375   Z_R12_H,Z_R12,
 376   Z_R13_H,Z_R13
 377 /*Z_R14_H,Z_R14*/   // return_pc
 378 /*Z_R15_H,Z_R15*/   // SP
 379 );
 380 
 381 reg_class z_lock_ptr_reg(
 382 /*Z_R0_H,Z_R0*/     // R0
 383 /*Z_R1_H,Z_R1*/
 384   Z_R2_H,Z_R2,
 385   Z_R3_H,Z_R3,
 386   Z_R4_H,Z_R4,
 387 /*Z_R5_H,Z_R5,*/
 388 /*Z_R6_H,Z_R6,*/
 389   Z_R7_H,Z_R7,
 390 /*Z_R8_H,Z_R8,*/    // Z_thread
 391   Z_R9_H,Z_R9,
 392   Z_R10_H,Z_R10,
 393   Z_R11_H,Z_R11,
 394   Z_R12_H,Z_R12,
 395   Z_R13_H,Z_R13
 396 /*Z_R14_H,Z_R14*/   // return_pc
 397 /*Z_R15_H,Z_R15*/   // SP
 398 );
 399 
 400 reg_class z_no_arg_ptr_reg(
 401 /*Z_R0_H,Z_R0*/        // R0
 402 /*Z_R1_H,Z_R1*/        // scratch
 403 /*Z_R2_H,Z_R2*/
 404 /*Z_R3_H,Z_R3*/
 405 /*Z_R4_H,Z_R4*/
 406 /*Z_R5_H,Z_R5*/
 407 /*Z_R6_H,Z_R6*/
 408   Z_R7_H, Z_R7,
 409 /*Z_R8_H,Z_R8*/        // Z_thread
 410   Z_R9_H,Z_R9,
 411   Z_R10_H,Z_R10,
 412   Z_R11_H,Z_R11,
 413   Z_R12_H,Z_R12,
 414   Z_R13_H,Z_R13
 415 /*Z_R14_H,Z_R14*/      // return_pc
 416 /*Z_R15_H,Z_R15*/      // SP
 417 );
 418 
 419 // Special class for storeP instructions, which can store SP or RPC to
 420 // TLS. (Note: Do not generalize this to "any_reg". If you add
 421 // another register, such as FP, to this mask, the allocator may try
 422 // to put a temp in it.)
 423 // Register class for memory access base registers,
 424 // This class is a superset of z_ptr_reg including Z_thread.
 425 reg_class z_memory_ptr_reg(
 426 /*Z_R0_H,Z_R0*/     // R0
 427 /*Z_R1_H,Z_R1*/
 428   Z_R2_H,Z_R2,
 429   Z_R3_H,Z_R3,
 430   Z_R4_H,Z_R4,
 431   Z_R5_H,Z_R5,
 432   Z_R6_H,Z_R6,
 433   Z_R7_H,Z_R7,
 434   Z_R8_H,Z_R8,      // Z_thread
 435   Z_R9_H,Z_R9,
 436   Z_R10_H,Z_R10,
 437   Z_R11_H,Z_R11,
 438   Z_R12_H,Z_R12,
 439   Z_R13_H,Z_R13
 440 /*Z_R14_H,Z_R14*/   // return_pc
 441 /*Z_R15_H,Z_R15*/   // SP
 442 );
 443 
 444 // Other special pointer regs.
 445 reg_class z_r1_regP(Z_R1_H,Z_R1);
 446 reg_class z_r9_regP(Z_R9_H,Z_R9);
 447 
 448 
 449 // Long Register Classes
 450 
 451 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
 452 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
 453 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
 454 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
 455 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
 456 
 457 // Longs in 1 register. Aligned adjacent hi/lo pairs.
 458 reg_class z_long_reg(
 459 /*Z_R0_H,Z_R0*/     // R0
 460 /*Z_R1_H,Z_R1*/
 461   Z_R2_H,Z_R2,
 462   Z_R3_H,Z_R3,
 463   Z_R4_H,Z_R4,
 464   Z_R5_H,Z_R5,
 465   Z_R6_H,Z_R6,
 466   Z_R7_H,Z_R7,
 467 /*Z_R8_H,Z_R8,*/    // Z_thread
 468   Z_R9_H,Z_R9,
 469   Z_R10_H,Z_R10,
 470   Z_R11_H,Z_R11,
 471   Z_R12_H,Z_R12,
 472   Z_R13_H,Z_R13
 473 /*Z_R14_H,Z_R14,*/  // return_pc
 474 /*Z_R15_H,Z_R15*/   // SP
 475 );
 476 
 477 // z_long_reg without even registers
 478 reg_class z_long_odd_reg(
 479 /*Z_R0_H,Z_R0*/     // R0
 480 /*Z_R1_H,Z_R1*/
 481   Z_R3_H,Z_R3,
 482   Z_R5_H,Z_R5,
 483   Z_R7_H,Z_R7,
 484   Z_R9_H,Z_R9,
 485   Z_R11_H,Z_R11,
 486   Z_R13_H,Z_R13
 487 /*Z_R14_H,Z_R14,*/  // return_pc
 488 /*Z_R15_H,Z_R15*/   // SP
 489 );
 490 
 491 // Special Class for Condition Code Flags Register
 492 
 493 reg_class z_condition_reg(
 494   Z_CR
 495 );
 496 
 497 // Scratch register for late profiling. Callee saved.
 498 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
 499 
 500 
 501 // Float Register Classes
 502 
 503 reg_class z_flt_reg(
 504   Z_F0,
 505 /*Z_F1,*/ // scratch
 506   Z_F2,
 507   Z_F3,
 508   Z_F4,
 509   Z_F5,
 510   Z_F6,
 511   Z_F7,
 512   Z_F8,
 513   Z_F9,
 514   Z_F10,
 515   Z_F11,
 516   Z_F12,
 517   Z_F13,
 518   Z_F14,
 519   Z_F15
 520 );
 521 reg_class z_rscratch1_flt_reg(Z_F1);
 522 
 523 // Double precision float registers have virtual `high halves' that
 524 // are needed by the allocator.
 525 reg_class z_dbl_reg(
 526   Z_F0,Z_F0_H,
 527 /*Z_F1,Z_F1_H,*/ // scratch
 528   Z_F2,Z_F2_H,
 529   Z_F3,Z_F3_H,
 530   Z_F4,Z_F4_H,
 531   Z_F5,Z_F5_H,
 532   Z_F6,Z_F6_H,
 533   Z_F7,Z_F7_H,
 534   Z_F8,Z_F8_H,
 535   Z_F9,Z_F9_H,
 536   Z_F10,Z_F10_H,
 537   Z_F11,Z_F11_H,
 538   Z_F12,Z_F12_H,
 539   Z_F13,Z_F13_H,
 540   Z_F14,Z_F14_H,
 541   Z_F15,Z_F15_H
 542 );
 543 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
 544 
 545 %}
 546 
 547 //----------DEFINITION BLOCK---------------------------------------------------
 548 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
 549 // Current support includes integer values in the range [0, 0x7FFFFFFF].
 550 // Format:
 551 //        int_def  <name>         (<int_value>, <expression>);
 552 // Generated Code in ad_<arch>.hpp
 553 //        #define  <name>   (<expression>)
 554 //        // value == <int_value>
 555 // Generated code in ad_<arch>.cpp adlc_verification()
 556 //        assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 557 //
 558 definitions %{
 559   // The default cost (of an ALU instruction).
 560   int_def DEFAULT_COST      (   100,     100);
 561   int_def DEFAULT_COST_LOW  (    80,      80);
 562   int_def DEFAULT_COST_HIGH (   120,     120);
 563   int_def HUGE_COST         (1000000, 1000000);
 564 
 565   // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
 566   int_def ALU_REG_COST      (   100, DEFAULT_COST);
 567   int_def ALU_MEMORY_COST   (   150,          150);
 568 
 569   // Memory refs are twice as expensive as run-of-the-mill.
 570   int_def MEMORY_REF_COST_HI (   220, 2 * DEFAULT_COST+20);
 571   int_def MEMORY_REF_COST    (   200, 2 * DEFAULT_COST);
 572   int_def MEMORY_REF_COST_LO (   180, 2 * DEFAULT_COST-20);
 573 
 574   // Branches are even more expensive.
 575   int_def BRANCH_COST       (   300, DEFAULT_COST * 3);
 576   int_def CALL_COST         (   300, DEFAULT_COST * 3);
 577 %}
 578 
 579 source %{
 580 
 581 #ifdef PRODUCT
 582 #define BLOCK_COMMENT(str)
 583 #define BIND(label)        __ bind(label)
 584 #else
 585 #define BLOCK_COMMENT(str) __ block_comment(str)
 586 #define BIND(label)        __ bind(label); BLOCK_COMMENT(#label ":")
 587 #endif
 588 
 589 #define __ _masm.
 590 
 591 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ?  4 : 6
 592 #define Z_DISP3_SIZE 6
 593 
 594 // Tertiary op of a LoadP or StoreP encoding.
 595 #define REGP_OP true
 596 
 597 // Given a register encoding, produce an Integer Register object.
 598 static Register reg_to_register_object(int register_encoding);
 599 
 600 // ****************************************************************************
 601 
 602 // REQUIRED FUNCTIONALITY
 603 
 604 // !!!!! Special hack to get all type of calls to specify the byte offset
 605 //       from the start of the call to the point where the return address
 606 //       will point.
 607 
 608 int MachCallStaticJavaNode::ret_addr_offset() {
 609   if (_method) {
 610     return 8;
 611   } else {
 612     return MacroAssembler::call_far_patchable_ret_addr_offset();
 613   }
 614 }
 615 
 616 int MachCallDynamicJavaNode::ret_addr_offset() {
 617   // Consider size of receiver type profiling (C2 tiers).
 618   int profile_receiver_type_size = 0;
 619 
 620   int vtable_index = this->_vtable_index;
 621   if (vtable_index == -4) {
 622     return 14 + profile_receiver_type_size;
 623   } else {
 624     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 625     return 36 + profile_receiver_type_size;
 626   }
 627 }
 628 
 629 int MachCallRuntimeNode::ret_addr_offset() {
 630   return 12 + MacroAssembler::call_far_patchable_ret_addr_offset();
 631 }
 632 
 633 // Compute padding required for nodes which need alignment
 634 //
 635 // The addresses of the call instructions needs to be 4-byte aligned to
 636 // ensure that they don't span a cache line so that they are atomically patchable.
 637 // The actual calls get emitted at different offsets within the node emitters.
 638 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
 639 
 640 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
 641   return (0 - current_offset) & 2;
 642 }
 643 
 644 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
 645   return (6 - current_offset) & 2;
 646 }
 647 
 648 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
 649   return (12 - current_offset) & 2;
 650 }
 651 
 652 int CallLeafDirectNode::compute_padding(int current_offset) const {
 653   return (12 - current_offset) & 2;
 654 }
 655 
 656 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
 657   return (12 - current_offset) & 2;
 658 }
 659 
 660 // Indicate if the safepoint node needs the polling page as an input.
 661 // Since z/Architecture does not have absolute addressing, it does.
 662 bool SafePointNode::needs_polling_address_input() {
 663   return true;
 664 }
 665 
 666 void emit_nop(CodeBuffer &cbuf) {
 667   MacroAssembler _masm(&cbuf);
 668   __ z_nop();
 669 }
 670 
 671 // Emit an interrupt that is caught by the debugger (for debugging compiler).
 672 void emit_break(CodeBuffer &cbuf) {
 673   MacroAssembler _masm(&cbuf);
 674   __ z_illtrap();
 675 }
 676 
 677 #if !defined(PRODUCT)
 678 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
 679   os->print("TA");
 680 }
 681 #endif
 682 
 683 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 684   emit_break(cbuf);
 685 }
 686 
 687 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 688   return MachNode::size(ra_);
 689 }
 690 
 691 static inline void z_emit16(CodeBuffer &cbuf, long value) {
 692   // 32bit instructions may become sign extended.
 693   assert(value >= 0, "unintended sign extension (int->long)");
 694   assert(value < (1L << 16), "instruction too large");
 695   *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value;
 696   cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short));
 697 }
 698 
 699 static inline void z_emit32(CodeBuffer &cbuf, long value) {
 700   // 32bit instructions may become sign extended.
 701   assert(value < (1L << 32), "instruction too large");
 702   *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value;
 703   cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int));
 704 }
 705 
 706 static inline void z_emit48(CodeBuffer &cbuf, long value) {
 707   // 32bit instructions may become sign extended.
 708   assert(value >= 0, "unintended sign extension (int->long)");
 709   assert(value < (1L << 48), "instruction too large");
 710   value = value<<16;
 711   memcpy(cbuf.insts_end(), (unsigned char*)&value, 6);
 712   cbuf.set_insts_end(cbuf.insts_end() + 6);
 713 }
 714 
 715 static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) {
 716   if (value < 0) {
 717     // There obviously has been an unintended sign extension (int->long). Revert it.
 718     value = (long)((unsigned long)((unsigned int)value));
 719   }
 720 
 721   if (value < (1L << 16)) { // 2-byte instruction
 722     z_emit16(cbuf, value);
 723     return 2;
 724   }
 725 
 726   if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store
 727     z_emit32(cbuf, value);
 728     return 4;
 729   }
 730 
 731   // 6-byte instruction, probably unaligned store.
 732   z_emit48(cbuf, value);
 733   return 6;
 734 }
 735 
 736 // Check effective address (at runtime) for required alignment.
 737 static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) {
 738   MacroAssembler _masm(&cbuf);
 739 
 740   __ z_lay(Z_R0, disp, index, base);
 741   __ z_nill(Z_R0, alignment-1);
 742   __ z_brc(Assembler::bcondEqual, +3);
 743   __ z_illtrap();
 744 }
 745 
 746 int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype,
 747                     PhaseRegAlloc* ra_, bool is_native_call = false) {
 748   __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
 749   address old_mark = __ inst_mark();
 750   unsigned int start_off = __ offset();
 751 
 752   if (is_native_call) {
 753     ShouldNotReachHere();
 754   }
 755 
 756   if (rtype == relocInfo::runtime_call_w_cp_type) {
 757     assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
 758     address call_addr = __ call_c_opt((address)entry_point);
 759     if (call_addr == NULL) {
 760       Compile::current()->env()->record_out_of_memory_failure();
 761       return -1;
 762     }
 763   } else {
 764     assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
 765            rtype == relocInfo::static_call_type, "unexpected rtype");
 766     __ relocate(rtype);
 767     // BRASL must be prepended with a nop to identify it in the instruction stream.
 768     __ z_nop();
 769     __ z_brasl(Z_R14, (address)entry_point);
 770   }
 771 
 772   unsigned int ret_off = __ offset();
 773 
 774   return (ret_off - start_off);
 775 }
 776 
 777 static int emit_call_reloc(MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) {
 778   __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
 779   address old_mark = __ inst_mark();
 780   unsigned int start_off = __ offset();
 781 
 782   relocInfo::relocType rtype = rspec.type();
 783   assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
 784          "unexpected rtype");
 785 
 786   __ relocate(rspec);
 787   __ z_nop();
 788   __ z_brasl(Z_R14, (address)entry_point);
 789 
 790   unsigned int ret_off = __ offset();
 791 
 792   return (ret_off - start_off);
 793 }
 794 
 795 //=============================================================================
 796 
 797 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
 798 int Compile::ConstantTable::calculate_table_base_offset() const {
 799   return 0;  // absolute addressing, no offset
 800 }
 801 
 802 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
 803 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
 804   ShouldNotReachHere();
 805 }
 806 
 807 // Even with PC-relative TOC addressing, we still need this node.
 808 // Float loads/stores do not support PC-relative addresses.
 809 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
 810   MacroAssembler _masm(&cbuf);
 811   Register Rtoc = as_Register(ra_->get_encode(this));
 812   __ load_toc(Rtoc);
 813 }
 814 
 815 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
 816   // PCrelative TOC access.
 817   return 6;   // sizeof(LARL)
 818 }
 819 
 820 #if !defined(PRODUCT)
 821 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
 822   Register r = as_Register(ra_->get_encode(this));
 823   st->print("LARL    %s,&constant_pool # MachConstantBaseNode", r->name());
 824 }
 825 #endif
 826 
 827 //=============================================================================
 828 
 829 #if !defined(PRODUCT)
 830 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 831   Compile* C = ra_->C;
 832   st->print_cr("--- MachPrologNode ---");
 833   st->print("\t");
 834   for (int i = 0; i < OptoPrologueNops; i++) {
 835     st->print_cr("NOP"); st->print("\t");
 836   }
 837 
 838   if (VerifyThread) {
 839     st->print_cr("Verify_Thread");
 840     st->print("\t");
 841   }
 842 
 843   long framesize = C->frame_size_in_bytes();
 844   int bangsize   = C->bang_size_in_bytes();
 845 
 846   // Calls to C2R adapters often do not accept exceptional returns.
 847   // We require that their callers must bang for them. But be
 848   // careful, because some VM calls (such as call site linkage) can
 849   // use several kilobytes of stack. But the stack safety zone should
 850   // account for that. See bugs 4446381, 4468289, 4497237.
 851   if (C->need_stack_bang(bangsize) && UseStackBanging) {
 852     st->print_cr("# stack bang"); st->print("\t");
 853   }
 854   st->print_cr("push_frame %d", (int)-framesize);
 855   st->print("\t");
 856 }
 857 #endif
 858 
 859 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 860   Compile* C = ra_->C;
 861   MacroAssembler _masm(&cbuf);
 862 
 863   __ verify_thread();
 864 
 865   size_t framesize = C->frame_size_in_bytes();
 866   size_t bangsize  = C->bang_size_in_bytes();
 867 
 868   assert(framesize % wordSize == 0, "must preserve wordSize alignment");
 869 
 870   if (C->clinit_barrier_on_entry()) {
 871     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
 872 
 873     Label L_skip_barrier;
 874     Register klass = Z_R1_scratch;
 875 
 876     // Notify OOP recorder (don't need the relocation)
 877     AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding());
 878     __ load_const_optimized(klass, md.value());
 879     __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
 880 
 881     __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
 882     __ z_br(klass);
 883 
 884     __ bind(L_skip_barrier);
 885   }
 886 
 887   // Calls to C2R adapters often do not accept exceptional returns.
 888   // We require that their callers must bang for them. But be
 889   // careful, because some VM calls (such as call site linkage) can
 890   // use several kilobytes of stack. But the stack safety zone should
 891   // account for that. See bugs 4446381, 4468289, 4497237.
 892   if (C->need_stack_bang(bangsize) && UseStackBanging) {
 893     __ generate_stack_overflow_check(bangsize);
 894   }
 895 
 896   assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
 897   __ save_return_pc();
 898 
 899   // The z/Architecture abi is already accounted for in `framesize' via the
 900   // 'out_preserve_stack_slots' declaration.
 901   __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
 902 
 903   if (C->has_mach_constant_base_node()) {
 904     // NOTE: We set the table base offset here because users might be
 905     // emitted before MachConstantBaseNode.
 906     Compile::ConstantTable& constant_table = C->constant_table();
 907     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
 908   }
 909 }
 910 
 911 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
 912   // Variable size. Determine dynamically.
 913   return MachNode::size(ra_);
 914 }
 915 
 916 int MachPrologNode::reloc() const {
 917   // Return number of relocatable values contained in this instruction.
 918   return 1; // One reloc entry for load_const(toc).
 919 }
 920 
 921 //=============================================================================
 922 
 923 #if !defined(PRODUCT)
 924 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
 925   os->print_cr("epilog");
 926   os->print("\t");
 927   if (do_polling() && ra_->C->is_method_compilation()) {
 928     os->print_cr("load_from_polling_page Z_R1_scratch");
 929     os->print("\t");
 930   }
 931 }
 932 #endif
 933 
 934 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 935   MacroAssembler _masm(&cbuf);
 936   Compile* C = ra_->C;
 937   __ verify_thread();
 938 
 939   // If this does safepoint polling, then do it here.
 940   bool need_polling = do_polling() && C->is_method_compilation();
 941 
 942   // Pop frame, restore return_pc, and all stuff needed by interpreter.
 943   int frame_size_in_bytes = Assembler::align((C->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
 944   __ pop_frame_restore_retPC(frame_size_in_bytes);
 945 
 946   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
 947     __ reserved_stack_check(Z_R14);
 948   }
 949 
 950   // Touch the polling page.
 951   if (need_polling) {
 952     if (SafepointMechanism::uses_thread_local_poll()) {
 953       __ z_lg(Z_R1_scratch, Address(Z_thread, Thread::polling_page_offset()));
 954     } else {
 955       AddressLiteral pp(os::get_polling_page());
 956       __ load_const_optimized(Z_R1_scratch, pp);
 957     }
 958     // We need to mark the code position where the load from the safepoint
 959     // polling page was emitted as relocInfo::poll_return_type here.
 960     __ relocate(relocInfo::poll_return_type);
 961     __ load_from_polling_page(Z_R1_scratch);
 962   }
 963 }
 964 
 965 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
 966   // Variable size. determine dynamically.
 967   return MachNode::size(ra_);
 968 }
 969 
 970 int MachEpilogNode::reloc() const {
 971   // Return number of relocatable values contained in this instruction.
 972   return 1; // One for load_from_polling_page.
 973 }
 974 
 975 const Pipeline * MachEpilogNode::pipeline() const {
 976   return MachNode::pipeline_class();
 977 }
 978 
 979 int MachEpilogNode::safepoint_offset() const {
 980   assert(do_polling(), "no return for this epilog node");
 981   return 0;
 982 }
 983 
 984 //=============================================================================
 985 
 986 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack.
 987 enum RC { rc_bad, rc_int, rc_float, rc_stack };
 988 
 989 static enum RC rc_class(OptoReg::Name reg) {
 990   // Return the register class for the given register. The given register
 991   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
 992   // enumeration in adGlobals_s390.hpp.
 993 
 994   if (reg == OptoReg::Bad) {
 995     return rc_bad;
 996   }
 997 
 998   // We have 32 integer register halves, starting at index 0.
 999   if (reg < 32) {
1000     return rc_int;
1001   }
1002 
1003   // We have 32 floating-point register halves, starting at index 32.
1004   if (reg < 32+32) {
1005     return rc_float;
1006   }
1007 
1008   // Between float regs & stack are the flags regs.
1009   assert(reg >= OptoReg::stack0(), "blow up if spilling flags");
1010   return rc_stack;
1011 }
1012 
1013 // Returns size as obtained from z_emit_instr.
1014 static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode,
1015                                    int reg, int offset, bool do_print, outputStream *os) {
1016 
1017   if (cbuf) {
1018     if (opcode > (1L<<32)) {
1019       return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
1020                          Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
1021     } else {
1022       return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
1023                          Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
1024     }
1025   }
1026 
1027 #if !defined(PRODUCT)
1028   if (do_print) {
1029     os->print("%s    %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
1030   }
1031 #endif
1032   return (opcode > (1L << 32)) ? 6 : 4;
1033 }
1034 
1035 static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
1036   if (cbuf) {
1037     MacroAssembler _masm(cbuf);
1038     __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
1039   }
1040 
1041 #if !defined(PRODUCT)
1042   else if (do_print) {
1043     os->print("MVC     %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
1044   }
1045 #endif
1046 
1047   return 6;
1048 }
1049 
1050 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
1051   // Get registers to move.
1052   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1053   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1054   OptoReg::Name dst_hi = ra_->get_reg_second(this);
1055   OptoReg::Name dst_lo = ra_->get_reg_first(this);
1056 
1057   enum RC src_hi_rc = rc_class(src_hi);
1058   enum RC src_lo_rc = rc_class(src_lo);
1059   enum RC dst_hi_rc = rc_class(dst_hi);
1060   enum RC dst_lo_rc = rc_class(dst_lo);
1061 
1062   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1063   bool is64 = (src_hi_rc != rc_bad);
1064   assert(!is64 ||
1065          ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
1066          "expected aligned-adjacent pairs");
1067 
1068   // Generate spill code!
1069 
1070   if (src_lo == dst_lo && src_hi == dst_hi) {
1071     return 0;            // Self copy, no move.
1072   }
1073 
1074   int  src_offset = ra_->reg2offset(src_lo);
1075   int  dst_offset = ra_->reg2offset(dst_lo);
1076   bool print = !do_size;
1077   bool src12 = Immediate::is_uimm12(src_offset);
1078   bool dst12 = Immediate::is_uimm12(dst_offset);
1079 
1080   const char   *mnemo = NULL;
1081   unsigned long opc = 0;
1082 
1083   // Memory->Memory Spill. Use Z_R0 to hold the value.
1084   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1085 
1086     assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
1087            "expected same type of move for high parts");
1088 
1089     if (src12 && dst12) {
1090       return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os);
1091     }
1092 
1093     int r0 = Z_R0_num;
1094     if (is64) {
1095       return z_ld_st_helper(cbuf, "LG  ", LG_ZOPC, r0, src_offset, print, os) +
1096              z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os);
1097     }
1098 
1099     return z_ld_st_helper(cbuf, "LY   ", LY_ZOPC, r0, src_offset, print, os) +
1100            z_ld_st_helper(cbuf, "STY  ", STY_ZOPC, r0, dst_offset, print, os);
1101   }
1102 
1103   // Check for float->int copy. Requires a trip through memory.
1104   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1105     Unimplemented();  // Unsafe, do not remove!
1106   }
1107 
1108   // Check for integer reg-reg copy.
1109   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1110     if (cbuf) {
1111       MacroAssembler _masm(cbuf);
1112       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1113       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1114       __ z_lgr(Rdst, Rsrc);
1115       return 4;
1116     }
1117 #if !defined(PRODUCT)
1118     // else
1119     if (print) {
1120       os->print("LGR     %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1121     }
1122 #endif
1123     return 4;
1124   }
1125 
1126   // Check for integer store.
1127   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1128     assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
1129            "expected same type of move for high parts");
1130 
1131     if (is64) {
1132       return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
1133     }
1134 
1135     // else
1136     mnemo = dst12 ? "ST  " : "STY ";
1137     opc = dst12 ? ST_ZOPC : STY_ZOPC;
1138 
1139     return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1140   }
1141 
1142   // Check for integer load
1143   // Always load cOops zero-extended. That doesn't hurt int loads.
1144   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1145 
1146     assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
1147            "expected same type of move for high parts");
1148 
1149     mnemo = is64 ? "LG  " : "LLGF";
1150     opc = is64 ? LG_ZOPC : LLGF_ZOPC;
1151 
1152     return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1153   }
1154 
1155   // Check for float reg-reg copy.
1156   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1157     if (cbuf) {
1158       MacroAssembler _masm(cbuf);
1159       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1160       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1161       __ z_ldr(Rdst, Rsrc);
1162       return 2;
1163     }
1164 #if !defined(PRODUCT)
1165     // else
1166     if (print) {
1167       os->print("LDR      %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1168     }
1169 #endif
1170     return 2;
1171   }
1172 
1173   // Check for float store.
1174   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1175     assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
1176            "expected same type of move for high parts");
1177 
1178     if (is64) {
1179       mnemo = dst12 ? "STD  " : "STDY ";
1180       opc = dst12 ? STD_ZOPC : STDY_ZOPC;
1181       return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1182     }
1183     // else
1184 
1185     mnemo = dst12 ? "STE  " : "STEY ";
1186     opc = dst12 ? STE_ZOPC : STEY_ZOPC;
1187     return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
1188   }
1189 
1190   // Check for float load.
1191   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1192     assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
1193            "expected same type of move for high parts");
1194 
1195     if (is64) {
1196       mnemo = src12 ? "LD   " : "LDY  ";
1197       opc = src12 ? LD_ZOPC : LDY_ZOPC;
1198       return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1199     }
1200     // else
1201 
1202     mnemo = src12 ? "LE   " : "LEY  ";
1203     opc = src12 ? LE_ZOPC : LEY_ZOPC;
1204     return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
1205   }
1206 
1207   // --------------------------------------------------------------------
1208   // Check for hi bits still needing moving. Only happens for misaligned
1209   // arguments to native calls.
1210   if (src_hi == dst_hi) {
1211     return 0;               // Self copy, no move.
1212   }
1213 
1214   assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1215   Unimplemented();  // Unsafe, do not remove!
1216 
1217   return 0; // never reached, but make the compiler shut up!
1218 }
1219 
1220 #if !defined(PRODUCT)
1221 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1222   if (ra_ && ra_->node_regs_max_index() > 0) {
1223     implementation(NULL, ra_, false, os);
1224   } else {
1225     if (req() == 2 && in(1)) {
1226       os->print("N%d = N%d\n", _idx, in(1)->_idx);
1227     } else {
1228       const char *c = "(";
1229       os->print("N%d = ", _idx);
1230       for (uint i = 1; i < req(); ++i) {
1231         os->print("%sN%d", c, in(i)->_idx);
1232         c = ", ";
1233       }
1234       os->print(")");
1235     }
1236   }
1237 }
1238 #endif
1239 
1240 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1241   implementation(&cbuf, ra_, false, NULL);
1242 }
1243 
1244 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1245   return implementation(NULL, ra_, true, NULL);
1246 }
1247 
1248 //=============================================================================
1249 
1250 #if !defined(PRODUCT)
1251 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
1252   os->print("NOP     # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
1253 }
1254 #endif
1255 
1256 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const {
1257   MacroAssembler _masm(&cbuf);
1258 
1259   int rem_space = 0;
1260   if (!(ra_->C->in_scratch_emit_size())) {
1261     rem_space = cbuf.insts()->remaining();
1262     if (rem_space <= _count*2 + 8) {
1263       tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
1264     }
1265   }
1266 
1267   for (int i = 0; i < _count; i++) {
1268     __ z_nop();
1269   }
1270 
1271   if (!(ra_->C->in_scratch_emit_size())) {
1272     if (rem_space <= _count*2 + 8) {
1273       int rem_space2 = cbuf.insts()->remaining();
1274       tty->print_cr(", after = %d", rem_space2);
1275     }
1276   }
1277 }
1278 
1279 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1280    return 2 * _count;
1281 }
1282 
1283 #if !defined(PRODUCT)
1284 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1285   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1286   if (ra_ && ra_->node_regs_max_index() > 0) {
1287     int reg = ra_->get_reg_first(this);
1288     os->print("ADDHI  %s, SP, %d\t//box node", Matcher::regName[reg], offset);
1289   } else {
1290     os->print("ADDHI  N%d = SP + %d\t// box node", _idx, offset);
1291   }
1292 }
1293 #endif
1294 
1295 // Take care of the size function, if you make changes here!
1296 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1297   MacroAssembler _masm(&cbuf);
1298 
1299   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1300   int reg = ra_->get_encode(this);
1301   __ z_lay(as_Register(reg), offset, Z_SP);
1302 }
1303 
1304 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1305   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1306   return 6;
1307 }
1308 
1309  %} // end source section
1310 
1311 //----------SOURCE BLOCK-------------------------------------------------------
1312 // This is a block of C++ code which provides values, functions, and
1313 // definitions necessary in the rest of the architecture description
1314 
1315 source_hpp %{
1316 
1317 // Header information of the source block.
1318 // Method declarations/definitions which are used outside
1319 // the ad-scope can conveniently be defined here.
1320 //
1321 // To keep related declarations/definitions/uses close together,
1322 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
1323 
1324 //--------------------------------------------------------------
1325 // Used for optimization in Compile::Shorten_branches
1326 //--------------------------------------------------------------
1327 
1328 class CallStubImpl {
1329  public:
1330 
1331   // call trampolines
1332   // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
1333   static uint size_call_trampoline() {
1334     return 0; // no call trampolines on this platform
1335   }
1336 
1337   // call trampolines
1338   // Number of relocations needed by a call trampoline stub.
1339   static uint reloc_call_trampoline() {
1340     return 0; // No call trampolines on this platform.
1341   }
1342 };
1343 
1344 %} // end source_hpp section
1345 
1346 source %{
1347 
1348 #if !defined(PRODUCT)
1349 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
1350   os->print_cr("---- MachUEPNode ----");
1351   os->print_cr("\tTA");
1352   os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
1353   os->print_cr("\tBR(Z_R1)");
1354   os->print_cr("\tTA  # pad with illtraps");
1355   os->print_cr("\t...");
1356   os->print_cr("\tTA");
1357   os->print_cr("\tLTGR    Z_R2, Z_R2");
1358   os->print_cr("\tBRU     ic_miss");
1359 }
1360 #endif
1361 
1362 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1363   MacroAssembler _masm(&cbuf);
1364   const int ic_miss_offset = 2;
1365 
1366   // Inline_cache contains a klass.
1367   Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1368   // ARG1 is the receiver oop.
1369   Register R2_receiver = Z_ARG1;
1370   int      klass_offset = oopDesc::klass_offset_in_bytes();
1371   AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub());
1372   Register R1_ic_miss_stub_addr = Z_R1_scratch;
1373 
1374   // Null check of receiver.
1375   // This is the null check of the receiver that actually should be
1376   // done in the caller. It's here because in case of implicit null
1377   // checks we get it for free.
1378   assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()),
1379          "second word in oop should not require explicit null check.");
1380   if (!ImplicitNullChecks) {
1381     Label valid;
1382     if (VM_Version::has_CompareBranch()) {
1383       __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid);
1384     } else {
1385       __ z_ltgr(R2_receiver, R2_receiver);
1386       __ z_bre(valid);
1387     }
1388     // The ic_miss_stub will handle the null pointer exception.
1389     __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
1390     __ z_br(R1_ic_miss_stub_addr);
1391     __ bind(valid);
1392   }
1393 
1394   // Check whether this method is the proper implementation for the class of
1395   // the receiver (ic miss check).
1396   {
1397     Label valid;
1398     // Compare cached class against klass from receiver.
1399     // This also does an implicit null check!
1400     __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false);
1401     __ z_bre(valid);
1402     // The inline cache points to the wrong method. Call the
1403     // ic_miss_stub to find the proper method.
1404     __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
1405     __ z_br(R1_ic_miss_stub_addr);
1406     __ bind(valid);
1407   }
1408 }
1409 
1410 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1411   // Determine size dynamically.
1412   return MachNode::size(ra_);
1413 }
1414 
1415 //=============================================================================
1416 
1417 %} // interrupt source section
1418 
1419 source_hpp %{ // Header information of the source block.
1420 
1421 class HandlerImpl {
1422  public:
1423 
1424   static int emit_exception_handler(CodeBuffer &cbuf);
1425   static int emit_deopt_handler(CodeBuffer& cbuf);
1426 
1427   static uint size_exception_handler() {
1428     return NativeJump::max_instruction_size();
1429   }
1430 
1431   static uint size_deopt_handler() {
1432     return NativeCall::max_instruction_size();
1433   }
1434 };
1435 
1436 %} // end source_hpp section
1437 
1438 source %{
1439 
1440 // This exception handler code snippet is placed after the method's
1441 // code. It is the return point if an exception occurred. it jumps to
1442 // the exception blob.
1443 //
1444 // If the method gets deoptimized, the method and this code snippet
1445 // get patched.
1446 //
1447 // 1) Trampoline code gets patched into the end of this exception
1448 //   handler. the trampoline code jumps to the deoptimization blob.
1449 //
1450 // 2) The return address in the method's code will get patched such
1451 //   that it jumps to the trampoline.
1452 //
1453 // 3) The handler will get patched such that it does not jump to the
1454 //   exception blob, but to an entry in the deoptimization blob being
1455 //   aware of the exception.
1456 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1457   Register temp_reg = Z_R1;
1458   MacroAssembler _masm(&cbuf);
1459 
1460   address base = __ start_a_stub(size_exception_handler());
1461   if (base == NULL) {
1462     return 0;          // CodeBuffer::expand failed
1463   }
1464 
1465   int offset = __ offset();
1466   // Use unconditional pc-relative jump with 32-bit range here.
1467   __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin());
1468   __ z_br(temp_reg);
1469 
1470   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1471 
1472   __ end_a_stub();
1473 
1474   return offset;
1475 }
1476 
1477 // Emit deopt handler code.
1478 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1479   MacroAssembler _masm(&cbuf);
1480   address        base = __ start_a_stub(size_deopt_handler());
1481 
1482   if (base == NULL) {
1483     return 0;  // CodeBuffer::expand failed
1484   }
1485 
1486   int offset = __ offset();
1487 
1488   // Size_deopt_handler() must be exact on zarch, so for simplicity
1489   // we do not use load_const_opt here.
1490   __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
1491   __ call(Z_R1);
1492   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1493 
1494   __ end_a_stub();
1495   return offset;
1496 }
1497 
1498 //=============================================================================
1499 
1500 
1501 // Given a register encoding, produce an Integer Register object.
1502 static Register reg_to_register_object(int register_encoding) {
1503   assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
1504   return as_Register(register_encoding);
1505 }
1506 
1507 const bool Matcher::match_rule_supported(int opcode) {
1508   if (!has_match_rule(opcode)) return false;
1509 
1510   switch (opcode) {
1511     case Op_CountLeadingZerosI:
1512     case Op_CountLeadingZerosL:
1513     case Op_CountTrailingZerosI:
1514     case Op_CountTrailingZerosL:
1515       // Implementation requires FLOGR instruction, which is available since z9.
1516       return true;
1517 
1518     case Op_ReverseBytesI:
1519     case Op_ReverseBytesL:
1520       return UseByteReverseInstruction;
1521 
1522     // PopCount supported by H/W from z/Architecture G5 (z196) on.
1523     case Op_PopCountI:
1524     case Op_PopCountL:
1525       return UsePopCountInstruction && VM_Version::has_PopCount();
1526 
1527     case Op_StrComp:
1528       return SpecialStringCompareTo;
1529     case Op_StrEquals:
1530       return SpecialStringEquals;
1531     case Op_StrIndexOf:
1532     case Op_StrIndexOfChar:
1533       return SpecialStringIndexOf;
1534 
1535     case Op_GetAndAddI:
1536     case Op_GetAndAddL:
1537       return true;
1538       // return VM_Version::has_AtomicMemWithImmALUOps();
1539     case Op_GetAndSetI:
1540     case Op_GetAndSetL:
1541     case Op_GetAndSetP:
1542     case Op_GetAndSetN:
1543       return true;  // General CAS implementation, always available.
1544 
1545     default:
1546       return true;  // Per default match rules are supported.
1547                     // BUT: make sure match rule is not disabled by a false predicate!
1548   }
1549 
1550   return true;  // Per default match rules are supported.
1551                 // BUT: make sure match rule is not disabled by a false predicate!
1552 }
1553 
1554 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1555   // TODO
1556   // Identify extra cases that we might want to provide match rules for
1557   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen.
1558   bool ret_value = match_rule_supported(opcode);
1559   // Add rules here.
1560 
1561   return ret_value;  // Per default match rules are supported.
1562 }
1563 
1564 int Matcher::regnum_to_fpu_offset(int regnum) {
1565   ShouldNotReachHere();
1566   return regnum - 32; // The FP registers are in the second chunk.
1567 }
1568 
1569 const bool Matcher::has_predicated_vectors(void) {
1570   return false;
1571 }
1572 
1573 const int Matcher::float_pressure(int default_pressure_threshold) {
1574   return default_pressure_threshold;
1575 }
1576 
1577 const bool Matcher::convL2FSupported(void) {
1578   return true; // False means that conversion is done by runtime call.
1579 }
1580 
1581 //----------SUPERWORD HELPERS----------------------------------------
1582 
1583 // Vector width in bytes.
1584 const int Matcher::vector_width_in_bytes(BasicType bt) {
1585   assert(MaxVectorSize == 8, "");
1586   return 8;
1587 }
1588 
1589 // Vector ideal reg.
1590 const uint Matcher::vector_ideal_reg(int size) {
1591   assert(MaxVectorSize == 8 && size == 8, "");
1592   return Op_RegL;
1593 }
1594 
1595 // Limits on vector size (number of elements) loaded into vector.
1596 const int Matcher::max_vector_size(const BasicType bt) {
1597   assert(is_java_primitive(bt), "only primitive type vectors");
1598   return vector_width_in_bytes(bt)/type2aelembytes(bt);
1599 }
1600 
1601 const int Matcher::min_vector_size(const BasicType bt) {
1602   return max_vector_size(bt); // Same as max.
1603 }
1604 
1605 const uint Matcher::vector_shift_count_ideal_reg(int size) {
1606   fatal("vector shift is not supported");
1607   return Node::NotAMachineReg;
1608 }
1609 
1610 // z/Architecture does support misaligned store/load at minimal extra cost.
1611 const bool Matcher::misaligned_vectors_ok() {
1612   return true;
1613 }
1614 
1615 // Not yet ported to z/Architecture.
1616 const bool Matcher::pass_original_key_for_aes() {
1617   return false;
1618 }
1619 
1620 // RETURNS: whether this branch offset is short enough that a short
1621 // branch can be used.
1622 //
1623 // If the platform does not provide any short branch variants, then
1624 // this method should return `false' for offset 0.
1625 //
1626 // `Compile::Fill_buffer' will decide on basis of this information
1627 // whether to do the pass `Compile::Shorten_branches' at all.
1628 //
1629 // And `Compile::Shorten_branches' will decide on basis of this
1630 // information whether to replace particular branch sites by short
1631 // ones.
1632 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1633   // On zarch short branches use a 16 bit signed immediate that
1634   // is the pc-relative offset in halfword (= 2 bytes) units.
1635   return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
1636 }
1637 
1638 const bool Matcher::isSimpleConstant64(jlong value) {
1639   // Probably always true, even if a temp register is required.
1640   return true;
1641 }
1642 
1643 // Should correspond to setting above
1644 const bool Matcher::init_array_count_is_in_bytes = false;
1645 
1646 // Suppress CMOVL. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet.
1647 const int Matcher::long_cmove_cost() { return ConditionalMoveLimit; }
1648 
1649 // Suppress CMOVF. Conditional move available on z/Architecture only from z196 onwards. Not exploited yet.
1650 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1651 
1652 // Does the CPU require postalloc expand (see block.cpp for description of postalloc expand)?
1653 const bool Matcher::require_postalloc_expand = false;
1654 
1655 // Do we need to mask the count passed to shift instructions or does
1656 // the cpu only look at the lower 5/6 bits anyway?
1657 // 32bit shifts mask in emitter, 64bit shifts need no mask.
1658 // Constant shift counts are handled in Ideal phase.
1659 const bool Matcher::need_masked_shift_count = false;
1660 
1661 // Set this as clone_shift_expressions.
1662 bool Matcher::narrow_oop_use_complex_address() {
1663   if (CompressedOops::base() == NULL && CompressedOops::shift() == 0) return true;
1664   return false;
1665 }
1666 
1667 bool Matcher::narrow_klass_use_complex_address() {
1668   NOT_LP64(ShouldNotCallThis());
1669   assert(UseCompressedClassPointers, "only for compressed klass code");
1670   // TODO HS25: z port if (MatchDecodeNodes) return true;
1671   return false;
1672 }
1673 
1674 bool Matcher::const_oop_prefer_decode() {
1675   // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
1676   return CompressedOops::base() == NULL;
1677 }
1678 
1679 bool Matcher::const_klass_prefer_decode() {
1680   // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
1681   return CompressedKlassPointers::base() == NULL;
1682 }
1683 
1684 // Is it better to copy float constants, or load them directly from memory?
1685 // Most RISCs will have to materialize an address into a
1686 // register first, so they would do better to copy the constant from stack.
1687 const bool Matcher::rematerialize_float_constants = false;
1688 
1689 // If CPU can load and store mis-aligned doubles directly then no fixup is
1690 // needed. Else we split the double into 2 integer pieces and move it
1691 // piece-by-piece. Only happens when passing doubles into C code as the
1692 // Java calling convention forces doubles to be aligned.
1693 const bool Matcher::misaligned_doubles_ok = true;
1694 
1695 // Advertise here if the CPU requires explicit rounding operations
1696 // to implement the UseStrictFP mode.
1697 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1698 
1699 // Do floats take an entire double register or just half?
1700 //
1701 // A float in resides in a zarch double register. When storing it by
1702 // z_std, it cannot be restored in C-code by reloading it as a double
1703 // and casting it into a float afterwards.
1704 bool Matcher::float_in_double() { return false; }
1705 
1706 // Do ints take an entire long register or just half?
1707 // The relevant question is how the int is callee-saved:
1708 // the whole long is written but de-opt'ing will have to extract
1709 // the relevant 32 bits.
1710 const bool Matcher::int_in_long = true;
1711 
1712 // Constants for c2c and c calling conventions.
1713 
1714 const MachRegisterNumbers z_iarg_reg[5] = {
1715   Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
1716 };
1717 
1718 const MachRegisterNumbers z_farg_reg[4] = {
1719   Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
1720 };
1721 
1722 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
1723 
1724 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
1725 
1726 // Return whether or not this register is ever used as an argument. This
1727 // function is used on startup to build the trampoline stubs in generateOptoStub.
1728 // Registers not mentioned will be killed by the VM call in the trampoline, and
1729 // arguments in those registers not be available to the callee.
1730 bool Matcher::can_be_java_arg(int reg) {
1731   // We return true for all registers contained in z_iarg_reg[] and
1732   // z_farg_reg[] and their virtual halves.
1733   // We must include the virtual halves in order to get STDs and LDs
1734   // instead of STWs and LWs in the trampoline stubs.
1735 
1736   if (reg == Z_R2_num || reg == Z_R2_H_num ||
1737       reg == Z_R3_num || reg == Z_R3_H_num ||
1738       reg == Z_R4_num || reg == Z_R4_H_num ||
1739       reg == Z_R5_num || reg == Z_R5_H_num ||
1740       reg == Z_R6_num || reg == Z_R6_H_num) {
1741     return true;
1742   }
1743 
1744   if (reg == Z_F0_num || reg == Z_F0_H_num ||
1745       reg == Z_F2_num || reg == Z_F2_H_num ||
1746       reg == Z_F4_num || reg == Z_F4_H_num ||
1747       reg == Z_F6_num || reg == Z_F6_H_num) {
1748     return true;
1749   }
1750 
1751   return false;
1752 }
1753 
1754 bool Matcher::is_spillable_arg(int reg) {
1755   return can_be_java_arg(reg);
1756 }
1757 
1758 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
1759   return false;
1760 }
1761 
1762 // Register for DIVI projection of divmodI
1763 RegMask Matcher::divI_proj_mask() {
1764   return _Z_RARG4_INT_REG_mask;
1765 }
1766 
1767 // Register for MODI projection of divmodI
1768 RegMask Matcher::modI_proj_mask() {
1769   return _Z_RARG3_INT_REG_mask;
1770 }
1771 
1772 // Register for DIVL projection of divmodL
1773 RegMask Matcher::divL_proj_mask() {
1774   return _Z_RARG4_LONG_REG_mask;
1775 }
1776 
1777 // Register for MODL projection of divmodL
1778 RegMask Matcher::modL_proj_mask() {
1779   return _Z_RARG3_LONG_REG_mask;
1780 }
1781 
1782 // Copied from sparc.
1783 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1784   return RegMask();
1785 }
1786 
1787 const bool Matcher::convi2l_type_required = true;
1788 
1789 // Should the Matcher clone shifts on addressing modes, expecting them
1790 // to be subsumed into complex addressing expressions or compute them
1791 // into registers?
1792 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
1793   return clone_base_plus_offset_address(m, mstack, address_visited);
1794 }
1795 
1796 void Compile::reshape_address(AddPNode* addp) {
1797 }
1798 
1799 %} // source
1800 
1801 //----------ENCODING BLOCK-----------------------------------------------------
1802 // This block specifies the encoding classes used by the compiler to output
1803 // byte streams. Encoding classes are parameterized macros used by
1804 // Machine Instruction Nodes in order to generate the bit encoding of the
1805 // instruction. Operands specify their base encoding interface with the
1806 // interface keyword. There are currently supported four interfaces,
1807 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1808 // operand to generate a function which returns its register number when
1809 // queried. CONST_INTER causes an operand to generate a function which
1810 // returns the value of the constant when queried. MEMORY_INTER causes an
1811 // operand to generate four functions which return the Base Register, the
1812 // Index Register, the Scale Value, and the Offset Value of the operand when
1813 // queried. COND_INTER causes an operand to generate six functions which
1814 // return the encoding code (ie - encoding bits for the instruction)
1815 // associated with each basic boolean condition for a conditional instruction.
1816 //
1817 // Instructions specify two basic values for encoding. Again, a function
1818 // is available to check if the constant displacement is an oop. They use the
1819 // ins_encode keyword to specify their encoding classes (which must be
1820 // a sequence of enc_class names, and their parameters, specified in
1821 // the encoding block), and they use the
1822 // opcode keyword to specify, in order, their primary, secondary, and
1823 // tertiary opcode. Only the opcode sections which a particular instruction
1824 // needs for encoding need to be specified.
1825 encode %{
1826   enc_class enc_unimplemented %{
1827     MacroAssembler _masm(&cbuf);
1828     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
1829   %}
1830 
1831   enc_class enc_untested %{
1832 #ifdef ASSERT
1833     MacroAssembler _masm(&cbuf);
1834     __ untested("Untested mach node encoding in AD file.");
1835 #endif
1836   %}
1837 
1838   enc_class z_rrform(iRegI dst, iRegI src) %{
1839     assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
1840     assert( ($primary >> 16)         == 0, "Instruction format error");
1841     z_emit16(cbuf, $primary |
1842              Assembler::reg($dst$$reg,8,16) |
1843              Assembler::reg($src$$reg,12,16));
1844   %}
1845 
1846   enc_class z_rreform(iRegI dst1, iRegI src2) %{
1847     assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
1848     z_emit32(cbuf, $primary |
1849              Assembler::reg($dst1$$reg,24,32) |
1850              Assembler::reg($src2$$reg,28,32));
1851   %}
1852 
1853   enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
1854     assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
1855     z_emit32(cbuf, $primary |
1856              Assembler::reg($dst1$$reg,24,32) |
1857              Assembler::reg($src2$$reg,28,32) |
1858              Assembler::reg($src3$$reg,16,32));
1859   %}
1860 
1861   enc_class z_riform_signed(iRegI dst, immI16 src) %{
1862     assert((($primary>>30) & 0x03) == 2, "Instruction format error");
1863     z_emit32(cbuf, $primary |
1864              Assembler::reg($dst$$reg,8,32) |
1865              Assembler::simm16($src$$constant,16,32));
1866   %}
1867 
1868   enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
1869     assert((($primary>>30) & 0x03) == 2, "Instruction format error");
1870     z_emit32(cbuf, $primary |
1871              Assembler::reg($dst$$reg,8,32) |
1872              Assembler::uimm16($src$$constant,16,32));
1873   %}
1874 
1875   enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
1876     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1877     z_emit48(cbuf, $primary |
1878              Assembler::reg($dst1$$reg,8,48) |
1879              Assembler::reg($src3$$reg,12,48) |
1880              Assembler::simm16($src2$$constant,16,48));
1881   %}
1882 
1883   enc_class z_rilform_signed(iRegI dst, immL32 src) %{
1884     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1885     z_emit48(cbuf, $primary |
1886              Assembler::reg($dst$$reg,8,48) |
1887              Assembler::simm32($src$$constant,16,48));
1888   %}
1889 
1890   enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
1891     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
1892     z_emit48(cbuf, $primary |
1893              Assembler::reg($dst$$reg,8,48) |
1894              Assembler::uimm32($src$$constant,16,48));
1895   %}
1896 
1897   enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
1898     z_emit48(cbuf, $primary |
1899              Assembler::reg($dst$$reg,8,48) |
1900              Assembler::reg($src1$$reg,12,48) |
1901              Assembler::simm20($src2$$constant));
1902   %}
1903 
1904   enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
1905     z_emit48(cbuf, $primary |
1906              Assembler::reg($dst$$reg,8,48) |
1907              Assembler::reg($src$$reg,12,48) |
1908              Assembler::reg($shft$$reg,16,48) |
1909              Assembler::simm20(0));
1910   %}
1911 
1912   enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
1913     assert((($primary>>30) & 0x03) == 1, "Instruction format error");
1914     z_emit32(cbuf, $primary |
1915              Assembler::reg($dst$$reg,8,32) |
1916              Assembler::reg($src1$$reg,12,32) |
1917              Assembler::reg($src2$$reg,16,32) |
1918              Assembler::uimm12($con$$constant,20,32));
1919   %}
1920 
1921   enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
1922     assert((($primary>>30) & 0x03) == 1, "Instruction format error");
1923     z_emit32(cbuf, $primary |
1924              Assembler::reg($dst$$reg,8,32) |
1925              Assembler::reg($src$$reg,16,32) |
1926              Assembler::uimm12($con$$constant,20,32));
1927   %}
1928 
1929   enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
1930     z_emit48(cbuf, $primary |
1931              Assembler::reg($dst$$reg,8,48) |
1932              Assembler::reg($src1$$reg,12,48) |
1933              Assembler::reg($src2$$reg,16,48) |
1934              Assembler::simm20($con$$constant));
1935   %}
1936 
1937   enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
1938     z_emit48(cbuf, $primary |
1939              Assembler::reg($dst$$reg,8,48) |
1940              Assembler::reg($src$$reg,16,48) |
1941              Assembler::simm20($con$$constant));
1942   %}
1943 
1944   // Direct memory arithmetic.
1945   enc_class z_siyform(memoryRSY mem, immI8 src) %{
1946     int      disp = $mem$$disp;
1947     Register base = reg_to_register_object($mem$$base);
1948     int      con  = $src$$constant;
1949 
1950     assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
1951     z_emit_inst(cbuf, $primary |
1952                 Assembler::regz(base,16,48) |
1953                 Assembler::simm20(disp) |
1954                 Assembler::simm8(con,8,48));
1955   %}
1956 
1957   enc_class z_silform(memoryRS mem, immI16 src) %{
1958     z_emit_inst(cbuf, $primary |
1959                 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
1960                 Assembler::uimm12($mem$$disp,20,48) |
1961                 Assembler::simm16($src$$constant,32,48));
1962   %}
1963 
1964   // Encoder for FP ALU reg/mem instructions (support only short displacements).
1965   enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
1966     Register Ridx = $mem$$index$$Register;
1967     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1968     if ($primary > (1L << 32)) {
1969       z_emit_inst(cbuf, $primary |
1970                   Assembler::reg($dst$$reg, 8, 48) |
1971                   Assembler::uimm12($mem$$disp, 20, 48) |
1972                   Assembler::reg(Ridx, 12, 48) |
1973                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1974     } else {
1975       z_emit_inst(cbuf, $primary |
1976                   Assembler::reg($dst$$reg, 8, 32) |
1977                   Assembler::uimm12($mem$$disp, 20, 32) |
1978                   Assembler::reg(Ridx, 12, 32) |
1979                   Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
1980     }
1981   %}
1982 
1983   enc_class z_form_rt_mem(iRegI dst, memory mem) %{
1984     Register Ridx = $mem$$index$$Register;
1985     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
1986     if ($primary > (1L<<32)) {
1987       z_emit_inst(cbuf, $primary |
1988                   Assembler::reg($dst$$reg, 8, 48) |
1989                   Assembler::simm20($mem$$disp) |
1990                   Assembler::reg(Ridx, 12, 48) |
1991                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
1992     } else {
1993       z_emit_inst(cbuf, $primary |
1994                   Assembler::reg($dst$$reg, 8, 32) |
1995                   Assembler::uimm12($mem$$disp, 20, 32) |
1996                   Assembler::reg(Ridx, 12, 32) |
1997                   Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
1998     }
1999   %}
2000 
2001   enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
2002     int isize = $secondary > 1L << 32 ? 48 : 32;
2003     Register Ridx = $mem$$index$$Register;
2004     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
2005 
2006     if (Displacement::is_shortDisp((long)$mem$$disp)) {
2007       z_emit_inst(cbuf, $secondary |
2008                   Assembler::reg($dst$$reg, 8, isize) |
2009                   Assembler::uimm12($mem$$disp, 20, isize) |
2010                   Assembler::reg(Ridx, 12, isize) |
2011                   Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2012     } else if (Displacement::is_validDisp((long)$mem$$disp)) {
2013       z_emit_inst(cbuf, $primary |
2014                   Assembler::reg($dst$$reg, 8, 48) |
2015                   Assembler::simm20($mem$$disp) |
2016                   Assembler::reg(Ridx, 12, 48) |
2017                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
2018     } else {
2019         MacroAssembler _masm(&cbuf);
2020         __ load_const_optimized(Z_R1_scratch, $mem$$disp);
2021         if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
2022         z_emit_inst(cbuf, $secondary |
2023                     Assembler::reg($dst$$reg, 8, isize) |
2024                     Assembler::uimm12(0, 20, isize) |
2025                     Assembler::reg(Z_R1_scratch, 12, isize) |
2026                     Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
2027     }
2028   %}
2029 
2030   enc_class z_enc_brul(Label lbl) %{
2031     MacroAssembler _masm(&cbuf);
2032     Label* p = $lbl$$label;
2033 
2034     // 'p' is `NULL' when this encoding class is used only to
2035     // determine the size of the encoded instruction.
2036     // Use a bound dummy label in that case.
2037     Label d;
2038     __ bind(d);
2039     Label& l = (NULL == p) ? d : *(p);
2040     __ z_brul(l);
2041   %}
2042 
2043   enc_class z_enc_bru(Label lbl) %{
2044     MacroAssembler _masm(&cbuf);
2045     Label* p = $lbl$$label;
2046 
2047     // 'p' is `NULL' when this encoding class is used only to
2048     // determine the size of the encoded instruction.
2049     // Use a bound dummy label in that case.
2050     Label d;
2051     __ bind(d);
2052     Label& l = (NULL == p) ? d : *(p);
2053     __ z_bru(l);
2054   %}
2055 
2056   enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
2057     MacroAssembler _masm(&cbuf);
2058     Label* p = $lbl$$label;
2059 
2060     // 'p' is `NULL' when this encoding class is used only to
2061     // determine the size of the encoded instruction.
2062     // Use a bound dummy label in that case.
2063     Label d;
2064     __ bind(d);
2065     Label& l = (NULL == p) ? d : *(p);
2066     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2067   %}
2068 
2069   enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
2070     MacroAssembler _masm(&cbuf);
2071     Label* p = $lbl$$label;
2072 
2073     // 'p' is `NULL' when this encoding class is used only to
2074     // determine the size of the encoded instruction.
2075     // Use a bound dummy label in that case.
2076     Label d;
2077     __ bind(d);
2078     Label& l = (NULL == p) ? d : *(p);
2079     __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
2080   %}
2081 
2082   enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2083     MacroAssembler _masm(&cbuf);
2084     Label* p = $lbl$$label;
2085 
2086     // 'p' is `NULL' when this encoding class is used only to
2087     // determine the size of the encoded instruction.
2088     // Use a bound dummy label in that case.
2089     Label d;
2090     __ bind(d);
2091     Label& l = (NULL == p) ? d : *(p);
2092     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2093     unsigned long instr = $primary;
2094     if (instr == CRJ_ZOPC) {
2095       __ z_crj($src1$$Register, $src2$$Register, cc, l);
2096     } else if (instr == CLRJ_ZOPC) {
2097       __ z_clrj($src1$$Register, $src2$$Register, cc, l);
2098     } else if (instr == CGRJ_ZOPC) {
2099       __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
2100     } else {
2101       guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
2102       __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
2103     }
2104   %}
2105 
2106   enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
2107     MacroAssembler _masm(&cbuf);
2108     Label* p = $lbl$$label;
2109 
2110     // 'p' is `NULL' when this encoding class is used only to
2111     // determine the size of the encoded instruction.
2112     // Use a bound dummy label in that case.
2113     Label d;
2114     __ bind(d);
2115     Label& l = (NULL == p) ? d : *(p);
2116 
2117     unsigned long instr = $primary;
2118     if (instr == CR_ZOPC) {
2119       __ z_cr($src1$$Register, $src2$$Register);
2120     } else if (instr == CLR_ZOPC) {
2121       __ z_clr($src1$$Register, $src2$$Register);
2122     } else if (instr == CGR_ZOPC) {
2123       __ z_cgr($src1$$Register, $src2$$Register);
2124     } else {
2125       guarantee(instr == CLGR_ZOPC, "opcode not implemented");
2126       __ z_clgr($src1$$Register, $src2$$Register);
2127     }
2128 
2129     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2130   %}
2131 
2132   enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2133     MacroAssembler _masm(&cbuf);
2134     Label* p = $lbl$$label;
2135 
2136     // 'p' is `NULL' when this encoding class is used only to
2137     // determine the size of the encoded instruction.
2138     // Use a bound dummy label in that case.
2139     Label d;
2140     __ bind(d);
2141     Label& l = (NULL == p) ? d : *(p);
2142 
2143     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2144     unsigned long instr = $primary;
2145     if (instr == CIJ_ZOPC) {
2146       __ z_cij($src1$$Register, $src2$$constant, cc, l);
2147     } else if (instr == CLIJ_ZOPC) {
2148       __ z_clij($src1$$Register, $src2$$constant, cc, l);
2149     } else if (instr == CGIJ_ZOPC) {
2150       __ z_cgij($src1$$Register, $src2$$constant, cc, l);
2151     } else {
2152       guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
2153       __ z_clgij($src1$$Register, $src2$$constant, cc, l);
2154     }
2155   %}
2156 
2157   enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
2158     MacroAssembler _masm(&cbuf);
2159     Label* p = $lbl$$label;
2160 
2161     // 'p' is `NULL' when this encoding class is used only to
2162     // determine the size of the encoded instruction.
2163     // Use a bound dummy label in that case.
2164     Label d;
2165     __ bind(d);
2166     Label& l = (NULL == p) ? d : *(p);
2167 
2168     unsigned long instr = $primary;
2169     if (instr == CHI_ZOPC) {
2170       __ z_chi($src1$$Register, $src2$$constant);
2171     } else if (instr == CLFI_ZOPC) {
2172       __ z_clfi($src1$$Register, $src2$$constant);
2173     } else if (instr == CGHI_ZOPC) {
2174       __ z_cghi($src1$$Register, $src2$$constant);
2175     } else {
2176       guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
2177       __ z_clgfi($src1$$Register, $src2$$constant);
2178     }
2179 
2180     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
2181   %}
2182 
2183   // Call from Java to runtime.
2184   enc_class z_enc_java_to_runtime_call(method meth) %{
2185     MacroAssembler _masm(&cbuf);
2186 
2187     // Save return pc before call to the place where we need it, since
2188     // callee doesn't.
2189     unsigned int start_off = __ offset();
2190     // Compute size of "larl + stg + call_c_opt".
2191     const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size();
2192     __ get_PC(Z_R14, size_of_code);
2193     __ save_return_pc();
2194     assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
2195 
2196     assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
2197     address call_addr = __ call_c_opt((address)$meth$$method);
2198     if (call_addr == NULL) {
2199       Compile::current()->env()->record_out_of_memory_failure();
2200       return;
2201     }
2202 
2203 #ifdef ASSERT
2204     // Plausibility check for size_of_code assumptions.
2205     unsigned int actual_ret_off = __ offset();
2206     assert(start_off + size_of_code == actual_ret_off, "wrong return_pc");
2207 #endif
2208   %}
2209 
2210   enc_class z_enc_java_static_call(method meth) %{
2211     // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
2212     // whom we intended to call.
2213     MacroAssembler _masm(&cbuf);
2214     int ret_offset = 0;
2215 
2216     if (!_method) {
2217       ret_offset = emit_call_reloc(_masm, $meth$$method,
2218                                    relocInfo::runtime_call_w_cp_type, ra_);
2219     } else {
2220       int method_index = resolved_method_index(cbuf);
2221       if (_optimized_virtual) {
2222         ret_offset = emit_call_reloc(_masm, $meth$$method,
2223                                      opt_virtual_call_Relocation::spec(method_index));
2224       } else {
2225         ret_offset = emit_call_reloc(_masm, $meth$$method,
2226                                      static_call_Relocation::spec(method_index));
2227       }
2228     }
2229     assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()");
2230 
2231     if (_method) { // Emit stub for static call.
2232       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2233       if (stub == NULL) {
2234         ciEnv::current()->record_failure("CodeCache is full");
2235         return;
2236       }
2237     }
2238   %}
2239 
2240   // Java dynamic call
2241   enc_class z_enc_java_dynamic_call(method meth) %{
2242     MacroAssembler _masm(&cbuf);
2243     unsigned int start_off = __ offset();
2244 
2245     int vtable_index = this->_vtable_index;
2246     if (vtable_index == -4) {
2247       Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2248       address virtual_call_oop_addr = NULL;
2249 
2250       AddressLiteral empty_ic((address) Universe::non_oop_word());
2251       virtual_call_oop_addr = __ pc();
2252       bool success = __ load_const_from_toc(ic_reg, empty_ic);
2253       if (!success) {
2254         Compile::current()->env()->record_out_of_memory_failure();
2255         return;
2256       }
2257 
2258       // Call to fixup routine. Fixup routine uses ScopeDesc info
2259       // to determine who we intended to call.
2260       int method_index = resolved_method_index(cbuf);
2261       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
2262       unsigned int ret_off = __ offset();
2263       assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
2264       ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_);
2265       assert(_method, "lazy_constant may be wrong when _method==null");
2266     } else {
2267       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2268       // Go through the vtable. Get receiver klass. Receiver already
2269       // checked for non-null. If we'll go thru a C2I adapter, the
2270       // interpreter expects method in Z_method.
2271       // Use Z_method to temporarily hold the klass oop.
2272       // Z_R1_scratch is destroyed.
2273       __ load_klass(Z_method, Z_R2);
2274 
2275       int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
2276       int v_off        = entry_offset + vtableEntry::method_offset_in_bytes();
2277 
2278       if (Displacement::is_validDisp(v_off) ) {
2279         // Can use load instruction with large offset.
2280         __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
2281       } else {
2282         // Worse case, must load offset into register.
2283         __ load_const(Z_R1_scratch, v_off);
2284         __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
2285       }
2286       // NOTE: for vtable dispatches, the vtable entry will never be
2287       // null. However it may very well end up in handle_wrong_method
2288       // if the method is abstract for the particular class.
2289       __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
2290       // Call target. Either compiled code or C2I adapter.
2291       __ z_basr(Z_R14, Z_R1_scratch);
2292       unsigned int ret_off = __ offset();
2293     }
2294   %}
2295 
2296   enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
2297     MacroAssembler _masm(&cbuf);
2298     Register Rdst = reg_to_register_object($dst$$reg);
2299     Register Rsrc = reg_to_register_object($src$$reg);
2300 
2301     // Don't emit code if operands are identical (same register).
2302     if (Rsrc != Rdst) {
2303       Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2304 
2305       if (VM_Version::has_LoadStoreConditional()) {
2306         __ z_locgr(Rdst, Rsrc, cc);
2307       } else {
2308         // Branch if not (cmp cr).
2309         Label done;
2310         __ z_brc(Assembler::inverse_condition(cc), done);
2311         __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
2312         __ bind(done);
2313       }
2314     }
2315   %}
2316 
2317   enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
2318     MacroAssembler _masm(&cbuf);
2319     Register Rdst = reg_to_register_object($dst$$reg);
2320     int      Csrc = $src$$constant;
2321     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
2322     Label done;
2323     // Branch if not (cmp cr).
2324     __ z_brc(Assembler::inverse_condition(cc), done);
2325     if (Csrc == 0) {
2326       // Don't set CC.
2327       __ clear_reg(Rdst, true, false);  // Use for int, long & ptr.
2328     } else {
2329       __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
2330     }
2331     __ bind(done);
2332   %}
2333 
2334   enc_class z_enc_cctobool(iRegI res) %{
2335     MacroAssembler _masm(&cbuf);
2336     Register Rres = reg_to_register_object($res$$reg);
2337 
2338     if (VM_Version::has_LoadStoreConditional()) {
2339       __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
2340       __ load_const_optimized(Rres, 1L);         // true  (succeed)
2341       __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
2342     } else {
2343       Label done;
2344       __ load_const_optimized(Rres, 0L); // false (failed)
2345       __ z_brne(done);                   // Assume true to be the common case.
2346       __ load_const_optimized(Rres, 1L); // true  (succeed)
2347       __ bind(done);
2348     }
2349   %}
2350 
2351   enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
2352     MacroAssembler _masm(&cbuf);
2353     Register Rcomp = reg_to_register_object($compare_value$$reg);
2354     Register Rnew  = reg_to_register_object($exchange_value$$reg);
2355     Register Raddr = reg_to_register_object($addr_ptr$$reg);
2356 
2357     __ z_cs(Rcomp, Rnew, 0, Raddr);
2358   %}
2359 
2360   enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
2361     MacroAssembler _masm(&cbuf);
2362     Register Rcomp = reg_to_register_object($compare_value$$reg);
2363     Register Rnew  = reg_to_register_object($exchange_value$$reg);
2364     Register Raddr = reg_to_register_object($addr_ptr$$reg);
2365 
2366     __ z_csg(Rcomp, Rnew, 0, Raddr);
2367   %}
2368 
2369   enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
2370     MacroAssembler _masm(&cbuf);
2371     Register Rdst = reg_to_register_object($dst$$reg);
2372     Register Rtmp = reg_to_register_object($tmp$$reg);
2373     guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2374     Label    retry;
2375 
2376     // Iterate until swap succeeds.
2377     __ z_llgf(Rtmp, $mem$$Address);  // current contents
2378     __ bind(retry);
2379       // Calculate incremented value.
2380       __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2381       __ z_brne(retry);                    // Yikes, concurrent update, need to retry.
2382     __ z_lgr(Rdst, Rtmp);                  // Exchanged value from memory is return value.
2383   %}
2384 
2385   enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
2386     MacroAssembler _masm(&cbuf);
2387     Register Rdst = reg_to_register_object($dst$$reg);
2388     Register Rtmp = reg_to_register_object($tmp$$reg);
2389     guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
2390     Label    retry;
2391 
2392     // Iterate until swap succeeds.
2393     __ z_lg(Rtmp, $mem$$Address);  // current contents
2394     __ bind(retry);
2395       // Calculate incremented value.
2396       __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
2397       __ z_brne(retry);                    // Yikes, concurrent update, need to retry.
2398     __ z_lgr(Rdst, Rtmp);                  // Exchanged value from memory is return value.
2399   %}
2400 
2401 %} // encode
2402 
2403 source %{
2404 
2405   // Check whether outs are all Stores. If so, we can omit clearing the upper
2406   // 32 bits after encoding.
2407   static bool all_outs_are_Stores(const Node *n) {
2408     for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
2409       Node *out = n->fast_out(k);
2410       if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
2411         // Most other outs are SpillCopy, but there are various other.
2412         // jvm98 has arond 9% Encodes where we return false.
2413         return false;
2414       }
2415     }
2416     return true;
2417   }
2418 
2419 %} // source
2420 
2421 
2422 //----------FRAME--------------------------------------------------------------
2423 // Definition of frame structure and management information.
2424 
2425 frame %{
2426   // What direction does stack grow in (assumed to be same for native & Java).
2427   stack_direction(TOWARDS_LOW);
2428 
2429   // These two registers define part of the calling convention between
2430   // compiled code and the interpreter.
2431 
2432   // Inline Cache Register
2433   inline_cache_reg(Z_R9); // Z_inline_cache
2434 
2435   // Argument pointer for I2C adapters
2436   //
2437   // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
2438   // interpreter_arg_ptr_reg(Z_R6);
2439 
2440   // Temporary in compiled entry-points
2441   // compiler_method_oop_reg(Z_R1);//Z_R1_scratch
2442 
2443   // Method Oop Register when calling interpreter
2444   interpreter_method_oop_reg(Z_R9);//Z_method
2445 
2446   // Optional: name the operand used by cisc-spilling to access
2447   // [stack_pointer + offset].
2448   cisc_spilling_operand_name(indOffset12);
2449 
2450   // Number of stack slots consumed by a Monitor enter.
2451   sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
2452 
2453   // Compiled code's Frame Pointer
2454   //
2455   // z/Architecture stack pointer
2456   frame_pointer(Z_R15); // Z_SP
2457 
2458   // Interpreter stores its frame pointer in a register which is
2459   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
2460   // interpreted java to compiled java.
2461   //
2462   // Z_state holds pointer to caller's cInterpreter.
2463   interpreter_frame_pointer(Z_R7); // Z_state
2464 
2465   // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
2466   stack_alignment(frame::alignment_in_bytes);
2467 
2468   in_preserve_stack_slots(frame::jit_in_preserve_size_in_4_byte_units);
2469 
2470   // A `slot' is assumed 4 bytes here!
2471   // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
2472 
2473   // Number of outgoing stack slots killed above the
2474   // out_preserve_stack_slots for calls to C. Supports the var-args
2475   // backing area for register parms.
2476   varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
2477 
2478   // The after-PROLOG location of the return address. Location of
2479   // return address specifies a type (REG or STACK) and a number
2480   // representing the register number (i.e. - use a register name) or
2481   // stack slot.
2482   return_addr(REG Z_R14);
2483 
2484   // This is the body of the function
2485   //
2486   // void Matcher::calling_convention(OptoRegPair* sig /* array of ideal regs */,
2487   //                                  uint length      /* length of array */,
2488   //                                  bool is_outgoing)
2489   //
2490   // The `sig' array is to be updated. Sig[j] represents the location
2491   // of the j-th argument, either a register or a stack slot.
2492 
2493   // Body of function which returns an integer array locating
2494   // arguments either in registers or in stack slots. Passed an array
2495   // of ideal registers called "sig" and a "length" count. Stack-slot
2496   // offsets are based on outgoing arguments, i.e. a CALLER setting up
2497   // arguments for a CALLEE. Incoming stack arguments are
2498   // automatically biased by the preserve_stack_slots field above.
2499   calling_convention %{
2500     // No difference between ingoing/outgoing just pass false.
2501     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2502   %}
2503 
2504   // Body of function which returns an integer array locating
2505   // arguments either in registers or in stack slots. Passed an array
2506   // of ideal registers called "sig" and a "length" count. Stack-slot
2507   // offsets are based on outgoing arguments, i.e. a CALLER setting up
2508   // arguments for a CALLEE. Incoming stack arguments are
2509   // automatically biased by the preserve_stack_slots field above.
2510   c_calling_convention %{
2511     // This is obviously always outgoing.
2512     // C argument must be in register AND stack slot.
2513     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2514   %}
2515 
2516   // Location of native (C/C++) and interpreter return values. This
2517   // is specified to be the same as Java. In the 32-bit VM, long
2518   // values are actually returned from native calls in O0:O1 and
2519   // returned to the interpreter in I0:I1. The copying to and from
2520   // the register pairs is done by the appropriate call and epilog
2521   // opcodes. This simplifies the register allocator.
2522   //
2523   // Use register pair for c return value.
2524   c_return_value %{
2525     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2526     static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2527     static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2528     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2529   %}
2530 
2531   // Use register pair for return value.
2532   // Location of compiled Java return values. Same as C
2533   return_value %{
2534     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
2535     static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
2536     static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
2537     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
2538   %}
2539 %}
2540 
2541 
2542 //----------ATTRIBUTES---------------------------------------------------------
2543 
2544 //----------Operand Attributes-------------------------------------------------
2545 op_attrib op_cost(1);          // Required cost attribute
2546 
2547 //----------Instruction Attributes---------------------------------------------
2548 
2549 // Cost attribute. required.
2550 ins_attrib ins_cost(DEFAULT_COST);
2551 
2552 // Is this instruction a non-matching short branch variant of some
2553 // long branch? Not required.
2554 ins_attrib ins_short_branch(0);
2555 
2556 // Indicates this is a trap based check node and final control-flow fixup
2557 // must generate a proper fall through.
2558 ins_attrib ins_is_TrapBasedCheckNode(true);
2559 
2560 // Attribute of instruction to tell how many constants the instruction will generate.
2561 // (optional attribute). Default: 0.
2562 ins_attrib ins_num_consts(0);
2563 
2564 // Required alignment attribute (must be a power of 2)
2565 // specifies the alignment that some part of the instruction (not
2566 // necessarily the start) requires. If > 1, a compute_padding()
2567 // function must be provided for the instruction.
2568 //
2569 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
2570 // instructions which depend on the proper alignment, because the
2571 // desired alignment isn't guaranteed for the call to "emit()" during
2572 // the size computation.
2573 ins_attrib ins_alignment(1);
2574 
2575 // Enforce/prohibit rematerializations.
2576 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
2577 //   then rematerialization of that instruction is prohibited and the
2578 //   instruction's value will be spilled if necessary.
2579 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
2580 //   then rematerialization is enforced and the instruction's value will
2581 //   never get spilled. a copy of the instruction will be inserted if
2582 //   necessary.
2583 //   Note: this may result in rematerializations in front of every use.
2584 // (optional attribute)
2585 ins_attrib ins_cannot_rematerialize(false);
2586 ins_attrib ins_should_rematerialize(false);
2587 
2588 //----------OPERANDS-----------------------------------------------------------
2589 // Operand definitions must precede instruction definitions for correct
2590 // parsing in the ADLC because operands constitute user defined types
2591 // which are used in instruction definitions.
2592 
2593 //----------Simple Operands----------------------------------------------------
2594 // Immediate Operands
2595 // Please note:
2596 // Formats are generated automatically for constants and base registers.
2597 
2598 //----------------------------------------------
2599 // SIGNED (shorter than INT) immediate operands
2600 //----------------------------------------------
2601 
2602 // Byte Immediate: constant 'int -1'
2603 operand immB_minus1() %{
2604   //         sign-ext constant      zero-ext constant
2605   predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
2606   match(ConI);
2607   op_cost(1);
2608   format %{ %}
2609   interface(CONST_INTER);
2610 %}
2611 
2612 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
2613 operand immB_n0m1() %{
2614   //                             sign-ext constant     zero-ext constant
2615   predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
2616   match(ConI);
2617   op_cost(1);
2618   format %{ %}
2619   interface(CONST_INTER);
2620 %}
2621 
2622 // Short Immediate: constant 'int -1'
2623 operand immS_minus1() %{
2624   //         sign-ext constant      zero-ext constant
2625   predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
2626   match(ConI);
2627   op_cost(1);
2628   format %{ %}
2629   interface(CONST_INTER);
2630 %}
2631 
2632 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
2633 operand immS_n0m1() %{
2634   //                             sign-ext constant     zero-ext constant
2635   predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
2636   match(ConI);
2637   op_cost(1);
2638   format %{ %}
2639   interface(CONST_INTER);
2640 %}
2641 
2642 //-----------------------------------------
2643 //  SIGNED INT immediate operands
2644 //-----------------------------------------
2645 
2646 // Integer Immediate: 32-bit
2647 operand immI() %{
2648   match(ConI);
2649   op_cost(1);
2650   format %{ %}
2651   interface(CONST_INTER);
2652 %}
2653 
2654 // Int Immediate: 20-bit
2655 operand immI20() %{
2656   predicate(Immediate::is_simm20(n->get_int()));
2657   match(ConI);
2658   op_cost(1);
2659   format %{ %}
2660   interface(CONST_INTER);
2661 %}
2662 
2663 // Integer Immediate: 16-bit
2664 operand immI16() %{
2665   predicate(Immediate::is_simm16(n->get_int()));
2666   match(ConI);
2667   op_cost(1);
2668   format %{ %}
2669   interface(CONST_INTER);
2670 %}
2671 
2672 // Integer Immediate: 8-bit
2673 operand immI8() %{
2674   predicate(Immediate::is_simm8(n->get_int()));
2675   match(ConI);
2676   op_cost(1);
2677   format %{ %}
2678   interface(CONST_INTER);
2679 %}
2680 
2681 // Integer Immediate: constant 'int 0'
2682 operand immI_0() %{
2683   predicate(n->get_int() == 0);
2684   match(ConI);
2685   op_cost(1);
2686   format %{ %}
2687   interface(CONST_INTER);
2688 %}
2689 
2690 // Integer Immediate: constant 'int -1'
2691 operand immI_minus1() %{
2692   predicate(n->get_int() == -1);
2693   match(ConI);
2694   op_cost(1);
2695   format %{ %}
2696   interface(CONST_INTER);
2697 %}
2698 
2699 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
2700 operand immI_n0m1() %{
2701   predicate(n->get_int() != 0 && n->get_int() != -1);
2702   match(ConI);
2703   op_cost(1);
2704   format %{ %}
2705   interface(CONST_INTER);
2706 %}
2707 
2708 //-------------------------------------------
2709 // UNSIGNED INT immediate operands
2710 //-------------------------------------------
2711 
2712 // Unsigned Integer Immediate: 32-bit
2713 operand uimmI() %{
2714   match(ConI);
2715   op_cost(1);
2716   format %{ %}
2717   interface(CONST_INTER);
2718 %}
2719 
2720 // Unsigned Integer Immediate: 16-bit
2721 operand uimmI16() %{
2722   predicate(Immediate::is_uimm16(n->get_int()));
2723   match(ConI);
2724   op_cost(1);
2725   format %{ %}
2726   interface(CONST_INTER);
2727 %}
2728 
2729 // Unsigned Integer Immediate: 12-bit
2730 operand uimmI12() %{
2731   predicate(Immediate::is_uimm12(n->get_int()));
2732   match(ConI);
2733   op_cost(1);
2734   format %{ %}
2735   interface(CONST_INTER);
2736 %}
2737 
2738 // Unsigned Integer Immediate: 12-bit
2739 operand uimmI8() %{
2740   predicate(Immediate::is_uimm8(n->get_int()));
2741   match(ConI);
2742   op_cost(1);
2743   format %{ %}
2744   interface(CONST_INTER);
2745 %}
2746 
2747 // Integer Immediate: 6-bit
2748 operand uimmI6() %{
2749   predicate(Immediate::is_uimm(n->get_int(), 6));
2750   match(ConI);
2751   op_cost(1);
2752   format %{ %}
2753   interface(CONST_INTER);
2754 %}
2755 
2756 // Integer Immediate: 5-bit
2757 operand uimmI5() %{
2758   predicate(Immediate::is_uimm(n->get_int(), 5));
2759   match(ConI);
2760   op_cost(1);
2761   format %{ %}
2762   interface(CONST_INTER);
2763 %}
2764 
2765 // Length for SS instructions, given in DWs,
2766 //   possible range [1..512], i.e. [8..4096] Bytes
2767 //   used     range [1..256], i.e. [8..2048] Bytes
2768 //   operand type int
2769 // Unsigned Integer Immediate: 9-bit
2770 operand SSlenDW() %{
2771   predicate(Immediate::is_uimm8(n->get_long()-1));
2772   match(ConL);
2773   op_cost(1);
2774   format %{ %}
2775   interface(CONST_INTER);
2776 %}
2777 
2778 //------------------------------------------
2779 // (UN)SIGNED INT specific values
2780 //------------------------------------------
2781 
2782 // Integer Immediate: the value 1
2783 operand immI_1() %{
2784   predicate(n->get_int() == 1);
2785   match(ConI);
2786   op_cost(1);
2787   format %{ %}
2788   interface(CONST_INTER);
2789 %}
2790 
2791 // Integer Immediate: the value 16.
2792 operand immI_16() %{
2793   predicate(n->get_int() == 16);
2794   match(ConI);
2795   op_cost(1);
2796   format %{ %}
2797   interface(CONST_INTER);
2798 %}
2799 
2800 // Integer Immediate: the value 24.
2801 operand immI_24() %{
2802   predicate(n->get_int() == 24);
2803   match(ConI);
2804   op_cost(1);
2805   format %{ %}
2806   interface(CONST_INTER);
2807 %}
2808 
2809 // Integer Immediate: the value 255
2810 operand immI_255() %{
2811   predicate(n->get_int() == 255);
2812   match(ConI);
2813   op_cost(1);
2814   format %{ %}
2815   interface(CONST_INTER);
2816 %}
2817 
2818 // Integer Immediate: the values 32-63
2819 operand immI_32_63() %{
2820   predicate(n->get_int() >= 32 && n->get_int() <= 63);
2821   match(ConI);
2822   op_cost(1);
2823   format %{ %}
2824   interface(CONST_INTER);
2825 %}
2826 
2827 // Unsigned Integer Immediate: LL-part, extended by 1s.
2828 operand uimmI_LL1() %{
2829   predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
2830   match(ConI);
2831   op_cost(1);
2832   format %{ %}
2833   interface(CONST_INTER);
2834 %}
2835 
2836 // Unsigned Integer Immediate: LH-part, extended by 1s.
2837 operand uimmI_LH1() %{
2838   predicate((n->get_int() & 0xFFFF) == 0xFFFF);
2839   match(ConI);
2840   op_cost(1);
2841   format %{ %}
2842   interface(CONST_INTER);
2843 %}
2844 
2845 //------------------------------------------
2846 // SIGNED LONG immediate operands
2847 //------------------------------------------
2848 
2849 operand immL() %{
2850   match(ConL);
2851   op_cost(1);
2852   format %{ %}
2853   interface(CONST_INTER);
2854 %}
2855 
2856 // Long Immediate: 32-bit
2857 operand immL32() %{
2858   predicate(Immediate::is_simm32(n->get_long()));
2859   match(ConL);
2860   op_cost(1);
2861   format %{ %}
2862   interface(CONST_INTER);
2863 %}
2864 
2865 // Long Immediate: 20-bit
2866 operand immL20() %{
2867   predicate(Immediate::is_simm20(n->get_long()));
2868   match(ConL);
2869   op_cost(1);
2870   format %{ %}
2871   interface(CONST_INTER);
2872 %}
2873 
2874 // Long Immediate: 16-bit
2875 operand immL16() %{
2876   predicate(Immediate::is_simm16(n->get_long()));
2877   match(ConL);
2878   op_cost(1);
2879   format %{ %}
2880   interface(CONST_INTER);
2881 %}
2882 
2883 // Long Immediate: 8-bit
2884 operand immL8() %{
2885   predicate(Immediate::is_simm8(n->get_long()));
2886   match(ConL);
2887   op_cost(1);
2888   format %{ %}
2889   interface(CONST_INTER);
2890 %}
2891 
2892 //--------------------------------------------
2893 // UNSIGNED LONG immediate operands
2894 //--------------------------------------------
2895 
2896 operand uimmL32() %{
2897   predicate(Immediate::is_uimm32(n->get_long()));
2898   match(ConL);
2899   op_cost(1);
2900   format %{ %}
2901   interface(CONST_INTER);
2902 %}
2903 
2904 // Unsigned Long Immediate: 16-bit
2905 operand uimmL16() %{
2906   predicate(Immediate::is_uimm16(n->get_long()));
2907   match(ConL);
2908   op_cost(1);
2909   format %{ %}
2910   interface(CONST_INTER);
2911 %}
2912 
2913 // Unsigned Long Immediate: 12-bit
2914 operand uimmL12() %{
2915   predicate(Immediate::is_uimm12(n->get_long()));
2916   match(ConL);
2917   op_cost(1);
2918   format %{ %}
2919   interface(CONST_INTER);
2920 %}
2921 
2922 // Unsigned Long Immediate: 8-bit
2923 operand uimmL8() %{
2924   predicate(Immediate::is_uimm8(n->get_long()));
2925   match(ConL);
2926   op_cost(1);
2927   format %{ %}
2928   interface(CONST_INTER);
2929 %}
2930 
2931 //-------------------------------------------
2932 // (UN)SIGNED LONG specific values
2933 //-------------------------------------------
2934 
2935 // Long Immediate: the value FF
2936 operand immL_FF() %{
2937   predicate(n->get_long() == 0xFFL);
2938   match(ConL);
2939   op_cost(1);
2940   format %{ %}
2941   interface(CONST_INTER);
2942 %}
2943 
2944 // Long Immediate: the value FFFF
2945 operand immL_FFFF() %{
2946   predicate(n->get_long() == 0xFFFFL);
2947   match(ConL);
2948   op_cost(1);
2949   format %{ %}
2950   interface(CONST_INTER);
2951 %}
2952 
2953 // Long Immediate: the value FFFFFFFF
2954 operand immL_FFFFFFFF() %{
2955   predicate(n->get_long() == 0xFFFFFFFFL);
2956   match(ConL);
2957   op_cost(1);
2958   format %{ %}
2959   interface(CONST_INTER);
2960 %}
2961 
2962 operand immL_0() %{
2963   predicate(n->get_long() == 0L);
2964   match(ConL);
2965   op_cost(1);
2966   format %{ %}
2967   interface(CONST_INTER);
2968 %}
2969 
2970 // Unsigned Long Immediate: LL-part, extended by 1s.
2971 operand uimmL_LL1() %{
2972   predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
2973   match(ConL);
2974   op_cost(1);
2975   format %{ %}
2976   interface(CONST_INTER);
2977 %}
2978 
2979 // Unsigned Long Immediate: LH-part, extended by 1s.
2980 operand uimmL_LH1() %{
2981   predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
2982   match(ConL);
2983   op_cost(1);
2984   format %{ %}
2985   interface(CONST_INTER);
2986 %}
2987 
2988 // Unsigned Long Immediate: HL-part, extended by 1s.
2989 operand uimmL_HL1() %{
2990   predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
2991   match(ConL);
2992   op_cost(1);
2993   format %{ %}
2994   interface(CONST_INTER);
2995 %}
2996 
2997 // Unsigned Long Immediate: HH-part, extended by 1s.
2998 operand uimmL_HH1() %{
2999   predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
3000   match(ConL);
3001   op_cost(1);
3002   format %{ %}
3003   interface(CONST_INTER);
3004 %}
3005 
3006 // Long Immediate: low 32-bit mask
3007 operand immL_32bits() %{
3008   predicate(n->get_long() == 0xFFFFFFFFL);
3009   match(ConL);
3010   op_cost(1);
3011   format %{ %}
3012   interface(CONST_INTER);
3013 %}
3014 
3015 //--------------------------------------
3016 //  POINTER immediate operands
3017 //--------------------------------------
3018 
3019 // Pointer Immediate: 64-bit
3020 operand immP() %{
3021   match(ConP);
3022   op_cost(1);
3023   format %{ %}
3024   interface(CONST_INTER);
3025 %}
3026 
3027 // Pointer Immediate: 32-bit
3028 operand immP32() %{
3029   predicate(Immediate::is_uimm32(n->get_ptr()));
3030   match(ConP);
3031   op_cost(1);
3032   format %{ %}
3033   interface(CONST_INTER);
3034 %}
3035 
3036 // Pointer Immediate: 16-bit
3037 operand immP16() %{
3038   predicate(Immediate::is_uimm16(n->get_ptr()));
3039   match(ConP);
3040   op_cost(1);
3041   format %{ %}
3042   interface(CONST_INTER);
3043 %}
3044 
3045 // Pointer Immediate: 8-bit
3046 operand immP8() %{
3047   predicate(Immediate::is_uimm8(n->get_ptr()));
3048   match(ConP);
3049   op_cost(1);
3050   format %{ %}
3051   interface(CONST_INTER);
3052 %}
3053 
3054 //-----------------------------------
3055 // POINTER specific values
3056 //-----------------------------------
3057 
3058 // Pointer Immediate: NULL
3059 operand immP0() %{
3060   predicate(n->get_ptr() == 0);
3061   match(ConP);
3062   op_cost(1);
3063   format %{ %}
3064   interface(CONST_INTER);
3065 %}
3066 
3067 //---------------------------------------------
3068 // NARROW POINTER immediate operands
3069 //---------------------------------------------
3070 
3071 // Narrow Pointer Immediate
3072 operand immN() %{
3073   match(ConN);
3074   op_cost(1);
3075   format %{ %}
3076   interface(CONST_INTER);
3077 %}
3078 
3079 operand immNKlass() %{
3080   match(ConNKlass);
3081   op_cost(1);
3082   format %{ %}
3083   interface(CONST_INTER);
3084 %}
3085 
3086 // Narrow Pointer Immediate
3087 operand immN8() %{
3088   predicate(Immediate::is_uimm8(n->get_narrowcon()));
3089   match(ConN);
3090   op_cost(1);
3091   format %{ %}
3092   interface(CONST_INTER);
3093 %}
3094 
3095 // Narrow NULL Pointer Immediate
3096 operand immN0() %{
3097   predicate(n->get_narrowcon() == 0);
3098   match(ConN);
3099   op_cost(1);
3100   format %{ %}
3101   interface(CONST_INTER);
3102 %}
3103 
3104 // FLOAT and DOUBLE immediate operands
3105 
3106 // Double Immediate
3107 operand immD() %{
3108   match(ConD);
3109   op_cost(1);
3110   format %{ %}
3111   interface(CONST_INTER);
3112 %}
3113 
3114 // Double Immediate: +-0
3115 operand immDpm0() %{
3116   predicate(n->getd() == 0);
3117   match(ConD);
3118   op_cost(1);
3119   format %{ %}
3120   interface(CONST_INTER);
3121 %}
3122 
3123 // Double Immediate: +0
3124 operand immDp0() %{
3125   predicate(jlong_cast(n->getd()) == 0);
3126   match(ConD);
3127   op_cost(1);
3128   format %{ %}
3129   interface(CONST_INTER);
3130 %}
3131 
3132 // Float Immediate
3133 operand immF() %{
3134   match(ConF);
3135   op_cost(1);
3136   format %{ %}
3137   interface(CONST_INTER);
3138 %}
3139 
3140 // Float Immediate: +-0
3141 operand immFpm0() %{
3142   predicate(n->getf() == 0);
3143   match(ConF);
3144   op_cost(1);
3145   format %{ %}
3146   interface(CONST_INTER);
3147 %}
3148 
3149 // Float Immediate: +0
3150 operand immFp0() %{
3151   predicate(jint_cast(n->getf()) == 0);
3152   match(ConF);
3153   op_cost(1);
3154   format %{ %}
3155   interface(CONST_INTER);
3156 %}
3157 
3158 // End of Immediate Operands
3159 
3160 // Integer Register Operands
3161 // Integer Register
3162 operand iRegI() %{
3163   constraint(ALLOC_IN_RC(z_int_reg));
3164   match(RegI);
3165   match(noArg_iRegI);
3166   match(rarg1RegI);
3167   match(rarg2RegI);
3168   match(rarg3RegI);
3169   match(rarg4RegI);
3170   match(rarg5RegI);
3171   match(noOdd_iRegI);
3172   match(revenRegI);
3173   match(roddRegI);
3174   format %{ %}
3175   interface(REG_INTER);
3176 %}
3177 
3178 operand noArg_iRegI() %{
3179   constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3180   match(RegI);
3181   format %{ %}
3182   interface(REG_INTER);
3183 %}
3184 
3185 // revenRegI and roddRegI constitute and even-odd-pair.
3186 operand revenRegI() %{
3187   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3188   match(iRegI);
3189   format %{ %}
3190   interface(REG_INTER);
3191 %}
3192 
3193 // revenRegI and roddRegI constitute and even-odd-pair.
3194 operand roddRegI() %{
3195   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3196   match(iRegI);
3197   format %{ %}
3198   interface(REG_INTER);
3199 %}
3200 
3201 operand rarg1RegI() %{
3202   constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3203   match(iRegI);
3204   format %{ %}
3205   interface(REG_INTER);
3206 %}
3207 
3208 operand rarg2RegI() %{
3209   constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3210   match(iRegI);
3211   format %{ %}
3212   interface(REG_INTER);
3213 %}
3214 
3215 operand rarg3RegI() %{
3216   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3217   match(iRegI);
3218   format %{ %}
3219   interface(REG_INTER);
3220 %}
3221 
3222 operand rarg4RegI() %{
3223   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3224   match(iRegI);
3225   format %{ %}
3226   interface(REG_INTER);
3227 %}
3228 
3229 operand rarg5RegI() %{
3230   constraint(ALLOC_IN_RC(z_rarg5_int_reg));
3231   match(iRegI);
3232   format %{ %}
3233   interface(REG_INTER);
3234 %}
3235 
3236 operand noOdd_iRegI() %{
3237   constraint(ALLOC_IN_RC(z_no_odd_int_reg));
3238   match(RegI);
3239   match(revenRegI);
3240   format %{ %}
3241   interface(REG_INTER);
3242 %}
3243 
3244 // Pointer Register
3245 operand iRegP() %{
3246   constraint(ALLOC_IN_RC(z_ptr_reg));
3247   match(RegP);
3248   match(noArg_iRegP);
3249   match(rarg1RegP);
3250   match(rarg2RegP);
3251   match(rarg3RegP);
3252   match(rarg4RegP);
3253   match(rarg5RegP);
3254   match(revenRegP);
3255   match(roddRegP);
3256   format %{ %}
3257   interface(REG_INTER);
3258 %}
3259 
3260 // thread operand
3261 operand threadRegP() %{
3262   constraint(ALLOC_IN_RC(z_thread_ptr_reg));
3263   match(RegP);
3264   format %{ "Z_THREAD" %}
3265   interface(REG_INTER);
3266 %}
3267 
3268 operand noArg_iRegP() %{
3269   constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
3270   match(iRegP);
3271   format %{ %}
3272   interface(REG_INTER);
3273 %}
3274 
3275 operand rarg1RegP() %{
3276   constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
3277   match(iRegP);
3278   format %{ %}
3279   interface(REG_INTER);
3280 %}
3281 
3282 operand rarg2RegP() %{
3283   constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
3284   match(iRegP);
3285   format %{ %}
3286   interface(REG_INTER);
3287 %}
3288 
3289 operand rarg3RegP() %{
3290   constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3291   match(iRegP);
3292   format %{ %}
3293   interface(REG_INTER);
3294 %}
3295 
3296 operand rarg4RegP() %{
3297   constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3298   match(iRegP);
3299   format %{ %}
3300   interface(REG_INTER);
3301 %}
3302 
3303 operand rarg5RegP() %{
3304   constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
3305   match(iRegP);
3306   format %{ %}
3307   interface(REG_INTER);
3308 %}
3309 
3310 operand memoryRegP() %{
3311   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3312   match(RegP);
3313   match(iRegP);
3314   match(threadRegP);
3315   format %{ %}
3316   interface(REG_INTER);
3317 %}
3318 
3319 // revenRegP and roddRegP constitute and even-odd-pair.
3320 operand revenRegP() %{
3321   constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
3322   match(iRegP);
3323   format %{ %}
3324   interface(REG_INTER);
3325 %}
3326 
3327 // revenRegP and roddRegP constitute and even-odd-pair.
3328 operand roddRegP() %{
3329   constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
3330   match(iRegP);
3331   format %{ %}
3332   interface(REG_INTER);
3333 %}
3334 
3335 operand lock_ptr_RegP() %{
3336   constraint(ALLOC_IN_RC(z_lock_ptr_reg));
3337   match(RegP);
3338   format %{ %}
3339   interface(REG_INTER);
3340 %}
3341 
3342 operand rscratch2RegP() %{
3343   constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg));
3344   match(RegP);
3345   format %{ %}
3346   interface(REG_INTER);
3347 %}
3348 
3349 operand iRegN() %{
3350   constraint(ALLOC_IN_RC(z_int_reg));
3351   match(RegN);
3352   match(noArg_iRegN);
3353   match(rarg1RegN);
3354   match(rarg2RegN);
3355   match(rarg3RegN);
3356   match(rarg4RegN);
3357   match(rarg5RegN);
3358   format %{ %}
3359   interface(REG_INTER);
3360 %}
3361 
3362 operand noArg_iRegN() %{
3363   constraint(ALLOC_IN_RC(z_no_arg_int_reg));
3364   match(iRegN);
3365   format %{ %}
3366   interface(REG_INTER);
3367 %}
3368 
3369 operand rarg1RegN() %{
3370   constraint(ALLOC_IN_RC(z_rarg1_int_reg));
3371   match(iRegN);
3372   format %{ %}
3373   interface(REG_INTER);
3374 %}
3375 
3376 operand rarg2RegN() %{
3377   constraint(ALLOC_IN_RC(z_rarg2_int_reg));
3378   match(iRegN);
3379   format %{ %}
3380   interface(REG_INTER);
3381 %}
3382 
3383 operand rarg3RegN() %{
3384   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
3385   match(iRegN);
3386   format %{ %}
3387   interface(REG_INTER);
3388 %}
3389 
3390 operand rarg4RegN() %{
3391   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
3392   match(iRegN);
3393   format %{ %}
3394   interface(REG_INTER);
3395 %}
3396 
3397 operand rarg5RegN() %{
3398   constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
3399   match(iRegN);
3400   format %{ %}
3401   interface(REG_INTER);
3402 %}
3403 
3404 // Long Register
3405 operand iRegL() %{
3406   constraint(ALLOC_IN_RC(z_long_reg));
3407   match(RegL);
3408   match(revenRegL);
3409   match(roddRegL);
3410   match(allRoddRegL);
3411   match(rarg1RegL);
3412   match(rarg5RegL);
3413   format %{ %}
3414   interface(REG_INTER);
3415 %}
3416 
3417 // revenRegL and roddRegL constitute and even-odd-pair.
3418 operand revenRegL() %{
3419   constraint(ALLOC_IN_RC(z_rarg3_long_reg));
3420   match(iRegL);
3421   format %{ %}
3422   interface(REG_INTER);
3423 %}
3424 
3425 // revenRegL and roddRegL constitute and even-odd-pair.
3426 operand roddRegL() %{
3427   constraint(ALLOC_IN_RC(z_rarg4_long_reg));
3428   match(iRegL);
3429   format %{ %}
3430   interface(REG_INTER);
3431 %}
3432 
3433 // available odd registers for iRegL
3434 operand allRoddRegL() %{
3435   constraint(ALLOC_IN_RC(z_long_odd_reg));
3436   match(iRegL);
3437   format %{ %}
3438   interface(REG_INTER);
3439 %}
3440 
3441 operand rarg1RegL() %{
3442   constraint(ALLOC_IN_RC(z_rarg1_long_reg));
3443   match(iRegL);
3444   format %{ %}
3445   interface(REG_INTER);
3446 %}
3447 
3448 operand rarg5RegL() %{
3449   constraint(ALLOC_IN_RC(z_rarg5_long_reg));
3450   match(iRegL);
3451   format %{ %}
3452   interface(REG_INTER);
3453 %}
3454 
3455 // Condition Code Flag Registers
3456 operand flagsReg() %{
3457   constraint(ALLOC_IN_RC(z_condition_reg));
3458   match(RegFlags);
3459   format %{ "CR" %}
3460   interface(REG_INTER);
3461 %}
3462 
3463 // Condition Code Flag Registers for rules with result tuples
3464 operand TD_flagsReg() %{
3465   constraint(ALLOC_IN_RC(z_condition_reg));
3466   match(RegFlags);
3467   format %{ "CR" %}
3468   interface(REG_TUPLE_DEST_INTER);
3469 %}
3470 
3471 operand regD() %{
3472   constraint(ALLOC_IN_RC(z_dbl_reg));
3473   match(RegD);
3474   format %{ %}
3475   interface(REG_INTER);
3476 %}
3477 
3478 operand rscratchRegD() %{
3479   constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg));
3480   match(RegD);
3481   format %{ %}
3482   interface(REG_INTER);
3483 %}
3484 
3485 operand regF() %{
3486   constraint(ALLOC_IN_RC(z_flt_reg));
3487   match(RegF);
3488   format %{ %}
3489   interface(REG_INTER);
3490 %}
3491 
3492 operand rscratchRegF() %{
3493   constraint(ALLOC_IN_RC(z_rscratch1_flt_reg));
3494   match(RegF);
3495   format %{ %}
3496   interface(REG_INTER);
3497 %}
3498 
3499 // Special Registers
3500 
3501 // Method Register
3502 operand inline_cache_regP(iRegP reg) %{
3503   constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
3504   match(reg);
3505   format %{ %}
3506   interface(REG_INTER);
3507 %}
3508 
3509 operand compiler_method_oop_regP(iRegP reg) %{
3510   constraint(ALLOC_IN_RC(z_r1_RegP)); // compiler_method_oop_reg
3511   match(reg);
3512   format %{ %}
3513   interface(REG_INTER);
3514 %}
3515 
3516 operand interpreter_method_oop_regP(iRegP reg) %{
3517   constraint(ALLOC_IN_RC(z_r9_regP)); // interpreter_method_oop_reg
3518   match(reg);
3519   format %{ %}
3520   interface(REG_INTER);
3521 %}
3522 
3523 // Operands to remove register moves in unscaled mode.
3524 // Match read/write registers with an EncodeP node if neither shift nor add are required.
3525 operand iRegP2N(iRegP reg) %{
3526   predicate(CompressedOops::shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL);
3527   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3528   match(EncodeP reg);
3529   format %{ "$reg" %}
3530   interface(REG_INTER)
3531 %}
3532 
3533 operand iRegN2P(iRegN reg) %{
3534   predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0 &&
3535             _leaf->as_DecodeN()->in(0) == NULL);
3536   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3537   match(DecodeN reg);
3538   format %{ "$reg" %}
3539   interface(REG_INTER)
3540 %}
3541 
3542 
3543 //----------Complex Operands---------------------------------------------------
3544 
3545 // Indirect Memory Reference
3546 operand indirect(memoryRegP base) %{
3547   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3548   match(base);
3549   op_cost(1);
3550   format %{ "#0[,$base]" %}
3551   interface(MEMORY_INTER) %{
3552     base($base);
3553     index(0xffffFFFF); // noreg
3554     scale(0x0);
3555     disp(0x0);
3556   %}
3557 %}
3558 
3559 // Indirect with Offset (long)
3560 operand indOffset20(memoryRegP base, immL20 offset) %{
3561   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3562   match(AddP base offset);
3563   op_cost(1);
3564   format %{ "$offset[,$base]" %}
3565   interface(MEMORY_INTER) %{
3566     base($base);
3567     index(0xffffFFFF); // noreg
3568     scale(0x0);
3569     disp($offset);
3570   %}
3571 %}
3572 
3573 operand indOffset20Narrow(iRegN base, immL20 offset) %{
3574   predicate(Matcher::narrow_oop_use_complex_address());
3575   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3576   match(AddP (DecodeN base) offset);
3577   op_cost(1);
3578   format %{ "$offset[,$base]" %}
3579   interface(MEMORY_INTER) %{
3580     base($base);
3581     index(0xffffFFFF); // noreg
3582     scale(0x0);
3583     disp($offset);
3584   %}
3585 %}
3586 
3587 // Indirect with Offset (short)
3588 operand indOffset12(memoryRegP base, uimmL12 offset) %{
3589   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3590   match(AddP base offset);
3591   op_cost(1);
3592   format %{ "$offset[[,$base]]" %}
3593   interface(MEMORY_INTER) %{
3594     base($base);
3595     index(0xffffFFFF); // noreg
3596     scale(0x0);
3597     disp($offset);
3598   %}
3599 %}
3600 
3601 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
3602   predicate(Matcher::narrow_oop_use_complex_address());
3603   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3604   match(AddP (DecodeN base) offset);
3605   op_cost(1);
3606   format %{ "$offset[[,$base]]" %}
3607   interface(MEMORY_INTER) %{
3608     base($base);
3609     index(0xffffFFFF); // noreg
3610     scale(0x0);
3611     disp($offset);
3612   %}
3613 %}
3614 
3615 // Indirect with Register Index
3616 operand indIndex(memoryRegP base, iRegL index) %{
3617   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3618   match(AddP base index);
3619   op_cost(1);
3620   format %{ "#0[($index,$base)]" %}
3621   interface(MEMORY_INTER) %{
3622     base($base);
3623     index($index);
3624     scale(0x0);
3625     disp(0x0);
3626   %}
3627 %}
3628 
3629 // Indirect with Offset (long) and index
3630 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
3631   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3632   match(AddP (AddP base index) offset);
3633   op_cost(1);
3634   format %{ "$offset[($index,$base)]" %}
3635   interface(MEMORY_INTER) %{
3636     base($base);
3637     index($index);
3638     scale(0x0);
3639     disp($offset);
3640   %}
3641 %}
3642 
3643 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
3644   predicate(Matcher::narrow_oop_use_complex_address());
3645   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3646   match(AddP (AddP (DecodeN base) index) offset);
3647   op_cost(1);
3648   format %{ "$offset[($index,$base)]" %}
3649   interface(MEMORY_INTER) %{
3650     base($base);
3651     index($index);
3652     scale(0x0);
3653     disp($offset);
3654   %}
3655 %}
3656 
3657 // Indirect with Offset (short) and index
3658 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
3659   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3660   match(AddP (AddP base index) offset);
3661   op_cost(1);
3662   format %{ "$offset[[($index,$base)]]" %}
3663   interface(MEMORY_INTER) %{
3664     base($base);
3665     index($index);
3666     scale(0x0);
3667     disp($offset);
3668   %}
3669 %}
3670 
3671 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
3672   predicate(Matcher::narrow_oop_use_complex_address());
3673   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
3674   match(AddP (AddP (DecodeN base) index) offset);
3675   op_cost(1);
3676   format %{ "$offset[[($index,$base)]]" %}
3677   interface(MEMORY_INTER) %{
3678     base($base);
3679     index($index);
3680     scale(0x0);
3681     disp($offset);
3682   %}
3683 %}
3684 
3685 //----------Special Memory Operands--------------------------------------------
3686 
3687 // Stack Slot Operand
3688 // This operand is used for loading and storing temporary values on
3689 // the stack where a match requires a value to flow through memory.
3690 operand stackSlotI(sRegI reg) %{
3691   constraint(ALLOC_IN_RC(stack_slots));
3692   op_cost(1);
3693   format %{ "[$reg(stackSlotI)]" %}
3694   interface(MEMORY_INTER) %{
3695     base(0xf);   // Z_SP
3696     index(0xffffFFFF); // noreg
3697     scale(0x0);
3698     disp($reg);  // stack offset
3699   %}
3700 %}
3701 
3702 operand stackSlotP(sRegP reg) %{
3703   constraint(ALLOC_IN_RC(stack_slots));
3704   op_cost(1);
3705   format %{ "[$reg(stackSlotP)]" %}
3706   interface(MEMORY_INTER) %{
3707     base(0xf);   // Z_SP
3708     index(0xffffFFFF); // noreg
3709     scale(0x0);
3710     disp($reg);  // Stack Offset
3711   %}
3712 %}
3713 
3714 operand stackSlotF(sRegF reg) %{
3715   constraint(ALLOC_IN_RC(stack_slots));
3716   op_cost(1);
3717   format %{ "[$reg(stackSlotF)]" %}
3718   interface(MEMORY_INTER) %{
3719     base(0xf);   // Z_SP
3720     index(0xffffFFFF); // noreg
3721     scale(0x0);
3722     disp($reg);  // Stack Offset
3723   %}
3724 %}
3725 
3726 operand stackSlotD(sRegD reg) %{
3727   constraint(ALLOC_IN_RC(stack_slots));
3728   op_cost(1);
3729   //match(RegD);
3730   format %{ "[$reg(stackSlotD)]" %}
3731   interface(MEMORY_INTER) %{
3732     base(0xf);   // Z_SP
3733     index(0xffffFFFF); // noreg
3734     scale(0x0);
3735     disp($reg);  // Stack Offset
3736   %}
3737 %}
3738 
3739 operand stackSlotL(sRegL reg) %{
3740   constraint(ALLOC_IN_RC(stack_slots));
3741   op_cost(1);  //match(RegL);
3742   format %{ "[$reg(stackSlotL)]" %}
3743   interface(MEMORY_INTER) %{
3744     base(0xf);   // Z_SP
3745     index(0xffffFFFF); // noreg
3746     scale(0x0);
3747     disp($reg);  // Stack Offset
3748   %}
3749 %}
3750 
3751 // Operands for expressing Control Flow
3752 // NOTE: Label is a predefined operand which should not be redefined in
3753 // the AD file. It is generically handled within the ADLC.
3754 
3755 //----------Conditional Branch Operands----------------------------------------
3756 // Comparison Op  - This is the operation of the comparison, and is limited to
3757 //                  the following set of codes:
3758 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3759 //
3760 // Other attributes of the comparison, such as unsignedness, are specified
3761 // by the comparison instruction that sets a condition code flags register.
3762 // That result is represented by a flags operand whose subtype is appropriate
3763 // to the unsignedness (etc.) of the comparison.
3764 //
3765 // Later, the instruction which matches both the Comparison Op (a Bool) and
3766 // the flags (produced by the Cmp) specifies the coding of the comparison op
3767 // by matching a specific subtype of Bool operand below.
3768 
3769 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
3770 // have mask bit #3 set.
3771 operand cmpOpT() %{
3772   match(Bool);
3773   format %{ "" %}
3774   interface(COND_INTER) %{
3775     equal(0x8);         // Assembler::bcondEqual
3776     not_equal(0x6);     // Assembler::bcondNotEqual
3777     less(0x4);          // Assembler::bcondLow
3778     greater_equal(0xa); // Assembler::bcondNotLow
3779     less_equal(0xc);    // Assembler::bcondNotHigh
3780     greater(0x2);       // Assembler::bcondHigh
3781     overflow(0x1);      // Assembler::bcondOverflow
3782     no_overflow(0xe);   // Assembler::bcondNotOverflow
3783   %}
3784 %}
3785 
3786 // When used for floating point comparisons: unordered is treated as less.
3787 operand cmpOpF() %{
3788   match(Bool);
3789   format %{ "" %}
3790   interface(COND_INTER) %{
3791     equal(0x8);
3792     not_equal(0x7);     // Includes 'unordered'.
3793     less(0x5);          // Includes 'unordered'.
3794     greater_equal(0xa);
3795     less_equal(0xd);    // Includes 'unordered'.
3796     greater(0x2);
3797     overflow(0x0);      // Not meaningful on z/Architecture.
3798     no_overflow(0x0);   // leave unchanged (zero) therefore
3799   %}
3800 %}
3801 
3802 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
3803 operand cmpOp() %{
3804   match(Bool);
3805   format %{ "" %}
3806   interface(COND_INTER) %{
3807     equal(0x8);
3808     not_equal(0x7);     // Includes 'unordered'.
3809     less(0x5);          // Includes 'unordered'.
3810     greater_equal(0xa);
3811     less_equal(0xd);    // Includes 'unordered'.
3812     greater(0x2);
3813     overflow(0x1);      // Assembler::bcondOverflow
3814     no_overflow(0xe);   // Assembler::bcondNotOverflow
3815   %}
3816 %}
3817 
3818 //----------OPERAND CLASSES----------------------------------------------------
3819 // Operand Classes are groups of operands that are used to simplify
3820 // instruction definitions by not requiring the AD writer to specify
3821 // seperate instructions for every form of operand when the
3822 // instruction accepts multiple operand types with the same basic
3823 // encoding and format.  The classic case of this is memory operands.
3824 // Indirect is not included since its use is limited to Compare & Swap
3825 
3826 // Most general memory operand, allows base, index, and long displacement.
3827 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3828 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
3829 
3830 // General memory operand, allows base, index, and short displacement.
3831 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
3832 
3833 // Memory operand, allows only base and long displacement.
3834 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
3835 
3836 // Memory operand, allows only base and short displacement.
3837 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
3838 
3839 // Operand classes to match encode and decode.
3840 opclass iRegN_P2N(iRegN);
3841 opclass iRegP_N2P(iRegP);
3842 
3843 
3844 //----------PIPELINE-----------------------------------------------------------
3845 pipeline %{
3846 
3847 //----------ATTRIBUTES---------------------------------------------------------
3848 attributes %{
3849   // z/Architecture instructions are of length 2, 4, or 6 bytes.
3850   variable_size_instructions;
3851   instruction_unit_size = 2;
3852 
3853   // Meaningless on z/Architecture.
3854   max_instructions_per_bundle = 1;
3855 
3856   // The z/Architecture processor fetches 64 bytes...
3857   instruction_fetch_unit_size = 64;
3858 
3859   // ...in one line.
3860   instruction_fetch_units = 1
3861 %}
3862 
3863 //----------RESOURCES----------------------------------------------------------
3864 // Resources are the functional units available to the machine.
3865 resources(
3866    Z_BR,     // branch unit
3867    Z_CR,     // condition unit
3868    Z_FX1,    // integer arithmetic unit 1
3869    Z_FX2,    // integer arithmetic unit 2
3870    Z_LDST1,  // load/store unit 1
3871    Z_LDST2,  // load/store unit 2
3872    Z_FP1,    // float arithmetic unit 1
3873    Z_FP2,    // float arithmetic unit 2
3874    Z_LDST = Z_LDST1 | Z_LDST2,
3875    Z_FX   = Z_FX1 | Z_FX2,
3876    Z_FP   = Z_FP1 | Z_FP2
3877   );
3878 
3879 //----------PIPELINE DESCRIPTION-----------------------------------------------
3880 // Pipeline Description specifies the stages in the machine's pipeline.
3881 pipe_desc(
3882    // TODO: adapt
3883    Z_IF,  // instruction fetch
3884    Z_IC,
3885    Z_D0,  // decode
3886    Z_D1,  // decode
3887    Z_D2,  // decode
3888    Z_D3,  // decode
3889    Z_Xfer1,
3890    Z_GD,  // group definition
3891    Z_MP,  // map
3892    Z_ISS, // issue
3893    Z_RF,  // resource fetch
3894    Z_EX1, // execute (all units)
3895    Z_EX2, // execute (FP, LDST)
3896    Z_EX3, // execute (FP, LDST)
3897    Z_EX4, // execute (FP)
3898    Z_EX5, // execute (FP)
3899    Z_EX6, // execute (FP)
3900    Z_WB,  // write back
3901    Z_Xfer2,
3902    Z_CP
3903   );
3904 
3905 //----------PIPELINE CLASSES---------------------------------------------------
3906 // Pipeline Classes describe the stages in which input and output are
3907 // referenced by the hardware pipeline.
3908 
3909 // Providing the `ins_pipe' declarations in the instruction
3910 // specifications seems to be of little use. So we use
3911 // `pipe_class_dummy' for all our instructions at present.
3912 pipe_class pipe_class_dummy() %{
3913   single_instruction;
3914   fixed_latency(4);
3915 %}
3916 
3917 // SIGTRAP based implicit range checks in compiled code.
3918 // Currently, no pipe classes are used on z/Architecture.
3919 pipe_class pipe_class_trap() %{
3920   single_instruction;
3921 %}
3922 
3923 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
3924   single_instruction;
3925   dst  : Z_EX1(write);
3926   src1 : Z_RF(read);
3927   src2 : Z_RF(read);
3928   Z_FX : Z_RF;
3929 %}
3930 
3931 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
3932   single_instruction;
3933   mem : Z_RF(read);
3934   dst : Z_WB(write);
3935   Z_LDST : Z_RF;
3936 %}
3937 
3938 define %{
3939   MachNop = pipe_class_dummy;
3940 %}
3941 
3942 %}
3943 
3944 //----------INSTRUCTIONS-------------------------------------------------------
3945 
3946 //---------- Chain stack slots between similar types --------
3947 
3948 // Load integer from stack slot.
3949 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
3950   match(Set dst src);
3951   ins_cost(MEMORY_REF_COST);
3952   // TODO: s390 port size(FIXED_SIZE);
3953   format %{ "L       $dst,$src\t # stk reload int" %}
3954   opcode(L_ZOPC);
3955   ins_encode(z_form_rt_mem(dst, src));
3956   ins_pipe(pipe_class_dummy);
3957 %}
3958 
3959 // Store integer to stack slot.
3960 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
3961   match(Set dst src);
3962   ins_cost(MEMORY_REF_COST);
3963   // TODO: s390 port size(FIXED_SIZE);
3964   format %{ "ST      $src,$dst\t # stk spill int" %}
3965   opcode(ST_ZOPC);
3966   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3967   ins_pipe(pipe_class_dummy);
3968 %}
3969 
3970 // Load long from stack slot.
3971 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
3972   match(Set dst src);
3973   ins_cost(MEMORY_REF_COST);
3974   // TODO: s390 port size(FIXED_SIZE);
3975   format %{ "LG      $dst,$src\t # stk reload long" %}
3976   opcode(LG_ZOPC);
3977   ins_encode(z_form_rt_mem(dst, src));
3978   ins_pipe(pipe_class_dummy);
3979 %}
3980 
3981 // Store long to stack slot.
3982 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
3983   match(Set dst src);
3984   ins_cost(MEMORY_REF_COST);
3985   size(6);
3986   format %{ "STG     $src,$dst\t # stk spill long" %}
3987   opcode(STG_ZOPC);
3988   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
3989   ins_pipe(pipe_class_dummy);
3990 %}
3991 
3992 // Load pointer from stack slot, 64-bit encoding.
3993 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
3994   match(Set dst src);
3995   ins_cost(MEMORY_REF_COST);
3996   // TODO: s390 port size(FIXED_SIZE);
3997   format %{ "LG      $dst,$src\t # stk reload ptr" %}
3998   opcode(LG_ZOPC);
3999   ins_encode(z_form_rt_mem(dst, src));
4000   ins_pipe(pipe_class_dummy);
4001 %}
4002 
4003 // Store pointer to stack slot.
4004 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
4005   match(Set dst src);
4006   ins_cost(MEMORY_REF_COST);
4007   // TODO: s390 port size(FIXED_SIZE);
4008   format %{ "STG     $src,$dst\t # stk spill ptr" %}
4009   opcode(STG_ZOPC);
4010   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
4011   ins_pipe(pipe_class_dummy);
4012 %}
4013 
4014 //  Float types
4015 
4016 // Load float value from stack slot.
4017 instruct stkF_to_regF(regF dst, stackSlotF src) %{
4018   match(Set dst src);
4019   ins_cost(MEMORY_REF_COST);
4020   size(4);
4021   format %{ "LE(Y)   $dst,$src\t # stk reload float" %}
4022   opcode(LE_ZOPC);
4023   ins_encode(z_form_rt_mem(dst, src));
4024   ins_pipe(pipe_class_dummy);
4025 %}
4026 
4027 // Store float value to stack slot.
4028 instruct regF_to_stkF(stackSlotF dst, regF src) %{
4029   match(Set dst src);
4030   ins_cost(MEMORY_REF_COST);
4031   size(4);
4032   format %{ "STE(Y)  $src,$dst\t # stk spill float" %}
4033   opcode(STE_ZOPC);
4034   ins_encode(z_form_rt_mem(src, dst));
4035   ins_pipe(pipe_class_dummy);
4036 %}
4037 
4038 // Load double value from stack slot.
4039 instruct stkD_to_regD(regD dst, stackSlotD src) %{
4040   match(Set dst src);
4041   ins_cost(MEMORY_REF_COST);
4042   // TODO: s390 port size(FIXED_SIZE);
4043   format %{ "LD(Y)   $dst,$src\t # stk reload double" %}
4044   opcode(LD_ZOPC);
4045   ins_encode(z_form_rt_mem(dst, src));
4046   ins_pipe(pipe_class_dummy);
4047 %}
4048 
4049 // Store double value to stack slot.
4050 instruct regD_to_stkD(stackSlotD dst, regD src) %{
4051   match(Set dst src);
4052   ins_cost(MEMORY_REF_COST);
4053   size(4);
4054   format %{ "STD(Y)  $src,$dst\t # stk spill double" %}
4055   opcode(STD_ZOPC);
4056   ins_encode(z_form_rt_mem(src, dst));
4057   ins_pipe(pipe_class_dummy);
4058 %}
4059 
4060 //----------Load/Store/Move Instructions---------------------------------------
4061 
4062 //----------Load Instructions--------------------------------------------------
4063 
4064 //------------------
4065 //  MEMORY
4066 //------------------
4067 
4068 //  BYTE
4069 // Load Byte (8bit signed)
4070 instruct loadB(iRegI dst, memory mem) %{
4071   match(Set dst (LoadB mem));
4072   ins_cost(MEMORY_REF_COST);
4073   size(Z_DISP3_SIZE);
4074   format %{ "LB      $dst, $mem\t # sign-extend byte to int" %}
4075   opcode(LB_ZOPC, LB_ZOPC);
4076   ins_encode(z_form_rt_mem_opt(dst, mem));
4077   ins_pipe(pipe_class_dummy);
4078 %}
4079 
4080 // Load Byte (8bit signed)
4081 instruct loadB2L(iRegL dst, memory mem) %{
4082   match(Set dst (ConvI2L (LoadB mem)));
4083   ins_cost(MEMORY_REF_COST);
4084   size(Z_DISP3_SIZE);
4085   format %{ "LGB     $dst, $mem\t # sign-extend byte to long" %}
4086   opcode(LGB_ZOPC, LGB_ZOPC);
4087   ins_encode(z_form_rt_mem_opt(dst, mem));
4088   ins_pipe(pipe_class_dummy);
4089 %}
4090 
4091 // Load Unsigned Byte (8bit UNsigned) into an int reg.
4092 instruct loadUB(iRegI dst, memory mem) %{
4093   match(Set dst (LoadUB mem));
4094   ins_cost(MEMORY_REF_COST);
4095   size(Z_DISP3_SIZE);
4096   format %{ "LLGC    $dst,$mem\t # zero-extend byte to int" %}
4097   opcode(LLGC_ZOPC, LLGC_ZOPC);
4098   ins_encode(z_form_rt_mem_opt(dst, mem));
4099   ins_pipe(pipe_class_dummy);
4100 %}
4101 
4102 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
4103 instruct loadUB2L(iRegL dst, memory mem) %{
4104   match(Set dst (ConvI2L (LoadUB mem)));
4105   ins_cost(MEMORY_REF_COST);
4106   size(Z_DISP3_SIZE);
4107   format %{ "LLGC    $dst,$mem\t # zero-extend byte to long" %}
4108   opcode(LLGC_ZOPC, LLGC_ZOPC);
4109   ins_encode(z_form_rt_mem_opt(dst, mem));
4110   ins_pipe(pipe_class_dummy);
4111 %}
4112 
4113 // CHAR/SHORT
4114 
4115 // Load Short (16bit signed)
4116 instruct loadS(iRegI dst, memory mem) %{
4117   match(Set dst (LoadS mem));
4118   ins_cost(MEMORY_REF_COST);
4119   size(Z_DISP_SIZE);
4120   format %{ "LH(Y)   $dst,$mem\t # sign-extend short to int" %}
4121   opcode(LHY_ZOPC, LH_ZOPC);
4122   ins_encode(z_form_rt_mem_opt(dst, mem));
4123   ins_pipe(pipe_class_dummy);
4124 %}
4125 
4126 // Load Short (16bit signed)
4127 instruct loadS2L(iRegL dst, memory mem) %{
4128   match(Set dst (ConvI2L (LoadS mem)));
4129   ins_cost(MEMORY_REF_COST);
4130   size(Z_DISP3_SIZE);
4131   format %{ "LGH     $dst,$mem\t # sign-extend short to long" %}
4132   opcode(LGH_ZOPC, LGH_ZOPC);
4133   ins_encode(z_form_rt_mem_opt(dst, mem));
4134   ins_pipe(pipe_class_dummy);
4135 %}
4136 
4137 // Load Char (16bit Unsigned)
4138 instruct loadUS(iRegI dst, memory mem) %{
4139   match(Set dst (LoadUS mem));
4140   ins_cost(MEMORY_REF_COST);
4141   size(Z_DISP3_SIZE);
4142   format %{ "LLGH    $dst,$mem\t # zero-extend short to int" %}
4143   opcode(LLGH_ZOPC, LLGH_ZOPC);
4144   ins_encode(z_form_rt_mem_opt(dst, mem));
4145   ins_pipe(pipe_class_dummy);
4146 %}
4147 
4148 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
4149 instruct loadUS2L(iRegL dst, memory mem) %{
4150   match(Set dst (ConvI2L (LoadUS mem)));
4151   ins_cost(MEMORY_REF_COST);
4152   size(Z_DISP3_SIZE);
4153   format %{ "LLGH    $dst,$mem\t # zero-extend short to long" %}
4154   opcode(LLGH_ZOPC, LLGH_ZOPC);
4155   ins_encode(z_form_rt_mem_opt(dst, mem));
4156   ins_pipe(pipe_class_dummy);
4157 %}
4158 
4159 // INT
4160 
4161 // Load Integer
4162 instruct loadI(iRegI dst, memory mem) %{
4163   match(Set dst (LoadI mem));
4164   ins_cost(MEMORY_REF_COST);
4165   size(Z_DISP_SIZE);
4166   format %{ "L(Y)    $dst,$mem\t #" %}
4167   opcode(LY_ZOPC, L_ZOPC);
4168   ins_encode(z_form_rt_mem_opt(dst, mem));
4169   ins_pipe(pipe_class_dummy);
4170 %}
4171 
4172 // Load and convert to long.
4173 instruct loadI2L(iRegL dst, memory mem) %{
4174   match(Set dst (ConvI2L (LoadI mem)));
4175   ins_cost(MEMORY_REF_COST);
4176   size(Z_DISP3_SIZE);
4177   format %{ "LGF     $dst,$mem\t #" %}
4178   opcode(LGF_ZOPC, LGF_ZOPC);
4179   ins_encode(z_form_rt_mem_opt(dst, mem));
4180   ins_pipe(pipe_class_dummy);
4181 %}
4182 
4183 // Load Unsigned Integer into a Long Register
4184 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
4185   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4186   ins_cost(MEMORY_REF_COST);
4187   size(Z_DISP3_SIZE);
4188   format %{ "LLGF    $dst,$mem\t # zero-extend int to long" %}
4189   opcode(LLGF_ZOPC, LLGF_ZOPC);
4190   ins_encode(z_form_rt_mem_opt(dst, mem));
4191   ins_pipe(pipe_class_dummy);
4192 %}
4193 
4194 // range = array length (=jint)
4195 // Load Range
4196 instruct loadRange(iRegI dst, memory mem) %{
4197   match(Set dst (LoadRange mem));
4198   ins_cost(MEMORY_REF_COST);
4199   size(Z_DISP_SIZE);
4200   format %{ "L(Y)    $dst,$mem\t # range" %}
4201   opcode(LY_ZOPC, L_ZOPC);
4202   ins_encode(z_form_rt_mem_opt(dst, mem));
4203   ins_pipe(pipe_class_dummy);
4204 %}
4205 
4206 // LONG
4207 
4208 // Load Long - aligned
4209 instruct loadL(iRegL dst, memory mem) %{
4210   match(Set dst (LoadL mem));
4211   ins_cost(MEMORY_REF_COST);
4212   size(Z_DISP3_SIZE);
4213   format %{ "LG      $dst,$mem\t # long" %}
4214   opcode(LG_ZOPC, LG_ZOPC);
4215   ins_encode(z_form_rt_mem_opt(dst, mem));
4216   ins_pipe(pipe_class_dummy);
4217 %}
4218 
4219 // Load Long - UNaligned
4220 instruct loadL_unaligned(iRegL dst, memory mem) %{
4221   match(Set dst (LoadL_unaligned mem));
4222   ins_cost(MEMORY_REF_COST);
4223   size(Z_DISP3_SIZE);
4224   format %{ "LG      $dst,$mem\t # unaligned long" %}
4225   opcode(LG_ZOPC, LG_ZOPC);
4226   ins_encode(z_form_rt_mem_opt(dst, mem));
4227   ins_pipe(pipe_class_dummy);
4228 %}
4229 
4230 
4231 // PTR
4232 
4233 // Load Pointer
4234 instruct loadP(iRegP dst, memory mem) %{
4235   match(Set dst (LoadP mem));
4236   ins_cost(MEMORY_REF_COST);
4237   size(Z_DISP3_SIZE);
4238   format %{ "LG      $dst,$mem\t # ptr" %}
4239   opcode(LG_ZOPC, LG_ZOPC);
4240   ins_encode(z_form_rt_mem_opt(dst, mem));
4241   ins_pipe(pipe_class_dummy);
4242 %}
4243 
4244 // LoadP + CastP2L
4245 instruct castP2X_loadP(iRegL dst, memory mem) %{
4246   match(Set dst (CastP2X (LoadP mem)));
4247   ins_cost(MEMORY_REF_COST);
4248   size(Z_DISP3_SIZE);
4249   format %{ "LG      $dst,$mem\t # ptr + p2x" %}
4250   opcode(LG_ZOPC, LG_ZOPC);
4251   ins_encode(z_form_rt_mem_opt(dst, mem));
4252   ins_pipe(pipe_class_dummy);
4253 %}
4254 
4255 // Load Klass Pointer
4256 instruct loadKlass(iRegP dst, memory mem) %{
4257   match(Set dst (LoadKlass mem));
4258   ins_cost(MEMORY_REF_COST);
4259   size(Z_DISP3_SIZE);
4260   format %{ "LG      $dst,$mem\t # klass ptr" %}
4261   opcode(LG_ZOPC, LG_ZOPC);
4262   ins_encode(z_form_rt_mem_opt(dst, mem));
4263   ins_pipe(pipe_class_dummy);
4264 %}
4265 
4266 instruct loadTOC(iRegL dst) %{
4267   effect(DEF dst);
4268   ins_cost(DEFAULT_COST);
4269   // TODO: s390 port size(FIXED_SIZE);
4270   // TODO: check why this attribute causes many unnecessary rematerializations.
4271   //
4272   // The graphs I saw just had high register pressure. Further the
4273   // register TOC is loaded to is overwritten by the constant short
4274   // after. Here something as round robin register allocation might
4275   // help. But rematerializing seems not to hurt, jack even seems to
4276   // improve slightly.
4277   //
4278   // Without this flag we get spill-split recycle sanity check
4279   // failures in
4280   // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
4281   // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
4282   // tlsLoadP has a huge amount of outs and forces the TOC down to the
4283   // stack. Later tlsLoadP is rematerialized, leaving the register
4284   // allocator with TOC on the stack and a badly placed reload.
4285   ins_should_rematerialize(true);
4286   format %{ "LARL    $dst, &constant_pool\t; load dynTOC" %}
4287   ins_encode %{ __ load_toc($dst$$Register); %}
4288   ins_pipe(pipe_class_dummy);
4289 %}
4290 
4291 // FLOAT
4292 
4293 // Load Float
4294 instruct loadF(regF dst, memory mem) %{
4295   match(Set dst (LoadF mem));
4296   ins_cost(MEMORY_REF_COST);
4297   size(Z_DISP_SIZE);
4298   format %{ "LE(Y)    $dst,$mem" %}
4299   opcode(LEY_ZOPC, LE_ZOPC);
4300   ins_encode(z_form_rt_mem_opt(dst, mem));
4301   ins_pipe(pipe_class_dummy);
4302 %}
4303 
4304 // DOUBLE
4305 
4306 // Load Double
4307 instruct loadD(regD dst, memory mem) %{
4308   match(Set dst (LoadD mem));
4309   ins_cost(MEMORY_REF_COST);
4310   size(Z_DISP_SIZE);
4311   format %{ "LD(Y)    $dst,$mem" %}
4312   opcode(LDY_ZOPC, LD_ZOPC);
4313   ins_encode(z_form_rt_mem_opt(dst, mem));
4314   ins_pipe(pipe_class_dummy);
4315 %}
4316 
4317 // Load Double - UNaligned
4318 instruct loadD_unaligned(regD dst, memory mem) %{
4319   match(Set dst (LoadD_unaligned mem));
4320   ins_cost(MEMORY_REF_COST);
4321   size(Z_DISP_SIZE);
4322   format %{ "LD(Y)    $dst,$mem" %}
4323   opcode(LDY_ZOPC, LD_ZOPC);
4324   ins_encode(z_form_rt_mem_opt(dst, mem));
4325   ins_pipe(pipe_class_dummy);
4326 %}
4327 
4328 
4329 //----------------------
4330 //  IMMEDIATES
4331 //----------------------
4332 
4333 instruct loadConI(iRegI dst, immI src) %{
4334   match(Set dst src);
4335   ins_cost(DEFAULT_COST);
4336   size(6);
4337   format %{ "LGFI    $dst,$src\t # (int)" %}
4338   ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
4339   ins_pipe(pipe_class_dummy);
4340 %}
4341 
4342 instruct loadConI16(iRegI dst, immI16 src) %{
4343   match(Set dst src);
4344   ins_cost(DEFAULT_COST_LOW);
4345   size(4);
4346   format %{ "LGHI    $dst,$src\t # (int)" %}
4347   ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
4348   ins_pipe(pipe_class_dummy);
4349 %}
4350 
4351 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
4352   match(Set dst src);
4353   effect(KILL cr);
4354   ins_cost(DEFAULT_COST_LOW);
4355   size(4);
4356   format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
4357   opcode(XGR_ZOPC);
4358   ins_encode(z_rreform(dst, dst));
4359   ins_pipe(pipe_class_dummy);
4360 %}
4361 
4362 instruct loadConUI16(iRegI dst, uimmI16 src) %{
4363   match(Set dst src);
4364   // TODO: s390 port size(FIXED_SIZE);
4365   format %{ "LLILL    $dst,$src" %}
4366   opcode(LLILL_ZOPC);
4367   ins_encode(z_riform_unsigned(dst, src) );
4368   ins_pipe(pipe_class_dummy);
4369 %}
4370 
4371 // Load long constant from TOC with pcrelative address.
4372 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
4373   match(Set dst src);
4374   ins_cost(MEMORY_REF_COST_LO);
4375   size(6);
4376   format %{ "LGRL    $dst,[pcrelTOC]\t # load long $src from table" %}
4377   ins_encode %{
4378     address long_address = __ long_constant($src$$constant);
4379     if (long_address == NULL) {
4380       Compile::current()->env()->record_out_of_memory_failure();
4381       return;
4382     }
4383     __ load_long_pcrelative($dst$$Register, long_address);
4384   %}
4385   ins_pipe(pipe_class_dummy);
4386 %}
4387 
4388 instruct loadConL32(iRegL dst, immL32 src) %{
4389   match(Set dst src);
4390   ins_cost(DEFAULT_COST);
4391   size(6);
4392   format %{ "LGFI     $dst,$src\t # (long)" %}
4393   ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
4394   ins_pipe(pipe_class_dummy);
4395 %}
4396 
4397 instruct loadConL16(iRegL dst, immL16 src) %{
4398   match(Set dst src);
4399   ins_cost(DEFAULT_COST_LOW);
4400   size(4);
4401   format %{ "LGHI     $dst,$src\t # (long)" %}
4402   ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
4403   ins_pipe(pipe_class_dummy);
4404 %}
4405 
4406 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
4407   match(Set dst src);
4408   effect(KILL cr);
4409   ins_cost(DEFAULT_COST_LOW);
4410   format %{ "LoadConL    $dst,$src\t # (long) XGR because ZERO is loaded" %}
4411   opcode(XGR_ZOPC);
4412   ins_encode(z_rreform(dst, dst));
4413   ins_pipe(pipe_class_dummy);
4414 %}
4415 
4416 // Load ptr constant from TOC with pc relative address.
4417 // Special handling for oop constants required.
4418 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
4419   match(Set dst src);
4420   ins_cost(MEMORY_REF_COST_LO);
4421   size(6);
4422   format %{ "LGRL    $dst,[pcrelTOC]\t # load ptr $src from table" %}
4423   ins_encode %{
4424     relocInfo::relocType constant_reloc = $src->constant_reloc();
4425     if (constant_reloc == relocInfo::oop_type) {
4426       AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
4427       bool success = __ load_oop_from_toc($dst$$Register, a);
4428       if (!success) {
4429         Compile::current()->env()->record_out_of_memory_failure();
4430         return;
4431       }
4432     } else if (constant_reloc == relocInfo::metadata_type) {
4433       AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
4434       address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
4435       if (const_toc_addr == NULL) {
4436         Compile::current()->env()->record_out_of_memory_failure();
4437         return;
4438       }
4439       __ load_long_pcrelative($dst$$Register, const_toc_addr);
4440     } else {          // Non-oop pointers, e.g. card mark base, heap top.
4441       address long_address = __ long_constant((jlong)$src$$constant);
4442       if (long_address == NULL) {
4443         Compile::current()->env()->record_out_of_memory_failure();
4444         return;
4445       }
4446       __ load_long_pcrelative($dst$$Register, long_address);
4447     }
4448   %}
4449   ins_pipe(pipe_class_dummy);
4450 %}
4451 
4452 // We don't use immP16 to avoid problems with oops.
4453 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
4454   match(Set dst src);
4455   effect(KILL cr);
4456   size(4);
4457   format %{ "XGR     $dst,$dst\t # NULL ptr" %}
4458   opcode(XGR_ZOPC);
4459   ins_encode(z_rreform(dst, dst));
4460   ins_pipe(pipe_class_dummy);
4461 %}
4462 
4463 //----------Load Float Constant Instructions-------------------------------------------------
4464 
4465 // We may not specify this instruction via an `expand' rule. If we do,
4466 // code selection will forget that this instruction needs a floating
4467 // point constant inserted into the code buffer. So `Shorten_branches'
4468 // will fail.
4469 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
4470   match(Set dst src);
4471   effect(KILL cr);
4472   ins_cost(MEMORY_REF_COST);
4473   size(6);
4474   // If this instruction rematerializes, it prolongs the live range
4475   // of the toc node, causing illegal graphs.
4476   ins_cannot_rematerialize(true);
4477   format %{ "LE(Y)    $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
4478   ins_encode %{
4479     __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4480   %}
4481   ins_pipe(pipe_class_dummy);
4482 %}
4483 
4484 // E may not specify this instruction via an `expand' rule. If we do,
4485 // code selection will forget that this instruction needs a floating
4486 // point constant inserted into the code buffer. So `Shorten_branches'
4487 // will fail.
4488 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
4489   match(Set dst src);
4490   effect(KILL cr);
4491   ins_cost(MEMORY_REF_COST);
4492   size(6);
4493   // If this instruction rematerializes, it prolongs the live range
4494   // of the toc node, causing illegal graphs.
4495   ins_cannot_rematerialize(true);
4496   format %{ "LD(Y)    $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
4497   ins_encode %{
4498     __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
4499   %}
4500   ins_pipe(pipe_class_dummy);
4501 %}
4502 
4503 // Special case: Load Const 0.0F
4504 
4505 // There's a special instr to clear a FP register.
4506 instruct loadConF0(regF dst, immFp0 src) %{
4507   match(Set dst src);
4508   ins_cost(DEFAULT_COST_LOW);
4509   size(4);
4510   format %{ "LZER     $dst,$src\t # clear to zero" %}
4511   opcode(LZER_ZOPC);
4512   ins_encode(z_rreform(dst, Z_F0));
4513   ins_pipe(pipe_class_dummy);
4514 %}
4515 
4516 // There's a special instr to clear a FP register.
4517 instruct loadConD0(regD dst, immDp0 src) %{
4518   match(Set dst src);
4519   ins_cost(DEFAULT_COST_LOW);
4520   size(4);
4521   format %{ "LZDR     $dst,$src\t # clear to zero" %}
4522   opcode(LZDR_ZOPC);
4523   ins_encode(z_rreform(dst, Z_F0));
4524   ins_pipe(pipe_class_dummy);
4525 %}
4526 
4527 
4528 //----------Store Instructions-------------------------------------------------
4529 
4530 // BYTE
4531 
4532 // Store Byte
4533 instruct storeB(memory mem, iRegI src) %{
4534   match(Set mem (StoreB mem src));
4535   ins_cost(MEMORY_REF_COST);
4536   size(Z_DISP_SIZE);
4537   format %{ "STC(Y)  $src,$mem\t # byte" %}
4538   opcode(STCY_ZOPC, STC_ZOPC);
4539   ins_encode(z_form_rt_mem_opt(src, mem));
4540   ins_pipe(pipe_class_dummy);
4541 %}
4542 
4543 instruct storeCM(memory mem, immI_0 src) %{
4544   match(Set mem (StoreCM mem src));
4545   ins_cost(MEMORY_REF_COST);
4546   // TODO: s390 port size(VARIABLE_SIZE);
4547   format %{ "STC(Y)  $src,$mem\t # CMS card-mark byte (must be 0!)" %}
4548   ins_encode %{
4549     guarantee($mem$$index$$Register != Z_R0, "content will not be used.");
4550     if ($mem$$index$$Register != noreg) {
4551       // Can't use clear_mem --> load const zero and store character.
4552       __ load_const_optimized(Z_R0_scratch, (long)0);
4553       if (Immediate::is_uimm12($mem$$disp)) {
4554         __ z_stc(Z_R0_scratch, $mem$$Address);
4555       } else {
4556         __ z_stcy(Z_R0_scratch, $mem$$Address);
4557       }
4558     } else {
4559       __ clear_mem(Address($mem$$Address), 1);
4560     }
4561   %}
4562   ins_pipe(pipe_class_dummy);
4563 %}
4564 
4565 // CHAR/SHORT
4566 
4567 // Store Char/Short
4568 instruct storeC(memory mem, iRegI src) %{
4569   match(Set mem (StoreC mem src));
4570   ins_cost(MEMORY_REF_COST);
4571   size(Z_DISP_SIZE);
4572   format %{ "STH(Y)  $src,$mem\t # short" %}
4573   opcode(STHY_ZOPC, STH_ZOPC);
4574   ins_encode(z_form_rt_mem_opt(src, mem));
4575   ins_pipe(pipe_class_dummy);
4576 %}
4577 
4578 // INT
4579 
4580 // Store Integer
4581 instruct storeI(memory mem, iRegI src) %{
4582   match(Set mem (StoreI mem src));
4583   ins_cost(MEMORY_REF_COST);
4584   size(Z_DISP_SIZE);
4585   format %{ "ST(Y)   $src,$mem\t # int" %}
4586   opcode(STY_ZOPC, ST_ZOPC);
4587   ins_encode(z_form_rt_mem_opt(src, mem));
4588   ins_pipe(pipe_class_dummy);
4589 %}
4590 
4591 // LONG
4592 
4593 // Store Long
4594 instruct storeL(memory mem, iRegL src) %{
4595   match(Set mem (StoreL mem src));
4596   ins_cost(MEMORY_REF_COST);
4597   size(Z_DISP3_SIZE);
4598   format %{ "STG     $src,$mem\t # long" %}
4599   opcode(STG_ZOPC, STG_ZOPC);
4600   ins_encode(z_form_rt_mem_opt(src, mem));
4601   ins_pipe(pipe_class_dummy);
4602 %}
4603 
4604 // PTR
4605 
4606 // Store Pointer
4607 instruct storeP(memory dst, memoryRegP src) %{
4608   match(Set dst (StoreP dst src));
4609   ins_cost(MEMORY_REF_COST);
4610   size(Z_DISP3_SIZE);
4611   format %{ "STG     $src,$dst\t # ptr" %}
4612   opcode(STG_ZOPC, STG_ZOPC);
4613   ins_encode(z_form_rt_mem_opt(src, dst));
4614   ins_pipe(pipe_class_dummy);
4615 %}
4616 
4617 // FLOAT
4618 
4619 // Store Float
4620 instruct storeF(memory mem, regF src) %{
4621   match(Set mem (StoreF mem src));
4622   ins_cost(MEMORY_REF_COST);
4623   size(Z_DISP_SIZE);
4624   format %{ "STE(Y)   $src,$mem\t # float" %}
4625   opcode(STEY_ZOPC, STE_ZOPC);
4626   ins_encode(z_form_rt_mem_opt(src, mem));
4627   ins_pipe(pipe_class_dummy);
4628 %}
4629 
4630 // DOUBLE
4631 
4632 // Store Double
4633 instruct storeD(memory mem, regD src) %{
4634   match(Set mem (StoreD mem src));
4635   ins_cost(MEMORY_REF_COST);
4636   size(Z_DISP_SIZE);
4637   format %{ "STD(Y)   $src,$mem\t # double" %}
4638   opcode(STDY_ZOPC, STD_ZOPC);
4639   ins_encode(z_form_rt_mem_opt(src, mem));
4640   ins_pipe(pipe_class_dummy);
4641 %}
4642 
4643 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
4644 
4645 // Should support match rule for PrefetchAllocation.
4646 // Still needed after 8068977 for PrefetchAllocate.
4647 instruct prefetchAlloc(memory mem) %{
4648   match(PrefetchAllocation mem);
4649   predicate(VM_Version::has_Prefetch());
4650   ins_cost(DEFAULT_COST);
4651   format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
4652   ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
4653   ins_pipe(pipe_class_dummy);
4654 %}
4655 
4656 //----------Memory init instructions------------------------------------------
4657 
4658 // Move Immediate to 1-byte memory.
4659 instruct memInitB(memoryRSY mem, immI8 src) %{
4660   match(Set mem (StoreB mem src));
4661   ins_cost(MEMORY_REF_COST);
4662   // TODO: s390 port size(VARIABLE_SIZE);
4663   format %{ "MVI     $mem,$src\t # direct mem init 1" %}
4664   ins_encode %{
4665     if (Immediate::is_uimm12((long)$mem$$disp)) {
4666       __ z_mvi($mem$$Address, $src$$constant);
4667     } else {
4668       __ z_mviy($mem$$Address, $src$$constant);
4669     }
4670   %}
4671   ins_pipe(pipe_class_dummy);
4672 %}
4673 
4674 // Move Immediate to 2-byte memory.
4675 instruct memInitC(memoryRS mem, immI16 src) %{
4676   match(Set mem (StoreC mem src));
4677   ins_cost(MEMORY_REF_COST);
4678   size(6);
4679   format %{ "MVHHI   $mem,$src\t # direct mem init 2" %}
4680   opcode(MVHHI_ZOPC);
4681   ins_encode(z_silform(mem, src));
4682   ins_pipe(pipe_class_dummy);
4683 %}
4684 
4685 // Move Immediate to 4-byte memory.
4686 instruct memInitI(memoryRS mem, immI16 src) %{
4687   match(Set mem (StoreI mem src));
4688   ins_cost(MEMORY_REF_COST);
4689   size(6);
4690   format %{ "MVHI    $mem,$src\t # direct mem init 4" %}
4691   opcode(MVHI_ZOPC);
4692   ins_encode(z_silform(mem, src));
4693   ins_pipe(pipe_class_dummy);
4694 %}
4695 
4696 
4697 // Move Immediate to 8-byte memory.
4698 instruct memInitL(memoryRS mem, immL16 src) %{
4699   match(Set mem (StoreL mem src));
4700   ins_cost(MEMORY_REF_COST);
4701   size(6);
4702   format %{ "MVGHI   $mem,$src\t # direct mem init 8" %}
4703   opcode(MVGHI_ZOPC);
4704   ins_encode(z_silform(mem, src));
4705   ins_pipe(pipe_class_dummy);
4706 %}
4707 
4708 // Move Immediate to 8-byte memory.
4709 instruct memInitP(memoryRS mem, immP16 src) %{
4710   match(Set mem (StoreP mem src));
4711   ins_cost(MEMORY_REF_COST);
4712   size(6);
4713   format %{ "MVGHI   $mem,$src\t # direct mem init 8" %}
4714   opcode(MVGHI_ZOPC);
4715   ins_encode(z_silform(mem, src));
4716   ins_pipe(pipe_class_dummy);
4717 %}
4718 
4719 
4720 //----------Instructions for compressed pointers (cOop and NKlass)-------------
4721 
4722 // See cOop encoding classes for elaborate comment.
4723 
4724 // Moved here because it is needed in expand rules for encode.
4725 // Long negation.
4726 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
4727   match(Set dst (SubL zero src));
4728   effect(KILL cr);
4729   size(4);
4730   format %{ "NEG     $dst, $src\t # long" %}
4731   ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
4732   ins_pipe(pipe_class_dummy);
4733 %}
4734 
4735 // Load Compressed Pointer
4736 
4737 // Load narrow oop
4738 instruct loadN(iRegN dst, memory mem) %{
4739   match(Set dst (LoadN mem));
4740   ins_cost(MEMORY_REF_COST);
4741   size(Z_DISP3_SIZE);
4742   format %{ "LoadN   $dst,$mem\t # (cOop)" %}
4743   opcode(LLGF_ZOPC, LLGF_ZOPC);
4744   ins_encode(z_form_rt_mem_opt(dst, mem));
4745   ins_pipe(pipe_class_dummy);
4746 %}
4747 
4748 // Load narrow Klass Pointer
4749 instruct loadNKlass(iRegN dst, memory mem) %{
4750   match(Set dst (LoadNKlass mem));
4751   ins_cost(MEMORY_REF_COST);
4752   size(Z_DISP3_SIZE);
4753   format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %}
4754   opcode(LLGF_ZOPC, LLGF_ZOPC);
4755   ins_encode(z_form_rt_mem_opt(dst, mem));
4756   ins_pipe(pipe_class_dummy);
4757 %}
4758 
4759 // Load constant Compressed Pointer
4760 
4761 instruct loadConN(iRegN dst, immN src) %{
4762   match(Set dst src);
4763   ins_cost(DEFAULT_COST);
4764   size(6);
4765   format %{ "loadConN    $dst,$src\t # (cOop)" %}
4766   ins_encode %{
4767     AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
4768     __ relocate(cOop.rspec(), 1);
4769     __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
4770   %}
4771   ins_pipe(pipe_class_dummy);
4772 %}
4773 
4774 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
4775   match(Set dst src);
4776   effect(KILL cr);
4777   ins_cost(DEFAULT_COST_LOW);
4778   size(4);
4779   format %{ "loadConN    $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
4780   opcode(XGR_ZOPC);
4781   ins_encode(z_rreform(dst, dst));
4782   ins_pipe(pipe_class_dummy);
4783 %}
4784 
4785 instruct loadConNKlass(iRegN dst, immNKlass src) %{
4786   match(Set dst src);
4787   ins_cost(DEFAULT_COST);
4788   size(6);
4789   format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
4790   ins_encode %{
4791     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4792     __ relocate(NKlass.rspec(), 1);
4793     __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
4794   %}
4795   ins_pipe(pipe_class_dummy);
4796 %}
4797 
4798 // Load and Decode Compressed Pointer
4799 // optimized variants for Unscaled cOops
4800 
4801 instruct decodeLoadN(iRegP dst, memory mem) %{
4802   match(Set dst (DecodeN (LoadN mem)));
4803   predicate(false && (CompressedOops::base()==NULL)&&(CompressedOops::shift()==0));
4804   ins_cost(MEMORY_REF_COST);
4805   size(Z_DISP3_SIZE);
4806   format %{ "DecodeLoadN  $dst,$mem\t # (cOop Load+Decode)" %}
4807   opcode(LLGF_ZOPC, LLGF_ZOPC);
4808   ins_encode(z_form_rt_mem_opt(dst, mem));
4809   ins_pipe(pipe_class_dummy);
4810 %}
4811 
4812 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
4813   match(Set dst (DecodeNKlass (LoadNKlass mem)));
4814   predicate(false && (CompressedKlassPointers::base()==NULL)&&(CompressedKlassPointers::shift()==0));
4815   ins_cost(MEMORY_REF_COST);
4816   size(Z_DISP3_SIZE);
4817   format %{ "DecodeLoadNKlass  $dst,$mem\t # (load/decode NKlass)" %}
4818   opcode(LLGF_ZOPC, LLGF_ZOPC);
4819   ins_encode(z_form_rt_mem_opt(dst, mem));
4820   ins_pipe(pipe_class_dummy);
4821 %}
4822 
4823 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
4824   match(Set dst (DecodeNKlass src));
4825   ins_cost(3 * DEFAULT_COST);
4826   size(12);
4827   format %{ "DecodeLoadConNKlass  $dst,$src\t # decode(cKlass)" %}
4828   ins_encode %{
4829     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
4830     __ relocate(NKlass.rspec(), 1);
4831     __ load_const($dst$$Register, (Klass*)NKlass.value());
4832   %}
4833   ins_pipe(pipe_class_dummy);
4834 %}
4835 
4836 // Decode Compressed Pointer
4837 
4838 // General decoder
4839 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
4840   match(Set dst (DecodeN src));
4841   effect(KILL cr);
4842   predicate(CompressedOops::base() == NULL || !ExpandLoadingBaseDecode);
4843   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4844   // TODO: s390 port size(VARIABLE_SIZE);
4845   format %{ "decodeN  $dst,$src\t # (decode cOop)" %}
4846   ins_encode %{  __ oop_decoder($dst$$Register, $src$$Register, true); %}
4847   ins_pipe(pipe_class_dummy);
4848 %}
4849 
4850 // General Klass decoder
4851 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
4852   match(Set dst (DecodeNKlass src));
4853   effect(KILL cr);
4854   ins_cost(3 * DEFAULT_COST);
4855   format %{ "decode_klass $dst,$src" %}
4856   ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
4857   ins_pipe(pipe_class_dummy);
4858 %}
4859 
4860 // General decoder
4861 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
4862   match(Set dst (DecodeN src));
4863   effect(KILL cr);
4864   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4865              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4866             (CompressedOops::base()== NULL || !ExpandLoadingBaseDecode_NN));
4867   ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4868   // TODO: s390 port size(VARIABLE_SIZE);
4869   format %{ "decodeN  $dst,$src\t # (decode cOop NN)" %}
4870   ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
4871   ins_pipe(pipe_class_dummy);
4872 %}
4873 
4874   instruct loadBase(iRegL dst, immL baseImm) %{
4875     effect(DEF dst, USE baseImm);
4876     predicate(false);
4877     format %{ "llihl    $dst=$baseImm \t// load heap base" %}
4878     ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
4879     ins_pipe(pipe_class_dummy);
4880   %}
4881 
4882   // Decoder for heapbased mode peeling off loading the base.
4883   instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4884     match(Set dst (DecodeN src base));
4885     // Note: Effect TEMP dst was used with the intention to get
4886     // different regs for dst and base, but this has caused ADLC to
4887     // generate wrong code. Oop_decoder generates additional lgr when
4888     // dst==base.
4889     effect(KILL cr);
4890     predicate(false);
4891     // TODO: s390 port size(VARIABLE_SIZE);
4892     format %{ "decodeN  $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
4893     ins_encode %{
4894       __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
4895                      (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
4896     %}
4897     ins_pipe(pipe_class_dummy);
4898   %}
4899 
4900   // Decoder for heapbased mode peeling off loading the base.
4901   instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
4902     match(Set dst (DecodeN src base));
4903     effect(KILL cr);
4904     predicate(false);
4905     // TODO: s390 port size(VARIABLE_SIZE);
4906     format %{ "decodeN  $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
4907     ins_encode %{
4908       __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
4909                      (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
4910     %}
4911     ins_pipe(pipe_class_dummy);
4912   %}
4913 
4914 // Decoder for heapbased mode peeling off loading the base.
4915 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4916   match(Set dst (DecodeN src));
4917   predicate(CompressedOops::base() != NULL && ExpandLoadingBaseDecode);
4918   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
4919   // TODO: s390 port size(VARIABLE_SIZE);
4920   expand %{
4921     immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
4922     iRegL base;
4923     loadBase(base, baseImm);
4924     decodeN_base(dst, src, base, cr);
4925   %}
4926 %}
4927 
4928 // Decoder for heapbased mode peeling off loading the base.
4929 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
4930   match(Set dst (DecodeN src));
4931   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
4932              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
4933             CompressedOops::base() != NULL && ExpandLoadingBaseDecode_NN);
4934   ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4935   // TODO: s390 port size(VARIABLE_SIZE);
4936   expand %{
4937     immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
4938     iRegL base;
4939     loadBase(base, baseImm);
4940     decodeN_NN_base(dst, src, base, cr);
4941   %}
4942 %}
4943 
4944 //  Encode Compressed Pointer
4945 
4946 // General encoder
4947 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
4948   match(Set dst (EncodeP src));
4949   effect(KILL cr);
4950   predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
4951             (CompressedOops::base() == 0 ||
4952              CompressedOops::base_disjoint() ||
4953              !ExpandLoadingBaseEncode));
4954   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4955   // TODO: s390 port size(VARIABLE_SIZE);
4956   format %{ "encodeP  $dst,$src\t # (encode cOop)" %}
4957   ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
4958   ins_pipe(pipe_class_dummy);
4959 %}
4960 
4961 // General class encoder
4962 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
4963   match(Set dst (EncodePKlass src));
4964   effect(KILL cr);
4965   format %{ "encode_klass $dst,$src" %}
4966   ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
4967   ins_pipe(pipe_class_dummy);
4968 %}
4969 
4970 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
4971   match(Set dst (EncodeP src));
4972   effect(KILL cr);
4973   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
4974             (CompressedOops::base() == 0 ||
4975              CompressedOops::base_disjoint() ||
4976              !ExpandLoadingBaseEncode_NN));
4977   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
4978   // TODO: s390 port size(VARIABLE_SIZE);
4979   format %{ "encodeP  $dst,$src\t # (encode cOop)" %}
4980   ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
4981   ins_pipe(pipe_class_dummy);
4982 %}
4983 
4984   // Encoder for heapbased mode peeling off loading the base.
4985   instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
4986     match(Set dst (EncodeP src (Binary base dst)));
4987     effect(TEMP_DEF dst);
4988     predicate(false);
4989     ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
4990     // TODO: s390 port size(VARIABLE_SIZE);
4991     format %{ "encodeP  $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %}
4992     ins_encode %{
4993       jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
4994         (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift());
4995       __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
4996     %}
4997     ins_pipe(pipe_class_dummy);
4998   %}
4999 
5000   // Encoder for heapbased mode peeling off loading the base.
5001   instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
5002     match(Set dst (EncodeP src base));
5003     effect(USE pow2_offset);
5004     predicate(false);
5005     ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
5006     // TODO: s390 port size(VARIABLE_SIZE);
5007     format %{ "encodeP  $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %}
5008     ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
5009     ins_pipe(pipe_class_dummy);
5010   %}
5011 
5012 // Encoder for heapbased mode peeling off loading the base.
5013 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5014   match(Set dst (EncodeP src));
5015   effect(KILL cr);
5016   predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
5017             (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode));
5018   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5019   // TODO: s390 port size(VARIABLE_SIZE);
5020   expand %{
5021     immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %}
5022     immL_0 zero %{ (0) %}
5023     flagsReg ccr;
5024     iRegL base;
5025     iRegL negBase;
5026     loadBase(base, baseImm);
5027     negL_reg_reg(negBase, zero, base, ccr);
5028     encodeP_base(dst, src, negBase);
5029   %}
5030 %}
5031 
5032 // Encoder for heapbased mode peeling off loading the base.
5033 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
5034   match(Set dst (EncodeP src));
5035   effect(KILL cr);
5036   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
5037             (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN));
5038   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
5039   // TODO: s390 port size(VARIABLE_SIZE);
5040   expand %{
5041     immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
5042     immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %}
5043     immL_0 zero %{ 0 %}
5044     flagsReg ccr;
5045     iRegL base;
5046     iRegL negBase;
5047     loadBase(base, baseImm);
5048     negL_reg_reg(negBase, zero, base, ccr);
5049     encodeP_NN_base(dst, src, negBase, pow2_offset);
5050   %}
5051 %}
5052 
5053 //  Store Compressed Pointer
5054 
5055 // Store Compressed Pointer
5056 instruct storeN(memory mem, iRegN_P2N src) %{
5057   match(Set mem (StoreN mem src));
5058   ins_cost(MEMORY_REF_COST);
5059   size(Z_DISP_SIZE);
5060   format %{ "ST      $src,$mem\t # (cOop)" %}
5061   opcode(STY_ZOPC, ST_ZOPC);
5062   ins_encode(z_form_rt_mem_opt(src, mem));
5063   ins_pipe(pipe_class_dummy);
5064 %}
5065 
5066 // Store Compressed Klass pointer
5067 instruct storeNKlass(memory mem, iRegN src) %{
5068   match(Set mem (StoreNKlass mem src));
5069   ins_cost(MEMORY_REF_COST);
5070   size(Z_DISP_SIZE);
5071   format %{ "ST      $src,$mem\t # (cKlass)" %}
5072   opcode(STY_ZOPC, ST_ZOPC);
5073   ins_encode(z_form_rt_mem_opt(src, mem));
5074   ins_pipe(pipe_class_dummy);
5075 %}
5076 
5077 // Compare Compressed Pointers
5078 
5079 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
5080   match(Set cr (CmpN src1 src2));
5081   ins_cost(DEFAULT_COST);
5082   size(2);
5083   format %{ "CLR     $src1,$src2\t # (cOop)" %}
5084   opcode(CLR_ZOPC);
5085   ins_encode(z_rrform(src1, src2));
5086   ins_pipe(pipe_class_dummy);
5087 %}
5088 
5089 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
5090   match(Set cr (CmpN src1 src2));
5091   ins_cost(DEFAULT_COST);
5092   size(6);
5093   format %{ "CLFI    $src1,$src2\t # (cOop) compare immediate narrow" %}
5094   ins_encode %{
5095     AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
5096     __ relocate(cOop.rspec(), 1);
5097     __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
5098   %}
5099   ins_pipe(pipe_class_dummy);
5100 %}
5101 
5102 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
5103   match(Set cr (CmpN src1 src2));
5104   ins_cost(DEFAULT_COST);
5105   size(6);
5106   format %{ "CLFI    $src1,$src2\t # (NKlass) compare immediate narrow" %}
5107   ins_encode %{
5108     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
5109     __ relocate(NKlass.rspec(), 1);
5110     __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
5111   %}
5112   ins_pipe(pipe_class_dummy);
5113 %}
5114 
5115 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
5116   match(Set cr (CmpN src1 src2));
5117   ins_cost(DEFAULT_COST);
5118   size(2);
5119   format %{ "LTR     $src1,$src2\t # (cOop) LTR because comparing against zero" %}
5120   opcode(LTR_ZOPC);
5121   ins_encode(z_rrform(src1, src1));
5122   ins_pipe(pipe_class_dummy);
5123 %}
5124 
5125 
5126 //----------MemBar Instructions-----------------------------------------------
5127 
5128 // Memory barrier flavors
5129 
5130 instruct membar_acquire() %{
5131   match(MemBarAcquire);
5132   match(LoadFence);
5133   ins_cost(4*MEMORY_REF_COST);
5134   size(0);
5135   format %{ "MEMBAR-acquire" %}
5136   ins_encode %{ __ z_acquire(); %}
5137   ins_pipe(pipe_class_dummy);
5138 %}
5139 
5140 instruct membar_acquire_lock() %{
5141   match(MemBarAcquireLock);
5142   ins_cost(0);
5143   size(0);
5144   format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
5145   ins_encode(/*empty*/);
5146   ins_pipe(pipe_class_dummy);
5147 %}
5148 
5149 instruct membar_release() %{
5150   match(MemBarRelease);
5151   match(StoreFence);
5152   ins_cost(4 * MEMORY_REF_COST);
5153   size(0);
5154   format %{ "MEMBAR-release" %}
5155   ins_encode %{ __ z_release(); %}
5156   ins_pipe(pipe_class_dummy);
5157 %}
5158 
5159 instruct membar_release_lock() %{
5160   match(MemBarReleaseLock);
5161   ins_cost(0);
5162   size(0);
5163   format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
5164   ins_encode(/*empty*/);
5165   ins_pipe(pipe_class_dummy);
5166 %}
5167 
5168 instruct membar_volatile() %{
5169   match(MemBarVolatile);
5170   ins_cost(4 * MEMORY_REF_COST);
5171   size(2);
5172   format %{ "MEMBAR-volatile" %}
5173   ins_encode %{ __ z_fence(); %}
5174   ins_pipe(pipe_class_dummy);
5175 %}
5176 
5177 instruct unnecessary_membar_volatile() %{
5178   match(MemBarVolatile);
5179   predicate(Matcher::post_store_load_barrier(n));
5180   ins_cost(0);
5181   size(0);
5182   format %{ "# MEMBAR-volatile (empty)" %}
5183   ins_encode(/*empty*/);
5184   ins_pipe(pipe_class_dummy);
5185 %}
5186 
5187 instruct membar_CPUOrder() %{
5188   match(MemBarCPUOrder);
5189   ins_cost(0);
5190   // TODO: s390 port size(FIXED_SIZE);
5191   format %{ "MEMBAR-CPUOrder (empty)" %}
5192   ins_encode(/*empty*/);
5193   ins_pipe(pipe_class_dummy);
5194 %}
5195 
5196 instruct membar_storestore() %{
5197   match(MemBarStoreStore);
5198   ins_cost(0);
5199   size(0);
5200   format %{ "MEMBAR-storestore (empty)" %}
5201   ins_encode();
5202   ins_pipe(pipe_class_dummy);
5203 %}
5204 
5205 
5206 //----------Register Move Instructions-----------------------------------------
5207 instruct roundDouble_nop(regD dst) %{
5208   match(Set dst (RoundDouble dst));
5209   ins_cost(0);
5210   // TODO: s390 port size(FIXED_SIZE);
5211   // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
5212   ins_encode();
5213   ins_pipe(pipe_class_dummy);
5214 %}
5215 
5216 instruct roundFloat_nop(regF dst) %{
5217   match(Set dst (RoundFloat dst));
5218   ins_cost(0);
5219   // TODO: s390 port size(FIXED_SIZE);
5220   // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
5221   ins_encode();
5222   ins_pipe(pipe_class_dummy);
5223 %}
5224 
5225 // Cast Long to Pointer for unsafe natives.
5226 instruct castX2P(iRegP dst, iRegL src) %{
5227   match(Set dst (CastX2P src));
5228   // TODO: s390 port size(VARIABLE_SIZE);
5229   format %{ "LGR     $dst,$src\t # CastX2P" %}
5230   ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5231   ins_pipe(pipe_class_dummy);
5232 %}
5233 
5234 // Cast Pointer to Long for unsafe natives.
5235 instruct castP2X(iRegL dst, iRegP_N2P src) %{
5236   match(Set dst (CastP2X src));
5237   // TODO: s390 port size(VARIABLE_SIZE);
5238   format %{ "LGR     $dst,$src\t # CastP2X" %}
5239   ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
5240   ins_pipe(pipe_class_dummy);
5241 %}
5242 
5243 instruct stfSSD(stackSlotD stkSlot, regD src) %{
5244   // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5245   match(Set stkSlot src);   // chain rule
5246   ins_cost(MEMORY_REF_COST);
5247   // TODO: s390 port size(FIXED_SIZE);
5248   format %{ " STD   $src,$stkSlot\t # stk" %}
5249   opcode(STD_ZOPC);
5250   ins_encode(z_form_rt_mem(src, stkSlot));
5251   ins_pipe(pipe_class_dummy);
5252 %}
5253 
5254 instruct stfSSF(stackSlotF stkSlot, regF src) %{
5255   // %%%% TODO: Tell the coalescer that this kind of node is a copy!
5256   match(Set stkSlot src);   // chain rule
5257   ins_cost(MEMORY_REF_COST);
5258   // TODO: s390 port size(FIXED_SIZE);
5259   format %{ "STE   $src,$stkSlot\t # stk" %}
5260   opcode(STE_ZOPC);
5261   ins_encode(z_form_rt_mem(src, stkSlot));
5262   ins_pipe(pipe_class_dummy);
5263 %}
5264 
5265 //----------Conditional Move---------------------------------------------------
5266 
5267 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
5268   match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5269   ins_cost(DEFAULT_COST + BRANCH_COST);
5270   // TODO: s390 port size(VARIABLE_SIZE);
5271   format %{ "CMoveN,$cmp   $dst,$src" %}
5272   ins_encode(z_enc_cmov_reg(cmp,dst,src));
5273   ins_pipe(pipe_class_dummy);
5274 %}
5275 
5276 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
5277   match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
5278   ins_cost(DEFAULT_COST + BRANCH_COST);
5279   // TODO: s390 port size(VARIABLE_SIZE);
5280   format %{ "CMoveN,$cmp   $dst,$src" %}
5281   ins_encode(z_enc_cmov_imm(cmp,dst,src));
5282   ins_pipe(pipe_class_dummy);
5283 %}
5284 
5285 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
5286   match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5287   ins_cost(DEFAULT_COST + BRANCH_COST);
5288   // TODO: s390 port size(VARIABLE_SIZE);
5289   format %{ "CMoveI,$cmp   $dst,$src" %}
5290   ins_encode(z_enc_cmov_reg(cmp,dst,src));
5291   ins_pipe(pipe_class_dummy);
5292 %}
5293 
5294 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
5295   match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
5296   ins_cost(DEFAULT_COST + BRANCH_COST);
5297   // TODO: s390 port size(VARIABLE_SIZE);
5298   format %{ "CMoveI,$cmp   $dst,$src" %}
5299   ins_encode(z_enc_cmov_imm(cmp,dst,src));
5300   ins_pipe(pipe_class_dummy);
5301 %}
5302 
5303 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
5304   match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5305   ins_cost(DEFAULT_COST + BRANCH_COST);
5306   // TODO: s390 port size(VARIABLE_SIZE);
5307   format %{ "CMoveP,$cmp    $dst,$src" %}
5308   ins_encode(z_enc_cmov_reg(cmp,dst,src));
5309   ins_pipe(pipe_class_dummy);
5310 %}
5311 
5312 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
5313   match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
5314   ins_cost(DEFAULT_COST + BRANCH_COST);
5315   // TODO: s390 port size(VARIABLE_SIZE);
5316   format %{ "CMoveP,$cmp  $dst,$src" %}
5317   ins_encode(z_enc_cmov_imm(cmp,dst,src));
5318   ins_pipe(pipe_class_dummy);
5319 %}
5320 
5321 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
5322   match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
5323   ins_cost(DEFAULT_COST + BRANCH_COST);
5324   // TODO: s390 port size(VARIABLE_SIZE);
5325   format %{ "CMoveF,$cmp   $dst,$src" %}
5326   ins_encode %{
5327     // Don't emit code if operands are identical (same register).
5328     if ($dst$$FloatRegister != $src$$FloatRegister) {
5329       Label done;
5330       __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5331       __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
5332       __ bind(done);
5333     }
5334   %}
5335   ins_pipe(pipe_class_dummy);
5336 %}
5337 
5338 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
5339   match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
5340   ins_cost(DEFAULT_COST + BRANCH_COST);
5341   // TODO: s390 port size(VARIABLE_SIZE);
5342   format %{ "CMoveD,$cmp   $dst,$src" %}
5343   ins_encode %{
5344     // Don't emit code if operands are identical (same register).
5345     if ($dst$$FloatRegister != $src$$FloatRegister) {
5346       Label done;
5347       __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
5348       __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
5349       __ bind(done);
5350     }
5351   %}
5352   ins_pipe(pipe_class_dummy);
5353 %}
5354 
5355 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
5356   match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5357   ins_cost(DEFAULT_COST + BRANCH_COST);
5358   // TODO: s390 port size(VARIABLE_SIZE);
5359   format %{ "CMoveL,$cmp  $dst,$src" %}
5360   ins_encode(z_enc_cmov_reg(cmp,dst,src));
5361   ins_pipe(pipe_class_dummy);
5362 %}
5363 
5364 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
5365   match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
5366   ins_cost(DEFAULT_COST + BRANCH_COST);
5367   // TODO: s390 port size(VARIABLE_SIZE);
5368   format %{ "CMoveL,$cmp  $dst,$src" %}
5369   ins_encode(z_enc_cmov_imm(cmp,dst,src));
5370   ins_pipe(pipe_class_dummy);
5371 %}
5372 
5373 //----------OS and Locking Instructions----------------------------------------
5374 
5375 // This name is KNOWN by the ADLC and cannot be changed.
5376 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
5377 // for this guy.
5378 instruct tlsLoadP(threadRegP dst) %{
5379   match(Set dst (ThreadLocal));
5380   ins_cost(0);
5381   size(0);
5382   ins_should_rematerialize(true);
5383   format %{ "# $dst=ThreadLocal" %}
5384   ins_encode(/* empty */);
5385   ins_pipe(pipe_class_dummy);
5386 %}
5387 
5388 instruct checkCastPP(iRegP dst) %{
5389   match(Set dst (CheckCastPP dst));
5390   size(0);
5391   format %{ "# checkcastPP of $dst" %}
5392   ins_encode(/*empty*/);
5393   ins_pipe(pipe_class_dummy);
5394 %}
5395 
5396 instruct castPP(iRegP dst) %{
5397   match(Set dst (CastPP dst));
5398   size(0);
5399   format %{ "# castPP of $dst" %}
5400   ins_encode(/*empty*/);
5401   ins_pipe(pipe_class_dummy);
5402 %}
5403 
5404 instruct castII(iRegI dst) %{
5405   match(Set dst (CastII dst));
5406   size(0);
5407   format %{ "# castII of $dst" %}
5408   ins_encode(/*empty*/);
5409   ins_pipe(pipe_class_dummy);
5410 %}
5411 
5412 
5413 //----------Conditional_store--------------------------------------------------
5414 // Conditional-store of the updated heap-top.
5415 // Used during allocation of the shared heap.
5416 // Sets flags (EQ) on success.
5417 
5418 // Implement LoadPLocked. Must be ordered against changes of the memory location
5419 // by storePConditional.
5420 // Don't know whether this is ever used.
5421 instruct loadPLocked(iRegP dst, memory mem) %{
5422   match(Set dst (LoadPLocked mem));
5423   ins_cost(MEMORY_REF_COST);
5424   size(Z_DISP3_SIZE);
5425   format %{ "LG      $dst,$mem\t # LoadPLocked" %}
5426   opcode(LG_ZOPC, LG_ZOPC);
5427   ins_encode(z_form_rt_mem_opt(dst, mem));
5428   ins_pipe(pipe_class_dummy);
5429 %}
5430 
5431 // As compareAndSwapP, but return flag register instead of boolean value in
5432 // int register.
5433 // This instruction is matched if UseTLAB is off. Needed to pass
5434 // option tests.  Mem_ptr must be a memory operand, else this node
5435 // does not get Flag_needs_anti_dependence_check set by adlc. If this
5436 // is not set this node can be rematerialized which leads to errors.
5437 instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{
5438   match(Set cr (StorePConditional mem_ptr (Binary oldval newval)));
5439   effect(KILL oldval);
5440   // TODO: s390 port size(FIXED_SIZE);
5441   format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
5442   ins_encode(z_enc_casL(oldval, newval, mem_ptr));
5443   ins_pipe(pipe_class_dummy);
5444 %}
5445 
5446 // As compareAndSwapL, but return flag register instead of boolean value in
5447 // int register.
5448 // Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory
5449 // operand, else this node does not get
5450 // Flag_needs_anti_dependence_check set by adlc. If this is not set
5451 // this node can be rematerialized which leads to errors.
5452 instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{
5453   match(Set cr (StoreLConditional mem_ptr (Binary oldval newval)));
5454   effect(KILL oldval);
5455   // TODO: s390 port size(FIXED_SIZE);
5456   format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
5457   ins_encode(z_enc_casL(oldval, newval, mem_ptr));
5458   ins_pipe(pipe_class_dummy);
5459 %}
5460 
5461 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
5462 
5463 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
5464   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
5465   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5466   size(16);
5467   format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
5468   ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5469              z_enc_cctobool(res));
5470   ins_pipe(pipe_class_dummy);
5471 %}
5472 
5473 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
5474   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
5475   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5476   size(18);
5477   format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
5478   ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5479              z_enc_cctobool(res));
5480   ins_pipe(pipe_class_dummy);
5481 %}
5482 
5483 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
5484   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
5485   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5486   size(18);
5487   format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
5488   ins_encode(z_enc_casL(oldval, newval, mem_ptr),
5489              z_enc_cctobool(res));
5490   ins_pipe(pipe_class_dummy);
5491 %}
5492 
5493 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
5494   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
5495   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
5496   size(16);
5497   format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
5498   ins_encode(z_enc_casI(oldval, newval, mem_ptr),
5499              z_enc_cctobool(res));
5500   ins_pipe(pipe_class_dummy);
5501 %}
5502 
5503 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
5504 
5505 // Exploit: direct memory arithmetic
5506 // Prereqs: - instructions available
5507 //          - instructions guarantee atomicity
5508 //          - immediate operand to be added
5509 //          - immediate operand is small enough (8-bit signed).
5510 //          - result of instruction is not used
5511 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
5512   match(Set dummy (GetAndAddI mem src));
5513   effect(KILL cr);
5514   predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5515   ins_cost(MEMORY_REF_COST);
5516   size(6);
5517   format %{ "ASI     [$mem],$src\t # GetAndAddI (atomic)" %}
5518   opcode(ASI_ZOPC);
5519   ins_encode(z_siyform(mem, src));
5520   ins_pipe(pipe_class_dummy);
5521 %}
5522 
5523 // Fallback: direct memory arithmetic not available
5524 // Disadvantages: - CS-Loop required, very expensive.
5525 //                - more code generated (26 to xx bytes vs. 6 bytes)
5526 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
5527   match(Set dst (GetAndAddI mem src));
5528   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5529   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5530   format %{ "BEGIN ATOMIC {\n\t"
5531             "  LGF     $dst,[$mem]\n\t"
5532             "  AHIK    $tmp,$dst,$src\n\t"
5533             "  CSY     $dst,$tmp,$mem\n\t"
5534             "  retry if failed\n\t"
5535             "} END ATOMIC"
5536          %}
5537   ins_encode %{
5538     Register Rdst = $dst$$Register;
5539     Register Rtmp = $tmp$$Register;
5540     int      Isrc = $src$$constant;
5541     Label    retry;
5542 
5543     // Iterate until update with incremented value succeeds.
5544     __ z_lgf(Rdst, $mem$$Address);    // current contents
5545     __ bind(retry);
5546       // Calculate incremented value.
5547       if (VM_Version::has_DistinctOpnds()) {
5548         __ z_ahik(Rtmp, Rdst, Isrc);
5549       } else {
5550         __ z_lr(Rtmp, Rdst);
5551         __ z_ahi(Rtmp, Isrc);
5552       }
5553       // Swap into memory location.
5554       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5555     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5556   %}
5557   ins_pipe(pipe_class_dummy);
5558 %}
5559 
5560 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
5561   match(Set dst (GetAndAddI mem src));
5562   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5563   ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
5564   format %{ "BEGIN ATOMIC {\n\t"
5565             "  LGF     $dst,[$mem]\n\t"
5566             "  LGR     $tmp,$dst\n\t"
5567             "  AFI     $tmp,$src\n\t"
5568             "  CSY     $dst,$tmp,$mem\n\t"
5569             "  retry if failed\n\t"
5570             "} END ATOMIC"
5571          %}
5572   ins_encode %{
5573     Register Rdst = $dst$$Register;
5574     Register Rtmp = $tmp$$Register;
5575     int      Isrc = $src$$constant;
5576     Label    retry;
5577 
5578     // Iterate until update with incremented value succeeds.
5579     __ z_lgf(Rdst, $mem$$Address);    // current contents
5580     __ bind(retry);
5581       // Calculate incremented value.
5582       __ z_lr(Rtmp, Rdst);
5583       __ z_afi(Rtmp, Isrc);
5584       // Swap into memory location.
5585       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5586     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5587   %}
5588   ins_pipe(pipe_class_dummy);
5589 %}
5590 
5591 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
5592   match(Set dst (GetAndAddI mem src));
5593   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5594   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5595   format %{ "BEGIN ATOMIC {\n\t"
5596             "  LGF     $dst,[$mem]\n\t"
5597             "  ARK     $tmp,$dst,$src\n\t"
5598             "  CSY     $dst,$tmp,$mem\n\t"
5599             "  retry if failed\n\t"
5600             "} END ATOMIC"
5601          %}
5602   ins_encode %{
5603     Register Rsrc = $src$$Register;
5604     Register Rdst = $dst$$Register;
5605     Register Rtmp = $tmp$$Register;
5606     Label    retry;
5607 
5608     // Iterate until update with incremented value succeeds.
5609     __ z_lgf(Rdst, $mem$$Address);  // current contents
5610     __ bind(retry);
5611       // Calculate incremented value.
5612       if (VM_Version::has_DistinctOpnds()) {
5613         __ z_ark(Rtmp, Rdst, Rsrc);
5614       } else {
5615         __ z_lr(Rtmp, Rdst);
5616         __ z_ar(Rtmp, Rsrc);
5617       }
5618       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5619     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5620   %}
5621   ins_pipe(pipe_class_dummy);
5622 %}
5623 
5624 
5625 // Exploit: direct memory arithmetic
5626 // Prereqs: - instructions available
5627 //          - instructions guarantee atomicity
5628 //          - immediate operand to be added
5629 //          - immediate operand is small enough (8-bit signed).
5630 //          - result of instruction is not used
5631 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
5632   match(Set dummy (GetAndAddL mem src));
5633   effect(KILL cr);
5634   predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
5635   ins_cost(MEMORY_REF_COST);
5636   size(6);
5637   format %{ "AGSI    [$mem],$src\t # GetAndAddL (atomic)" %}
5638   opcode(AGSI_ZOPC);
5639   ins_encode(z_siyform(mem, src));
5640   ins_pipe(pipe_class_dummy);
5641 %}
5642 
5643 // Fallback: direct memory arithmetic not available
5644 // Disadvantages: - CS-Loop required, very expensive.
5645 //                - more code generated (26 to xx bytes vs. 6 bytes)
5646 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
5647   match(Set dst (GetAndAddL mem src));
5648   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5649   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5650   format %{ "BEGIN ATOMIC {\n\t"
5651             "  LG      $dst,[$mem]\n\t"
5652             "  AGHIK   $tmp,$dst,$src\n\t"
5653             "  CSG     $dst,$tmp,$mem\n\t"
5654             "  retry if failed\n\t"
5655             "} END ATOMIC"
5656          %}
5657   ins_encode %{
5658     Register Rdst = $dst$$Register;
5659     Register Rtmp = $tmp$$Register;
5660     int      Isrc = $src$$constant;
5661     Label    retry;
5662 
5663     // Iterate until update with incremented value succeeds.
5664     __ z_lg(Rdst, $mem$$Address);  // current contents
5665     __ bind(retry);
5666       // Calculate incremented value.
5667       if (VM_Version::has_DistinctOpnds()) {
5668         __ z_aghik(Rtmp, Rdst, Isrc);
5669       } else {
5670         __ z_lgr(Rtmp, Rdst);
5671         __ z_aghi(Rtmp, Isrc);
5672       }
5673       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5674     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5675   %}
5676   ins_pipe(pipe_class_dummy);
5677 %}
5678 
5679 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
5680   match(Set dst (GetAndAddL mem src));
5681   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5682   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5683   format %{ "BEGIN ATOMIC {\n\t"
5684             "  LG      $dst,[$mem]\n\t"
5685             "  LGR     $tmp,$dst\n\t"
5686             "  AGFI    $tmp,$src\n\t"
5687             "  CSG     $dst,$tmp,$mem\n\t"
5688             "  retry if failed\n\t"
5689             "} END ATOMIC"
5690          %}
5691   ins_encode %{
5692     Register Rdst = $dst$$Register;
5693     Register Rtmp = $tmp$$Register;
5694     int      Isrc = $src$$constant;
5695     Label    retry;
5696 
5697     // Iterate until update with incremented value succeeds.
5698     __ z_lg(Rdst, $mem$$Address);  // current contents
5699     __ bind(retry);
5700       // Calculate incremented value.
5701       __ z_lgr(Rtmp, Rdst);
5702       __ z_agfi(Rtmp, Isrc);
5703       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5704     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5705   %}
5706   ins_pipe(pipe_class_dummy);
5707 %}
5708 
5709 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
5710   match(Set dst (GetAndAddL mem src));
5711   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
5712   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
5713   format %{ "BEGIN ATOMIC {\n\t"
5714             "  LG      $dst,[$mem]\n\t"
5715             "  AGRK    $tmp,$dst,$src\n\t"
5716             "  CSG     $dst,$tmp,$mem\n\t"
5717             "  retry if failed\n\t"
5718             "} END ATOMIC"
5719          %}
5720   ins_encode %{
5721     Register Rsrc = $src$$Register;
5722     Register Rdst = $dst$$Register;
5723     Register Rtmp = $tmp$$Register;
5724     Label    retry;
5725 
5726     // Iterate until update with incremented value succeeds.
5727     __ z_lg(Rdst, $mem$$Address);  // current contents
5728     __ bind(retry);
5729       // Calculate incremented value.
5730       if (VM_Version::has_DistinctOpnds()) {
5731         __ z_agrk(Rtmp, Rdst, Rsrc);
5732       } else {
5733         __ z_lgr(Rtmp, Rdst);
5734         __ z_agr(Rtmp, Rsrc);
5735       }
5736       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
5737     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
5738   %}
5739   ins_pipe(pipe_class_dummy);
5740 %}
5741 
5742 // Increment value in memory, save old value in dst.
5743 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
5744   match(Set dst (GetAndAddI mem src));
5745   predicate(VM_Version::has_LoadAndALUAtomicV1());
5746   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5747   size(6);
5748   format %{ "LAA     $dst,$src,[$mem]" %}
5749   ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
5750   ins_pipe(pipe_class_dummy);
5751 %}
5752 
5753 // Increment value in memory, save old value in dst.
5754 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
5755   match(Set dst (GetAndAddL mem src));
5756   predicate(VM_Version::has_LoadAndALUAtomicV1());
5757   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5758   size(6);
5759   format %{ "LAAG    $dst,$src,[$mem]" %}
5760   ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
5761   ins_pipe(pipe_class_dummy);
5762 %}
5763 
5764 
5765 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
5766   match(Set dst (GetAndSetI mem dst));
5767   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5768   format %{ "XCHGI   $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
5769   ins_encode(z_enc_SwapI(mem, dst, tmp));
5770   ins_pipe(pipe_class_dummy);
5771 %}
5772 
5773 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
5774   match(Set dst (GetAndSetL mem dst));
5775   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5776   format %{ "XCHGL   $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
5777   ins_encode(z_enc_SwapL(mem, dst, tmp));
5778   ins_pipe(pipe_class_dummy);
5779 %}
5780 
5781 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
5782   match(Set dst (GetAndSetN mem dst));
5783   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5784   format %{ "XCHGN   $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
5785   ins_encode(z_enc_SwapI(mem, dst, tmp));
5786   ins_pipe(pipe_class_dummy);
5787 %}
5788 
5789 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
5790   match(Set dst (GetAndSetP mem dst));
5791   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
5792   format %{ "XCHGP   $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
5793   ins_encode(z_enc_SwapL(mem, dst, tmp));
5794   ins_pipe(pipe_class_dummy);
5795 %}
5796 
5797 
5798 //----------Arithmetic Instructions--------------------------------------------
5799 
5800 // The rules are sorted by right operand type and operand length. Please keep
5801 // it that way.
5802 // Left operand type is always reg. Left operand len is I, L, P
5803 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
5804 // Special instruction formats, e.g. multi-operand, are inserted at the end.
5805 
5806 // ADD
5807 
5808 // REG = REG + REG
5809 
5810 // Register Addition
5811 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
5812   match(Set dst (AddI dst src));
5813   effect(KILL cr);
5814   // TODO: s390 port size(FIXED_SIZE);
5815   format %{ "AR      $dst,$src\t # int  CISC ALU" %}
5816   opcode(AR_ZOPC);
5817   ins_encode(z_rrform(dst, src));
5818   ins_pipe(pipe_class_dummy);
5819 %}
5820 
5821 // Avoid use of LA(Y) for general ALU operation.
5822 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
5823   match(Set dst (AddI src1 src2));
5824   effect(KILL cr);
5825   predicate(VM_Version::has_DistinctOpnds());
5826   ins_cost(DEFAULT_COST);
5827   size(4);
5828   format %{ "ARK     $dst,$src1,$src2\t # int  RISC ALU" %}
5829   opcode(ARK_ZOPC);
5830   ins_encode(z_rrfform(dst, src1, src2));
5831   ins_pipe(pipe_class_dummy);
5832 %}
5833 
5834 // REG = REG + IMM
5835 
5836 // Avoid use of LA(Y) for general ALU operation.
5837 // Immediate Addition
5838 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
5839   match(Set dst (AddI dst con));
5840   effect(KILL cr);
5841   ins_cost(DEFAULT_COST);
5842   // TODO: s390 port size(FIXED_SIZE);
5843   format %{ "AHI     $dst,$con\t # int  CISC ALU" %}
5844   opcode(AHI_ZOPC);
5845   ins_encode(z_riform_signed(dst, con));
5846   ins_pipe(pipe_class_dummy);
5847 %}
5848 
5849 // Avoid use of LA(Y) for general ALU operation.
5850 // Immediate Addition
5851 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
5852   match(Set dst (AddI src con));
5853   effect(KILL cr);
5854   predicate( VM_Version::has_DistinctOpnds());
5855   ins_cost(DEFAULT_COST);
5856   // TODO: s390 port size(FIXED_SIZE);
5857   format %{ "AHIK    $dst,$src,$con\t # int  RISC ALU" %}
5858   opcode(AHIK_ZOPC);
5859   ins_encode(z_rieform_d(dst, src, con));
5860   ins_pipe(pipe_class_dummy);
5861 %}
5862 
5863 // Immediate Addition
5864 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
5865   match(Set dst (AddI dst src));
5866   effect(KILL cr);
5867   ins_cost(DEFAULT_COST_HIGH);
5868   size(6);
5869   format %{ "AFI     $dst,$src" %}
5870   opcode(AFI_ZOPC);
5871   ins_encode(z_rilform_signed(dst, src));
5872   ins_pipe(pipe_class_dummy);
5873 %}
5874 
5875 // Immediate Addition
5876 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
5877   match(Set dst (AddI src con));
5878   predicate(PreferLAoverADD);
5879   ins_cost(DEFAULT_COST_LOW);
5880   size(4);
5881   format %{ "LA      $dst,$con(,$src)\t # int d12(,b)" %}
5882   opcode(LA_ZOPC);
5883   ins_encode(z_rxform_imm_reg(dst, con, src));
5884   ins_pipe(pipe_class_dummy);
5885 %}
5886 
5887 // Immediate Addition
5888 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
5889   match(Set dst (AddI src con));
5890   predicate(PreferLAoverADD);
5891   ins_cost(DEFAULT_COST);
5892   size(6);
5893   format %{ "LAY     $dst,$con(,$src)\t # int d20(,b)" %}
5894   opcode(LAY_ZOPC);
5895   ins_encode(z_rxyform_imm_reg(dst, con, src));
5896   ins_pipe(pipe_class_dummy);
5897 %}
5898 
5899 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
5900   match(Set dst (AddI (AddI src1 src2) con));
5901   predicate( PreferLAoverADD);
5902   ins_cost(DEFAULT_COST_LOW);
5903   size(4);
5904   format %{ "LA      $dst,$con($src1,$src2)\t # int d12(x,b)" %}
5905   opcode(LA_ZOPC);
5906   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
5907   ins_pipe(pipe_class_dummy);
5908 %}
5909 
5910 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
5911   match(Set dst (AddI (AddI src1 src2) con));
5912   predicate(PreferLAoverADD);
5913   ins_cost(DEFAULT_COST);
5914   size(6);
5915   format %{ "LAY     $dst,$con($src1,$src2)\t # int d20(x,b)" %}
5916   opcode(LAY_ZOPC);
5917   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
5918   ins_pipe(pipe_class_dummy);
5919 %}
5920 
5921 // REG = REG + MEM
5922 
5923 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
5924   match(Set dst (AddI dst (LoadI src)));
5925   effect(KILL cr);
5926   ins_cost(MEMORY_REF_COST);
5927   // TODO: s390 port size(VARIABLE_SIZE);
5928   format %{ "A(Y)    $dst, $src\t # int" %}
5929   opcode(AY_ZOPC, A_ZOPC);
5930   ins_encode(z_form_rt_mem_opt(dst, src));
5931   ins_pipe(pipe_class_dummy);
5932 %}
5933 
5934 // MEM = MEM + IMM
5935 
5936 // Add Immediate to 4-byte memory operand and result
5937 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
5938   match(Set mem (StoreI mem (AddI (LoadI mem) src)));
5939   effect(KILL cr);
5940   predicate(VM_Version::has_MemWithImmALUOps());
5941   ins_cost(MEMORY_REF_COST);
5942   size(6);
5943   format %{ "ASI     $mem,$src\t # direct mem add 4" %}
5944   opcode(ASI_ZOPC);
5945   ins_encode(z_siyform(mem, src));
5946   ins_pipe(pipe_class_dummy);
5947 %}
5948 
5949 
5950 //
5951 
5952 // REG = REG + REG
5953 
5954 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
5955   match(Set dst (AddL dst (ConvI2L src)));
5956   effect(KILL cr);
5957   size(4);
5958   format %{ "AGFR    $dst,$src\t # long<-int CISC ALU" %}
5959   opcode(AGFR_ZOPC);
5960   ins_encode(z_rreform(dst, src));
5961   ins_pipe(pipe_class_dummy);
5962 %}
5963 
5964 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
5965   match(Set dst (AddL dst src));
5966   effect(KILL cr);
5967   // TODO: s390 port size(FIXED_SIZE);
5968   format %{ "AGR     $dst, $src\t # long CISC ALU" %}
5969   opcode(AGR_ZOPC);
5970   ins_encode(z_rreform(dst, src));
5971   ins_pipe(pipe_class_dummy);
5972 %}
5973 
5974 // Avoid use of LA(Y) for general ALU operation.
5975 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
5976   match(Set dst (AddL src1 src2));
5977   effect(KILL cr);
5978   predicate(VM_Version::has_DistinctOpnds());
5979   ins_cost(DEFAULT_COST);
5980   size(4);
5981   format %{ "AGRK    $dst,$src1,$src2\t # long RISC ALU" %}
5982   opcode(AGRK_ZOPC);
5983   ins_encode(z_rrfform(dst, src1, src2));
5984   ins_pipe(pipe_class_dummy);
5985 %}
5986 
5987 // REG = REG + IMM
5988 
5989 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
5990   match(Set dst (AddL src con));
5991   predicate( PreferLAoverADD);
5992   ins_cost(DEFAULT_COST_LOW);
5993   size(4);
5994   format %{ "LA      $dst,$con(,$src)\t # long d12(,b)" %}
5995   opcode(LA_ZOPC);
5996   ins_encode(z_rxform_imm_reg(dst, con, src));
5997   ins_pipe(pipe_class_dummy);
5998 %}
5999 
6000 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
6001   match(Set dst (AddL src con));
6002   predicate(PreferLAoverADD);
6003   ins_cost(DEFAULT_COST);
6004   size(6);
6005   format %{ "LAY     $dst,$con(,$src)\t # long d20(,b)" %}
6006   opcode(LAY_ZOPC);
6007   ins_encode(z_rxyform_imm_reg(dst, con, src));
6008   ins_pipe(pipe_class_dummy);
6009 %}
6010 
6011 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
6012   match(Set dst (AddL dst con));
6013   effect(KILL cr);
6014   ins_cost(DEFAULT_COST_HIGH);
6015   size(6);
6016   format %{ "AGFI    $dst,$con\t # long CISC ALU" %}
6017   opcode(AGFI_ZOPC);
6018   ins_encode(z_rilform_signed(dst, con));
6019   ins_pipe(pipe_class_dummy);
6020 %}
6021 
6022 // Avoid use of LA(Y) for general ALU operation.
6023 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
6024   match(Set dst (AddL dst con));
6025   effect(KILL cr);
6026   ins_cost(DEFAULT_COST);
6027   // TODO: s390 port size(FIXED_SIZE);
6028   format %{ "AGHI    $dst,$con\t # long CISC ALU" %}
6029   opcode(AGHI_ZOPC);
6030   ins_encode(z_riform_signed(dst, con));
6031   ins_pipe(pipe_class_dummy);
6032 %}
6033 
6034 // Avoid use of LA(Y) for general ALU operation.
6035 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
6036   match(Set dst (AddL src con));
6037   effect(KILL cr);
6038   predicate( VM_Version::has_DistinctOpnds());
6039   ins_cost(DEFAULT_COST);
6040   size(6);
6041   format %{ "AGHIK   $dst,$src,$con\t # long RISC ALU" %}
6042   opcode(AGHIK_ZOPC);
6043   ins_encode(z_rieform_d(dst, src, con));
6044   ins_pipe(pipe_class_dummy);
6045 %}
6046 
6047 // REG = REG + MEM
6048 
6049 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6050   match(Set dst (AddL dst (ConvI2L (LoadI src))));
6051   effect(KILL cr);
6052   ins_cost(MEMORY_REF_COST);
6053   size(Z_DISP3_SIZE);
6054   format %{ "AGF     $dst, $src\t # long/int" %}
6055   opcode(AGF_ZOPC, AGF_ZOPC);
6056   ins_encode(z_form_rt_mem_opt(dst, src));
6057   ins_pipe(pipe_class_dummy);
6058 %}
6059 
6060 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6061   match(Set dst (AddL dst (LoadL src)));
6062   effect(KILL cr);
6063   ins_cost(MEMORY_REF_COST);
6064   size(Z_DISP3_SIZE);
6065   format %{ "AG      $dst, $src\t # long" %}
6066   opcode(AG_ZOPC, AG_ZOPC);
6067   ins_encode(z_form_rt_mem_opt(dst, src));
6068   ins_pipe(pipe_class_dummy);
6069 %}
6070 
6071 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
6072   match(Set dst (AddL (AddL src1 src2) con));
6073   predicate( PreferLAoverADD);
6074   ins_cost(DEFAULT_COST_LOW);
6075   size(4);
6076   format %{ "LA     $dst,$con($src1,$src2)\t # long d12(x,b)" %}
6077   opcode(LA_ZOPC);
6078   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6079   ins_pipe(pipe_class_dummy);
6080 %}
6081 
6082 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
6083   match(Set dst (AddL (AddL src1 src2) con));
6084   predicate(PreferLAoverADD);
6085   ins_cost(DEFAULT_COST);
6086   size(6);
6087   format %{ "LAY    $dst,$con($src1,$src2)\t # long d20(x,b)" %}
6088   opcode(LAY_ZOPC);
6089   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6090   ins_pipe(pipe_class_dummy);
6091 %}
6092 
6093 // MEM = MEM + IMM
6094 
6095 // Add Immediate to 8-byte memory operand and result.
6096 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6097   match(Set mem (StoreL mem (AddL (LoadL mem) src)));
6098   effect(KILL cr);
6099   predicate(VM_Version::has_MemWithImmALUOps());
6100   ins_cost(MEMORY_REF_COST);
6101   size(6);
6102   format %{ "AGSI    $mem,$src\t # direct mem add 8" %}
6103   opcode(AGSI_ZOPC);
6104   ins_encode(z_siyform(mem, src));
6105   ins_pipe(pipe_class_dummy);
6106 %}
6107 
6108 
6109 // REG = REG + REG
6110 
6111 // Ptr Addition
6112 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
6113   match(Set dst (AddP src1 src2));
6114   predicate( PreferLAoverADD);
6115   ins_cost(DEFAULT_COST);
6116   size(4);
6117   format %{ "LA      $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
6118   opcode(LA_ZOPC);
6119   ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
6120   ins_pipe(pipe_class_dummy);
6121 %}
6122 
6123 // Ptr Addition
6124 // Avoid use of LA(Y) for general ALU operation.
6125 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
6126   match(Set dst (AddP dst src));
6127   effect(KILL cr);
6128   predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6129   ins_cost(DEFAULT_COST);
6130   // TODO: s390 port size(FIXED_SIZE);
6131   format %{ "ALGR    $dst,$src\t # ptr CICS ALU" %}
6132   opcode(ALGR_ZOPC);
6133   ins_encode(z_rreform(dst, src));
6134   ins_pipe(pipe_class_dummy);
6135 %}
6136 
6137 // Ptr Addition
6138 // Avoid use of LA(Y) for general ALU operation.
6139 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
6140   match(Set dst (AddP src1 src2));
6141   effect(KILL cr);
6142   predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6143   ins_cost(DEFAULT_COST);
6144   // TODO: s390 port size(FIXED_SIZE);
6145   format %{ "ALGRK   $dst,$src1,$src2\t # ptr RISC ALU" %}
6146   opcode(ALGRK_ZOPC);
6147   ins_encode(z_rrfform(dst, src1, src2));
6148   ins_pipe(pipe_class_dummy);
6149 %}
6150 
6151 // REG = REG + IMM
6152 
6153 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
6154   match(Set dst (AddP src con));
6155   predicate( PreferLAoverADD);
6156   ins_cost(DEFAULT_COST_LOW);
6157   size(4);
6158   format %{ "LA      $dst,$con(,$src)\t # ptr d12(,b)" %}
6159   opcode(LA_ZOPC);
6160   ins_encode(z_rxform_imm_reg(dst, con, src));
6161   ins_pipe(pipe_class_dummy);
6162 %}
6163 
6164 // Avoid use of LA(Y) for general ALU operation.
6165 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
6166   match(Set dst (AddP dst src));
6167   effect(KILL cr);
6168   predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
6169   ins_cost(DEFAULT_COST);
6170   // TODO: s390 port size(FIXED_SIZE);
6171   format %{ "AGHI    $dst,$src\t # ptr CISC ALU" %}
6172   opcode(AGHI_ZOPC);
6173   ins_encode(z_riform_signed(dst, src));
6174   ins_pipe(pipe_class_dummy);
6175 %}
6176 
6177 // Avoid use of LA(Y) for general ALU operation.
6178 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
6179   match(Set dst (AddP src con));
6180   effect(KILL cr);
6181   predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
6182   ins_cost(DEFAULT_COST);
6183   // TODO: s390 port size(FIXED_SIZE);
6184   format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
6185   opcode(ALGHSIK_ZOPC);
6186   ins_encode(z_rieform_d(dst, src, con));
6187   ins_pipe(pipe_class_dummy);
6188 %}
6189 
6190 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
6191   match(Set dst (AddP src con));
6192   predicate(PreferLAoverADD);
6193   ins_cost(DEFAULT_COST);
6194   size(6);
6195   format %{ "LAY     $dst,$con(,$src)\t # ptr d20(,b)" %}
6196   opcode(LAY_ZOPC);
6197   ins_encode(z_rxyform_imm_reg(dst, con, src));
6198   ins_pipe(pipe_class_dummy);
6199 %}
6200 
6201 // Pointer Immediate Addition
6202 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
6203   match(Set dst (AddP dst src));
6204   effect(KILL cr);
6205   ins_cost(DEFAULT_COST_HIGH);
6206   // TODO: s390 port size(FIXED_SIZE);
6207   format %{ "AGFI    $dst,$src\t # ptr" %}
6208   opcode(AGFI_ZOPC);
6209   ins_encode(z_rilform_signed(dst, src));
6210   ins_pipe(pipe_class_dummy);
6211 %}
6212 
6213 // REG = REG1 + REG2 + IMM
6214 
6215 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
6216   match(Set dst (AddP (AddP src1 src2) con));
6217   predicate( PreferLAoverADD);
6218   ins_cost(DEFAULT_COST_LOW);
6219   size(4);
6220   format %{ "LA      $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6221   opcode(LA_ZOPC);
6222   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6223   ins_pipe(pipe_class_dummy);
6224 %}
6225 
6226 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
6227   match(Set dst (AddP (AddP src1 src2) con));
6228   predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0);
6229   ins_cost(DEFAULT_COST_LOW);
6230   size(4);
6231   format %{ "LA      $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
6232   opcode(LA_ZOPC);
6233   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
6234   ins_pipe(pipe_class_dummy);
6235 %}
6236 
6237 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
6238   match(Set dst (AddP (AddP src1 src2) con));
6239   predicate(PreferLAoverADD);
6240   ins_cost(DEFAULT_COST);
6241   // TODO: s390 port size(FIXED_SIZE);
6242   format %{ "LAY     $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6243   opcode(LAY_ZOPC);
6244   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6245   ins_pipe(pipe_class_dummy);
6246 %}
6247 
6248 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
6249   match(Set dst (AddP (AddP src1 src2) con));
6250   predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0);
6251   ins_cost(DEFAULT_COST);
6252   // TODO: s390 port size(FIXED_SIZE);
6253   format %{ "LAY     $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
6254   opcode(LAY_ZOPC);
6255   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
6256   ins_pipe(pipe_class_dummy);
6257 %}
6258 
6259 // MEM = MEM + IMM
6260 
6261 // Add Immediate to 8-byte memory operand and result
6262 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
6263   match(Set mem (StoreP mem (AddP (LoadP mem) src)));
6264   effect(KILL cr);
6265   predicate(VM_Version::has_MemWithImmALUOps());
6266   ins_cost(MEMORY_REF_COST);
6267   size(6);
6268   format %{ "AGSI    $mem,$src\t # direct mem add 8 (ptr)" %}
6269   opcode(AGSI_ZOPC);
6270   ins_encode(z_siyform(mem, src));
6271   ins_pipe(pipe_class_dummy);
6272 %}
6273 
6274 // SUB
6275 
6276 // Register Subtraction
6277 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
6278   match(Set dst (SubI dst src));
6279   effect(KILL cr);
6280   // TODO: s390 port size(FIXED_SIZE);
6281   format %{ "SR      $dst,$src\t # int  CISC ALU" %}
6282   opcode(SR_ZOPC);
6283   ins_encode(z_rrform(dst, src));
6284   ins_pipe(pipe_class_dummy);
6285 %}
6286 
6287 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
6288   match(Set dst (SubI src1 src2));
6289   effect(KILL cr);
6290   predicate(VM_Version::has_DistinctOpnds());
6291   ins_cost(DEFAULT_COST);
6292   size(4);
6293   format %{ "SRK     $dst,$src1,$src2\t # int  RISC ALU" %}
6294   opcode(SRK_ZOPC);
6295   ins_encode(z_rrfform(dst, src1, src2));
6296   ins_pipe(pipe_class_dummy);
6297 %}
6298 
6299 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
6300   match(Set dst (SubI dst (LoadI src)));
6301   effect(KILL cr);
6302   ins_cost(MEMORY_REF_COST);
6303   // TODO: s390 port size(VARIABLE_SIZE);
6304   format %{ "S(Y)    $dst, $src\t # int" %}
6305   opcode(SY_ZOPC, S_ZOPC);
6306   ins_encode(z_form_rt_mem_opt(dst, src));
6307   ins_pipe(pipe_class_dummy);
6308 %}
6309 
6310 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
6311   match(Set dst (SubI zero src));
6312   effect(KILL cr);
6313   size(2);
6314   format %{ "NEG     $dst, $src" %}
6315   ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
6316   ins_pipe(pipe_class_dummy);
6317 %}
6318 
6319 //
6320 
6321 // Long subtraction
6322 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
6323   match(Set dst (SubL dst src));
6324   effect(KILL cr);
6325   // TODO: s390 port size(FIXED_SIZE);
6326   format %{ "SGR     $dst,$src\t # int  CISC ALU" %}
6327   opcode(SGR_ZOPC);
6328   ins_encode(z_rreform(dst, src));
6329   ins_pipe(pipe_class_dummy);
6330 %}
6331 
6332 // Avoid use of LA(Y) for general ALU operation.
6333 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
6334   match(Set dst (SubL src1 src2));
6335   effect(KILL cr);
6336   predicate(VM_Version::has_DistinctOpnds());
6337   ins_cost(DEFAULT_COST);
6338   size(4);
6339   format %{ "SGRK    $dst,$src1,$src2\t # int  RISC ALU" %}
6340   opcode(SGRK_ZOPC);
6341   ins_encode(z_rrfform(dst, src1, src2));
6342   ins_pipe(pipe_class_dummy);
6343 %}
6344 
6345 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
6346   match(Set dst (SubL dst (ConvI2L src)));
6347   effect(KILL cr);
6348   size(4);
6349   format %{ "SGFR    $dst, $src\t # int  CISC ALU" %}
6350   opcode(SGFR_ZOPC);
6351   ins_encode(z_rreform(dst, src));
6352   ins_pipe(pipe_class_dummy);
6353 %}
6354 
6355 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
6356   match(Set dst (SubL dst (ConvI2L (LoadI src))));
6357   effect(KILL cr);
6358   ins_cost(MEMORY_REF_COST);
6359   size(Z_DISP3_SIZE);
6360   format %{ "SGF     $dst, $src\t # long/int" %}
6361   opcode(SGF_ZOPC, SGF_ZOPC);
6362   ins_encode(z_form_rt_mem_opt(dst, src));
6363   ins_pipe(pipe_class_dummy);
6364 %}
6365 
6366 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
6367   match(Set dst (SubL dst (LoadL src)));
6368   effect(KILL cr);
6369   ins_cost(MEMORY_REF_COST);
6370   size(Z_DISP3_SIZE);
6371   format %{ "SG      $dst, $src\t # long" %}
6372   opcode(SG_ZOPC, SG_ZOPC);
6373   ins_encode(z_form_rt_mem_opt(dst, src));
6374   ins_pipe(pipe_class_dummy);
6375 %}
6376 
6377 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
6378 
6379 //  MUL
6380 
6381 // Register Multiplication
6382 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
6383   match(Set dst (MulI dst src));
6384   ins_cost(DEFAULT_COST);
6385   size(4);
6386   format %{ "MSR     $dst, $src" %}
6387   opcode(MSR_ZOPC);
6388   ins_encode(z_rreform(dst, src));
6389   ins_pipe(pipe_class_dummy);
6390 %}
6391 
6392 // Immediate Multiplication
6393 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
6394   match(Set dst (MulI dst con));
6395   ins_cost(DEFAULT_COST);
6396   // TODO: s390 port size(FIXED_SIZE);
6397   format %{ "MHI     $dst,$con" %}
6398   opcode(MHI_ZOPC);
6399   ins_encode(z_riform_signed(dst,con));
6400   ins_pipe(pipe_class_dummy);
6401 %}
6402 
6403 // Immediate (32bit) Multiplication
6404 instruct mulI_reg_imm32(iRegI dst, immI con) %{
6405   match(Set dst (MulI dst con));
6406   ins_cost(DEFAULT_COST);
6407   size(6);
6408   format %{ "MSFI    $dst,$con" %}
6409   opcode(MSFI_ZOPC);
6410   ins_encode(z_rilform_signed(dst,con));
6411   ins_pipe(pipe_class_dummy);
6412 %}
6413 
6414 instruct mulI_Reg_mem(iRegI dst, memory src)%{
6415   match(Set dst (MulI dst (LoadI src)));
6416   ins_cost(MEMORY_REF_COST);
6417   // TODO: s390 port size(VARIABLE_SIZE);
6418   format %{ "MS(Y)   $dst, $src\t # int" %}
6419   opcode(MSY_ZOPC, MS_ZOPC);
6420   ins_encode(z_form_rt_mem_opt(dst, src));
6421   ins_pipe(pipe_class_dummy);
6422 %}
6423 
6424 //
6425 
6426 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
6427   match(Set dst (MulL dst (ConvI2L src)));
6428   ins_cost(DEFAULT_COST);
6429   // TODO: s390 port size(FIXED_SIZE);
6430   format %{ "MSGFR   $dst $src\t # long/int" %}
6431   opcode(MSGFR_ZOPC);
6432   ins_encode(z_rreform(dst, src));
6433   ins_pipe(pipe_class_dummy);
6434 %}
6435 
6436 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
6437   match(Set dst (MulL dst src));
6438   ins_cost(DEFAULT_COST);
6439   size(4);
6440   format %{ "MSGR    $dst $src\t # long" %}
6441   opcode(MSGR_ZOPC);
6442   ins_encode(z_rreform(dst, src));
6443   ins_pipe(pipe_class_dummy);
6444 %}
6445 
6446 // Immediate Multiplication
6447 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
6448   match(Set dst (MulL dst src));
6449   ins_cost(DEFAULT_COST);
6450   // TODO: s390 port size(FIXED_SIZE);
6451   format %{ "MGHI    $dst,$src\t # long" %}
6452   opcode(MGHI_ZOPC);
6453   ins_encode(z_riform_signed(dst, src));
6454   ins_pipe(pipe_class_dummy);
6455 %}
6456 
6457 // Immediate (32bit) Multiplication
6458 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
6459   match(Set dst (MulL dst con));
6460   ins_cost(DEFAULT_COST);
6461   size(6);
6462   format %{ "MSGFI   $dst,$con" %}
6463   opcode(MSGFI_ZOPC);
6464   ins_encode(z_rilform_signed(dst,con));
6465   ins_pipe(pipe_class_dummy);
6466 %}
6467 
6468 instruct mulL_Reg_memI(iRegL dst, memory src)%{
6469   match(Set dst (MulL dst (ConvI2L (LoadI src))));
6470   ins_cost(MEMORY_REF_COST);
6471   size(Z_DISP3_SIZE);
6472   format %{ "MSGF    $dst, $src\t # long" %}
6473   opcode(MSGF_ZOPC, MSGF_ZOPC);
6474   ins_encode(z_form_rt_mem_opt(dst, src));
6475   ins_pipe(pipe_class_dummy);
6476 %}
6477 
6478 instruct mulL_Reg_mem(iRegL dst, memory src)%{
6479   match(Set dst (MulL dst (LoadL src)));
6480   ins_cost(MEMORY_REF_COST);
6481   size(Z_DISP3_SIZE);
6482   format %{ "MSG     $dst, $src\t # long" %}
6483   opcode(MSG_ZOPC, MSG_ZOPC);
6484   ins_encode(z_form_rt_mem_opt(dst, src));
6485   ins_pipe(pipe_class_dummy);
6486 %}
6487 
6488 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{
6489   match(Set Rdst (MulHiL Rsrc1 Rsrc2));
6490   effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr);
6491   ins_cost(7*DEFAULT_COST);
6492   // TODO: s390 port size(VARIABLE_SIZE);
6493   format %{ "MulHiL  $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %}
6494   ins_encode%{
6495     Register dst  = $Rdst$$Register;
6496     Register src1 = $Rsrc1$$Register;
6497     Register src2 = $Rsrc2$$Register;
6498     Register tmp1 = $Rtmp1$$Register;
6499     Register tmp2 = $Rdst$$Register;
6500     // z/Architecture has only unsigned multiply (64 * 64 -> 128).
6501     // implementing mulhs(a,b) = mulhu(a,b) – (a & (b>>63)) – (b & (a>>63))
6502     __ z_srag(tmp2, src1, 63);  // a>>63
6503     __ z_srag(tmp1, src2, 63);  // b>>63
6504     __ z_ngr(tmp2, src2);       // b & (a>>63)
6505     __ z_ngr(tmp1, src1);       // a & (b>>63)
6506     __ z_agr(tmp1, tmp2);       // ((a & (b>>63)) + (b & (a>>63)))
6507     __ z_mlgr(dst, src2);       // tricky: 128-bit product is written to even/odd pair (dst,src1),
6508                                 //         multiplicand is taken from oddReg (src1), multiplier in src2.
6509     __ z_sgr(dst, tmp1);
6510   %}
6511   ins_pipe(pipe_class_dummy);
6512 %}
6513 
6514 //  DIV
6515 
6516 // Integer DIVMOD with Register, both quotient and mod results
6517 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
6518   match(DivModI dst1src1 src2);
6519   effect(KILL cr);
6520   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6521   size((VM_Version::has_CompareBranch() ? 24 : 26));
6522   format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
6523   ins_encode %{
6524     Register d1s1 = $dst1src1$$Register;
6525     Register d2   = $dst2$$Register;
6526     Register s2   = $src2$$Register;
6527 
6528     assert_different_registers(d1s1, s2);
6529 
6530     Label do_div, done_div;
6531     if (VM_Version::has_CompareBranch()) {
6532       __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
6533     } else {
6534       __ z_chi(s2, -1);
6535       __ z_brne(do_div);
6536     }
6537     __ z_lcr(d1s1, d1s1);
6538     __ clear_reg(d2, false, false);
6539     __ z_bru(done_div);
6540     __ bind(do_div);
6541     __ z_lgfr(d1s1, d1s1);
6542     __ z_dsgfr(d2, s2);
6543     __ bind(done_div);
6544   %}
6545   ins_pipe(pipe_class_dummy);
6546 %}
6547 
6548 
6549 // Register Division
6550 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
6551   match(Set dst (DivI src1 src2));
6552   effect(KILL tmp, KILL cr);
6553   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6554   size((VM_Version::has_CompareBranch() ? 20 : 22));
6555   format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
6556   ins_encode %{
6557     Register a = $src1$$Register;
6558     Register b = $src2$$Register;
6559     Register t = $dst$$Register;
6560 
6561     assert_different_registers(t, b);
6562 
6563     Label do_div, done_div;
6564     if (VM_Version::has_CompareBranch()) {
6565       __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6566     } else {
6567       __ z_chi(b, -1);
6568       __ z_brne(do_div);
6569     }
6570     __ z_lcr(t, a);
6571     __ z_bru(done_div);
6572     __ bind(do_div);
6573     __ z_lgfr(t, a);
6574     __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
6575     __ bind(done_div);
6576   %}
6577   ins_pipe(pipe_class_dummy);
6578 %}
6579 
6580 // Immediate Division
6581 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
6582   match(Set dst (DivI src1 src2));
6583   effect(KILL tmp, KILL cr);  // R0 is killed, too.
6584   ins_cost(2 * DEFAULT_COST);
6585   // TODO: s390 port size(VARIABLE_SIZE);
6586   format %{ "DIV_const  $dst,$src1,$src2" %}
6587   ins_encode %{
6588     // No sign extension of Rdividend needed here.
6589     if ($src2$$constant != -1) {
6590       __ z_lghi(Z_R0_scratch, $src2$$constant);
6591       __ z_lgfr($dst$$Register, $src1$$Register);
6592       __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6593     } else {
6594       __ z_lcr($dst$$Register, $src1$$Register);
6595     }
6596   %}
6597   ins_pipe(pipe_class_dummy);
6598 %}
6599 
6600 // Long DIVMOD with Register, both quotient and mod results
6601 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
6602   match(DivModL dst1src1 src2);
6603   effect(KILL cr);
6604   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6605   size((VM_Version::has_CompareBranch() ? 22 : 24));
6606   format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
6607   ins_encode %{
6608     Register d1s1 = $dst1src1$$Register;
6609     Register d2   = $dst2$$Register;
6610     Register s2   = $src2$$Register;
6611 
6612     Label do_div, done_div;
6613     if (VM_Version::has_CompareBranch()) {
6614       __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
6615     } else {
6616       __ z_cghi(s2, -1);
6617       __ z_brne(do_div);
6618     }
6619     __ z_lcgr(d1s1, d1s1);
6620     // indicate unused result
6621     (void) __ clear_reg(d2, true, false);
6622     __ z_bru(done_div);
6623     __ bind(do_div);
6624     __ z_dsgr(d2, s2);
6625     __ bind(done_div);
6626   %}
6627   ins_pipe(pipe_class_dummy);
6628 %}
6629 
6630 // Register Long Division
6631 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
6632   match(Set dst (DivL dst src));
6633   effect(KILL tmp, KILL cr);
6634   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6635   size((VM_Version::has_CompareBranch() ? 18 : 20));
6636   format %{ "DIVG_checked  $dst, $src\t # long, treats special case 0x80../-1" %}
6637   ins_encode %{
6638     Register b = $src$$Register;
6639     Register t = $dst$$Register;
6640 
6641     Label done_div;
6642     __ z_lcgr(t, t);    // Does no harm. divisor is in other register.
6643     if (VM_Version::has_CompareBranch()) {
6644       __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6645     } else {
6646       __ z_cghi(b, -1);
6647       __ z_bre(done_div);
6648     }
6649     __ z_lcgr(t, t);    // Restore sign.
6650     __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
6651     __ bind(done_div);
6652   %}
6653   ins_pipe(pipe_class_dummy);
6654 %}
6655 
6656 // Immediate Long Division
6657 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
6658   match(Set dst (DivL src1 src2));
6659   effect(KILL tmp, KILL cr);  // R0 is killed, too.
6660   ins_cost(2 * DEFAULT_COST);
6661   // TODO: s390 port size(VARIABLE_SIZE);
6662   format %{ "DIVG_const  $dst,$src1,$src2\t # long" %}
6663   ins_encode %{
6664     if ($src2$$constant != -1) {
6665       __ z_lghi(Z_R0_scratch, $src2$$constant);
6666       __ lgr_if_needed($dst$$Register, $src1$$Register);
6667       __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
6668     } else {
6669       __ z_lcgr($dst$$Register, $src1$$Register);
6670     }
6671   %}
6672   ins_pipe(pipe_class_dummy);
6673 %}
6674 
6675 // REM
6676 
6677 // Integer Remainder
6678 // Register Remainder
6679 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
6680   match(Set dst (ModI src1 src2));
6681   effect(KILL tmp, KILL cr);
6682   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6683   // TODO: s390 port size(VARIABLE_SIZE);
6684   format %{ "MOD_checked   $dst,$src1,$src2" %}
6685   ins_encode %{
6686     Register a = $src1$$Register;
6687     Register b = $src2$$Register;
6688     Register t = $dst$$Register;
6689     assert_different_registers(t->successor(), b);
6690 
6691     Label do_div, done_div;
6692 
6693     if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
6694       (void) __ clear_reg(t, true, false);  // Does no harm. Operands are in other regs.
6695       if (VM_Version::has_CompareBranch()) {
6696         __ z_cij(b, -1, Assembler::bcondEqual, done_div);
6697       } else {
6698         __ z_chi(b, -1);
6699         __ z_bre(done_div);
6700       }
6701       __ z_lgfr(t->successor(), a);
6702       __ z_dsgfr(t/* t is even part of a register pair. */, b);
6703     } else {
6704       if (VM_Version::has_CompareBranch()) {
6705         __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
6706       } else {
6707         __ z_chi(b, -1);
6708         __ z_brne(do_div);
6709       }
6710       __ clear_reg(t, true, false);
6711       __ z_bru(done_div);
6712       __ bind(do_div);
6713       __ z_lgfr(t->successor(), a);
6714       __ z_dsgfr(t/* t is even part of a register pair. */, b);
6715     }
6716     __ bind(done_div);
6717   %}
6718   ins_pipe(pipe_class_dummy);
6719 %}
6720 
6721 // Immediate Remainder
6722 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
6723   match(Set dst (ModI src1 src2));
6724   effect(KILL tmp, KILL cr); // R0 is killed, too.
6725   ins_cost(3 * DEFAULT_COST);
6726   // TODO: s390 port size(VARIABLE_SIZE);
6727   format %{ "MOD_const  $dst,src1,$src2" %}
6728   ins_encode %{
6729     assert_different_registers($dst$$Register, $src1$$Register);
6730     assert_different_registers($dst$$Register->successor(), $src1$$Register);
6731     int divisor = $src2$$constant;
6732 
6733     if (divisor != -1) {
6734       __ z_lghi(Z_R0_scratch, divisor);
6735       __ z_lgfr($dst$$Register->successor(), $src1$$Register);
6736       __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
6737     } else {
6738       __ clear_reg($dst$$Register, true, false);
6739     }
6740   %}
6741   ins_pipe(pipe_class_dummy);
6742 %}
6743 
6744 // Register Long Remainder
6745 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
6746   match(Set dst (ModL src1 src2));
6747   effect(KILL src1, KILL cr); // R0 is killed, too.
6748   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
6749   // TODO: s390 port size(VARIABLE_SIZE);
6750   format %{ "MODG_checked   $dst,$src1,$src2" %}
6751   ins_encode %{
6752     Register a = $src1$$Register;
6753     Register b = $src2$$Register;
6754     Register t = $dst$$Register;
6755     assert(t->successor() == a, "(t,a) is an even-odd pair" );
6756 
6757     Label do_div, done_div;
6758     if (t->encoding() != b->encoding()) {
6759       (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
6760       if (VM_Version::has_CompareBranch()) {
6761         __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
6762       } else {
6763         __ z_cghi(b, -1);
6764         __ z_bre(done_div);
6765       }
6766       __ z_dsgr(t, b);
6767     } else {
6768       if (VM_Version::has_CompareBranch()) {
6769         __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
6770       } else {
6771         __ z_cghi(b, -1);
6772         __ z_brne(do_div);
6773       }
6774       __ clear_reg(t, true, false);
6775       __ z_bru(done_div);
6776       __ bind(do_div);
6777       __ z_dsgr(t, b);
6778     }
6779     __ bind(done_div);
6780   %}
6781   ins_pipe(pipe_class_dummy);
6782 %}
6783 
6784 // Register Long Remainder
6785 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
6786   match(Set dst (ModL src1 src2));
6787   effect(KILL tmp, KILL cr); // R0 is killed, too.
6788   ins_cost(3 * DEFAULT_COST);
6789   // TODO: s390 port size(VARIABLE_SIZE);
6790   format %{ "MODG_const  $dst,src1,$src2\t # long" %}
6791   ins_encode %{
6792     int divisor = $src2$$constant;
6793     if (divisor != -1) {
6794       __ z_lghi(Z_R0_scratch, divisor);
6795       __ z_lgr($dst$$Register->successor(), $src1$$Register);
6796       __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch);  // Instruction kills tmp.
6797     } else {
6798       __ clear_reg($dst$$Register, true, false);
6799     }
6800   %}
6801   ins_pipe(pipe_class_dummy);
6802 %}
6803 
6804 // SHIFT
6805 
6806 // Shift left logical
6807 
6808 // Register Shift Left variable
6809 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
6810   match(Set dst (LShiftI src nbits));
6811   effect(KILL cr); // R1 is killed, too.
6812   ins_cost(3 * DEFAULT_COST);
6813   size(14);
6814   format %{ "SLL     $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %}
6815   ins_encode %{
6816     __ z_lgr(Z_R1_scratch, $nbits$$Register);
6817     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6818     __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
6819   %}
6820   ins_pipe(pipe_class_dummy);
6821 %}
6822 
6823 // Register Shift Left Immediate
6824 // Constant shift count is masked in ideal graph already.
6825 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
6826   match(Set dst (LShiftI src nbits));
6827   size(6);
6828   format %{ "SLL     $dst,$src,$nbits\t # use RISC-like SLLG also for int" %}
6829   ins_encode %{
6830     int Nbit = $nbits$$constant;
6831     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6832     __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6833   %}
6834   ins_pipe(pipe_class_dummy);
6835 %}
6836 
6837 // Register Shift Left Immediate by 1bit
6838 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
6839   match(Set dst (LShiftI src nbits));
6840   predicate(PreferLAoverADD);
6841   ins_cost(DEFAULT_COST_LOW);
6842   size(4);
6843   format %{ "LA      $dst,#0($src,$src)\t # SLL by 1 (int)" %}
6844   ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
6845   ins_pipe(pipe_class_dummy);
6846 %}
6847 
6848 // Register Shift Left Long
6849 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
6850   match(Set dst (LShiftL src1 nbits));
6851   size(6);
6852   format %{ "SLLG    $dst,$src1,[$nbits]" %}
6853   opcode(SLLG_ZOPC);
6854   ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
6855   ins_pipe(pipe_class_dummy);
6856 %}
6857 
6858 // Register Shift Left Long Immediate
6859 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
6860   match(Set dst (LShiftL src1 nbits));
6861   size(6);
6862   format %{ "SLLG    $dst,$src1,$nbits" %}
6863   opcode(SLLG_ZOPC);
6864   ins_encode(z_rsyform_const(dst, src1, nbits));
6865   ins_pipe(pipe_class_dummy);
6866 %}
6867 
6868 // Register Shift Left Long Immediate by 1bit
6869 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
6870   match(Set dst (LShiftL src1 nbits));
6871   predicate(PreferLAoverADD);
6872   ins_cost(DEFAULT_COST_LOW);
6873   size(4);
6874   format %{ "LA      $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
6875   ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
6876   ins_pipe(pipe_class_dummy);
6877 %}
6878 
6879 // Shift right arithmetic
6880 
6881 // Register Arithmetic Shift Right
6882 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
6883   match(Set dst (RShiftI dst src));
6884   effect(KILL cr); // R1 is killed, too.
6885   ins_cost(3 * DEFAULT_COST);
6886   size(12);
6887   format %{ "SRA     $dst,[$src] & 31" %}
6888   ins_encode %{
6889     __ z_lgr(Z_R1_scratch, $src$$Register);
6890     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6891     __ z_sra($dst$$Register, 0, Z_R1_scratch);
6892   %}
6893   ins_pipe(pipe_class_dummy);
6894 %}
6895 
6896 // Register Arithmetic Shift Right Immediate
6897 // Constant shift count is masked in ideal graph already.
6898 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
6899   match(Set dst (RShiftI dst src));
6900   effect(KILL cr);
6901   size(4);
6902   format %{ "SRA     $dst,$src" %}
6903   ins_encode %{
6904     int Nbit = $src$$constant;
6905     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6906     __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6907   %}
6908   ins_pipe(pipe_class_dummy);
6909 %}
6910 
6911 // Register Arithmetic Shift Right Long
6912 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
6913   match(Set dst (RShiftL src1 src2));
6914   effect(KILL cr);
6915   size(6);
6916   format %{ "SRAG    $dst,$src1,[$src2]" %}
6917   opcode(SRAG_ZOPC);
6918   ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6919   ins_pipe(pipe_class_dummy);
6920 %}
6921 
6922 // Register Arithmetic Shift Right Long Immediate
6923 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
6924   match(Set dst (RShiftL src1 src2));
6925   effect(KILL cr);
6926   size(6);
6927   format %{ "SRAG    $dst,$src1,$src2" %}
6928   opcode(SRAG_ZOPC);
6929   ins_encode(z_rsyform_const(dst, src1, src2));
6930   ins_pipe(pipe_class_dummy);
6931 %}
6932 
6933 //  Shift right logical
6934 
6935 // Register Shift Right
6936 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
6937   match(Set dst (URShiftI dst src));
6938   effect(KILL cr); // R1 is killed, too.
6939   ins_cost(3 * DEFAULT_COST);
6940   size(12);
6941   format %{ "SRL     $dst,[$src] & 31" %}
6942   ins_encode %{
6943     __ z_lgr(Z_R1_scratch, $src$$Register);
6944     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
6945     __ z_srl($dst$$Register, 0, Z_R1_scratch);
6946   %}
6947   ins_pipe(pipe_class_dummy);
6948 %}
6949 
6950 // Register Shift Right Immediate
6951 // Constant shift count is masked in ideal graph already.
6952 instruct srlI_reg_imm(iRegI dst, immI src) %{
6953   match(Set dst (URShiftI dst src));
6954   size(4);
6955   format %{ "SRL     $dst,$src" %}
6956   ins_encode %{
6957     int Nbit = $src$$constant;
6958     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
6959     __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
6960   %}
6961   ins_pipe(pipe_class_dummy);
6962 %}
6963 
6964 // Register Shift Right Long
6965 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
6966   match(Set dst (URShiftL src1 src2));
6967   size(6);
6968   format %{ "SRLG    $dst,$src1,[$src2]" %}
6969   opcode(SRLG_ZOPC);
6970   ins_encode(z_rsyform_reg_reg(dst, src1, src2));
6971   ins_pipe(pipe_class_dummy);
6972 %}
6973 
6974 // Register Shift Right Long Immediate
6975 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
6976   match(Set dst (URShiftL src1 src2));
6977   size(6);
6978   format %{ "SRLG    $dst,$src1,$src2" %}
6979   opcode(SRLG_ZOPC);
6980   ins_encode(z_rsyform_const(dst, src1, src2));
6981   ins_pipe(pipe_class_dummy);
6982 %}
6983 
6984 // Register Shift Right Immediate with a CastP2X
6985 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
6986   match(Set dst (URShiftL (CastP2X src1) src2));
6987   size(6);
6988   format %{ "SRLG    $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
6989   opcode(SRLG_ZOPC);
6990   ins_encode(z_rsyform_const(dst, src1, src2));
6991   ins_pipe(pipe_class_dummy);
6992 %}
6993 
6994 //----------Rotate Instructions------------------------------------------------
6995 
6996 // Rotate left 32bit.
6997 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
6998   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
6999   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7000   size(6);
7001   format %{ "RLL     $dst,$src,$lshift\t # ROTL32" %}
7002   opcode(RLL_ZOPC);
7003   ins_encode(z_rsyform_const(dst, src, lshift));
7004   ins_pipe(pipe_class_dummy);
7005 %}
7006 
7007 // Rotate left 64bit.
7008 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
7009   match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
7010   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7011   size(6);
7012   format %{ "RLLG    $dst,$src,$lshift\t # ROTL64" %}
7013   opcode(RLLG_ZOPC);
7014   ins_encode(z_rsyform_const(dst, src, lshift));
7015   ins_pipe(pipe_class_dummy);
7016 %}
7017 
7018 // Rotate right 32bit.
7019 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
7020   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
7021   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
7022   // TODO: s390 port size(FIXED_SIZE);
7023   format %{ "RLL     $dst,$src,$rshift\t # ROTR32" %}
7024   opcode(RLL_ZOPC);
7025   ins_encode(z_rsyform_const(dst, src, rshift));
7026   ins_pipe(pipe_class_dummy);
7027 %}
7028 
7029 // Rotate right 64bit.
7030 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
7031   match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
7032   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
7033   // TODO: s390 port size(FIXED_SIZE);
7034   format %{ "RLLG    $dst,$src,$rshift\t # ROTR64" %}
7035   opcode(RLLG_ZOPC);
7036   ins_encode(z_rsyform_const(dst, src, rshift));
7037   ins_pipe(pipe_class_dummy);
7038 %}
7039 
7040 
7041 //----------Overflow Math Instructions-----------------------------------------
7042 
7043 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7044   match(Set cr (OverflowAddI op1 op2));
7045   effect(DEF cr, USE op1, USE op2);
7046   // TODO: s390 port size(FIXED_SIZE);
7047   format %{ "AR      $op1,$op2\t # overflow check int" %}
7048   ins_encode %{
7049     __ z_lr(Z_R0_scratch, $op1$$Register);
7050     __ z_ar(Z_R0_scratch, $op2$$Register);
7051   %}
7052   ins_pipe(pipe_class_dummy);
7053 %}
7054 
7055 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7056   match(Set cr (OverflowAddI op1 op2));
7057   effect(DEF cr, USE op1, USE op2);
7058   // TODO: s390 port size(VARIABLE_SIZE);
7059   format %{ "AR      $op1,$op2\t # overflow check int" %}
7060   ins_encode %{
7061     __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7062     __ z_ar(Z_R0_scratch, $op1$$Register);
7063   %}
7064   ins_pipe(pipe_class_dummy);
7065 %}
7066 
7067 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7068   match(Set cr (OverflowAddL op1 op2));
7069   effect(DEF cr, USE op1, USE op2);
7070   // TODO: s390 port size(FIXED_SIZE);
7071   format %{ "AGR     $op1,$op2\t # overflow check long" %}
7072   ins_encode %{
7073     __ z_lgr(Z_R0_scratch, $op1$$Register);
7074     __ z_agr(Z_R0_scratch, $op2$$Register);
7075   %}
7076   ins_pipe(pipe_class_dummy);
7077 %}
7078 
7079 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7080   match(Set cr (OverflowAddL op1 op2));
7081   effect(DEF cr, USE op1, USE op2);
7082   // TODO: s390 port size(VARIABLE_SIZE);
7083   format %{ "AGR     $op1,$op2\t # overflow check long" %}
7084   ins_encode %{
7085     __ load_const_optimized(Z_R0_scratch, $op2$$constant);
7086     __ z_agr(Z_R0_scratch, $op1$$Register);
7087   %}
7088   ins_pipe(pipe_class_dummy);
7089 %}
7090 
7091 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
7092   match(Set cr (OverflowSubI op1 op2));
7093   effect(DEF cr, USE op1, USE op2);
7094   // TODO: s390 port size(FIXED_SIZE);
7095   format %{ "SR      $op1,$op2\t # overflow check int" %}
7096   ins_encode %{
7097     __ z_lr(Z_R0_scratch, $op1$$Register);
7098     __ z_sr(Z_R0_scratch, $op2$$Register);
7099   %}
7100   ins_pipe(pipe_class_dummy);
7101 %}
7102 
7103 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
7104   match(Set cr (OverflowSubI op1 op2));
7105   effect(DEF cr, USE op1, USE op2);
7106   // TODO: s390 port size(VARIABLE_SIZE);
7107   format %{ "SR      $op1,$op2\t # overflow check int" %}
7108   ins_encode %{
7109     __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7110     __ z_lr(Z_R0_scratch, $op1$$Register);
7111     __ z_sr(Z_R0_scratch, Z_R1_scratch);
7112   %}
7113   ins_pipe(pipe_class_dummy);
7114 %}
7115 
7116 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
7117   match(Set cr (OverflowSubL op1 op2));
7118   effect(DEF cr, USE op1, USE op2);
7119   // TODO: s390 port size(FIXED_SIZE);
7120   format %{ "SGR     $op1,$op2\t # overflow check long" %}
7121   ins_encode %{
7122     __ z_lgr(Z_R0_scratch, $op1$$Register);
7123     __ z_sgr(Z_R0_scratch, $op2$$Register);
7124   %}
7125   ins_pipe(pipe_class_dummy);
7126 %}
7127 
7128 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
7129   match(Set cr (OverflowSubL op1 op2));
7130   effect(DEF cr, USE op1, USE op2);
7131   // TODO: s390 port size(VARIABLE_SIZE);
7132   format %{ "SGR     $op1,$op2\t # overflow check long" %}
7133   ins_encode %{
7134     __ load_const_optimized(Z_R1_scratch, $op2$$constant);
7135     __ z_lgr(Z_R0_scratch, $op1$$Register);
7136     __ z_sgr(Z_R0_scratch, Z_R1_scratch);
7137   %}
7138   ins_pipe(pipe_class_dummy);
7139 %}
7140 
7141 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
7142   match(Set cr (OverflowSubI zero op2));
7143   effect(DEF cr, USE op2);
7144   format %{ "NEG    $op2\t # overflow check int" %}
7145   ins_encode %{
7146     __ clear_reg(Z_R0_scratch, false, false);
7147     __ z_sr(Z_R0_scratch, $op2$$Register);
7148   %}
7149   ins_pipe(pipe_class_dummy);
7150 %}
7151 
7152 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
7153   match(Set cr (OverflowSubL zero op2));
7154   effect(DEF cr, USE op2);
7155   format %{ "NEGG    $op2\t # overflow check long" %}
7156   ins_encode %{
7157     __ clear_reg(Z_R0_scratch, true, false);
7158     __ z_sgr(Z_R0_scratch, $op2$$Register);
7159   %}
7160   ins_pipe(pipe_class_dummy);
7161 %}
7162 
7163 // No intrinsics for multiplication, since there is no easy way
7164 // to check for overflow.
7165 
7166 
7167 //----------Floating Point Arithmetic Instructions-----------------------------
7168 
7169 //  ADD
7170 
7171 //  Add float single precision
7172 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
7173   match(Set dst (AddF dst src));
7174   effect(KILL cr);
7175   ins_cost(ALU_REG_COST);
7176   size(4);
7177   format %{ "AEBR     $dst,$src" %}
7178   opcode(AEBR_ZOPC);
7179   ins_encode(z_rreform(dst, src));
7180   ins_pipe(pipe_class_dummy);
7181 %}
7182 
7183 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7184   match(Set dst (AddF dst (LoadF src)));
7185   effect(KILL cr);
7186   ins_cost(ALU_MEMORY_COST);
7187   size(6);
7188   format %{ "AEB      $dst,$src\t # floatMemory" %}
7189   opcode(AEB_ZOPC);
7190   ins_encode(z_form_rt_memFP(dst, src));
7191   ins_pipe(pipe_class_dummy);
7192 %}
7193 
7194 // Add float double precision
7195 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
7196   match(Set dst (AddD dst src));
7197   effect(KILL cr);
7198   ins_cost(ALU_REG_COST);
7199   size(4);
7200   format %{ "ADBR     $dst,$src" %}
7201   opcode(ADBR_ZOPC);
7202   ins_encode(z_rreform(dst, src));
7203   ins_pipe(pipe_class_dummy);
7204 %}
7205 
7206 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7207   match(Set dst (AddD dst (LoadD src)));
7208   effect(KILL cr);
7209   ins_cost(ALU_MEMORY_COST);
7210   size(6);
7211   format %{ "ADB      $dst,$src\t # doubleMemory" %}
7212   opcode(ADB_ZOPC);
7213   ins_encode(z_form_rt_memFP(dst, src));
7214   ins_pipe(pipe_class_dummy);
7215 %}
7216 
7217 // SUB
7218 
7219 // Sub float single precision
7220 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
7221   match(Set dst (SubF dst src));
7222   effect(KILL cr);
7223   ins_cost(ALU_REG_COST);
7224   size(4);
7225   format %{ "SEBR     $dst,$src" %}
7226   opcode(SEBR_ZOPC);
7227   ins_encode(z_rreform(dst, src));
7228   ins_pipe(pipe_class_dummy);
7229 %}
7230 
7231 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
7232   match(Set dst (SubF dst (LoadF src)));
7233   effect(KILL cr);
7234   ins_cost(ALU_MEMORY_COST);
7235   size(6);
7236   format %{ "SEB      $dst,$src\t # floatMemory" %}
7237   opcode(SEB_ZOPC);
7238   ins_encode(z_form_rt_memFP(dst, src));
7239   ins_pipe(pipe_class_dummy);
7240 %}
7241 
7242 //  Sub float double precision
7243 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
7244   match(Set dst (SubD dst src));
7245   effect(KILL cr);
7246   ins_cost(ALU_REG_COST);
7247   size(4);
7248   format %{ "SDBR     $dst,$src" %}
7249   opcode(SDBR_ZOPC);
7250   ins_encode(z_rreform(dst, src));
7251   ins_pipe(pipe_class_dummy);
7252 %}
7253 
7254 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
7255   match(Set dst (SubD dst (LoadD src)));
7256   effect(KILL cr);
7257   ins_cost(ALU_MEMORY_COST);
7258   size(6);
7259   format %{ "SDB      $dst,$src\t # doubleMemory" %}
7260   opcode(SDB_ZOPC);
7261   ins_encode(z_form_rt_memFP(dst, src));
7262   ins_pipe(pipe_class_dummy);
7263 %}
7264 
7265 // MUL
7266 
7267 // Mul float single precision
7268 instruct mulF_reg_reg(regF dst, regF src) %{
7269   match(Set dst (MulF dst src));
7270   // CC unchanged by MUL.
7271   ins_cost(ALU_REG_COST);
7272   size(4);
7273   format %{ "MEEBR    $dst,$src" %}
7274   opcode(MEEBR_ZOPC);
7275   ins_encode(z_rreform(dst, src));
7276   ins_pipe(pipe_class_dummy);
7277 %}
7278 
7279 instruct mulF_reg_mem(regF dst, memoryRX src)%{
7280   match(Set dst (MulF dst (LoadF src)));
7281   // CC unchanged by MUL.
7282   ins_cost(ALU_MEMORY_COST);
7283   size(6);
7284   format %{ "MEEB     $dst,$src\t # floatMemory" %}
7285   opcode(MEEB_ZOPC);
7286   ins_encode(z_form_rt_memFP(dst, src));
7287   ins_pipe(pipe_class_dummy);
7288 %}
7289 
7290 //  Mul float double precision
7291 instruct mulD_reg_reg(regD dst, regD src) %{
7292   match(Set dst (MulD dst src));
7293   // CC unchanged by MUL.
7294   ins_cost(ALU_REG_COST);
7295   size(4);
7296   format %{ "MDBR     $dst,$src" %}
7297   opcode(MDBR_ZOPC);
7298   ins_encode(z_rreform(dst, src));
7299   ins_pipe(pipe_class_dummy);
7300 %}
7301 
7302 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7303   match(Set dst (MulD dst (LoadD src)));
7304   // CC unchanged by MUL.
7305   ins_cost(ALU_MEMORY_COST);
7306   size(6);
7307   format %{ "MDB      $dst,$src\t # doubleMemory" %}
7308   opcode(MDB_ZOPC);
7309   ins_encode(z_form_rt_memFP(dst, src));
7310   ins_pipe(pipe_class_dummy);
7311 %}
7312 
7313 // Multiply-Accumulate
7314 // src1 * src2 + dst
7315 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
7316   match(Set dst (FmaF dst (Binary src1 src2)));
7317   // CC unchanged by MUL-ADD.
7318   ins_cost(ALU_REG_COST);
7319   size(4);
7320   format %{ "MAEBR    $dst, $src1, $src2" %}
7321   ins_encode %{
7322     __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7323   %}
7324   ins_pipe(pipe_class_dummy);
7325 %}
7326 
7327 // src1 * src2 + dst
7328 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
7329   match(Set dst (FmaD dst (Binary src1 src2)));
7330   // CC unchanged by MUL-ADD.
7331   ins_cost(ALU_REG_COST);
7332   size(4);
7333   format %{ "MADBR    $dst, $src1, $src2" %}
7334   ins_encode %{
7335     __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7336   %}
7337   ins_pipe(pipe_class_dummy);
7338 %}
7339 
7340 // src1 * src2 - dst
7341 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
7342   match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
7343   // CC unchanged by MUL-SUB.
7344   ins_cost(ALU_REG_COST);
7345   size(4);
7346   format %{ "MSEBR    $dst, $src1, $src2" %}
7347   ins_encode %{
7348     __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7349   %}
7350   ins_pipe(pipe_class_dummy);
7351 %}
7352 
7353 // src1 * src2 - dst
7354 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
7355   match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
7356   // CC unchanged by MUL-SUB.
7357   ins_cost(ALU_REG_COST);
7358   size(4);
7359   format %{ "MSDBR    $dst, $src1, $src2" %}
7360   ins_encode %{
7361     __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7362   %}
7363   ins_pipe(pipe_class_dummy);
7364 %}
7365 
7366 // src1 * src2 + dst
7367 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7368   match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
7369   // CC unchanged by MUL-ADD.
7370   ins_cost(ALU_MEMORY_COST);
7371   size(6);
7372   format %{ "MAEB     $dst, $src1, $src2" %}
7373   ins_encode %{
7374     __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
7375               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7376   %}
7377   ins_pipe(pipe_class_dummy);
7378 %}
7379 
7380 // src1 * src2 + dst
7381 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7382   match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
7383   // CC unchanged by MUL-ADD.
7384   ins_cost(ALU_MEMORY_COST);
7385   size(6);
7386   format %{ "MADB     $dst, $src1, $src2" %}
7387   ins_encode %{
7388     __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
7389               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7390   %}
7391   ins_pipe(pipe_class_dummy);
7392 %}
7393 
7394 // src1 * src2 - dst
7395 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7396   match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
7397   // CC unchanged by MUL-SUB.
7398   ins_cost(ALU_MEMORY_COST);
7399   size(6);
7400   format %{ "MSEB     $dst, $src1, $src2" %}
7401   ins_encode %{
7402     __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
7403               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7404   %}
7405   ins_pipe(pipe_class_dummy);
7406 %}
7407 
7408 // src1 * src2 - dst
7409 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7410   match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
7411   // CC unchanged by MUL-SUB.
7412   ins_cost(ALU_MEMORY_COST);
7413   size(6);
7414   format %{ "MSDB    $dst, $src1, $src2" %}
7415   ins_encode %{
7416     __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
7417               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7418   %}
7419   ins_pipe(pipe_class_dummy);
7420 %}
7421 
7422 // src1 * src2 + dst
7423 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7424   match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
7425   // CC unchanged by MUL-ADD.
7426   ins_cost(ALU_MEMORY_COST);
7427   size(6);
7428   format %{ "MAEB     $dst, $src1, $src2" %}
7429   ins_encode %{
7430     __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
7431               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7432   %}
7433   ins_pipe(pipe_class_dummy);
7434 %}
7435 
7436 // src1 * src2 + dst
7437 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7438   match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
7439   // CC unchanged by MUL-ADD.
7440   ins_cost(ALU_MEMORY_COST);
7441   size(6);
7442   format %{ "MADB     $dst, $src1, $src2" %}
7443   ins_encode %{
7444     __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
7445               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7446   %}
7447   ins_pipe(pipe_class_dummy);
7448 %}
7449 
7450 // src1 * src2 - dst
7451 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7452   match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
7453   // CC unchanged by MUL-SUB.
7454   ins_cost(ALU_MEMORY_COST);
7455   size(6);
7456   format %{ "MSEB     $dst, $src1, $src2" %}
7457   ins_encode %{
7458     __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
7459               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7460   %}
7461   ins_pipe(pipe_class_dummy);
7462 %}
7463 
7464 // src1 * src2 - dst
7465 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7466   match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
7467   // CC unchanged by MUL-SUB.
7468   ins_cost(ALU_MEMORY_COST);
7469   size(6);
7470   format %{ "MSDB    $dst, $src1, $src2" %}
7471   ins_encode %{
7472     __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
7473               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7474   %}
7475   ins_pipe(pipe_class_dummy);
7476 %}
7477 
7478 //  DIV
7479 
7480 //  Div float single precision
7481 instruct divF_reg_reg(regF dst, regF src) %{
7482   match(Set dst (DivF dst src));
7483   // CC unchanged by DIV.
7484   ins_cost(ALU_REG_COST);
7485   size(4);
7486   format %{ "DEBR     $dst,$src" %}
7487   opcode(DEBR_ZOPC);
7488   ins_encode(z_rreform(dst, src));
7489   ins_pipe(pipe_class_dummy);
7490 %}
7491 
7492 instruct divF_reg_mem(regF dst, memoryRX src)%{
7493   match(Set dst (DivF dst (LoadF src)));
7494   // CC unchanged by DIV.
7495   ins_cost(ALU_MEMORY_COST);
7496   size(6);
7497   format %{ "DEB      $dst,$src\t # floatMemory" %}
7498   opcode(DEB_ZOPC);
7499   ins_encode(z_form_rt_memFP(dst, src));
7500   ins_pipe(pipe_class_dummy);
7501 %}
7502 
7503 //  Div float double precision
7504 instruct divD_reg_reg(regD dst, regD src) %{
7505   match(Set dst (DivD dst src));
7506   // CC unchanged by DIV.
7507   ins_cost(ALU_REG_COST);
7508   size(4);
7509   format %{ "DDBR     $dst,$src" %}
7510   opcode(DDBR_ZOPC);
7511   ins_encode(z_rreform(dst, src));
7512   ins_pipe(pipe_class_dummy);
7513 %}
7514 
7515 instruct divD_reg_mem(regD dst, memoryRX src)%{
7516   match(Set dst (DivD dst (LoadD src)));
7517   // CC unchanged by DIV.
7518   ins_cost(ALU_MEMORY_COST);
7519   size(6);
7520   format %{ "DDB      $dst,$src\t # doubleMemory" %}
7521   opcode(DDB_ZOPC);
7522   ins_encode(z_form_rt_memFP(dst, src));
7523   ins_pipe(pipe_class_dummy);
7524 %}
7525 
7526 // ABS
7527 
7528 // Absolute float single precision
7529 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
7530   match(Set dst (AbsF src));
7531   effect(KILL cr);
7532   size(4);
7533   format %{ "LPEBR    $dst,$src\t float" %}
7534   opcode(LPEBR_ZOPC);
7535   ins_encode(z_rreform(dst, src));
7536   ins_pipe(pipe_class_dummy);
7537 %}
7538 
7539 // Absolute float double precision
7540 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
7541   match(Set dst (AbsD src));
7542   effect(KILL cr);
7543   size(4);
7544   format %{ "LPDBR    $dst,$src\t double" %}
7545   opcode(LPDBR_ZOPC);
7546   ins_encode(z_rreform(dst, src));
7547   ins_pipe(pipe_class_dummy);
7548 %}
7549 
7550 //  NEG(ABS)
7551 
7552 // Negative absolute float single precision
7553 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
7554   match(Set dst (NegF (AbsF src)));
7555   effect(KILL cr);
7556   size(4);
7557   format %{ "LNEBR    $dst,$src\t float" %}
7558   opcode(LNEBR_ZOPC);
7559   ins_encode(z_rreform(dst, src));
7560   ins_pipe(pipe_class_dummy);
7561 %}
7562 
7563 // Negative absolute float double precision
7564 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
7565   match(Set dst (NegD (AbsD src)));
7566   effect(KILL cr);
7567   size(4);
7568   format %{ "LNDBR    $dst,$src\t double" %}
7569   opcode(LNDBR_ZOPC);
7570   ins_encode(z_rreform(dst, src));
7571   ins_pipe(pipe_class_dummy);
7572 %}
7573 
7574 // NEG
7575 
7576 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
7577   match(Set dst (NegF src));
7578   effect(KILL cr);
7579   size(4);
7580   format %{ "NegF     $dst,$src\t float" %}
7581   ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
7582   ins_pipe(pipe_class_dummy);
7583 %}
7584 
7585 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
7586   match(Set dst (NegD src));
7587   effect(KILL cr);
7588   size(4);
7589   format %{ "NegD     $dst,$src\t double" %}
7590   ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
7591   ins_pipe(pipe_class_dummy);
7592 %}
7593 
7594 // SQRT
7595 
7596 // Sqrt float precision
7597 instruct sqrtF_reg(regF dst, regF src) %{
7598   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7599   // CC remains unchanged.
7600   ins_cost(ALU_REG_COST);
7601   size(4);
7602   format %{ "SQEBR    $dst,$src" %}
7603   opcode(SQEBR_ZOPC);
7604   ins_encode(z_rreform(dst, src));
7605   ins_pipe(pipe_class_dummy);
7606 %}
7607 
7608 // Sqrt double precision
7609 instruct sqrtD_reg(regD dst, regD src) %{
7610   match(Set dst (SqrtD src));
7611   // CC remains unchanged.
7612   ins_cost(ALU_REG_COST);
7613   size(4);
7614   format %{ "SQDBR    $dst,$src" %}
7615   opcode(SQDBR_ZOPC);
7616   ins_encode(z_rreform(dst, src));
7617   ins_pipe(pipe_class_dummy);
7618 %}
7619 
7620 instruct sqrtF_mem(regF dst, memoryRX src) %{
7621   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7622   // CC remains unchanged.
7623   ins_cost(ALU_MEMORY_COST);
7624   size(6);
7625   format %{ "SQEB     $dst,$src\t # floatMemory" %}
7626   opcode(SQEB_ZOPC);
7627   ins_encode(z_form_rt_memFP(dst, src));
7628   ins_pipe(pipe_class_dummy);
7629 %}
7630 
7631 instruct sqrtD_mem(regD dst, memoryRX src) %{
7632   match(Set dst (SqrtD src));
7633   // CC remains unchanged.
7634   ins_cost(ALU_MEMORY_COST);
7635   // TODO: s390 port size(FIXED_SIZE);
7636   format %{ "SQDB     $dst,$src\t # doubleMemory" %}
7637   opcode(SQDB_ZOPC);
7638   ins_encode(z_form_rt_memFP(dst, src));
7639   ins_pipe(pipe_class_dummy);
7640 %}
7641 
7642 //----------Logical Instructions-----------------------------------------------
7643 
7644 // Register And
7645 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7646   match(Set dst (AndI dst src));
7647   effect(KILL cr);
7648   ins_cost(DEFAULT_COST_LOW);
7649   size(2);
7650   format %{ "NR      $dst,$src\t # int" %}
7651   opcode(NR_ZOPC);
7652   ins_encode(z_rrform(dst, src));
7653   ins_pipe(pipe_class_dummy);
7654 %}
7655 
7656 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7657   match(Set dst (AndI dst (LoadI src)));
7658   effect(KILL cr);
7659   ins_cost(MEMORY_REF_COST);
7660   // TODO: s390 port size(VARIABLE_SIZE);
7661   format %{ "N(Y)    $dst, $src\t # int" %}
7662   opcode(NY_ZOPC, N_ZOPC);
7663   ins_encode(z_form_rt_mem_opt(dst, src));
7664   ins_pipe(pipe_class_dummy);
7665 %}
7666 
7667 // Immediate And
7668 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7669   match(Set dst (AndI dst src));
7670   effect(KILL cr);
7671   ins_cost(DEFAULT_COST_HIGH);
7672   size(6);
7673   format %{ "NILF    $dst,$src" %}
7674   opcode(NILF_ZOPC);
7675   ins_encode(z_rilform_unsigned(dst, src));
7676   ins_pipe(pipe_class_dummy);
7677 %}
7678 
7679 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
7680   match(Set dst (AndI dst src));
7681   effect(KILL cr);
7682   ins_cost(DEFAULT_COST);
7683   size(4);
7684   format %{ "NILH    $dst,$src" %}
7685   ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7686   ins_pipe(pipe_class_dummy);
7687 %}
7688 
7689 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
7690   match(Set dst (AndI dst src));
7691   effect(KILL cr);
7692   ins_cost(DEFAULT_COST);
7693   size(4);
7694   format %{ "NILL    $dst,$src" %}
7695   ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7696   ins_pipe(pipe_class_dummy);
7697 %}
7698 
7699 // Register And Long
7700 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7701   match(Set dst (AndL dst src));
7702   effect(KILL cr);
7703   ins_cost(DEFAULT_COST);
7704   size(4);
7705   format %{ "NGR     $dst,$src\t # long" %}
7706   opcode(NGR_ZOPC);
7707   ins_encode(z_rreform(dst, src));
7708   ins_pipe(pipe_class_dummy);
7709 %}
7710 
7711 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7712   match(Set dst (AndL dst (LoadL src)));
7713   effect(KILL cr);
7714   ins_cost(MEMORY_REF_COST);
7715   size(Z_DISP3_SIZE);
7716   format %{ "NG      $dst, $src\t # long" %}
7717   opcode(NG_ZOPC, NG_ZOPC);
7718   ins_encode(z_form_rt_mem_opt(dst, src));
7719   ins_pipe(pipe_class_dummy);
7720 %}
7721 
7722 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
7723   match(Set dst (AndL dst src));
7724   effect(KILL cr);
7725   ins_cost(DEFAULT_COST);
7726   size(4);
7727   format %{ "NILL    $dst,$src\t # long" %}
7728   ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
7729   ins_pipe(pipe_class_dummy);
7730 %}
7731 
7732 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
7733   match(Set dst (AndL dst src));
7734   effect(KILL cr);
7735   ins_cost(DEFAULT_COST);
7736   size(4);
7737   format %{ "NILH    $dst,$src\t # long" %}
7738   ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
7739   ins_pipe(pipe_class_dummy);
7740 %}
7741 
7742 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
7743   match(Set dst (AndL dst src));
7744   effect(KILL cr);
7745   ins_cost(DEFAULT_COST);
7746   size(4);
7747   format %{ "NIHL    $dst,$src\t # long" %}
7748   ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
7749   ins_pipe(pipe_class_dummy);
7750 %}
7751 
7752 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
7753   match(Set dst (AndL dst src));
7754   effect(KILL cr);
7755   ins_cost(DEFAULT_COST);
7756   size(4);
7757   format %{ "NIHH    $dst,$src\t # long" %}
7758   ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
7759   ins_pipe(pipe_class_dummy);
7760 %}
7761 
7762 //  OR
7763 
7764 // Or Instructions
7765 // Register Or
7766 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7767   match(Set dst (OrI dst src));
7768   effect(KILL cr);
7769   size(2);
7770   format %{ "OR      $dst,$src" %}
7771   opcode(OR_ZOPC);
7772   ins_encode(z_rrform(dst, src));
7773   ins_pipe(pipe_class_dummy);
7774 %}
7775 
7776 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7777   match(Set dst (OrI dst (LoadI src)));
7778   effect(KILL cr);
7779   ins_cost(MEMORY_REF_COST);
7780   // TODO: s390 port size(VARIABLE_SIZE);
7781   format %{ "O(Y)    $dst, $src\t # int" %}
7782   opcode(OY_ZOPC, O_ZOPC);
7783   ins_encode(z_form_rt_mem_opt(dst, src));
7784   ins_pipe(pipe_class_dummy);
7785 %}
7786 
7787 // Immediate Or
7788 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
7789   match(Set dst (OrI dst con));
7790   effect(KILL cr);
7791   size(4);
7792   format %{ "OILL    $dst,$con" %}
7793   opcode(OILL_ZOPC);
7794   ins_encode(z_riform_unsigned(dst,con));
7795   ins_pipe(pipe_class_dummy);
7796 %}
7797 
7798 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
7799   match(Set dst (OrI dst con));
7800   effect(KILL cr);
7801   ins_cost(DEFAULT_COST_HIGH);
7802   size(6);
7803   format %{ "OILF    $dst,$con" %}
7804   opcode(OILF_ZOPC);
7805   ins_encode(z_rilform_unsigned(dst,con));
7806   ins_pipe(pipe_class_dummy);
7807 %}
7808 
7809 // Register Or Long
7810 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7811   match(Set dst (OrL dst src));
7812   effect(KILL cr);
7813   ins_cost(DEFAULT_COST);
7814   size(4);
7815   format %{ "OGR      $dst,$src\t # long" %}
7816   opcode(OGR_ZOPC);
7817   ins_encode(z_rreform(dst, src));
7818   ins_pipe(pipe_class_dummy);
7819 %}
7820 
7821 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7822   match(Set dst (OrL dst (LoadL src)));
7823   effect(KILL cr);
7824   ins_cost(MEMORY_REF_COST);
7825   size(Z_DISP3_SIZE);
7826   format %{ "OG      $dst, $src\t # long" %}
7827   opcode(OG_ZOPC, OG_ZOPC);
7828   ins_encode(z_form_rt_mem_opt(dst, src));
7829   ins_pipe(pipe_class_dummy);
7830 %}
7831 
7832 // Immediate Or long
7833 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
7834   match(Set dst (OrL dst con));
7835   effect(KILL cr);
7836   ins_cost(DEFAULT_COST);
7837   size(4);
7838   format %{ "OILL    $dst,$con\t # long" %}
7839   opcode(OILL_ZOPC);
7840   ins_encode(z_riform_unsigned(dst,con));
7841   ins_pipe(pipe_class_dummy);
7842 %}
7843 
7844 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
7845   match(Set dst (OrI dst con));
7846   effect(KILL cr);
7847   ins_cost(DEFAULT_COST_HIGH);
7848   // TODO: s390 port size(FIXED_SIZE);
7849   format %{ "OILF    $dst,$con\t # long" %}
7850   opcode(OILF_ZOPC);
7851   ins_encode(z_rilform_unsigned(dst,con));
7852   ins_pipe(pipe_class_dummy);
7853 %}
7854 
7855 // XOR
7856 
7857 // Register Xor
7858 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7859   match(Set dst (XorI dst src));
7860   effect(KILL cr);
7861   size(2);
7862   format %{ "XR      $dst,$src" %}
7863   opcode(XR_ZOPC);
7864   ins_encode(z_rrform(dst, src));
7865   ins_pipe(pipe_class_dummy);
7866 %}
7867 
7868 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
7869   match(Set dst (XorI dst (LoadI src)));
7870   effect(KILL cr);
7871   ins_cost(MEMORY_REF_COST);
7872   // TODO: s390 port size(VARIABLE_SIZE);
7873   format %{ "X(Y)    $dst, $src\t # int" %}
7874   opcode(XY_ZOPC, X_ZOPC);
7875   ins_encode(z_form_rt_mem_opt(dst, src));
7876   ins_pipe(pipe_class_dummy);
7877 %}
7878 
7879 // Immediate Xor
7880 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
7881   match(Set dst (XorI dst src));
7882   effect(KILL cr);
7883   ins_cost(DEFAULT_COST_HIGH);
7884   size(6);
7885   format %{ "XILF    $dst,$src" %}
7886   opcode(XILF_ZOPC);
7887   ins_encode(z_rilform_unsigned(dst, src));
7888   ins_pipe(pipe_class_dummy);
7889 %}
7890 
7891 // Register Xor Long
7892 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
7893   match(Set dst (XorL dst src));
7894   effect(KILL cr);
7895   ins_cost(DEFAULT_COST);
7896   size(4);
7897   format %{ "XGR     $dst,$src\t # long" %}
7898   opcode(XGR_ZOPC);
7899   ins_encode(z_rreform(dst, src));
7900   ins_pipe(pipe_class_dummy);
7901 %}
7902 
7903 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
7904   match(Set dst (XorL dst (LoadL src)));
7905   effect(KILL cr);
7906   ins_cost(MEMORY_REF_COST);
7907   size(Z_DISP3_SIZE);
7908   format %{ "XG      $dst, $src\t # long" %}
7909   opcode(XG_ZOPC, XG_ZOPC);
7910   ins_encode(z_form_rt_mem_opt(dst, src));
7911   ins_pipe(pipe_class_dummy);
7912 %}
7913 
7914 // Immediate Xor Long
7915 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
7916   match(Set dst (XorL dst con));
7917   effect(KILL cr);
7918   ins_cost(DEFAULT_COST_HIGH);
7919   size(6);
7920   format %{ "XILF    $dst,$con\t # long" %}
7921   opcode(XILF_ZOPC);
7922   ins_encode(z_rilform_unsigned(dst,con));
7923   ins_pipe(pipe_class_dummy);
7924 %}
7925 
7926 //----------Convert to Boolean-------------------------------------------------
7927 
7928 // Convert integer to boolean.
7929 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
7930   match(Set dst (Conv2B src));
7931   effect(KILL cr);
7932   ins_cost(3 * DEFAULT_COST);
7933   size(6);
7934   format %{ "convI2B $dst,$src" %}
7935   ins_encode %{
7936     __ z_lnr($dst$$Register, $src$$Register);  // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
7937     __ z_srl($dst$$Register, 31);              // Rdst := sign(Rdest)
7938   %}
7939   ins_pipe(pipe_class_dummy);
7940 %}
7941 
7942 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
7943   match(Set dst (Conv2B src));
7944   effect(KILL cr);
7945   ins_cost(3 * DEFAULT_COST);
7946   size(10);
7947   format %{ "convP2B $dst,$src" %}
7948   ins_encode %{
7949     __ z_lngr($dst$$Register, $src$$Register);     // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
7950     __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
7951   %}
7952   ins_pipe(pipe_class_dummy);
7953 %}
7954 
7955 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
7956   match(Set dst (CmpLTMask dst src));
7957   effect(KILL cr);
7958   ins_cost(2 * DEFAULT_COST);
7959   size(18);
7960   format %{ "Set $dst CmpLTMask $dst,$src" %}
7961   ins_encode %{
7962     // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
7963     __ z_lgfr(Z_R0_scratch, $src$$Register);
7964     __ z_lgfr($dst$$Register, $dst$$Register);
7965     __ z_sgr($dst$$Register, Z_R0_scratch);
7966     __ z_srag($dst$$Register, $dst$$Register, 63);
7967   %}
7968   ins_pipe(pipe_class_dummy);
7969 %}
7970 
7971 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
7972   match(Set dst (CmpLTMask dst zero));
7973   effect(KILL cr);
7974   ins_cost(DEFAULT_COST);
7975   size(4);
7976   format %{ "Set $dst CmpLTMask $dst,$zero" %}
7977   ins_encode %{ __ z_sra($dst$$Register, 31); %}
7978   ins_pipe(pipe_class_dummy);
7979 %}
7980 
7981 
7982 //----------Arithmetic Conversion Instructions---------------------------------
7983 // The conversions operations are all Alpha sorted. Please keep it that way!
7984 
7985 instruct convD2F_reg(regF dst, regD src) %{
7986   match(Set dst (ConvD2F src));
7987   // CC remains unchanged.
7988   size(4);
7989   format %{ "LEDBR   $dst,$src" %}
7990   opcode(LEDBR_ZOPC);
7991   ins_encode(z_rreform(dst, src));
7992   ins_pipe(pipe_class_dummy);
7993 %}
7994 
7995 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
7996   match(Set dst (ConvF2I src));
7997   effect(KILL cr);
7998   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
7999   size(16);
8000   format %{ "convF2I  $dst,$src" %}
8001   ins_encode %{
8002     Label done;
8003     __ clear_reg($dst$$Register, false, false);  // Initialize with result for unordered: 0.
8004     __ z_cebr($src$$FloatRegister, $src$$FloatRegister);   // Round.
8005     __ z_brno(done);                             // Result is zero if unordered argument.
8006     __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8007     __ bind(done);
8008   %}
8009   ins_pipe(pipe_class_dummy);
8010 %}
8011 
8012 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
8013   match(Set dst (ConvD2I src));
8014   effect(KILL cr);
8015   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8016   size(16);
8017   format %{ "convD2I  $dst,$src" %}
8018   ins_encode %{
8019     Label done;
8020     __ clear_reg($dst$$Register, false, false);  // Initialize with result for unordered: 0.
8021     __ z_cdbr($src$$FloatRegister, $src$$FloatRegister);   // Round.
8022     __ z_brno(done);                             // Result is zero if unordered argument.
8023     __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8024     __ bind(done);
8025   %}
8026   ins_pipe(pipe_class_dummy);
8027 %}
8028 
8029 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
8030   match(Set dst (ConvF2L src));
8031   effect(KILL cr);
8032   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8033   size(16);
8034   format %{ "convF2L  $dst,$src" %}
8035   ins_encode %{
8036     Label done;
8037     __ clear_reg($dst$$Register, true, false);  // Initialize with result for unordered: 0.
8038     __ z_cebr($src$$FloatRegister, $src$$FloatRegister);   // Round.
8039     __ z_brno(done);                             // Result is zero if unordered argument.
8040     __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8041     __ bind(done);
8042   %}
8043   ins_pipe(pipe_class_dummy);
8044 %}
8045 
8046 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
8047   match(Set dst (ConvD2L src));
8048   effect(KILL cr);
8049   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8050   size(16);
8051   format %{ "convD2L  $dst,$src" %}
8052   ins_encode %{
8053     Label done;
8054     __ clear_reg($dst$$Register, true, false);  // Initialize with result for unordered: 0.
8055     __ z_cdbr($src$$FloatRegister, $src$$FloatRegister);   // Round.
8056     __ z_brno(done);                             // Result is zero if unordered argument.
8057     __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
8058     __ bind(done);
8059   %}
8060   ins_pipe(pipe_class_dummy);
8061 %}
8062 
8063 instruct convF2D_reg(regD dst, regF src) %{
8064   match(Set dst (ConvF2D src));
8065   // CC remains unchanged.
8066   size(4);
8067   format %{ "LDEBR   $dst,$src" %}
8068   opcode(LDEBR_ZOPC);
8069   ins_encode(z_rreform(dst, src));
8070   ins_pipe(pipe_class_dummy);
8071 %}
8072 
8073 instruct convF2D_mem(regD dst, memoryRX src) %{
8074   match(Set dst (ConvF2D src));
8075   // CC remains unchanged.
8076   size(6);
8077   format %{ "LDEB    $dst,$src" %}
8078   opcode(LDEB_ZOPC);
8079   ins_encode(z_form_rt_memFP(dst, src));
8080   ins_pipe(pipe_class_dummy);
8081 %}
8082 
8083 instruct convI2D_reg(regD dst, iRegI src) %{
8084   match(Set dst (ConvI2D src));
8085   // CC remains unchanged.
8086   ins_cost(DEFAULT_COST);
8087   size(4);
8088   format %{ "CDFBR   $dst,$src" %}
8089   opcode(CDFBR_ZOPC);
8090   ins_encode(z_rreform(dst, src));
8091   ins_pipe(pipe_class_dummy);
8092 %}
8093 
8094 // Optimization that saves up to two memory operations for each conversion.
8095 instruct convI2F_ireg(regF dst, iRegI src) %{
8096   match(Set dst (ConvI2F src));
8097   // CC remains unchanged.
8098   ins_cost(DEFAULT_COST);
8099   size(4);
8100   format %{ "CEFBR   $dst,$src\t # convert int to float" %}
8101   opcode(CEFBR_ZOPC);
8102   ins_encode(z_rreform(dst, src));
8103   ins_pipe(pipe_class_dummy);
8104 %}
8105 
8106 instruct convI2L_reg(iRegL dst, iRegI src) %{
8107   match(Set dst (ConvI2L src));
8108   size(4);
8109   format %{ "LGFR    $dst,$src\t # int->long" %}
8110   opcode(LGFR_ZOPC);
8111   ins_encode(z_rreform(dst, src));
8112   ins_pipe(pipe_class_dummy);
8113 %}
8114 
8115 // Zero-extend convert int to long.
8116 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
8117   match(Set dst (AndL (ConvI2L src) mask));
8118   size(4);
8119   format %{ "LLGFR   $dst, $src \t # zero-extend int to long" %}
8120   ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8121   ins_pipe(pipe_class_dummy);
8122 %}
8123 
8124 // Zero-extend convert int to long.
8125 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
8126   match(Set dst (AndL (ConvI2L (LoadI src)) mask));
8127   // Uses load_const_optmized, so size can vary.
8128   // TODO: s390 port size(VARIABLE_SIZE);
8129   format %{ "LLGF    $dst, $src \t # zero-extend int to long" %}
8130   opcode(LLGF_ZOPC, LLGF_ZOPC);
8131   ins_encode(z_form_rt_mem_opt(dst, src));
8132   ins_pipe(pipe_class_dummy);
8133 %}
8134 
8135 // Zero-extend long
8136 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
8137   match(Set dst (AndL src mask));
8138   size(4);
8139   format %{ "LLGFR   $dst, $src \t # zero-extend long to long" %}
8140   ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
8141   ins_pipe(pipe_class_dummy);
8142 %}
8143 
8144 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
8145   match(Set dst (RShiftI (LShiftI src amount) amount));
8146   size(4);
8147   format %{ "LHR     $dst,$src\t short->int" %}
8148   opcode(LHR_ZOPC);
8149   ins_encode(z_rreform(dst, src));
8150   ins_pipe(pipe_class_dummy);
8151 %}
8152 
8153 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
8154   match(Set dst (RShiftI (LShiftI src amount) amount));
8155   size(4);
8156   format %{ "LBR     $dst,$src\t byte->int" %}
8157   opcode(LBR_ZOPC);
8158   ins_encode(z_rreform(dst, src));
8159   ins_pipe(pipe_class_dummy);
8160 %}
8161 
8162 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8163   match(Set dst (MoveF2I src));
8164   ins_cost(MEMORY_REF_COST);
8165   size(4);
8166   format %{ "L       $dst,$src\t # MoveF2I" %}
8167   opcode(L_ZOPC);
8168   ins_encode(z_form_rt_mem(dst, src));
8169   ins_pipe(pipe_class_dummy);
8170 %}
8171 
8172 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
8173 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8174   match(Set dst (MoveI2F src));
8175   ins_cost(MEMORY_REF_COST);
8176   // TODO: s390 port size(FIXED_SIZE);
8177   format %{ "LE      $dst,$src\t # MoveI2F" %}
8178   opcode(LE_ZOPC);
8179   ins_encode(z_form_rt_mem(dst, src));
8180   ins_pipe(pipe_class_dummy);
8181 %}
8182 
8183 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8184   match(Set dst (MoveD2L src));
8185   ins_cost(MEMORY_REF_COST);
8186   size(6);
8187   format %{ "LG      $src,$dst\t # MoveD2L" %}
8188   opcode(LG_ZOPC);
8189   ins_encode(z_form_rt_mem(dst, src));
8190   ins_pipe(pipe_class_dummy);
8191 %}
8192 
8193 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8194   match(Set dst (MoveL2D src));
8195   ins_cost(MEMORY_REF_COST);
8196   size(4);
8197   format %{ "LD      $dst,$src\t # MoveL2D" %}
8198   opcode(LD_ZOPC);
8199   ins_encode(z_form_rt_mem(dst, src));
8200   ins_pipe(pipe_class_dummy);
8201 %}
8202 
8203 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8204   match(Set dst (MoveI2F src));
8205   ins_cost(MEMORY_REF_COST);
8206   size(4);
8207   format %{ "ST      $src,$dst\t # MoveI2F" %}
8208   opcode(ST_ZOPC);
8209   ins_encode(z_form_rt_mem(src, dst));
8210   ins_pipe(pipe_class_dummy);
8211 %}
8212 
8213 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8214   match(Set dst (MoveD2L src));
8215   effect(DEF dst, USE src);
8216   ins_cost(MEMORY_REF_COST);
8217   size(4);
8218   format %{ "STD     $src,$dst\t # MoveD2L" %}
8219   opcode(STD_ZOPC);
8220   ins_encode(z_form_rt_mem(src,dst));
8221   ins_pipe(pipe_class_dummy);
8222 %}
8223 
8224 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8225   match(Set dst (MoveL2D src));
8226   ins_cost(MEMORY_REF_COST);
8227   size(6);
8228   format %{ "STG     $src,$dst\t # MoveL2D" %}
8229   opcode(STG_ZOPC);
8230   ins_encode(z_form_rt_mem(src,dst));
8231   ins_pipe(pipe_class_dummy);
8232 %}
8233 
8234 instruct convL2F_reg(regF dst, iRegL src) %{
8235   match(Set dst (ConvL2F src));
8236   // CC remains unchanged.
8237   ins_cost(DEFAULT_COST);
8238   size(4);
8239   format %{ "CEGBR   $dst,$src" %}
8240   opcode(CEGBR_ZOPC);
8241   ins_encode(z_rreform(dst, src));
8242   ins_pipe(pipe_class_dummy);
8243 %}
8244 
8245 instruct convL2D_reg(regD dst, iRegL src) %{
8246   match(Set dst (ConvL2D src));
8247   // CC remains unchanged.
8248   ins_cost(DEFAULT_COST);
8249   size(4);
8250   format %{ "CDGBR   $dst,$src" %}
8251   opcode(CDGBR_ZOPC);
8252   ins_encode(z_rreform(dst, src));
8253   ins_pipe(pipe_class_dummy);
8254 %}
8255 
8256 instruct convL2I_reg(iRegI dst, iRegL src) %{
8257   match(Set dst (ConvL2I src));
8258   // TODO: s390 port size(VARIABLE_SIZE);
8259   format %{ "LR      $dst,$src\t # long->int (if needed)" %}
8260   ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
8261   ins_pipe(pipe_class_dummy);
8262 %}
8263 
8264 // Register Shift Right Immediate
8265 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
8266   match(Set dst (ConvL2I (RShiftL src cnt)));
8267   effect(KILL cr);
8268   size(6);
8269   format %{ "SRAG    $dst,$src,$cnt" %}
8270   opcode(SRAG_ZOPC);
8271   ins_encode(z_rsyform_const(dst, src, cnt));
8272   ins_pipe(pipe_class_dummy);
8273 %}
8274 
8275 //----------TRAP based zero checks and range checks----------------------------
8276 
8277 // SIGTRAP based implicit range checks in compiled code.
8278 // A range check in the ideal world has one of the following shapes:
8279 //   - (If le (CmpU length index)), (IfTrue  throw exception)
8280 //   - (If lt (CmpU index length)), (IfFalse throw exception)
8281 //
8282 // Match range check 'If le (CmpU length index)'
8283 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
8284   match(If cmp (CmpU length index));
8285   effect(USE labl);
8286   predicate(TrapBasedRangeChecks &&
8287             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
8288             PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
8289             Matcher::branches_to_uncommon_trap(_leaf));
8290   ins_cost(1);
8291   // TODO: s390 port size(FIXED_SIZE);
8292 
8293   ins_is_TrapBasedCheckNode(true);
8294 
8295   format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
8296   ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
8297   ins_pipe(pipe_class_trap);
8298 %}
8299 
8300 // Match range check 'If lt (CmpU index length)'
8301 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
8302   match(If cmp (CmpU index length));
8303   effect(USE labl, KILL cr);
8304   predicate(TrapBasedRangeChecks &&
8305             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8306             _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8307             Matcher::branches_to_uncommon_trap(_leaf));
8308   ins_cost(1);
8309   // TODO: s390 port size(FIXED_SIZE);
8310 
8311   ins_is_TrapBasedCheckNode(true);
8312 
8313   format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
8314   ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
8315   ins_pipe(pipe_class_trap);
8316 %}
8317 
8318 // Match range check 'If lt (CmpU index length)'
8319 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
8320   match(If cmp (CmpU index length));
8321   effect(USE labl);
8322   predicate(TrapBasedRangeChecks &&
8323             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
8324             _leaf->as_If ()->_prob >= PROB_ALWAYS &&
8325             Matcher::branches_to_uncommon_trap(_leaf));
8326   ins_cost(1);
8327   // TODO: s390 port size(FIXED_SIZE);
8328 
8329   ins_is_TrapBasedCheckNode(true);
8330 
8331   format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
8332   ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
8333   ins_pipe(pipe_class_trap);
8334 %}
8335 
8336 // Implicit zero checks (more implicit null checks).
8337 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
8338   match(If cmp (CmpP value zero));
8339   effect(USE labl);
8340   predicate(TrapBasedNullChecks &&
8341             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8342             _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8343             Matcher::branches_to_uncommon_trap(_leaf));
8344   size(6);
8345 
8346   ins_is_TrapBasedCheckNode(true);
8347 
8348   format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
8349   ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
8350   ins_pipe(pipe_class_trap);
8351 %}
8352 
8353 // Implicit zero checks (more implicit null checks).
8354 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
8355   match(If cmp (CmpN value zero));
8356   effect(USE labl);
8357   predicate(TrapBasedNullChecks &&
8358             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
8359             _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
8360             Matcher::branches_to_uncommon_trap(_leaf));
8361   size(6);
8362 
8363   ins_is_TrapBasedCheckNode(true);
8364 
8365   format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
8366   ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
8367   ins_pipe(pipe_class_trap);
8368 %}
8369 
8370 //----------Compare instructions-----------------------------------------------
8371 
8372 // INT signed
8373 
8374 // Compare Integers
8375 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8376   match(Set cr (CmpI op1 op2));
8377   size(2);
8378   format %{ "CR      $op1,$op2" %}
8379   opcode(CR_ZOPC);
8380   ins_encode(z_rrform(op1, op2));
8381   ins_pipe(pipe_class_dummy);
8382 %}
8383 
8384 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
8385   match(Set cr (CmpI op1 op2));
8386   size(6);
8387   format %{ "CFI     $op1,$op2" %}
8388   opcode(CFI_ZOPC);
8389   ins_encode(z_rilform_signed(op1, op2));
8390   ins_pipe(pipe_class_dummy);
8391 %}
8392 
8393 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
8394   match(Set cr (CmpI op1 op2));
8395   size(4);
8396   format %{ "CHI     $op1,$op2" %}
8397   opcode(CHI_ZOPC);
8398   ins_encode(z_riform_signed(op1, op2));
8399   ins_pipe(pipe_class_dummy);
8400 %}
8401 
8402 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
8403   match(Set cr (CmpI op1 zero));
8404   ins_cost(DEFAULT_COST_LOW);
8405   size(2);
8406   format %{ "LTR     $op1,$op1" %}
8407   opcode(LTR_ZOPC);
8408   ins_encode(z_rrform(op1, op1));
8409   ins_pipe(pipe_class_dummy);
8410 %}
8411 
8412 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8413   match(Set cr (CmpI op1 (LoadI op2)));
8414   ins_cost(MEMORY_REF_COST);
8415   // TODO: s390 port size(VARIABLE_SIZE);
8416   format %{ "C(Y)    $op1, $op2\t # int" %}
8417   opcode(CY_ZOPC, C_ZOPC);
8418   ins_encode(z_form_rt_mem_opt(op1, op2));
8419   ins_pipe(pipe_class_dummy);
8420 %}
8421 
8422 // INT unsigned
8423 
8424 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
8425   match(Set cr (CmpU op1 op2));
8426   size(2);
8427   format %{ "CLR     $op1,$op2\t # unsigned" %}
8428   opcode(CLR_ZOPC);
8429   ins_encode(z_rrform(op1, op2));
8430   ins_pipe(pipe_class_dummy);
8431 %}
8432 
8433 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
8434   match(Set cr (CmpU op1 op2));
8435   size(6);
8436   format %{ "CLFI    $op1,$op2\t # unsigned" %}
8437   opcode(CLFI_ZOPC);
8438   ins_encode(z_rilform_unsigned(op1, op2));
8439   ins_pipe(pipe_class_dummy);
8440 %}
8441 
8442 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
8443   match(Set cr (CmpU op1 (LoadI op2)));
8444   ins_cost(MEMORY_REF_COST);
8445   // TODO: s390 port size(VARIABLE_SIZE);
8446   format %{ "CL(Y)   $op1, $op2\t # unsigned" %}
8447   opcode(CLY_ZOPC, CL_ZOPC);
8448   ins_encode(z_form_rt_mem_opt(op1, op2));
8449   ins_pipe(pipe_class_dummy);
8450 %}
8451 
8452 // LONG signed
8453 
8454 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8455   match(Set cr (CmpL op1 op2));
8456   size(4);
8457   format %{ "CGR     $op1,$op2\t # long" %}
8458   opcode(CGR_ZOPC);
8459   ins_encode(z_rreform(op1, op2));
8460   ins_pipe(pipe_class_dummy);
8461 %}
8462 
8463 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
8464   match(Set cr (CmpL op1 (ConvI2L op2)));
8465   size(4);
8466   format %{ "CGFR    $op1,$op2\t # long/int" %}
8467   opcode(CGFR_ZOPC);
8468   ins_encode(z_rreform(op1, op2));
8469   ins_pipe(pipe_class_dummy);
8470 %}
8471 
8472 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
8473   match(Set cr (CmpL op1 con));
8474   size(6);
8475   format %{ "CGFI    $op1,$con" %}
8476   opcode(CGFI_ZOPC);
8477   ins_encode(z_rilform_signed(op1, con));
8478   ins_pipe(pipe_class_dummy);
8479 %}
8480 
8481 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
8482   match(Set cr (CmpL op1 con));
8483   size(4);
8484   format %{ "CGHI    $op1,$con" %}
8485   opcode(CGHI_ZOPC);
8486   ins_encode(z_riform_signed(op1, con));
8487   ins_pipe(pipe_class_dummy);
8488 %}
8489 
8490 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
8491   match(Set cr (CmpL op1 con));
8492   ins_cost(DEFAULT_COST_LOW);
8493   size(4);
8494   format %{ "LTGR    $op1,$op1" %}
8495   opcode(LTGR_ZOPC);
8496   ins_encode(z_rreform(op1, op1));
8497   ins_pipe(pipe_class_dummy);
8498 %}
8499 
8500 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
8501   match(Set cr (CmpL (ConvI2L op1) con));
8502   ins_cost(DEFAULT_COST_LOW);
8503   size(4);
8504   format %{ "LTGFR    $op1,$op1" %}
8505   opcode(LTGFR_ZOPC);
8506   ins_encode(z_rreform(op1, op1));
8507   ins_pipe(pipe_class_dummy);
8508 %}
8509 
8510 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
8511   match(Set cr (CmpL dst (LoadL src)));
8512   ins_cost(MEMORY_REF_COST);
8513   size(Z_DISP3_SIZE);
8514   format %{ "CG      $dst, $src\t # long" %}
8515   opcode(CG_ZOPC, CG_ZOPC);
8516   ins_encode(z_form_rt_mem_opt(dst, src));
8517   ins_pipe(pipe_class_dummy);
8518 %}
8519 
8520 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
8521   match(Set cr (CmpL dst (ConvI2L (LoadI src))));
8522   ins_cost(MEMORY_REF_COST);
8523   size(Z_DISP3_SIZE);
8524   format %{ "CGF     $dst, $src\t # long/int" %}
8525   opcode(CGF_ZOPC, CGF_ZOPC);
8526   ins_encode(z_form_rt_mem_opt(dst, src));
8527   ins_pipe(pipe_class_dummy);
8528 %}
8529 
8530 //  LONG unsigned
8531 // Added CmpUL for LoopPredicate.
8532 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
8533   match(Set cr (CmpUL op1 op2));
8534   size(4);
8535   format %{ "CLGR    $op1,$op2\t # long" %}
8536   opcode(CLGR_ZOPC);
8537   ins_encode(z_rreform(op1, op2));
8538   ins_pipe(pipe_class_dummy);
8539 %}
8540 
8541 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{
8542   match(Set cr (CmpUL op1 con));
8543   size(6);
8544   format %{ "CLGFI   $op1,$con" %}
8545   opcode(CLGFI_ZOPC);
8546   ins_encode(z_rilform_unsigned(op1, con));
8547   ins_pipe(pipe_class_dummy);
8548 %}
8549 
8550 //  PTR unsigned
8551 
8552 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
8553   match(Set cr (CmpP op1 op2));
8554   size(4);
8555   format %{ "CLGR    $op1,$op2\t # ptr" %}
8556   opcode(CLGR_ZOPC);
8557   ins_encode(z_rreform(op1, op2));
8558   ins_pipe(pipe_class_dummy);
8559 %}
8560 
8561 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
8562   match(Set cr (CmpP op1 op2));
8563   ins_cost(DEFAULT_COST_LOW);
8564   size(4);
8565   format %{ "LTGR    $op1, $op1\t # ptr" %}
8566   opcode(LTGR_ZOPC);
8567   ins_encode(z_rreform(op1, op1));
8568   ins_pipe(pipe_class_dummy);
8569 %}
8570 
8571 // Don't use LTGFR which performs sign extend.
8572 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
8573   match(Set cr (CmpP (DecodeN op1) op2));
8574   predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0);
8575   ins_cost(DEFAULT_COST_LOW);
8576   size(2);
8577   format %{ "LTR    $op1, $op1\t # ptr" %}
8578   opcode(LTR_ZOPC);
8579   ins_encode(z_rrform(op1, op1));
8580   ins_pipe(pipe_class_dummy);
8581 %}
8582 
8583 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
8584   match(Set cr (CmpP dst (LoadP src)));
8585   ins_cost(MEMORY_REF_COST);
8586   size(Z_DISP3_SIZE);
8587   format %{ "CLG     $dst, $src\t # ptr" %}
8588   opcode(CLG_ZOPC, CLG_ZOPC);
8589   ins_encode(z_form_rt_mem_opt(dst, src));
8590   ins_pipe(pipe_class_dummy);
8591 %}
8592 
8593 //----------Max and Min--------------------------------------------------------
8594 
8595 // Max Register with Register
8596 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8597   match(Set dst (MinI src1 src2));
8598   effect(KILL cr);
8599   predicate(VM_Version::has_LoadStoreConditional());
8600   ins_cost(3 * DEFAULT_COST);
8601   // TODO: s390 port size(VARIABLE_SIZE);
8602   format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
8603   ins_encode %{
8604     Register Rdst = $dst$$Register;
8605     Register Rsrc1 = $src1$$Register;
8606     Register Rsrc2 = $src2$$Register;
8607 
8608     if (Rsrc1 == Rsrc2) {
8609       if (Rdst != Rsrc1) {
8610         __ z_lgfr(Rdst, Rsrc1);
8611       }
8612     } else if (Rdst == Rsrc1) {   // Rdst preset with src1.
8613       __ z_cr(Rsrc1, Rsrc2);      // Move src2 only if src1 is NotLow.
8614       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8615     } else if (Rdst == Rsrc2) {   // Rdst preset with src2.
8616       __ z_cr(Rsrc2, Rsrc1);      // Move src1 only if src2 is NotLow.
8617       __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
8618     } else {
8619       // Rdst is disjoint from operands, move in either case.
8620       __ z_cr(Rsrc1, Rsrc2);
8621       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
8622       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8623     }
8624   %}
8625   ins_pipe(pipe_class_dummy);
8626 %}
8627 
8628 // Min Register with Register.
8629 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8630   match(Set dst (MinI src1 src2));
8631   effect(KILL cr);
8632   predicate(VM_Version::has_CompareBranch());
8633   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8634   // TODO: s390 port size(VARIABLE_SIZE);
8635   format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
8636   ins_encode %{
8637     Register Rdst = $dst$$Register;
8638     Register Rsrc1 = $src1$$Register;
8639     Register Rsrc2 = $src2$$Register;
8640     Label done;
8641 
8642     if (Rsrc1 == Rsrc2) {
8643       if (Rdst != Rsrc1) {
8644         __ z_lgfr(Rdst, Rsrc1);
8645       }
8646     } else if (Rdst == Rsrc1) {
8647       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8648       __ z_lgfr(Rdst, Rsrc2);
8649     } else if (Rdst == Rsrc2) {
8650       __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
8651       __ z_lgfr(Rdst, Rsrc1);
8652     } else {
8653       __ z_lgfr(Rdst, Rsrc1);
8654       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
8655       __ z_lgfr(Rdst, Rsrc2);
8656     }
8657     __ bind(done);
8658   %}
8659   ins_pipe(pipe_class_dummy);
8660 %}
8661 
8662 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8663   match(Set dst (MinI src1 src2));
8664   effect(KILL cr);
8665   predicate(!VM_Version::has_CompareBranch());
8666   ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8667   // TODO: s390 port size(VARIABLE_SIZE);
8668   format %{ "MinI $dst $src1,$src2\t MinI" %}
8669   ins_encode %{
8670     Register Rdst = $dst$$Register;
8671     Register Rsrc1 = $src1$$Register;
8672     Register Rsrc2 = $src2$$Register;
8673     Label done;
8674 
8675     if (Rsrc1 == Rsrc2) {
8676       if (Rdst != Rsrc1) {
8677         __ z_lgfr(Rdst, Rsrc1);
8678       }
8679     } else if (Rdst == Rsrc1) {
8680       __ z_cr(Rsrc1, Rsrc2);
8681       __ z_brl(done);
8682       __ z_lgfr(Rdst, Rsrc2);
8683     } else if (Rdst == Rsrc2) {
8684       __ z_cr(Rsrc2, Rsrc1);
8685       __ z_brl(done);
8686       __ z_lgfr(Rdst, Rsrc1);
8687     } else {
8688       __ z_lgfr(Rdst, Rsrc1);
8689       __ z_cr(Rsrc1, Rsrc2);
8690       __ z_brl(done);
8691       __ z_lgfr(Rdst, Rsrc2);
8692     }
8693     __ bind(done);
8694   %}
8695   ins_pipe(pipe_class_dummy);
8696 %}
8697 
8698 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8699   match(Set dst (MinI src1 src2));
8700   effect(KILL cr);
8701   predicate(VM_Version::has_LoadStoreConditional());
8702   ins_cost(3 * DEFAULT_COST);
8703   // TODO: s390 port size(VARIABLE_SIZE);
8704   format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
8705   ins_encode %{
8706     Register Rdst = $dst$$Register;
8707     Register Rsrc1 = $src1$$Register;
8708     int      Isrc2 = $src2$$constant;
8709 
8710     if (Rdst == Rsrc1) {
8711       __ load_const_optimized(Z_R0_scratch, Isrc2);
8712       __ z_cfi(Rsrc1, Isrc2);
8713       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8714     } else {
8715       __ load_const_optimized(Rdst, Isrc2);
8716       __ z_cfi(Rsrc1, Isrc2);
8717       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8718     }
8719   %}
8720   ins_pipe(pipe_class_dummy);
8721 %}
8722 
8723 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8724   match(Set dst (MinI src1 src2));
8725   effect(KILL cr);
8726   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8727   // TODO: s390 port size(VARIABLE_SIZE);
8728   format %{ "MinI $dst $src1,$src2\t MinI const32" %}
8729   ins_encode %{
8730     Label done;
8731     if ($dst$$Register != $src1$$Register) {
8732       __ z_lgfr($dst$$Register, $src1$$Register);
8733     }
8734     __ z_cfi($src1$$Register, $src2$$constant);
8735     __ z_brl(done);
8736     __ z_lgfi($dst$$Register, $src2$$constant);
8737     __ bind(done);
8738   %}
8739   ins_pipe(pipe_class_dummy);
8740 %}
8741 
8742 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8743   match(Set dst (MinI src1 src2));
8744   effect(KILL cr);
8745   predicate(VM_Version::has_LoadStoreConditional());
8746   ins_cost(3 * DEFAULT_COST);
8747   // TODO: s390 port size(VARIABLE_SIZE);
8748   format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
8749   ins_encode %{
8750     Register Rdst = $dst$$Register;
8751     Register Rsrc1 = $src1$$Register;
8752     int      Isrc2 = $src2$$constant;
8753 
8754     if (Rdst == Rsrc1) {
8755       __ load_const_optimized(Z_R0_scratch, Isrc2);
8756       __ z_chi(Rsrc1, Isrc2);
8757       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
8758     } else {
8759       __ load_const_optimized(Rdst, Isrc2);
8760       __ z_chi(Rsrc1, Isrc2);
8761       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
8762     }
8763   %}
8764   ins_pipe(pipe_class_dummy);
8765 %}
8766 
8767 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8768   match(Set dst (MinI src1 src2));
8769   effect(KILL cr);
8770   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8771   // TODO: s390 port size(VARIABLE_SIZE);
8772   format %{ "MinI $dst $src1,$src2\t MinI const16" %}
8773   ins_encode %{
8774     Label done;
8775     if ($dst$$Register != $src1$$Register) {
8776       __ z_lgfr($dst$$Register, $src1$$Register);
8777     }
8778     __ z_chi($src1$$Register, $src2$$constant);
8779     __ z_brl(done);
8780     __ z_lghi($dst$$Register, $src2$$constant);
8781     __ bind(done);
8782   %}
8783   ins_pipe(pipe_class_dummy);
8784 %}
8785 
8786 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8787   match(Set dst (MinI src1 src2));
8788   effect(KILL cr);
8789   predicate(VM_Version::has_CompareBranch());
8790   ins_cost(DEFAULT_COST + BRANCH_COST);
8791   // TODO: s390 port size(VARIABLE_SIZE);
8792   format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
8793   ins_encode %{
8794     Label done;
8795     if ($dst$$Register != $src1$$Register) {
8796       __ z_lgfr($dst$$Register, $src1$$Register);
8797     }
8798     __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
8799     __ z_lghi($dst$$Register, $src2$$constant);
8800     __ bind(done);
8801   %}
8802   ins_pipe(pipe_class_dummy);
8803 %}
8804 
8805 // Max Register with Register
8806 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8807   match(Set dst (MaxI src1 src2));
8808   effect(KILL cr);
8809   predicate(VM_Version::has_LoadStoreConditional());
8810   ins_cost(3 * DEFAULT_COST);
8811   // TODO: s390 port size(VARIABLE_SIZE);
8812   format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
8813   ins_encode %{
8814     Register Rdst = $dst$$Register;
8815     Register Rsrc1 = $src1$$Register;
8816     Register Rsrc2 = $src2$$Register;
8817 
8818     if (Rsrc1 == Rsrc2) {
8819       if (Rdst != Rsrc1) {
8820         __ z_lgfr(Rdst, Rsrc1);
8821       }
8822     } else if (Rdst == Rsrc1) { // Rdst preset with src1.
8823       __ z_cr(Rsrc1, Rsrc2);    // Move src2 only if src1 is NotHigh.
8824       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8825     } else if (Rdst == Rsrc2) { // Rdst preset with src2.
8826       __ z_cr(Rsrc2, Rsrc1);    // Move src1 only if src2 is NotHigh.
8827       __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
8828     } else {                    // Rdst is disjoint from operands, move in either case.
8829       __ z_cr(Rsrc1, Rsrc2);
8830       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
8831       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8832     }
8833   %}
8834   ins_pipe(pipe_class_dummy);
8835 %}
8836 
8837 // Max Register with Register
8838 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8839   match(Set dst (MaxI src1 src2));
8840   effect(KILL cr);
8841   predicate(VM_Version::has_CompareBranch());
8842   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8843   // TODO: s390 port size(VARIABLE_SIZE);
8844   format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
8845   ins_encode %{
8846     Register Rdst = $dst$$Register;
8847     Register Rsrc1 = $src1$$Register;
8848     Register Rsrc2 = $src2$$Register;
8849     Label done;
8850 
8851     if (Rsrc1 == Rsrc2) {
8852       if (Rdst != Rsrc1) {
8853         __ z_lgfr(Rdst, Rsrc1);
8854       }
8855     } else if (Rdst == Rsrc1) {
8856       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
8857       __ z_lgfr(Rdst, Rsrc2);
8858     } else if (Rdst == Rsrc2) {
8859       __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
8860       __ z_lgfr(Rdst, Rsrc1);
8861     } else {
8862       __ z_lgfr(Rdst, Rsrc1);
8863       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
8864       __ z_lgfr(Rdst, Rsrc2);
8865     }
8866     __ bind(done);
8867   %}
8868   ins_pipe(pipe_class_dummy);
8869 %}
8870 
8871 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
8872   match(Set dst (MaxI src1 src2));
8873   effect(KILL cr);
8874   predicate(!VM_Version::has_CompareBranch());
8875   ins_cost(3 * DEFAULT_COST + BRANCH_COST);
8876   // TODO: s390 port size(VARIABLE_SIZE);
8877   format %{ "MaxI $dst $src1,$src2\t MaxI" %}
8878   ins_encode %{
8879     Register Rdst = $dst$$Register;
8880     Register Rsrc1 = $src1$$Register;
8881     Register Rsrc2 = $src2$$Register;
8882     Label done;
8883 
8884     if (Rsrc1 == Rsrc2) {
8885       if (Rdst != Rsrc1) {
8886         __ z_lgfr(Rdst, Rsrc1);
8887       }
8888     } else if (Rdst == Rsrc1) {
8889       __ z_cr(Rsrc1, Rsrc2);
8890       __ z_brh(done);
8891       __ z_lgfr(Rdst, Rsrc2);
8892     } else if (Rdst == Rsrc2) {
8893       __ z_cr(Rsrc2, Rsrc1);
8894       __ z_brh(done);
8895       __ z_lgfr(Rdst, Rsrc1);
8896     } else {
8897       __ z_lgfr(Rdst, Rsrc1);
8898       __ z_cr(Rsrc1, Rsrc2);
8899       __ z_brh(done);
8900       __ z_lgfr(Rdst, Rsrc2);
8901     }
8902 
8903     __ bind(done);
8904   %}
8905 
8906   ins_pipe(pipe_class_dummy);
8907 %}
8908 
8909 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8910   match(Set dst (MaxI src1 src2));
8911   effect(KILL cr);
8912   predicate(VM_Version::has_LoadStoreConditional());
8913   ins_cost(3 * DEFAULT_COST);
8914   // TODO: s390 port size(VARIABLE_SIZE);
8915   format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
8916   ins_encode %{
8917     Register Rdst = $dst$$Register;
8918     Register Rsrc1 = $src1$$Register;
8919     int      Isrc2 = $src2$$constant;
8920 
8921     if (Rdst == Rsrc1) {
8922       __ load_const_optimized(Z_R0_scratch, Isrc2);
8923       __ z_cfi(Rsrc1, Isrc2);
8924       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
8925     } else {
8926       __ load_const_optimized(Rdst, Isrc2);
8927       __ z_cfi(Rsrc1, Isrc2);
8928       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8929     }
8930   %}
8931   ins_pipe(pipe_class_dummy);
8932 %}
8933 
8934 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
8935   match(Set dst (MaxI src1 src2));
8936   effect(KILL cr);
8937   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8938   // TODO: s390 port size(VARIABLE_SIZE);
8939   format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
8940   ins_encode %{
8941     Label done;
8942     if ($dst$$Register != $src1$$Register) {
8943       __ z_lgfr($dst$$Register, $src1$$Register);
8944     }
8945     __ z_cfi($src1$$Register, $src2$$constant);
8946     __ z_brh(done);
8947     __ z_lgfi($dst$$Register, $src2$$constant);
8948     __ bind(done);
8949   %}
8950   ins_pipe(pipe_class_dummy);
8951 %}
8952 
8953 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8954   match(Set dst (MaxI src1 src2));
8955   effect(KILL cr);
8956   predicate(VM_Version::has_LoadStoreConditional());
8957   ins_cost(3 * DEFAULT_COST);
8958   // TODO: s390 port size(VARIABLE_SIZE);
8959   format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
8960   ins_encode %{
8961     Register Rdst = $dst$$Register;
8962     Register Rsrc1 = $src1$$Register;
8963     int      Isrc2 = $src2$$constant;
8964     if (Rdst == Rsrc1) {
8965       __ load_const_optimized(Z_R0_scratch, Isrc2);
8966       __ z_chi(Rsrc1, Isrc2);
8967       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
8968     } else {
8969       __ load_const_optimized(Rdst, Isrc2);
8970       __ z_chi(Rsrc1, Isrc2);
8971       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
8972     }
8973   %}
8974   ins_pipe(pipe_class_dummy);
8975 %}
8976 
8977 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
8978   match(Set dst (MaxI src1 src2));
8979   effect(KILL cr);
8980   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
8981   // TODO: s390 port size(VARIABLE_SIZE);
8982   format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
8983   ins_encode %{
8984     Label done;
8985     if ($dst$$Register != $src1$$Register) {
8986       __ z_lgfr($dst$$Register, $src1$$Register);
8987     }
8988     __ z_chi($src1$$Register, $src2$$constant);
8989     __ z_brh(done);
8990     __ z_lghi($dst$$Register, $src2$$constant);
8991     __ bind(done);
8992   %}
8993   ins_pipe(pipe_class_dummy);
8994 %}
8995 
8996 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
8997   match(Set dst (MaxI src1 src2));
8998   effect(KILL cr);
8999   predicate(VM_Version::has_CompareBranch());
9000   ins_cost(DEFAULT_COST + BRANCH_COST);
9001   // TODO: s390 port size(VARIABLE_SIZE);
9002   format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
9003   ins_encode %{
9004     Label done;
9005     if ($dst$$Register != $src1$$Register) {
9006       __ z_lgfr($dst$$Register, $src1$$Register);
9007     }
9008     __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
9009     __ z_lghi($dst$$Register, $src2$$constant);
9010     __ bind(done);
9011   %}
9012   ins_pipe(pipe_class_dummy);
9013 %}
9014 
9015 //----------Abs---------------------------------------------------------------
9016 
9017 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
9018   match(Set dst (AbsI src));
9019   effect(KILL cr);
9020   ins_cost(DEFAULT_COST_LOW);
9021   // TODO: s390 port size(FIXED_SIZE);
9022   format %{ "LPR     $dst, $src" %}
9023   opcode(LPR_ZOPC);
9024   ins_encode(z_rrform(dst, src));
9025   ins_pipe(pipe_class_dummy);
9026 %}
9027 
9028 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
9029   match(Set dst (SubI zero (AbsI src)));
9030   effect(KILL cr);
9031   ins_cost(DEFAULT_COST_LOW);
9032   // TODO: s390 port size(FIXED_SIZE);
9033   format %{ "LNR     $dst, $src" %}
9034   opcode(LNR_ZOPC);
9035   ins_encode(z_rrform(dst, src));
9036   ins_pipe(pipe_class_dummy);
9037 %}
9038 
9039 //----------Float Compares----------------------------------------------------
9040 
9041 // Compare floating, generate condition code.
9042 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
9043   match(Set cr (CmpF src1 src2));
9044   ins_cost(ALU_REG_COST);
9045   size(4);
9046   format %{ "FCMPcc   $src1,$src2\t # float" %}
9047   ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
9048   ins_pipe(pipe_class_dummy);
9049 %}
9050 
9051 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
9052   match(Set cr (CmpD src1 src2));
9053   ins_cost(ALU_REG_COST);
9054   size(4);
9055   format %{ "FCMPcc   $src1,$src2 \t # double" %}
9056   ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
9057   ins_pipe(pipe_class_dummy);
9058 %}
9059 
9060 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
9061   match(Set cr (CmpF src1 (LoadF src2)));
9062   ins_cost(ALU_MEMORY_COST);
9063   size(6);
9064   format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
9065   opcode(CEB_ZOPC);
9066   ins_encode(z_form_rt_memFP(src1, src2));
9067   ins_pipe(pipe_class_dummy);
9068 %}
9069 
9070 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
9071   match(Set cr (CmpD src1 (LoadD src2)));
9072   ins_cost(ALU_MEMORY_COST);
9073   size(6);
9074   format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
9075   opcode(CDB_ZOPC);
9076   ins_encode(z_form_rt_memFP(src1, src2));
9077   ins_pipe(pipe_class_dummy);
9078 %}
9079 
9080 // Compare floating, generate condition code
9081 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
9082   match(Set cr (CmpF src1 src2));
9083   ins_cost(DEFAULT_COST);
9084   size(4);
9085   format %{ "LTEBR    $src1,$src1\t # float" %}
9086   opcode(LTEBR_ZOPC);
9087   ins_encode(z_rreform(src1, src1));
9088   ins_pipe(pipe_class_dummy);
9089 %}
9090 
9091 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
9092   match(Set cr (CmpD src1 src2));
9093   ins_cost(DEFAULT_COST);
9094   size(4);
9095   format %{ "LTDBR    $src1,$src1 \t # double" %}
9096   opcode(LTDBR_ZOPC);
9097   ins_encode(z_rreform(src1, src1));
9098   ins_pipe(pipe_class_dummy);
9099 %}
9100 
9101 // Compare floating, generate -1,0,1
9102 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
9103   match(Set dst (CmpF3 src1 src2));
9104   effect(KILL cr);
9105   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9106   size(24);
9107   format %{ "CmpF3    $dst,$src1,$src2" %}
9108   ins_encode %{
9109     // compare registers
9110     __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
9111     // Convert condition code into -1,0,1, where
9112     // -1 means unordered or less
9113     //  0 means equal
9114     //  1 means greater.
9115     if (VM_Version::has_LoadStoreConditional()) {
9116       Register one       = Z_R0_scratch;
9117       Register minus_one = Z_R1_scratch;
9118       __ z_lghi(minus_one, -1);
9119       __ z_lghi(one, 1);
9120       __ z_lghi( $dst$$Register, 0);
9121       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
9122       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9123     } else {
9124       Label done;
9125       __ clear_reg($dst$$Register, true, false);
9126       __ z_bre(done);
9127       __ z_lhi($dst$$Register, 1);
9128       __ z_brh(done);
9129       __ z_lhi($dst$$Register, -1);
9130       __ bind(done);
9131     }
9132   %}
9133   ins_pipe(pipe_class_dummy);
9134 %}
9135 
9136 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
9137   match(Set dst (CmpD3 src1 src2));
9138   effect(KILL cr);
9139   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9140   size(24);
9141   format %{ "CmpD3    $dst,$src1,$src2" %}
9142   ins_encode %{
9143     // compare registers
9144     __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
9145     // Convert condition code into -1,0,1, where
9146     // -1 means unordered or less
9147     //  0 means equal
9148     //  1 means greater.
9149     if (VM_Version::has_LoadStoreConditional()) {
9150       Register one       = Z_R0_scratch;
9151       Register minus_one = Z_R1_scratch;
9152       __ z_lghi(minus_one, -1);
9153       __ z_lghi(one, 1);
9154       __ z_lghi( $dst$$Register, 0);
9155       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
9156       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
9157     } else {
9158       Label done;
9159       // indicate unused result
9160       (void) __ clear_reg($dst$$Register, true, false);
9161       __ z_bre(done);
9162       __ z_lhi($dst$$Register, 1);
9163       __ z_brh(done);
9164       __ z_lhi($dst$$Register, -1);
9165       __ bind(done);
9166     }
9167   %}
9168   ins_pipe(pipe_class_dummy);
9169 %}
9170 
9171 //----------Branches---------------------------------------------------------
9172 // Jump
9173 
9174 // Direct Branch.
9175 instruct branch(label labl) %{
9176   match(Goto);
9177   effect(USE labl);
9178   ins_cost(BRANCH_COST);
9179   size(4);
9180   format %{ "BRU     $labl" %}
9181   ins_encode(z_enc_bru(labl));
9182   ins_pipe(pipe_class_dummy);
9183   // If set to 1 this indicates that the current instruction is a
9184   // short variant of a long branch. This avoids using this
9185   // instruction in first-pass matching. It will then only be used in
9186   // the `Shorten_branches' pass.
9187   ins_short_branch(1);
9188 %}
9189 
9190 // Direct Branch.
9191 instruct branchFar(label labl) %{
9192   match(Goto);
9193   effect(USE labl);
9194   ins_cost(BRANCH_COST);
9195   size(6);
9196   format %{ "BRUL   $labl" %}
9197   ins_encode(z_enc_brul(labl));
9198   ins_pipe(pipe_class_dummy);
9199   // This is not a short variant of a branch, but the long variant.
9200   ins_short_branch(0);
9201 %}
9202 
9203 // Conditional Near Branch
9204 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
9205   // Same match rule as `branchConFar'.
9206   match(If cmp cr);
9207   effect(USE lbl);
9208   ins_cost(BRANCH_COST);
9209   size(4);
9210   format %{ "branch_con_short,$cmp   $lbl" %}
9211   ins_encode(z_enc_branch_con_short(cmp, lbl));
9212   ins_pipe(pipe_class_dummy);
9213   // If set to 1 this indicates that the current instruction is a
9214   // short variant of a long branch. This avoids using this
9215   // instruction in first-pass matching. It will then only be used in
9216   // the `Shorten_branches' pass.
9217   ins_short_branch(1);
9218 %}
9219 
9220 // This is for cases when the z/Architecture conditional branch instruction
9221 // does not reach far enough. So we emit a far branch here, which is
9222 // more expensive.
9223 //
9224 // Conditional Far Branch
9225 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
9226   // Same match rule as `branchCon'.
9227   match(If cmp cr);
9228   effect(USE cr, USE lbl);
9229   // Make more expensive to prefer compare_and_branch over separate instructions.
9230   ins_cost(2 * BRANCH_COST);
9231   size(6);
9232   format %{ "branch_con_far,$cmp   $lbl" %}
9233   ins_encode(z_enc_branch_con_far(cmp, lbl));
9234   ins_pipe(pipe_class_dummy);
9235   // This is not a short variant of a branch, but the long variant..
9236   ins_short_branch(0);
9237 %}
9238 
9239 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
9240   match(CountedLoopEnd cmp cr);
9241   effect(USE labl);
9242   ins_cost(BRANCH_COST);
9243   size(4);
9244   format %{ "branch_con_short,$cmp   $labl\t # counted loop end" %}
9245   ins_encode(z_enc_branch_con_short(cmp, labl));
9246   ins_pipe(pipe_class_dummy);
9247   // If set to 1 this indicates that the current instruction is a
9248   // short variant of a long branch. This avoids using this
9249   // instruction in first-pass matching. It will then only be used in
9250   // the `Shorten_branches' pass.
9251   ins_short_branch(1);
9252 %}
9253 
9254 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
9255   match(CountedLoopEnd cmp cr);
9256   effect(USE labl);
9257   ins_cost(BRANCH_COST);
9258   size(6);
9259   format %{ "branch_con_far,$cmp   $labl\t # counted loop end" %}
9260   ins_encode(z_enc_branch_con_far(cmp, labl));
9261   ins_pipe(pipe_class_dummy);
9262   // This is not a short variant of a branch, but the long variant.
9263   ins_short_branch(0);
9264 %}
9265 
9266 //----------Compare and Branch (short distance)------------------------------
9267 
9268 // INT REG operands for loop counter processing.
9269 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9270   match(CountedLoopEnd boolnode (CmpI src1 src2));
9271   effect(USE labl, KILL cr);
9272   predicate(VM_Version::has_CompareBranch());
9273   ins_cost(BRANCH_COST);
9274   // TODO: s390 port size(FIXED_SIZE);
9275   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end SHORT" %}
9276   opcode(CRJ_ZOPC);
9277   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9278   ins_pipe(pipe_class_dummy);
9279   ins_short_branch(1);
9280 %}
9281 
9282 // INT REG operands.
9283 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9284   match(If boolnode (CmpI src1 src2));
9285   effect(USE labl, KILL cr);
9286   predicate(VM_Version::has_CompareBranch());
9287   ins_cost(BRANCH_COST);
9288   // TODO: s390 port size(FIXED_SIZE);
9289   format %{ "CRJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
9290   opcode(CRJ_ZOPC);
9291   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9292   ins_pipe(pipe_class_dummy);
9293   ins_short_branch(1);
9294 %}
9295 
9296 // Unsigned INT REG operands
9297 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9298   match(If boolnode (CmpU src1 src2));
9299   effect(USE labl, KILL cr);
9300   predicate(VM_Version::has_CompareBranch());
9301   ins_cost(BRANCH_COST);
9302   // TODO: s390 port size(FIXED_SIZE);
9303   format %{ "CLRJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
9304   opcode(CLRJ_ZOPC);
9305   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9306   ins_pipe(pipe_class_dummy);
9307   ins_short_branch(1);
9308 %}
9309 
9310 // LONG REG operands
9311 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9312   match(If boolnode (CmpL src1 src2));
9313   effect(USE labl, KILL cr);
9314   predicate(VM_Version::has_CompareBranch());
9315   ins_cost(BRANCH_COST);
9316   // TODO: s390 port size(FIXED_SIZE);
9317   format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9318   opcode(CGRJ_ZOPC);
9319   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9320   ins_pipe(pipe_class_dummy);
9321   ins_short_branch(1);
9322 %}
9323 
9324 //  PTR REG operands
9325 
9326 // Separate rules for regular and narrow oops.  ADLC can't recognize
9327 // rules with polymorphic operands to be sisters -> shorten_branches
9328 // will not shorten.
9329 
9330 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9331   match(If boolnode (CmpP src1 src2));
9332   effect(USE labl, KILL cr);
9333   predicate(VM_Version::has_CompareBranch());
9334   ins_cost(BRANCH_COST);
9335   // TODO: s390 port size(FIXED_SIZE);
9336   format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9337   opcode(CLGRJ_ZOPC);
9338   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9339   ins_pipe(pipe_class_dummy);
9340   ins_short_branch(1);
9341 %}
9342 
9343 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9344   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9345   effect(USE labl, KILL cr);
9346   predicate(VM_Version::has_CompareBranch());
9347   ins_cost(BRANCH_COST);
9348   // TODO: s390 port size(FIXED_SIZE);
9349   format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9350   opcode(CLGRJ_ZOPC);
9351   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
9352   ins_pipe(pipe_class_dummy);
9353   ins_short_branch(1);
9354 %}
9355 
9356 // INT REG/IMM operands for loop counter processing
9357 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9358   match(CountedLoopEnd boolnode (CmpI src1 src2));
9359   effect(USE labl, KILL cr);
9360   predicate(VM_Version::has_CompareBranch());
9361   ins_cost(BRANCH_COST);
9362   // TODO: s390 port size(FIXED_SIZE);
9363   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end SHORT" %}
9364   opcode(CIJ_ZOPC);
9365   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9366   ins_pipe(pipe_class_dummy);
9367   ins_short_branch(1);
9368 %}
9369 
9370 // INT REG/IMM operands
9371 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9372   match(If boolnode (CmpI src1 src2));
9373   effect(USE labl, KILL cr);
9374   predicate(VM_Version::has_CompareBranch());
9375   ins_cost(BRANCH_COST);
9376   // TODO: s390 port size(FIXED_SIZE);
9377   format %{ "CIJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
9378   opcode(CIJ_ZOPC);
9379   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9380   ins_pipe(pipe_class_dummy);
9381   ins_short_branch(1);
9382 %}
9383 
9384 // INT REG/IMM operands
9385 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9386   match(If boolnode (CmpU src1 src2));
9387   effect(USE labl, KILL cr);
9388   predicate(VM_Version::has_CompareBranch());
9389   ins_cost(BRANCH_COST);
9390   // TODO: s390 port size(FIXED_SIZE);
9391   format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9392   opcode(CLIJ_ZOPC);
9393   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9394   ins_pipe(pipe_class_dummy);
9395   ins_short_branch(1);
9396 %}
9397 
9398 // LONG REG/IMM operands
9399 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9400   match(If boolnode (CmpL src1 src2));
9401   effect(USE labl, KILL cr);
9402   predicate(VM_Version::has_CompareBranch());
9403   ins_cost(BRANCH_COST);
9404   // TODO: s390 port size(FIXED_SIZE);
9405   format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9406   opcode(CGIJ_ZOPC);
9407   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9408   ins_pipe(pipe_class_dummy);
9409   ins_short_branch(1);
9410 %}
9411 
9412 // PTR REG-imm operands
9413 
9414 // Separate rules for regular and narrow oops. ADLC can't recognize
9415 // rules with polymorphic operands to be sisters -> shorten_branches
9416 // will not shorten.
9417 
9418 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9419   match(If boolnode (CmpP src1 src2));
9420   effect(USE labl, KILL cr);
9421   predicate(VM_Version::has_CompareBranch());
9422   ins_cost(BRANCH_COST);
9423   // TODO: s390 port size(FIXED_SIZE);
9424   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9425   opcode(CLGIJ_ZOPC);
9426   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9427   ins_pipe(pipe_class_dummy);
9428   ins_short_branch(1);
9429 %}
9430 
9431 // Compare against zero only, do not mix N and P oops (encode/decode required).
9432 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9433   match(If boolnode (CmpP (DecodeN src1) src2));
9434   effect(USE labl, KILL cr);
9435   predicate(VM_Version::has_CompareBranch());
9436   ins_cost(BRANCH_COST);
9437   // TODO: s390 port size(FIXED_SIZE);
9438   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9439   opcode(CLGIJ_ZOPC);
9440   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9441   ins_pipe(pipe_class_dummy);
9442   ins_short_branch(1);
9443 %}
9444 
9445 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9446   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9447   effect(USE labl, KILL cr);
9448   predicate(VM_Version::has_CompareBranch());
9449   ins_cost(BRANCH_COST);
9450   // TODO: s390 port size(FIXED_SIZE);
9451   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
9452   opcode(CLGIJ_ZOPC);
9453   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
9454   ins_pipe(pipe_class_dummy);
9455   ins_short_branch(1);
9456 %}
9457 
9458 
9459 //----------Compare and Branch (far distance)------------------------------
9460 
9461 // INT REG operands for loop counter processing
9462 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9463   match(CountedLoopEnd boolnode (CmpI src1 src2));
9464   effect(USE labl, KILL cr);
9465   predicate(VM_Version::has_CompareBranch());
9466   ins_cost(BRANCH_COST+DEFAULT_COST);
9467   // TODO: s390 port size(FIXED_SIZE);
9468   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end FAR" %}
9469   opcode(CR_ZOPC, BRCL_ZOPC);
9470   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9471   ins_pipe(pipe_class_dummy);
9472   ins_short_branch(0);
9473 %}
9474 
9475 // INT REG operands
9476 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9477   match(If boolnode (CmpI src1 src2));
9478   effect(USE labl, KILL cr);
9479   predicate(VM_Version::has_CompareBranch());
9480   ins_cost(BRANCH_COST+DEFAULT_COST);
9481   // TODO: s390 port size(FIXED_SIZE);
9482   format %{ "CRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9483   opcode(CR_ZOPC, BRCL_ZOPC);
9484   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9485   ins_pipe(pipe_class_dummy);
9486   ins_short_branch(0);
9487 %}
9488 
9489 // INT REG operands
9490 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
9491   match(If boolnode (CmpU src1 src2));
9492   effect(USE labl, KILL cr);
9493   predicate(VM_Version::has_CompareBranch());
9494   ins_cost(BRANCH_COST+DEFAULT_COST);
9495   // TODO: s390 port size(FIXED_SIZE);
9496   format %{ "CLRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9497   opcode(CLR_ZOPC, BRCL_ZOPC);
9498   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9499   ins_pipe(pipe_class_dummy);
9500   ins_short_branch(0);
9501 %}
9502 
9503 // LONG REG operands
9504 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
9505   match(If boolnode (CmpL src1 src2));
9506   effect(USE labl, KILL cr);
9507   predicate(VM_Version::has_CompareBranch());
9508   ins_cost(BRANCH_COST+DEFAULT_COST);
9509   // TODO: s390 port size(FIXED_SIZE);
9510   format %{ "CGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9511   opcode(CGR_ZOPC, BRCL_ZOPC);
9512   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9513   ins_pipe(pipe_class_dummy);
9514   ins_short_branch(0);
9515 %}
9516 
9517 // PTR REG operands
9518 
9519 // Separate rules for regular and narrow oops. ADLC can't recognize
9520 // rules with polymorphic operands to be sisters -> shorten_branches
9521 // will not shorten.
9522 
9523 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
9524   match(If boolnode (CmpP src1 src2));
9525   effect(USE labl, KILL cr);
9526   predicate(VM_Version::has_CompareBranch());
9527   ins_cost(BRANCH_COST+DEFAULT_COST);
9528   // TODO: s390 port size(FIXED_SIZE);
9529   format %{ "CLGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9530   opcode(CLGR_ZOPC, BRCL_ZOPC);
9531   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9532   ins_pipe(pipe_class_dummy);
9533   ins_short_branch(0);
9534 %}
9535 
9536 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
9537   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9538   effect(USE labl, KILL cr);
9539   predicate(VM_Version::has_CompareBranch());
9540   ins_cost(BRANCH_COST+DEFAULT_COST);
9541   // TODO: s390 port size(FIXED_SIZE);
9542   format %{ "CLGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9543   opcode(CLGR_ZOPC, BRCL_ZOPC);
9544   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
9545   ins_pipe(pipe_class_dummy);
9546   ins_short_branch(0);
9547 %}
9548 
9549 // INT REG/IMM operands for loop counter processing
9550 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9551   match(CountedLoopEnd boolnode (CmpI src1 src2));
9552   effect(USE labl, KILL cr);
9553   predicate(VM_Version::has_CompareBranch());
9554   ins_cost(BRANCH_COST+DEFAULT_COST);
9555   // TODO: s390 port size(FIXED_SIZE);
9556   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end FAR" %}
9557   opcode(CHI_ZOPC, BRCL_ZOPC);
9558   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9559   ins_pipe(pipe_class_dummy);
9560   ins_short_branch(0);
9561 %}
9562 
9563 // INT REG/IMM operands
9564 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
9565   match(If boolnode (CmpI src1 src2));
9566   effect(USE labl, KILL cr);
9567   predicate(VM_Version::has_CompareBranch());
9568   ins_cost(BRANCH_COST+DEFAULT_COST);
9569   // TODO: s390 port size(FIXED_SIZE);
9570   format %{ "CIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9571   opcode(CHI_ZOPC, BRCL_ZOPC);
9572   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9573   ins_pipe(pipe_class_dummy);
9574   ins_short_branch(0);
9575 %}
9576 
9577 // INT REG/IMM operands
9578 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
9579   match(If boolnode (CmpU src1 src2));
9580   effect(USE labl, KILL cr);
9581   predicate(VM_Version::has_CompareBranch());
9582   ins_cost(BRANCH_COST+DEFAULT_COST);
9583   // TODO: s390 port size(FIXED_SIZE);
9584   format %{ "CLIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9585   opcode(CLFI_ZOPC, BRCL_ZOPC);
9586   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9587   ins_pipe(pipe_class_dummy);
9588   ins_short_branch(0);
9589 %}
9590 
9591 // LONG REG/IMM operands
9592 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
9593   match(If boolnode (CmpL src1 src2));
9594   effect(USE labl, KILL cr);
9595   predicate(VM_Version::has_CompareBranch());
9596   ins_cost(BRANCH_COST+DEFAULT_COST);
9597   // TODO: s390 port size(FIXED_SIZE);
9598   format %{ "CGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9599   opcode(CGHI_ZOPC, BRCL_ZOPC);
9600   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9601   ins_pipe(pipe_class_dummy);
9602   ins_short_branch(0);
9603 %}
9604 
9605 // PTR REG-imm operands
9606 
9607 // Separate rules for regular and narrow oops. ADLC can't recognize
9608 // rules with polymorphic operands to be sisters -> shorten_branches
9609 // will not shorten.
9610 
9611 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
9612   match(If boolnode (CmpP src1 src2));
9613   effect(USE labl, KILL cr);
9614   predicate(VM_Version::has_CompareBranch());
9615   ins_cost(BRANCH_COST+DEFAULT_COST);
9616   // TODO: s390 port size(FIXED_SIZE);
9617   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9618   opcode(CLGFI_ZOPC, BRCL_ZOPC);
9619   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9620   ins_pipe(pipe_class_dummy);
9621   ins_short_branch(0);
9622 %}
9623 
9624 // Compare against zero only, do not mix N and P oops (encode/decode required).
9625 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
9626   match(If boolnode (CmpP (DecodeN src1) src2));
9627   effect(USE labl, KILL cr);
9628   predicate(VM_Version::has_CompareBranch());
9629   ins_cost(BRANCH_COST+DEFAULT_COST);
9630   // TODO: s390 port size(FIXED_SIZE);
9631   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9632   opcode(CLGFI_ZOPC, BRCL_ZOPC);
9633   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9634   ins_pipe(pipe_class_dummy);
9635   ins_short_branch(0);
9636 %}
9637 
9638 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
9639   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
9640   effect(USE labl, KILL cr);
9641   predicate(VM_Version::has_CompareBranch());
9642   ins_cost(BRANCH_COST+DEFAULT_COST);
9643   // TODO: s390 port size(FIXED_SIZE);
9644   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
9645   opcode(CLGFI_ZOPC, BRCL_ZOPC);
9646   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
9647   ins_pipe(pipe_class_dummy);
9648   ins_short_branch(0);
9649 %}
9650 
9651 // ============================================================================
9652 // Long Compare
9653 
9654 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9655 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9656 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9657 // are collapsed internally in the ADLC's dfa-gen code. The match for
9658 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9659 // foo match ends up with the wrong leaf. One fix is to not match both
9660 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9661 // both forms beat the trinary form of long-compare and both are very useful
9662 // on platforms which have few registers.
9663 
9664 // Manifest a CmpL3 result in an integer register. Very painful.
9665 // This is the test to avoid.
9666 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
9667   match(Set dst (CmpL3 src1 src2));
9668   effect(KILL cr);
9669   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
9670   size(24);
9671   format %{ "CmpL3 $dst,$src1,$src2" %}
9672   ins_encode %{
9673     Label done;
9674     // compare registers
9675     __ z_cgr($src1$$Register, $src2$$Register);
9676     // Convert condition code into -1,0,1, where
9677     // -1 means less
9678     //  0 means equal
9679     //  1 means greater.
9680     if (VM_Version::has_LoadStoreConditional()) {
9681       Register one       = Z_R0_scratch;
9682       Register minus_one = Z_R1_scratch;
9683       __ z_lghi(minus_one, -1);
9684       __ z_lghi(one, 1);
9685       __ z_lghi( $dst$$Register, 0);
9686       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
9687       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
9688     } else {
9689       __ clear_reg($dst$$Register, true, false);
9690       __ z_bre(done);
9691       __ z_lhi($dst$$Register, 1);
9692       __ z_brh(done);
9693       __ z_lhi($dst$$Register, -1);
9694     }
9695     __ bind(done);
9696   %}
9697   ins_pipe(pipe_class_dummy);
9698 %}
9699 
9700 // ============================================================================
9701 // Safepoint Instruction
9702 
9703 instruct safePoint() %{
9704   match(SafePoint);
9705   predicate(false);
9706   // TODO: s390 port size(FIXED_SIZE);
9707   format %{ "UNIMPLEMENTED Safepoint_ " %}
9708   ins_encode(enc_unimplemented());
9709   ins_pipe(pipe_class_dummy);
9710 %}
9711 
9712 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
9713   match(SafePoint poll);
9714   effect(USE poll, KILL cr); // R0 is killed, too.
9715   // TODO: s390 port size(FIXED_SIZE);
9716   format %{ "TM      #0[,$poll],#111\t # Safepoint: poll for GC" %}
9717   ins_encode %{
9718     // Mark the code position where the load from the safepoint
9719     // polling page was emitted as relocInfo::poll_type.
9720     __ relocate(relocInfo::poll_type);
9721     __ load_from_polling_page($poll$$Register);
9722   %}
9723   ins_pipe(pipe_class_dummy);
9724 %}
9725 
9726 // ============================================================================
9727 
9728 // Call Instructions
9729 
9730 // Call Java Static Instruction
9731 instruct CallStaticJavaDirect_dynTOC(method meth) %{
9732   match(CallStaticJava);
9733   effect(USE meth);
9734   ins_cost(CALL_COST);
9735   // TODO: s390 port size(VARIABLE_SIZE);
9736   format %{ "CALL,static dynTOC $meth; ==> " %}
9737   ins_encode( z_enc_java_static_call(meth) );
9738   ins_pipe(pipe_class_dummy);
9739   ins_alignment(2);
9740 %}
9741 
9742 // Call Java Dynamic Instruction
9743 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
9744   match(CallDynamicJava);
9745   effect(USE meth);
9746   ins_cost(CALL_COST);
9747   // TODO: s390 port size(VARIABLE_SIZE);
9748   format %{ "CALL,dynamic dynTOC $meth; ==> " %}
9749   ins_encode(z_enc_java_dynamic_call(meth));
9750   ins_pipe(pipe_class_dummy);
9751   ins_alignment(2);
9752 %}
9753 
9754 // Call Runtime Instruction
9755 instruct CallRuntimeDirect(method meth) %{
9756   match(CallRuntime);
9757   effect(USE meth);
9758   ins_cost(CALL_COST);
9759   // TODO: s390 port size(VARIABLE_SIZE);
9760   ins_num_consts(1);
9761   ins_alignment(2);
9762   format %{ "CALL,runtime" %}
9763   ins_encode( z_enc_java_to_runtime_call(meth) );
9764   ins_pipe(pipe_class_dummy);
9765 %}
9766 
9767 // Call runtime without safepoint - same as CallRuntime
9768 instruct CallLeafDirect(method meth) %{
9769   match(CallLeaf);
9770   effect(USE meth);
9771   ins_cost(CALL_COST);
9772   // TODO: s390 port size(VARIABLE_SIZE);
9773   ins_num_consts(1);
9774   ins_alignment(2);
9775   format %{ "CALL,runtime leaf $meth" %}
9776   ins_encode( z_enc_java_to_runtime_call(meth) );
9777   ins_pipe(pipe_class_dummy);
9778 %}
9779 
9780 // Call runtime without safepoint - same as CallLeaf
9781 instruct CallLeafNoFPDirect(method meth) %{
9782   match(CallLeafNoFP);
9783   effect(USE meth);
9784   ins_cost(CALL_COST);
9785   // TODO: s390 port size(VARIABLE_SIZE);
9786   ins_num_consts(1);
9787   format %{ "CALL,runtime leaf nofp $meth" %}
9788   ins_encode( z_enc_java_to_runtime_call(meth) );
9789   ins_pipe(pipe_class_dummy);
9790   ins_alignment(2);
9791 %}
9792 
9793 // Tail Call; Jump from runtime stub to Java code.
9794 // Also known as an 'interprocedural jump'.
9795 // Target of jump will eventually return to caller.
9796 // TailJump below removes the return address.
9797 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_oop) %{
9798   match(TailCall jump_target method_oop);
9799   ins_cost(CALL_COST);
9800   size(2);
9801   format %{ "Jmp     $jump_target\t # $method_oop holds method oop" %}
9802   ins_encode %{ __ z_br($jump_target$$Register); %}
9803   ins_pipe(pipe_class_dummy);
9804 %}
9805 
9806 // Return Instruction
9807 instruct Ret() %{
9808   match(Return);
9809   size(2);
9810   format %{ "BR(Z_R14) // branch to link register" %}
9811   ins_encode %{ __ z_br(Z_R14); %}
9812   ins_pipe(pipe_class_dummy);
9813 %}
9814 
9815 // Tail Jump; remove the return address; jump to target.
9816 // TailCall above leaves the return address around.
9817 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9818 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9819 // "restore" before this instruction (in Epilogue), we need to materialize it
9820 // in %i0.
9821 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
9822   match(TailJump jump_target ex_oop);
9823   ins_cost(CALL_COST);
9824   size(8);
9825   format %{ "TailJump $jump_target" %}
9826   ins_encode %{
9827     __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
9828     __ z_br($jump_target$$Register);
9829   %}
9830   ins_pipe(pipe_class_dummy);
9831 %}
9832 
9833 // Create exception oop: created by stack-crawling runtime code.
9834 // Created exception is now available to this handler, and is setup
9835 // just prior to jumping to this handler. No code emitted.
9836 instruct CreateException(rarg1RegP ex_oop) %{
9837   match(Set ex_oop (CreateEx));
9838   ins_cost(0);
9839   size(0);
9840   format %{ "# exception oop; no code emitted" %}
9841   ins_encode(/*empty*/);
9842   ins_pipe(pipe_class_dummy);
9843 %}
9844 
9845 // Rethrow exception: The exception oop will come in the first
9846 // argument position. Then JUMP (not call) to the rethrow stub code.
9847 instruct RethrowException() %{
9848   match(Rethrow);
9849   ins_cost(CALL_COST);
9850   // TODO: s390 port size(VARIABLE_SIZE);
9851   format %{ "Jmp    rethrow_stub" %}
9852   ins_encode %{
9853     cbuf.set_insts_mark();
9854     __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
9855     __ z_br(Z_R1_scratch);
9856   %}
9857   ins_pipe(pipe_class_dummy);
9858 %}
9859 
9860 // Die now.
9861 instruct ShouldNotReachHere() %{
9862   match(Halt);
9863   ins_cost(CALL_COST);
9864   size(2);
9865   format %{ "ILLTRAP; ShouldNotReachHere" %}
9866   ins_encode %{ __ z_illtrap(); %}
9867   ins_pipe(pipe_class_dummy);
9868 %}
9869 
9870 // ============================================================================
9871 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9872 // array for an instance of the superklass. Set a hidden internal cache on a
9873 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9874 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9875 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
9876                              rarg4RegP scratch1, rarg5RegP scratch2) %{
9877   match(Set index (PartialSubtypeCheck sub super));
9878   effect(KILL pcc, KILL scratch1, KILL scratch2);
9879   ins_cost(10 * DEFAULT_COST);
9880   // TODO: s390 port size(FIXED_SIZE);
9881   format %{ "  CALL   PartialSubtypeCheck\n" %}
9882   ins_encode %{
9883     AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
9884     __ load_const_optimized(Z_ARG4, stub_address);
9885     __ z_basr(Z_R14, Z_ARG4);
9886   %}
9887   ins_pipe(pipe_class_dummy);
9888 %}
9889 
9890 instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero,
9891                                      rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{
9892   match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero));
9893   effect(KILL scratch1, KILL scratch2, KILL index);
9894   ins_cost(10 * DEFAULT_COST);
9895   // TODO: s390 port size(FIXED_SIZE);
9896   format %{ "CALL   PartialSubtypeCheck_vs_zero\n" %}
9897   ins_encode %{
9898     AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
9899     __ load_const_optimized(Z_ARG4, stub_address);
9900     __ z_basr(Z_R14, Z_ARG4);
9901   %}
9902   ins_pipe(pipe_class_dummy);
9903 %}
9904 
9905 // ============================================================================
9906 // inlined locking and unlocking
9907 
9908 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
9909   match(Set pcc (FastLock oop box));
9910   effect(TEMP tmp1, TEMP tmp2);
9911   ins_cost(100);
9912   // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized.
9913   format %{ "FASTLOCK  $oop, $box; KILL Z_ARG4, Z_ARG5" %}
9914   ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
9915                                              UseBiasedLocking && !UseOptoBiasInlining); %}
9916   ins_pipe(pipe_class_dummy);
9917 %}
9918 
9919 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
9920   match(Set pcc (FastUnlock oop box));
9921   effect(TEMP tmp1, TEMP tmp2);
9922   ins_cost(100);
9923   // TODO: s390 port size(FIXED_SIZE);  // emitted code depends on UseBiasedLocking being on/off.
9924   format %{ "FASTUNLOCK  $oop, $box; KILL Z_ARG4, Z_ARG5" %}
9925   ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register,
9926                                                UseBiasedLocking && !UseOptoBiasInlining); %}
9927   ins_pipe(pipe_class_dummy);
9928 %}
9929 
9930 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
9931   match(Set dummy (ClearArray cnt base));
9932   effect(KILL cr);
9933   ins_cost(100);
9934   // TODO: s390 port size(VARIABLE_SIZE);       // Variable in size due to varying #instructions.
9935   format %{ "ClearArrayConst $cnt,$base" %}
9936   ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
9937   ins_pipe(pipe_class_dummy);
9938 %}
9939 
9940 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
9941   match(Set dummy (ClearArray cnt base));
9942   effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
9943   ins_cost(200);
9944   // TODO: s390 port size(VARIABLE_SIZE);       // Variable in size due to optimized constant loader.
9945   format %{ "ClearArrayConstBig $cnt,$base" %}
9946   ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %}
9947   ins_pipe(pipe_class_dummy);
9948 %}
9949 
9950 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
9951   match(Set dummy (ClearArray cnt base));
9952   effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
9953   ins_cost(300);
9954   // TODO: s390 port size(FIXED_SIZE);  // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
9955   format %{ "ClearArrayVar $cnt,$base" %}
9956   ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %}
9957   ins_pipe(pipe_class_dummy);
9958 %}
9959 
9960 // ============================================================================
9961 // CompactStrings
9962 
9963 // String equals
9964 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9965   match(Set result (StrEquals (Binary str1 str2) cnt));
9966   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9967   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
9968   ins_cost(300);
9969   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
9970   ins_encode %{
9971     __ array_equals(false, $str1$$Register, $str2$$Register,
9972                     $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
9973                     $result$$Register, true /* byte */);
9974   %}
9975   ins_pipe(pipe_class_dummy);
9976 %}
9977 
9978 instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
9979   match(Set result (StrEquals (Binary str1 str2) cnt));
9980   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
9981   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
9982   ins_cost(300);
9983   format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %}
9984   ins_encode %{
9985     __ array_equals(false, $str1$$Register, $str2$$Register,
9986                     $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
9987                     $result$$Register, false /* byte */);
9988   %}
9989   ins_pipe(pipe_class_dummy);
9990 %}
9991 
9992 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
9993   match(Set result (StrEquals (Binary str1 str2) cnt));
9994   effect(KILL cr); // R0 is killed, too.
9995   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
9996   ins_cost(100);
9997   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
9998   ins_encode %{
9999     const int cnt_imm = $cnt$$constant;
10000     if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
10001     __ z_lhi($result$$Register, 1);
10002     if (cnt_imm) {
10003       if (VM_Version::has_LoadStoreConditional()) {
10004         __ z_lhi(Z_R0_scratch, 0);
10005         __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10006       } else {
10007         Label Lskip;
10008         __ z_bre(Lskip);
10009         __ clear_reg($result$$Register);
10010         __ bind(Lskip);
10011       }
10012     }
10013   %}
10014   ins_pipe(pipe_class_dummy);
10015 %}
10016 
10017 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
10018   match(Set result (StrEquals (Binary str1 str2) cnt));
10019   effect(KILL cr); // R0 is killed, too.
10020   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
10021   ins_cost(100);
10022   format %{ "String Equals $str1,$str2,$cnt -> $result" %}
10023   ins_encode %{
10024     const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
10025     if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
10026     __ z_lhi($result$$Register, 1);
10027     if (cnt_imm) {
10028       if (VM_Version::has_LoadStoreConditional()) {
10029         __ z_lhi(Z_R0_scratch, 0);
10030         __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
10031       } else {
10032         Label Lskip;
10033         __ z_bre(Lskip);
10034         __ clear_reg($result$$Register);
10035         __ bind(Lskip);
10036       }
10037     }
10038   %}
10039   ins_pipe(pipe_class_dummy);
10040 %}
10041 
10042 // Array equals
10043 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10044   match(Set result (AryEq ary1 ary2));
10045   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10046   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10047   ins_cost(300);
10048   format %{ "Array Equals $ary1,$ary2 -> $result" %}
10049   ins_encode %{
10050     __ array_equals(true, $ary1$$Register, $ary2$$Register,
10051                     noreg, $oddReg$$Register, $evenReg$$Register,
10052                     $result$$Register, true /* byte */);
10053   %}
10054   ins_pipe(pipe_class_dummy);
10055 %}
10056 
10057 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10058   match(Set result (AryEq ary1 ary2));
10059   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10060   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10061   ins_cost(300);
10062   format %{ "Array Equals $ary1,$ary2 -> $result" %}
10063   ins_encode %{
10064     __ array_equals(true, $ary1$$Register, $ary2$$Register,
10065                     noreg, $oddReg$$Register, $evenReg$$Register,
10066                     $result$$Register, false /* byte */);
10067   %}
10068   ins_pipe(pipe_class_dummy);
10069 %}
10070 
10071 // String CompareTo
10072 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10073   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10074   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10075   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10076   ins_cost(300);
10077   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10078   ins_encode %{
10079     __ string_compare($str1$$Register, $str2$$Register,
10080                       $cnt1$$Register, $cnt2$$Register,
10081                       $oddReg$$Register, $evenReg$$Register,
10082                       $result$$Register, StrIntrinsicNode::LL);
10083   %}
10084   ins_pipe(pipe_class_dummy);
10085 %}
10086 
10087 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10088   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10089   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10090   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
10091   ins_cost(300);
10092   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10093   ins_encode %{
10094     __ string_compare($str1$$Register, $str2$$Register,
10095                       $cnt1$$Register, $cnt2$$Register,
10096                       $oddReg$$Register, $evenReg$$Register,
10097                       $result$$Register, StrIntrinsicNode::UU);
10098   %}
10099   ins_pipe(pipe_class_dummy);
10100 %}
10101 
10102 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10103   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10104   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10105   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10106   ins_cost(300);
10107   format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10108   ins_encode %{
10109     __ string_compare($str1$$Register, $str2$$Register,
10110                       $cnt1$$Register, $cnt2$$Register,
10111                       $oddReg$$Register, $evenReg$$Register,
10112                       $result$$Register, StrIntrinsicNode::LU);
10113   %}
10114   ins_pipe(pipe_class_dummy);
10115 %}
10116 
10117 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10118   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10119   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10120   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10121   ins_cost(300);
10122   format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10123   ins_encode %{
10124     __ string_compare($str2$$Register, $str1$$Register,
10125                       $cnt2$$Register, $cnt1$$Register,
10126                       $oddReg$$Register, $evenReg$$Register,
10127                       $result$$Register, StrIntrinsicNode::UL);
10128   %}
10129   ins_pipe(pipe_class_dummy);
10130 %}
10131 
10132 // String IndexOfChar
10133 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10134   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10135   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10136   ins_cost(200);
10137   format %{ "String IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10138   ins_encode %{
10139     __ string_indexof_char($result$$Register,
10140                            $haystack$$Register, $haycnt$$Register,
10141                            $ch$$Register, 0 /* unused, ch is in register */,
10142                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10143   %}
10144   ins_pipe(pipe_class_dummy);
10145 %}
10146 
10147 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10148   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10149   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10150   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10151   ins_cost(200);
10152   format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10153   ins_encode %{
10154     immPOper *needleOper = (immPOper *)$needle;
10155     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10156     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10157     jchar chr;
10158 #ifdef VM_LITTLE_ENDIAN
10159     Unimplemented();
10160 #else
10161     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10162            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10163 #endif
10164     __ string_indexof_char($result$$Register,
10165                            $haystack$$Register, $haycnt$$Register,
10166                            noreg, chr,
10167                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10168   %}
10169   ins_pipe(pipe_class_dummy);
10170 %}
10171 
10172 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10173   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10174   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10175   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10176   ins_cost(200);
10177   format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10178   ins_encode %{
10179     immPOper *needleOper = (immPOper *)$needle;
10180     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10181     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10182     jchar chr = (jchar)needle_values->element_value(0).as_byte();
10183     __ string_indexof_char($result$$Register,
10184                            $haystack$$Register, $haycnt$$Register,
10185                            noreg, chr,
10186                            $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10187   %}
10188   ins_pipe(pipe_class_dummy);
10189 %}
10190 
10191 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10192   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10193   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10194   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10195   ins_cost(200);
10196   format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10197   ins_encode %{
10198     immPOper *needleOper = (immPOper *)$needle;
10199     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10200     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10201     jchar chr = (jchar)needle_values->element_value(0).as_byte();
10202     __ string_indexof_char($result$$Register,
10203                            $haystack$$Register, $haycnt$$Register,
10204                            noreg, chr,
10205                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10206   %}
10207   ins_pipe(pipe_class_dummy);
10208 %}
10209 
10210 // String IndexOf
10211 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10212   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10213   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10214   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10215   ins_cost(250);
10216   format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10217   ins_encode %{
10218     __ string_indexof($result$$Register,
10219                       $haystack$$Register, $haycnt$$Register,
10220                       $needle$$Register, noreg, $needlecntImm$$constant,
10221                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10222   %}
10223   ins_pipe(pipe_class_dummy);
10224 %}
10225 
10226 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10227   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10228   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10229   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10230   ins_cost(250);
10231   format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10232   ins_encode %{
10233     __ string_indexof($result$$Register,
10234                       $haystack$$Register, $haycnt$$Register,
10235                       $needle$$Register, noreg, $needlecntImm$$constant,
10236                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10237   %}
10238   ins_pipe(pipe_class_dummy);
10239 %}
10240 
10241 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10242   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10243   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10244   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10245   ins_cost(250);
10246   format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10247   ins_encode %{
10248     __ string_indexof($result$$Register,
10249                       $haystack$$Register, $haycnt$$Register,
10250                       $needle$$Register, noreg, $needlecntImm$$constant,
10251                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10252   %}
10253   ins_pipe(pipe_class_dummy);
10254 %}
10255 
10256 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10257   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10258   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10259   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10260   ins_cost(300);
10261   format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10262   ins_encode %{
10263     __ string_indexof($result$$Register,
10264                       $haystack$$Register, $haycnt$$Register,
10265                       $needle$$Register, $needlecnt$$Register, 0,
10266                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10267   %}
10268   ins_pipe(pipe_class_dummy);
10269 %}
10270 
10271 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10272   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10273   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10274   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10275   ins_cost(300);
10276   format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10277   ins_encode %{
10278     __ string_indexof($result$$Register,
10279                       $haystack$$Register, $haycnt$$Register,
10280                       $needle$$Register, $needlecnt$$Register, 0,
10281                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10282   %}
10283   ins_pipe(pipe_class_dummy);
10284 %}
10285 
10286 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10287   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10288   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10289   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10290   ins_cost(300);
10291   format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10292   ins_encode %{
10293     __ string_indexof($result$$Register,
10294                       $haystack$$Register, $haycnt$$Register,
10295                       $needle$$Register, $needlecnt$$Register, 0,
10296                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10297   %}
10298   ins_pipe(pipe_class_dummy);
10299 %}
10300 
10301 // char[] to byte[] compression
10302 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
10303   match(Set result (StrCompressedCopy src (Binary dst len)));
10304   effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10305   ins_cost(300);
10306   format %{ "String Compress $src->$dst($len) -> $result" %}
10307   ins_encode %{
10308     __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10309                        $tmp$$Register, false);
10310   %}
10311   ins_pipe(pipe_class_dummy);
10312 %}
10313 
10314 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10315 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10316 //  match(Set dummy (StrInflatedCopy src (Binary dst len)));
10317 //  effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10318 //  predicate(VM_Version::has_ETF2Enhancements());
10319 //  ins_cost(300);
10320 //  format %{ "String Inflate (trot) $dst,$src($len)" %}
10321 //  ins_encode %{
10322 //    __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10323 //  %}
10324 //  ins_pipe(pipe_class_dummy);
10325 //%}
10326 
10327 // byte[] to char[] inflation
10328 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, flagsReg cr) %{
10329   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10330   effect(TEMP tmp, KILL cr); // R0, R1 are killed, too.
10331   ins_cost(300);
10332   format %{ "String Inflate $src->$dst($len)" %}
10333   ins_encode %{
10334     __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10335   %}
10336   ins_pipe(pipe_class_dummy);
10337 %}
10338 
10339 // byte[] to char[] inflation
10340 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, flagsReg cr) %{
10341   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10342   effect(TEMP tmp, KILL cr); // R0, R1 are killed, too.
10343   ins_cost(300);
10344   format %{ "String Inflate (constLen) $src->$dst($len)" %}
10345   ins_encode %{
10346     __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant);
10347   %}
10348   ins_pipe(pipe_class_dummy);
10349 %}
10350 
10351 // StringCoding.java intrinsics
10352 instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10353   match(Set result (HasNegatives ary1 len));
10354   effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10355   ins_cost(300);
10356   format %{ "has negatives byte[] $ary1($len) -> $result" %}
10357   ins_encode %{
10358     __ has_negatives($result$$Register, $ary1$$Register, $len$$Register,
10359                      $oddReg$$Register, $evenReg$$Register, $tmp$$Register);
10360   %}
10361   ins_pipe(pipe_class_dummy);
10362 %}
10363 
10364 // encode char[] to byte[] in ISO_8859_1
10365 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
10366   match(Set result (EncodeISOArray src (Binary dst len)));
10367   effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10368   ins_cost(300);
10369   format %{ "Encode array $src->$dst($len) -> $result" %}
10370   ins_encode %{
10371     __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10372                        $tmp$$Register, true);
10373   %}
10374   ins_pipe(pipe_class_dummy);
10375 %}
10376 
10377 
10378 //----------PEEPHOLE RULES-----------------------------------------------------
10379 // These must follow all instruction definitions as they use the names
10380 // defined in the instructions definitions.
10381 //
10382 // peepmatch (root_instr_name [preceeding_instruction]*);
10383 //
10384 // peepconstraint %{
10385 // (instruction_number.operand_name relational_op instruction_number.operand_name
10386 //  [, ...]);
10387 // // instruction numbers are zero-based using left to right order in peepmatch
10388 //
10389 // peepreplace (instr_name([instruction_number.operand_name]*));
10390 // // provide an instruction_number.operand_name for each operand that appears
10391 // // in the replacement instruction's match rule
10392 //
10393 // ---------VM FLAGS---------------------------------------------------------
10394 //
10395 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10396 //
10397 // Each peephole rule is given an identifying number starting with zero and
10398 // increasing by one in the order seen by the parser. An individual peephole
10399 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10400 // on the command-line.
10401 //
10402 // ---------CURRENT LIMITATIONS----------------------------------------------
10403 //
10404 // Only match adjacent instructions in same basic block
10405 // Only equality constraints
10406 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10407 // Only one replacement instruction
10408 //
10409 // ---------EXAMPLE----------------------------------------------------------
10410 //
10411 // // pertinent parts of existing instructions in architecture description
10412 // instruct movI(eRegI dst, eRegI src) %{
10413 //   match(Set dst (CopyI src));
10414 // %}
10415 //
10416 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10417 //   match(Set dst (AddI dst src));
10418 //   effect(KILL cr);
10419 // %}
10420 //
10421 // // Change (inc mov) to lea
10422 // peephole %{
10423 //   // increment preceeded by register-register move
10424 //   peepmatch (incI_eReg movI);
10425 //   // require that the destination register of the increment
10426 //   // match the destination register of the move
10427 //   peepconstraint (0.dst == 1.dst);
10428 //   // construct a replacement instruction that sets
10429 //   // the destination to (move's source register + one)
10430 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10431 // %}
10432 //
10433 // Implementation no longer uses movX instructions since
10434 // machine-independent system no longer uses CopyX nodes.
10435 //
10436 // peephole %{
10437 //   peepmatch (incI_eReg movI);
10438 //   peepconstraint (0.dst == 1.dst);
10439 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10440 // %}
10441 //
10442 // peephole %{
10443 //   peepmatch (decI_eReg movI);
10444 //   peepconstraint (0.dst == 1.dst);
10445 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10446 // %}
10447 //
10448 // peephole %{
10449 //   peepmatch (addI_eReg_imm movI);
10450 //   peepconstraint (0.dst == 1.dst);
10451 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10452 // %}
10453 //
10454 // peephole %{
10455 //   peepmatch (addP_eReg_imm movP);
10456 //   peepconstraint (0.dst == 1.dst);
10457 //   peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10458 // %}
10459 
10460 
10461 //  This peephole rule does not work, probably because ADLC can't handle two effects:
10462 //  Effect 1 is defining 0.op1 and effect 2 is setting CC
10463 // condense a load from memory and subsequent test for zero
10464 // into a single, more efficient ICM instruction.
10465 // peephole %{
10466 //   peepmatch (compI_iReg_imm0 loadI);
10467 //   peepconstraint (1.dst == 0.op1);
10468 //   peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10469 // %}
10470 
10471 // // Change load of spilled value to only a spill
10472 // instruct storeI(memory mem, eRegI src) %{
10473 //   match(Set mem (StoreI mem src));
10474 // %}
10475 //
10476 // instruct loadI(eRegI dst, memory mem) %{
10477 //   match(Set dst (LoadI mem));
10478 // %}
10479 //
10480 peephole %{
10481   peepmatch (loadI storeI);
10482   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10483   peepreplace (storeI(1.mem 1.mem 1.src));
10484 %}
10485 
10486 peephole %{
10487   peepmatch (loadL storeL);
10488   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10489   peepreplace (storeL(1.mem 1.mem 1.src));
10490 %}
10491 
10492 peephole %{
10493   peepmatch (loadP storeP);
10494   peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10495   peepreplace (storeP(1.dst 1.dst 1.src));
10496 %}
10497 
10498 //----------SUPERWORD RULES---------------------------------------------------
10499 
10500 //  Expand rules for special cases
10501 
10502 instruct expand_storeF(stackSlotF mem, regF src) %{
10503   // No match rule, false predicate, for expand only.
10504   effect(DEF mem, USE src);
10505   predicate(false);
10506   ins_cost(MEMORY_REF_COST);
10507   // TODO: s390 port size(FIXED_SIZE);
10508   format %{ "STE      $src,$mem\t # replicate(float2stack)" %}
10509   opcode(STE_ZOPC, STE_ZOPC);
10510   ins_encode(z_form_rt_mem(src, mem));
10511   ins_pipe(pipe_class_dummy);
10512 %}
10513 
10514 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10515   // No match rule, false predicate, for expand only.
10516   effect(DEF dst, USE mem);
10517   predicate(false);
10518   ins_cost(MEMORY_REF_COST);
10519   // TODO: s390 port size(FIXED_SIZE);
10520   format %{ "LLGF     $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10521   opcode(LLGF_ZOPC, LLGF_ZOPC);
10522   ins_encode(z_form_rt_mem(dst, mem));
10523   ins_pipe(pipe_class_dummy);
10524 %}
10525 
10526 // Replicate scalar int to packed int values (8 Bytes)
10527 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10528   // Dummy match rule, false predicate, for expand only.
10529   match(Set dst (ConvI2L src));
10530   predicate(false);
10531   ins_cost(DEFAULT_COST);
10532   // TODO: s390 port size(FIXED_SIZE);
10533   format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10534   ins_encode %{
10535     if ($dst$$Register == $src$$Register) {
10536       __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10537       __ z_ogr($dst$$Register, Z_R0_scratch);
10538     }  else {
10539       __ z_sllg($dst$$Register, $src$$Register, 64-32);
10540       __ z_ogr( $dst$$Register, $src$$Register);
10541     }
10542   %}
10543   ins_pipe(pipe_class_dummy);
10544 %}
10545 
10546 // Replication
10547 
10548 // Exploit rotate_then_insert, if available
10549 // Replicate scalar byte to packed byte values (8 Bytes).
10550 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10551   match(Set dst (ReplicateB src));
10552   effect(KILL cr);
10553   predicate((n->as_Vector()->length() == 8));
10554   format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10555   ins_encode %{
10556     if ($dst$$Register != $src$$Register) {
10557       __ z_lgr($dst$$Register, $src$$Register);
10558     }
10559     __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55,  8, false);
10560     __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10561     __ rotate_then_insert($dst$$Register, $dst$$Register,  0, 31, 32, false);
10562   %}
10563   ins_pipe(pipe_class_dummy);
10564 %}
10565 
10566 // Replicate scalar byte to packed byte values (8 Bytes).
10567 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10568   match(Set dst (ReplicateB src));
10569   predicate(n->as_Vector()->length() == 8);
10570   ins_should_rematerialize(true);
10571   format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10572   ins_encode %{
10573     int64_t  Isrc8 = $src$$constant & 0x000000ff;
10574     int64_t Isrc16 =  Isrc8 <<  8 |  Isrc8;
10575     int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10576     assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10577 
10578     __ z_llilf($dst$$Register, Isrc32);
10579     __ z_iihf($dst$$Register, Isrc32);
10580   %}
10581   ins_pipe(pipe_class_dummy);
10582 %}
10583 
10584 // Replicate scalar byte to packed byte values (8 Bytes).
10585 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10586   match(Set dst (ReplicateB src));
10587   predicate(n->as_Vector()->length() == 8);
10588   ins_should_rematerialize(true);
10589   format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10590   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10591   ins_pipe(pipe_class_dummy);
10592 %}
10593 
10594 // Replicate scalar byte to packed byte values (8 Bytes).
10595 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10596   match(Set dst (ReplicateB src));
10597   predicate(n->as_Vector()->length() == 8);
10598   ins_should_rematerialize(true);
10599   format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10600   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10601   ins_pipe(pipe_class_dummy);
10602 %}
10603 
10604 // Exploit rotate_then_insert, if available
10605 // Replicate scalar short to packed short values (8 Bytes).
10606 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10607   match(Set dst (ReplicateS src));
10608   effect(KILL cr);
10609   predicate((n->as_Vector()->length() == 4));
10610   format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10611   ins_encode %{
10612     if ($dst$$Register != $src$$Register) {
10613       __ z_lgr($dst$$Register, $src$$Register);
10614     }
10615     __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10616     __ rotate_then_insert($dst$$Register, $dst$$Register,  0, 31, 32, false);
10617   %}
10618   ins_pipe(pipe_class_dummy);
10619 %}
10620 
10621 // Replicate scalar short to packed short values (8 Bytes).
10622 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10623   match(Set dst (ReplicateS src));
10624   predicate(n->as_Vector()->length() == 4);
10625   ins_should_rematerialize(true);
10626   format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10627   ins_encode %{
10628     int64_t Isrc16 = $src$$constant & 0x0000ffff;
10629     int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10630     assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10631            ") should be handled by other match rules.", $src$$constant);
10632 
10633     __ z_llilf($dst$$Register, Isrc32);
10634     __ z_iihf($dst$$Register, Isrc32);
10635   %}
10636   ins_pipe(pipe_class_dummy);
10637 %}
10638 
10639 // Replicate scalar short to packed short values (8 Bytes).
10640 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10641   match(Set dst (ReplicateS src));
10642   predicate(n->as_Vector()->length() == 4);
10643   ins_should_rematerialize(true);
10644   format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10645   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10646   ins_pipe(pipe_class_dummy);
10647 %}
10648 
10649 // Replicate scalar short to packed short values (8 Bytes).
10650 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10651   match(Set dst (ReplicateS src));
10652   predicate(n->as_Vector()->length() == 4);
10653   ins_should_rematerialize(true);
10654   format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10655   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10656   ins_pipe(pipe_class_dummy);
10657 %}
10658 
10659 // Exploit rotate_then_insert, if available.
10660 // Replicate scalar int to packed int values (8 Bytes).
10661 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10662   match(Set dst (ReplicateI src));
10663   effect(KILL cr);
10664   predicate((n->as_Vector()->length() == 2));
10665   format %{ "REPLIC2I $dst,$src\t # pack2I" %}
10666   ins_encode %{
10667     if ($dst$$Register != $src$$Register) {
10668       __ z_lgr($dst$$Register, $src$$Register);
10669     }
10670     __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10671   %}
10672   ins_pipe(pipe_class_dummy);
10673 %}
10674 
10675 // Replicate scalar int to packed int values (8 Bytes).
10676 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
10677   match(Set dst (ReplicateI src));
10678   predicate(n->as_Vector()->length() == 2);
10679   ins_should_rematerialize(true);
10680   format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
10681   ins_encode %{
10682     int64_t Isrc32 = $src$$constant;
10683     assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
10684 
10685     __ z_llilf($dst$$Register, Isrc32);
10686     __ z_iihf($dst$$Register, Isrc32);
10687   %}
10688   ins_pipe(pipe_class_dummy);
10689 %}
10690 
10691 // Replicate scalar int to packed int values (8 Bytes).
10692 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
10693   match(Set dst (ReplicateI src));
10694   predicate(n->as_Vector()->length() == 2);
10695   ins_should_rematerialize(true);
10696   format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
10697   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10698   ins_pipe(pipe_class_dummy);
10699 %}
10700 
10701 // Replicate scalar int to packed int values (8 Bytes).
10702 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
10703   match(Set dst (ReplicateI src));
10704   predicate(n->as_Vector()->length() == 2);
10705   ins_should_rematerialize(true);
10706   format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
10707   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10708   ins_pipe(pipe_class_dummy);
10709 %}
10710 
10711 //
10712 
10713 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
10714   match(Set dst (ReplicateF src));
10715   effect(KILL cr);
10716   predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10717   format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
10718   expand %{
10719     stackSlotF tmp;
10720     iRegL      tmp2;
10721     expand_storeF(tmp, src);
10722     expand_LoadLogical_I2L(tmp2, tmp);
10723     expand_Repl2I_reg(dst, tmp2);
10724   %}
10725 %}
10726 
10727 // Replicate scalar float to packed float values in GREG (8 Bytes).
10728 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
10729   match(Set dst (ReplicateF src));
10730   effect(KILL cr);
10731   predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10732   format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
10733   ins_encode %{
10734     assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
10735     __ z_lgdr($dst$$Register, $src$$FloatRegister);
10736 
10737     __ z_srlg(Z_R0_scratch, $dst$$Register, 32);  // Floats are left-justified in 64bit reg.
10738     __ z_iilf($dst$$Register, 0);                 // Save a "result not ready" stall.
10739     __ z_ogr($dst$$Register, Z_R0_scratch);
10740   %}
10741   ins_pipe(pipe_class_dummy);
10742 %}
10743 
10744 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
10745 instruct Repl2F_imm(iRegL dst, immF src) %{
10746   match(Set dst (ReplicateF src));
10747   predicate(n->as_Vector()->length() == 2);
10748   ins_should_rematerialize(true);
10749   format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
10750   ins_encode %{
10751     union {
10752       int   Isrc32;
10753       float Fsrc32;
10754     };
10755     Fsrc32 = $src$$constant;
10756     __ z_llilf($dst$$Register, Isrc32);
10757     __ z_iihf($dst$$Register, Isrc32);
10758   %}
10759   ins_pipe(pipe_class_dummy);
10760 %}
10761 
10762 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
10763 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
10764 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
10765   match(Set dst (ReplicateF src));
10766   predicate(n->as_Vector()->length() == 2);
10767   ins_should_rematerialize(true);
10768   format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
10769   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10770   ins_pipe(pipe_class_dummy);
10771 %}
10772 
10773 // Store
10774 
10775 // Store Aligned Packed Byte register to memory (8 Bytes).
10776 instruct storeA8B(memory mem, iRegL src) %{
10777   match(Set mem (StoreVector mem src));
10778   predicate(n->as_StoreVector()->memory_size() == 8);
10779   ins_cost(MEMORY_REF_COST);
10780   // TODO: s390 port size(VARIABLE_SIZE);
10781   format %{ "STG     $src,$mem\t # ST(packed8B)" %}
10782   opcode(STG_ZOPC, STG_ZOPC);
10783   ins_encode(z_form_rt_mem_opt(src, mem));
10784   ins_pipe(pipe_class_dummy);
10785 %}
10786 
10787 // Load
10788 
10789 instruct loadV8(iRegL dst, memory mem) %{
10790   match(Set dst (LoadVector mem));
10791   predicate(n->as_LoadVector()->memory_size() == 8);
10792   ins_cost(MEMORY_REF_COST);
10793   // TODO: s390 port size(VARIABLE_SIZE);
10794   format %{ "LG      $dst,$mem\t # L(packed8B)" %}
10795   opcode(LG_ZOPC, LG_ZOPC);
10796   ins_encode(z_form_rt_mem_opt(dst, mem));
10797   ins_pipe(pipe_class_dummy);
10798 %}
10799 
10800 //----------POPULATION COUNT RULES--------------------------------------------
10801 
10802 // Byte reverse
10803 
10804 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
10805   match(Set dst (ReverseBytesI src));
10806   predicate(UseByteReverseInstruction);  // See Matcher::match_rule_supported
10807   ins_cost(DEFAULT_COST);
10808   size(4);
10809   format %{ "LRVR    $dst,$src\t # byte reverse int" %}
10810   opcode(LRVR_ZOPC);
10811   ins_encode(z_rreform(dst, src));
10812   ins_pipe(pipe_class_dummy);
10813 %}
10814 
10815 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
10816   match(Set dst (ReverseBytesL src));
10817   predicate(UseByteReverseInstruction);  // See Matcher::match_rule_supported
10818   ins_cost(DEFAULT_COST);
10819   // TODO: s390 port size(FIXED_SIZE);
10820   format %{ "LRVGR   $dst,$src\t # byte reverse long" %}
10821   opcode(LRVGR_ZOPC);
10822   ins_encode(z_rreform(dst, src));
10823   ins_pipe(pipe_class_dummy);
10824 %}
10825 
10826 // Leading zeroes
10827 
10828 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
10829 // returns the bit position of the leftmost 1 in the 64bit source register.
10830 // As the bits are numbered from left to right (0..63), the returned
10831 // position index is equivalent to the number of leading zeroes.
10832 // If no 1-bit is found (i.e. the regsiter contains zero), the instruction
10833 // returns position 64. That's exactly what we need.
10834 
10835 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10836   match(Set dst (CountLeadingZerosI src));
10837   effect(KILL tmp, KILL cr);
10838   ins_cost(3 * DEFAULT_COST);
10839   size(14);
10840   format %{ "SLLG    $dst,$src,32\t # no need to always count 32 zeroes first\n\t"
10841             "IILH    $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t"
10842             "FLOGR   $dst,$dst"
10843          %}
10844   ins_encode %{
10845     // Performance experiments indicate that "FLOGR" is using some kind of
10846     // iteration to find the leftmost "1" bit.
10847     //
10848     // The prior implementation zero-extended the 32-bit argument to 64 bit,
10849     // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
10850     // We could gain measurable speedup in micro benchmark:
10851     //
10852     //               leading   trailing
10853     //   z10:   int     2.04       1.68
10854     //         long     1.00       1.02
10855     //   z196:  int     0.99       1.23
10856     //         long     1.00       1.11
10857     //
10858     // By shifting the argument into the high-word instead of zero-extending it.
10859     // The add'l branch on condition (taken for a zero argument, very infrequent,
10860     // good prediction) is well compensated for by the savings.
10861     //
10862     // We leave the previous implementation in for some time in the future when
10863     // the "FLOGR" instruction may become less iterative.
10864 
10865     // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
10866     __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
10867     __ z_iilh($dst$$Register, 0x8000);   // Insert "stop bit" to force result 32 for zero src.
10868     __ z_flogr($dst$$Register, $dst$$Register);
10869   %}
10870   ins_pipe(pipe_class_dummy);
10871 %}
10872 
10873 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
10874   match(Set dst (CountLeadingZerosL src));
10875   effect(KILL tmp, KILL cr);
10876   ins_cost(DEFAULT_COST);
10877   size(4);
10878   format %{ "FLOGR   $dst,$src \t # count leading zeros (long)\n\t" %}
10879   ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
10880   ins_pipe(pipe_class_dummy);
10881 %}
10882 
10883 // trailing zeroes
10884 
10885 // We transform the trailing zeroes problem to a leading zeroes problem
10886 // such that can use the FLOGR instruction to our advantage.
10887 
10888 // With
10889 //   tmp1 = src - 1
10890 // we flip all trailing zeroes to ones and the rightmost one to zero.
10891 // All other bits remain unchanged.
10892 // With the complement
10893 //   tmp2 = ~src
10894 // we get all ones in the trailing zeroes positions. Thus,
10895 //   tmp3 = tmp1 & tmp2
10896 // yields ones in the trailing zeroes positions and zeroes elsewhere.
10897 // Now we can apply FLOGR and get 64-(trailing zeroes).
10898 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10899   match(Set dst (CountTrailingZerosI src));
10900   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10901   ins_cost(8 * DEFAULT_COST);
10902   // TODO: s390 port size(FIXED_SIZE);  // Emitted code depends on PreferLAoverADD being on/off.
10903   format %{ "LLGFR   $dst,$src  \t # clear upper 32 bits (we are dealing with int)\n\t"
10904             "LCGFR   $tmp,$src  \t # load 2's complement (32->64 bit)\n\t"
10905             "AGHI    $dst,-1    \t # tmp1 = src-1\n\t"
10906             "AGHI    $tmp,-1    \t # tmp2 = -src-1 = ~src\n\t"
10907             "NGR     $dst,$tmp  \t # tmp3 = tmp1&tmp2\n\t"
10908             "FLOGR   $dst,$dst  \t # count trailing zeros (int)\n\t"
10909             "AHI     $dst,-64   \t # tmp4 = 64-(trailing zeroes)-64\n\t"
10910             "LCR     $dst,$dst  \t # res = -tmp4"
10911          %}
10912   ins_encode %{
10913     Register Rdst = $dst$$Register;
10914     Register Rsrc = $src$$Register;
10915     // Rtmp only needed for for zero-argument shortcut. With kill effect in
10916     // match rule Rsrc = roddReg would be possible, saving one register.
10917     Register Rtmp = $tmp$$Register;
10918 
10919     assert_different_registers(Rdst, Rsrc, Rtmp);
10920 
10921     // Algorithm:
10922     // - Isolate the least significant (rightmost) set bit using (src & (-src)).
10923     //   All other bits in the result are zero.
10924     // - Find the "leftmost one" bit position in the single-bit result from previous step.
10925     // - 63-("leftmost one" bit position) gives the # of trailing zeros.
10926 
10927     // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
10928     Label done;
10929     __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
10930     __ z_lcgfr(Rtmp, Rsrc);
10931     __ z_bre(done);                    // Taken very infrequently, good prediction, no BHT entry.
10932 
10933     __ z_nr(Rtmp, Rsrc);               // (src) & (-src) leaves nothing but least significant bit.
10934     __ z_ahi(Rtmp,  -1);               // Subtract one to fill all trailing zero positions with ones.
10935                                        // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
10936                                        // into upper half of reg. Not relevant with sllg below.
10937     __ z_sllg(Rdst, Rtmp, 32);         // Shift interesting contents to upper half of register.
10938     __ z_bre(done);                    // Shortcut for argument = 1, result will be 0.
10939                                        // Depends on CC set by ahi above.
10940                                        // Taken very infrequently, good prediction, no BHT entry.
10941                                        // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
10942                                        // after SLLG Rdst == 0(64bit)).
10943     __ z_flogr(Rdst, Rdst);            // Kills tmp which is the oddReg for dst.
10944     __ add2reg(Rdst,  -32);            // 32-pos(leftmost1) is #trailing zeros
10945     __ z_lcgfr(Rdst, Rdst);            // Provide 64bit result at no cost.
10946     __ bind(done);
10947   %}
10948   ins_pipe(pipe_class_dummy);
10949 %}
10950 
10951 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
10952   match(Set dst (CountTrailingZerosL src));
10953   effect(TEMP_DEF dst, KILL tmp, KILL cr);
10954   ins_cost(8 * DEFAULT_COST);
10955   // TODO: s390 port size(FIXED_SIZE);  // Emitted code depends on PreferLAoverADD being on/off.
10956   format %{ "LCGR    $dst,$src  \t # preserve src\n\t"
10957             "NGR     $dst,$src  \t #\n\t"
10958             "AGHI    $dst,-1    \t # tmp1 = src-1\n\t"
10959             "FLOGR   $dst,$dst  \t # count trailing zeros (long), kill $tmp\n\t"
10960             "AHI     $dst,-64   \t # tmp4 = 64-(trailing zeroes)-64\n\t"
10961             "LCR     $dst,$dst  \t #"
10962          %}
10963   ins_encode %{
10964     Register Rdst = $dst$$Register;
10965     Register Rsrc = $src$$Register;
10966     assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
10967 
10968     // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
10969     __ z_lcgr(Rdst, Rsrc);
10970     __ z_ngr(Rdst, Rsrc);
10971     __ add2reg(Rdst,   -1);
10972     __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
10973     __ add2reg(Rdst,  -64);
10974     __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
10975   %}
10976   ins_pipe(pipe_class_dummy);
10977 %}
10978 
10979 
10980 // bit count
10981 
10982 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10983   match(Set dst (PopCountI src));
10984   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10985   predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10986   ins_cost(DEFAULT_COST);
10987   size(24);
10988   format %{ "POPCNT  $dst,$src\t # pop count int" %}
10989   ins_encode %{
10990     Register Rdst = $dst$$Register;
10991     Register Rsrc = $src$$Register;
10992     Register Rtmp = $tmp$$Register;
10993 
10994     // Prefer compile-time assertion over run-time SIGILL.
10995     assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10996     assert_different_registers(Rdst, Rtmp);
10997 
10998     // Version 2: shows 10%(z196) improvement over original.
10999     __ z_popcnt(Rdst, Rsrc);
11000     __ z_srlg(Rtmp, Rdst, 16); // calc  byte4+byte6 and byte5+byte7
11001     __ z_alr(Rdst, Rtmp);      //   into byte6 and byte7
11002     __ z_srlg(Rtmp, Rdst,  8); // calc (byte4+byte6) + (byte5+byte7)
11003     __ z_alr(Rdst, Rtmp);      //   into byte7
11004     __ z_llgcr(Rdst, Rdst);    // zero-extend sum
11005   %}
11006   ins_pipe(pipe_class_dummy);
11007 %}
11008 
11009 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
11010   match(Set dst (PopCountL src));
11011   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
11012   predicate(UsePopCountInstruction && VM_Version::has_PopCount());
11013   ins_cost(DEFAULT_COST);
11014   // TODO: s390 port size(FIXED_SIZE);
11015   format %{ "POPCNT  $dst,$src\t # pop count long" %}
11016   ins_encode %{
11017     Register Rdst = $dst$$Register;
11018     Register Rsrc = $src$$Register;
11019     Register Rtmp = $tmp$$Register;
11020 
11021     // Prefer compile-time assertion over run-time SIGILL.
11022     assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
11023     assert_different_registers(Rdst, Rtmp);
11024 
11025     // Original version. Using LA instead of algr seems to be a really bad idea (-35%).
11026     __ z_popcnt(Rdst, Rsrc);
11027     __ z_ahhlr(Rdst, Rdst, Rdst);
11028     __ z_sllg(Rtmp, Rdst, 16);
11029     __ z_algr(Rdst, Rtmp);
11030     __ z_sllg(Rtmp, Rdst,  8);
11031     __ z_algr(Rdst, Rtmp);
11032     __ z_srlg(Rdst, Rdst, 56);
11033   %}
11034   ins_pipe(pipe_class_dummy);
11035 %}
11036 
11037 //----------SMARTSPILL RULES---------------------------------------------------
11038 // These must follow all instruction definitions as they use the names
11039 // defined in the instructions definitions.
11040 
11041 // ============================================================================
11042 // TYPE PROFILING RULES