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src/hotspot/cpu/x86/assembler_x86.cpp

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*** 787,798 **** case 0x57: // xorps case 0x58: // addpd case 0x59: // mulpd case 0x6E: // movd case 0x7E: // movd - case 0x6F: // movdq - case 0x7F: // movdq case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush case 0xFE: // paddd debug_only(has_disp32 = true); break; --- 787,796 ----
*** 1378,1396 **** int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); emit_int8((unsigned char)0xDC); emit_int8(0xC0 | encode); } - void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { - assert(VM_Version::supports_vaes(), "requires vaes support/enabling"); - InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); - attributes.set_is_evex_instruction(); - int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); - emit_int8((unsigned char)0xDC); - emit_int8((unsigned char)(0xC0 | encode)); - } - void Assembler::aesenclast(XMMRegister dst, Address src) { assert(VM_Version::supports_aes(), ""); InstructionMark im(this); InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); --- 1376,1385 ----
*** 1404,1422 **** int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); emit_int8((unsigned char)0xDD); emit_int8((unsigned char)(0xC0 | encode)); } - void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { - assert(VM_Version::supports_vaes(), "requires vaes support/enabling"); - InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); - attributes.set_is_evex_instruction(); - int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); - emit_int8((unsigned char)0xDD); - emit_int8((unsigned char)(0xC0 | encode)); - } - void Assembler::andl(Address dst, int32_t imm32) { InstructionMark im(this); prefix(dst); emit_int8((unsigned char)0x81); emit_operand(rsp, dst, 4); --- 1393,1402 ----
*** 2272,2289 **** emit_int8(0x0F); emit_int8((unsigned char)0xAE); emit_int8((unsigned char)0xF0); } - // Emit sfence instruction - void Assembler::sfence() { - NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) - emit_int8(0x0F); - emit_int8((unsigned char)0xAE); - emit_int8((unsigned char)0xF8); - } - void Assembler::mov(Register dst, Register src) { LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); } void Assembler::movapd(XMMRegister dst, XMMRegister src) { --- 2252,2261 ----
*** 4300,4310 **** simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); emit_int8(0x70); emit_operand(dst, src); emit_int8(mode & 0xFF); } - void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { assert(VM_Version::supports_evex(), "requires EVEX support"); assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, ""); InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); attributes.set_is_evex_instruction(); --- 4272,4281 ----
*** 8623,8671 **** prefix(REX_W); emit_int8((unsigned char)0x99); } void Assembler::clflush(Address adr) { - assert(VM_Version::supports_clflush(), "should do"); prefix(adr); emit_int8(0x0F); emit_int8((unsigned char)0xAE); emit_operand(rdi, adr); } - void Assembler::clflushopt(Address adr) { - assert(VM_Version::supports_clflushopt(), "should do!"); - // adr should be base reg only with no index or offset - assert(adr.index() == noreg, "index should be noreg"); - assert(adr.scale() == Address::no_scale, "scale should be no_scale"); - assert(adr.disp() == 0, "displacement should be 0"); - // instruction prefix is 0x66 - emit_int8(0x66); - prefix(adr); - // opcode family is 0x0f 0xAE - emit_int8(0x0F); - emit_int8((unsigned char)0xAE); - // extended opcode byte is 7 == rdi - emit_operand(rdi, adr); - } - - void Assembler::clwb(Address adr) { - assert(VM_Version::supports_clwb(), "should do!"); - // adr should be base reg only with no index or offset - assert(adr.index() == noreg, "index should be noreg"); - assert(adr.scale() == Address::no_scale, "scale should be no_scale"); - assert(adr.disp() == 0, "displacement should be 0"); - // instruction prefix is 0x66 - emit_int8(0x66); - prefix(adr); - // opcode family is 0x0f 0xAE - emit_int8(0x0F); - emit_int8((unsigned char)0xAE); - // extended opcode byte is 6 == rsi - emit_operand(rsi, adr); - } - void Assembler::cmovq(Condition cc, Register dst, Register src) { int encode = prefixq_and_encode(dst->encoding(), src->encoding()); emit_int8(0x0F); emit_int8(0x40 | cc); emit_int8((unsigned char)(0xC0 | encode)); --- 8594,8609 ----
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