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src/hotspot/cpu/x86/assembler_x86.cpp

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 772       break;
 773 
 774     case 0x70: // pshufd r, r/a, #8
 775       debug_only(has_disp32 = true); // has both kinds of operands!
 776     case 0x73: // psrldq r, #8
 777       tail_size = 1;
 778       break;
 779 
 780     case 0x12: // movlps
 781     case 0x28: // movaps
 782     case 0x2E: // ucomiss
 783     case 0x2F: // comiss
 784     case 0x54: // andps
 785     case 0x55: // andnps
 786     case 0x56: // orps
 787     case 0x57: // xorps
 788     case 0x58: // addpd
 789     case 0x59: // mulpd
 790     case 0x6E: // movd
 791     case 0x7E: // movd
 792     case 0x6F: // movdq
 793     case 0x7F: // movdq
 794     case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
 795     case 0xFE: // paddd
 796       debug_only(has_disp32 = true);
 797       break;
 798 
 799     case 0xAD: // shrd r, a, %cl
 800     case 0xAF: // imul r, a
 801     case 0xBE: // movsbl r, a (movsxb)
 802     case 0xBF: // movswl r, a (movsxw)
 803     case 0xB6: // movzbl r, a (movzxb)
 804     case 0xB7: // movzwl r, a (movzxw)
 805     case REP16(0x40): // cmovl cc, r, a
 806     case 0xB0: // cmpxchgb
 807     case 0xB1: // cmpxchg
 808     case 0xC1: // xaddl
 809     case 0xC7: // cmpxchg8
 810     case REP16(0x90): // setcc a
 811       debug_only(has_disp32 = true);
 812       // fall out of the switch to decode the address
 813       break;


1363   emit_int8((unsigned char)(0xC0 | encode));
1364 }
1365 
1366 void Assembler::aesenc(XMMRegister dst, Address src) {
1367   assert(VM_Version::supports_aes(), "");
1368   InstructionMark im(this);
1369   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1370   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1371   emit_int8((unsigned char)0xDC);
1372   emit_operand(dst, src);
1373 }
1374 
1375 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1376   assert(VM_Version::supports_aes(), "");
1377   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1378   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1379   emit_int8((unsigned char)0xDC);
1380   emit_int8(0xC0 | encode);
1381 }
1382 
1383 void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1384   assert(VM_Version::supports_vaes(), "requires vaes support/enabling");
1385   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1386   attributes.set_is_evex_instruction();
1387   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1388   emit_int8((unsigned char)0xDC);
1389   emit_int8((unsigned char)(0xC0 | encode));
1390 }
1391 
1392 void Assembler::aesenclast(XMMRegister dst, Address src) {
1393   assert(VM_Version::supports_aes(), "");
1394   InstructionMark im(this);
1395   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1396   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1397   emit_int8((unsigned char)0xDD);
1398   emit_operand(dst, src);
1399 }
1400 
1401 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1402   assert(VM_Version::supports_aes(), "");
1403   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1404   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1405   emit_int8((unsigned char)0xDD);
1406   emit_int8((unsigned char)(0xC0 | encode));
1407 }
1408 
1409 void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1410   assert(VM_Version::supports_vaes(), "requires vaes support/enabling");
1411   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1412   attributes.set_is_evex_instruction();
1413   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1414   emit_int8((unsigned char)0xDD);
1415   emit_int8((unsigned char)(0xC0 | encode));
1416 }
1417 
1418 void Assembler::andl(Address dst, int32_t imm32) {
1419   InstructionMark im(this);
1420   prefix(dst);
1421   emit_int8((unsigned char)0x81);
1422   emit_operand(rsp, dst, 4);
1423   emit_int32(imm32);
1424 }
1425 
1426 void Assembler::andl(Register dst, int32_t imm32) {
1427   prefix(dst);
1428   emit_arith(0x81, 0xE0, dst, imm32);
1429 }
1430 
1431 void Assembler::andl(Register dst, Address src) {
1432   InstructionMark im(this);
1433   prefix(src, dst);
1434   emit_int8(0x23);
1435   emit_operand(dst, src);
1436 }
1437 


2257   emit_int8((unsigned char)0xF0);
2258 }
2259 
2260 void Assembler::lzcntl(Register dst, Register src) {
2261   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2262   emit_int8((unsigned char)0xF3);
2263   int encode = prefix_and_encode(dst->encoding(), src->encoding());
2264   emit_int8(0x0F);
2265   emit_int8((unsigned char)0xBD);
2266   emit_int8((unsigned char)(0xC0 | encode));
2267 }
2268 
2269 // Emit mfence instruction
2270 void Assembler::mfence() {
2271   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2272   emit_int8(0x0F);
2273   emit_int8((unsigned char)0xAE);
2274   emit_int8((unsigned char)0xF0);
2275 }
2276 
2277 // Emit sfence instruction
2278 void Assembler::sfence() {
2279   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2280   emit_int8(0x0F);
2281   emit_int8((unsigned char)0xAE);
2282   emit_int8((unsigned char)0xF8);
2283 }
2284 
2285 void Assembler::mov(Register dst, Register src) {
2286   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2287 }
2288 
2289 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2290   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2291   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2292   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2293   attributes.set_rex_vex_w_reverted();
2294   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2295   emit_int8(0x28);
2296   emit_int8((unsigned char)(0xC0 | encode));
2297 }
2298 
2299 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2300   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2301   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2302   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2303   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2304   emit_int8(0x28);


4285   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4286   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4287   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4288   emit_int8(0x70);
4289   emit_int8((unsigned char)(0xC0 | encode));
4290   emit_int8(mode & 0xFF);
4291 }
4292 
4293 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4294   assert(isByte(mode), "invalid value");
4295   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4296   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4297   InstructionMark im(this);
4298   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4299   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4300   simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4301   emit_int8(0x70);
4302   emit_operand(dst, src);
4303   emit_int8(mode & 0xFF);
4304 }
4305 
4306 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4307   assert(VM_Version::supports_evex(), "requires EVEX support");
4308   assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4309   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4310   attributes.set_is_evex_instruction();
4311   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4312   emit_int8(0x43);
4313   emit_int8((unsigned char)(0xC0 | encode));
4314   emit_int8(imm8 & 0xFF);
4315 }
4316 
4317 void Assembler::psrldq(XMMRegister dst, int shift) {
4318   // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4319   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4320   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4321   int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4322   emit_int8(0x73);
4323   emit_int8((unsigned char)(0xC0 | encode));
4324   emit_int8(shift);
4325 }


8608   int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8609   emit_int8((unsigned char)0xF3);
8610   emit_int8((unsigned char)(0xC0 | encode));
8611 }
8612 
8613 void Assembler::blsrq(Register dst, Address src) {
8614   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8615   InstructionMark im(this);
8616   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8617   vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8618   emit_int8((unsigned char)0xF3);
8619   emit_operand(rcx, src);
8620 }
8621 
8622 void Assembler::cdqq() {
8623   prefix(REX_W);
8624   emit_int8((unsigned char)0x99);
8625 }
8626 
8627 void Assembler::clflush(Address adr) {
8628   assert(VM_Version::supports_clflush(), "should do");
8629   prefix(adr);
8630   emit_int8(0x0F);
8631   emit_int8((unsigned char)0xAE);
8632   emit_operand(rdi, adr);
8633 }
8634 
8635 void Assembler::clflushopt(Address adr) {
8636   assert(VM_Version::supports_clflushopt(), "should do!");
8637   // adr should be base reg only with no index or offset
8638   assert(adr.index() == noreg, "index should be noreg");
8639   assert(adr.scale() == Address::no_scale, "scale should be no_scale");
8640   assert(adr.disp() == 0, "displacement should be 0");
8641   // instruction prefix is 0x66
8642   emit_int8(0x66);
8643   prefix(adr);
8644   // opcode family is 0x0f 0xAE
8645   emit_int8(0x0F);
8646   emit_int8((unsigned char)0xAE);
8647   // extended opcode byte is 7 == rdi
8648   emit_operand(rdi, adr);
8649 }
8650 
8651 void Assembler::clwb(Address adr) {
8652   assert(VM_Version::supports_clwb(), "should do!");
8653   // adr should be base reg only with no index or offset
8654   assert(adr.index() == noreg, "index should be noreg");
8655   assert(adr.scale() == Address::no_scale, "scale should be no_scale");
8656   assert(adr.disp() == 0, "displacement should be 0");
8657   // instruction prefix is 0x66
8658   emit_int8(0x66);
8659   prefix(adr);
8660   // opcode family is 0x0f 0xAE
8661   emit_int8(0x0F);
8662   emit_int8((unsigned char)0xAE);
8663   // extended opcode byte is 6 == rsi
8664   emit_operand(rsi, adr);
8665 }
8666 
8667 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8668   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8669   emit_int8(0x0F);
8670   emit_int8(0x40 | cc);
8671   emit_int8((unsigned char)(0xC0 | encode));
8672 }
8673 
8674 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8675   InstructionMark im(this);
8676   prefixq(src, dst);
8677   emit_int8(0x0F);
8678   emit_int8(0x40 | cc);
8679   emit_operand(dst, src);
8680 }
8681 
8682 void Assembler::cmpq(Address dst, int32_t imm32) {
8683   InstructionMark im(this);
8684   prefixq(dst);




 772       break;
 773 
 774     case 0x70: // pshufd r, r/a, #8
 775       debug_only(has_disp32 = true); // has both kinds of operands!
 776     case 0x73: // psrldq r, #8
 777       tail_size = 1;
 778       break;
 779 
 780     case 0x12: // movlps
 781     case 0x28: // movaps
 782     case 0x2E: // ucomiss
 783     case 0x2F: // comiss
 784     case 0x54: // andps
 785     case 0x55: // andnps
 786     case 0x56: // orps
 787     case 0x57: // xorps
 788     case 0x58: // addpd
 789     case 0x59: // mulpd
 790     case 0x6E: // movd
 791     case 0x7E: // movd


 792     case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
 793     case 0xFE: // paddd
 794       debug_only(has_disp32 = true);
 795       break;
 796 
 797     case 0xAD: // shrd r, a, %cl
 798     case 0xAF: // imul r, a
 799     case 0xBE: // movsbl r, a (movsxb)
 800     case 0xBF: // movswl r, a (movsxw)
 801     case 0xB6: // movzbl r, a (movzxb)
 802     case 0xB7: // movzwl r, a (movzxw)
 803     case REP16(0x40): // cmovl cc, r, a
 804     case 0xB0: // cmpxchgb
 805     case 0xB1: // cmpxchg
 806     case 0xC1: // xaddl
 807     case 0xC7: // cmpxchg8
 808     case REP16(0x90): // setcc a
 809       debug_only(has_disp32 = true);
 810       // fall out of the switch to decode the address
 811       break;


1361   emit_int8((unsigned char)(0xC0 | encode));
1362 }
1363 
1364 void Assembler::aesenc(XMMRegister dst, Address src) {
1365   assert(VM_Version::supports_aes(), "");
1366   InstructionMark im(this);
1367   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1368   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1369   emit_int8((unsigned char)0xDC);
1370   emit_operand(dst, src);
1371 }
1372 
1373 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1374   assert(VM_Version::supports_aes(), "");
1375   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1376   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1377   emit_int8((unsigned char)0xDC);
1378   emit_int8(0xC0 | encode);
1379 }
1380 









1381 void Assembler::aesenclast(XMMRegister dst, Address src) {
1382   assert(VM_Version::supports_aes(), "");
1383   InstructionMark im(this);
1384   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1385   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1386   emit_int8((unsigned char)0xDD);
1387   emit_operand(dst, src);
1388 }
1389 
1390 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1391   assert(VM_Version::supports_aes(), "");
1392   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1393   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1394   emit_int8((unsigned char)0xDD);
1395   emit_int8((unsigned char)(0xC0 | encode));
1396 }
1397 









1398 void Assembler::andl(Address dst, int32_t imm32) {
1399   InstructionMark im(this);
1400   prefix(dst);
1401   emit_int8((unsigned char)0x81);
1402   emit_operand(rsp, dst, 4);
1403   emit_int32(imm32);
1404 }
1405 
1406 void Assembler::andl(Register dst, int32_t imm32) {
1407   prefix(dst);
1408   emit_arith(0x81, 0xE0, dst, imm32);
1409 }
1410 
1411 void Assembler::andl(Register dst, Address src) {
1412   InstructionMark im(this);
1413   prefix(src, dst);
1414   emit_int8(0x23);
1415   emit_operand(dst, src);
1416 }
1417 


2237   emit_int8((unsigned char)0xF0);
2238 }
2239 
2240 void Assembler::lzcntl(Register dst, Register src) {
2241   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2242   emit_int8((unsigned char)0xF3);
2243   int encode = prefix_and_encode(dst->encoding(), src->encoding());
2244   emit_int8(0x0F);
2245   emit_int8((unsigned char)0xBD);
2246   emit_int8((unsigned char)(0xC0 | encode));
2247 }
2248 
2249 // Emit mfence instruction
2250 void Assembler::mfence() {
2251   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2252   emit_int8(0x0F);
2253   emit_int8((unsigned char)0xAE);
2254   emit_int8((unsigned char)0xF0);
2255 }
2256 








2257 void Assembler::mov(Register dst, Register src) {
2258   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2259 }
2260 
2261 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2262   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2263   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2264   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2265   attributes.set_rex_vex_w_reverted();
2266   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2267   emit_int8(0x28);
2268   emit_int8((unsigned char)(0xC0 | encode));
2269 }
2270 
2271 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2272   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2273   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2274   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2275   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2276   emit_int8(0x28);


4257   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4258   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4259   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4260   emit_int8(0x70);
4261   emit_int8((unsigned char)(0xC0 | encode));
4262   emit_int8(mode & 0xFF);
4263 }
4264 
4265 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4266   assert(isByte(mode), "invalid value");
4267   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4268   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4269   InstructionMark im(this);
4270   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4271   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4272   simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4273   emit_int8(0x70);
4274   emit_operand(dst, src);
4275   emit_int8(mode & 0xFF);
4276 }

4277 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4278   assert(VM_Version::supports_evex(), "requires EVEX support");
4279   assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4280   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4281   attributes.set_is_evex_instruction();
4282   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4283   emit_int8(0x43);
4284   emit_int8((unsigned char)(0xC0 | encode));
4285   emit_int8(imm8 & 0xFF);
4286 }
4287 
4288 void Assembler::psrldq(XMMRegister dst, int shift) {
4289   // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4290   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4291   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4292   int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4293   emit_int8(0x73);
4294   emit_int8((unsigned char)(0xC0 | encode));
4295   emit_int8(shift);
4296 }


8579   int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8580   emit_int8((unsigned char)0xF3);
8581   emit_int8((unsigned char)(0xC0 | encode));
8582 }
8583 
8584 void Assembler::blsrq(Register dst, Address src) {
8585   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8586   InstructionMark im(this);
8587   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8588   vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8589   emit_int8((unsigned char)0xF3);
8590   emit_operand(rcx, src);
8591 }
8592 
8593 void Assembler::cdqq() {
8594   prefix(REX_W);
8595   emit_int8((unsigned char)0x99);
8596 }
8597 
8598 void Assembler::clflush(Address adr) {

8599   prefix(adr);
8600   emit_int8(0x0F);
8601   emit_int8((unsigned char)0xAE);
8602   emit_operand(rdi, adr);
































8603 }
8604 
8605 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8606   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8607   emit_int8(0x0F);
8608   emit_int8(0x40 | cc);
8609   emit_int8((unsigned char)(0xC0 | encode));
8610 }
8611 
8612 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8613   InstructionMark im(this);
8614   prefixq(src, dst);
8615   emit_int8(0x0F);
8616   emit_int8(0x40 | cc);
8617   emit_operand(dst, src);
8618 }
8619 
8620 void Assembler::cmpq(Address dst, int32_t imm32) {
8621   InstructionMark im(this);
8622   prefixq(dst);


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