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src/hotspot/cpu/x86/assembler_x86.hpp

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 951   void addr_nop_7();
 952   void addr_nop_8();
 953 
 954   // Add Scalar Double-Precision Floating-Point Values
 955   void addsd(XMMRegister dst, Address src);
 956   void addsd(XMMRegister dst, XMMRegister src);
 957 
 958   // Add Scalar Single-Precision Floating-Point Values
 959   void addss(XMMRegister dst, Address src);
 960   void addss(XMMRegister dst, XMMRegister src);
 961 
 962   // AES instructions
 963   void aesdec(XMMRegister dst, Address src);
 964   void aesdec(XMMRegister dst, XMMRegister src);
 965   void aesdeclast(XMMRegister dst, Address src);
 966   void aesdeclast(XMMRegister dst, XMMRegister src);
 967   void aesenc(XMMRegister dst, Address src);
 968   void aesenc(XMMRegister dst, XMMRegister src);
 969   void aesenclast(XMMRegister dst, Address src);
 970   void aesenclast(XMMRegister dst, XMMRegister src);
 971   // Vector AES instructions
 972   void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 973   void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 974   void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 975   void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 976 
 977   void andl(Address  dst, int32_t imm32);
 978   void andl(Register dst, int32_t imm32);
 979   void andl(Register dst, Address src);
 980   void andl(Register dst, Register src);
 981 
 982   void andq(Address  dst, int32_t imm32);
 983   void andq(Register dst, int32_t imm32);
 984   void andq(Register dst, Address src);
 985   void andq(Register dst, Register src);
 986 
 987   // BMI instructions
 988   void andnl(Register dst, Register src1, Register src2);
 989   void andnl(Register dst, Register src1, Address src2);
 990   void andnq(Register dst, Register src1, Register src2);
 991   void andnq(Register dst, Register src1, Address src2);
 992 
 993   void blsil(Register dst, Register src);


1011 #ifdef _LP64
1012   void bsfq(Register dst, Register src);
1013   void bsrq(Register dst, Register src);
1014 #endif
1015 
1016   void bswapl(Register reg);
1017 
1018   void bswapq(Register reg);
1019 
1020   void call(Label& L, relocInfo::relocType rtype);
1021   void call(Register reg);  // push pc; pc <- reg
1022   void call(Address adr);   // push pc; pc <- adr
1023 
1024   void cdql();
1025 
1026   void cdqq();
1027 
1028   void cld();
1029 
1030   void clflush(Address adr);
1031   void clflushopt(Address adr);
1032   void clwb(Address adr);
1033 
1034   void cmovl(Condition cc, Register dst, Register src);
1035   void cmovl(Condition cc, Register dst, Address src);
1036 
1037   void cmovq(Condition cc, Register dst, Register src);
1038   void cmovq(Condition cc, Register dst, Address src);
1039 
1040 
1041   void cmpb(Address dst, int imm8);
1042 
1043   void cmpl(Address dst, int32_t imm32);
1044 
1045   void cmpl(Register dst, int32_t imm32);
1046   void cmpl(Register dst, Register src);
1047   void cmpl(Register dst, Address src);
1048 
1049   void cmpq(Address dst, int32_t imm32);
1050   void cmpq(Address dst, Register src);
1051 
1052   void cmpq(Register dst, int32_t imm32);


1389       // cache line, as this will also avoid possible second-order effects
1390       // with locked ops against the cache line. Our choice of offset
1391       // is bounded by x86 operand encoding, which should stay within
1392       // [-128; +127] to have the 8-byte displacement encoding.
1393       //
1394       // Any change to this code may need to revisit other places in
1395       // the code where this idiom is used, in particular the
1396       // orderAccess code.
1397 
1398       int offset = -VM_Version::L1_line_size();
1399       if (offset < -128) {
1400         offset = -128;
1401       }
1402 
1403       lock();
1404       addl(Address(rsp, offset), 0);// Assert the lock# signal here
1405     }
1406   }
1407 
1408   void mfence();
1409   void sfence();
1410 
1411   // Moves
1412 
1413   void mov64(Register dst, int64_t imm64);
1414 
1415   void movb(Address dst, Register src);
1416   void movb(Address dst, int imm8);
1417   void movb(Register dst, Address src);
1418 
1419   void movddup(XMMRegister dst, XMMRegister src);
1420 
1421   void kmovbl(KRegister dst, Register src);
1422   void kmovbl(Register dst, KRegister src);
1423   void kmovwl(KRegister dst, Register src);
1424   void kmovwl(KRegister dst, Address src);
1425   void kmovwl(Register dst, KRegister src);
1426   void kmovdl(KRegister dst, Register src);
1427   void kmovdl(Register dst, KRegister src);
1428   void kmovql(KRegister dst, KRegister src);
1429   void kmovql(Address dst, KRegister src);




 951   void addr_nop_7();
 952   void addr_nop_8();
 953 
 954   // Add Scalar Double-Precision Floating-Point Values
 955   void addsd(XMMRegister dst, Address src);
 956   void addsd(XMMRegister dst, XMMRegister src);
 957 
 958   // Add Scalar Single-Precision Floating-Point Values
 959   void addss(XMMRegister dst, Address src);
 960   void addss(XMMRegister dst, XMMRegister src);
 961 
 962   // AES instructions
 963   void aesdec(XMMRegister dst, Address src);
 964   void aesdec(XMMRegister dst, XMMRegister src);
 965   void aesdeclast(XMMRegister dst, Address src);
 966   void aesdeclast(XMMRegister dst, XMMRegister src);
 967   void aesenc(XMMRegister dst, Address src);
 968   void aesenc(XMMRegister dst, XMMRegister src);
 969   void aesenclast(XMMRegister dst, Address src);
 970   void aesenclast(XMMRegister dst, XMMRegister src);



 971   void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 972   void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
 973 
 974   void andl(Address  dst, int32_t imm32);
 975   void andl(Register dst, int32_t imm32);
 976   void andl(Register dst, Address src);
 977   void andl(Register dst, Register src);
 978 
 979   void andq(Address  dst, int32_t imm32);
 980   void andq(Register dst, int32_t imm32);
 981   void andq(Register dst, Address src);
 982   void andq(Register dst, Register src);
 983 
 984   // BMI instructions
 985   void andnl(Register dst, Register src1, Register src2);
 986   void andnl(Register dst, Register src1, Address src2);
 987   void andnq(Register dst, Register src1, Register src2);
 988   void andnq(Register dst, Register src1, Address src2);
 989 
 990   void blsil(Register dst, Register src);


1008 #ifdef _LP64
1009   void bsfq(Register dst, Register src);
1010   void bsrq(Register dst, Register src);
1011 #endif
1012 
1013   void bswapl(Register reg);
1014 
1015   void bswapq(Register reg);
1016 
1017   void call(Label& L, relocInfo::relocType rtype);
1018   void call(Register reg);  // push pc; pc <- reg
1019   void call(Address adr);   // push pc; pc <- adr
1020 
1021   void cdql();
1022 
1023   void cdqq();
1024 
1025   void cld();
1026 
1027   void clflush(Address adr);


1028 
1029   void cmovl(Condition cc, Register dst, Register src);
1030   void cmovl(Condition cc, Register dst, Address src);
1031 
1032   void cmovq(Condition cc, Register dst, Register src);
1033   void cmovq(Condition cc, Register dst, Address src);
1034 
1035 
1036   void cmpb(Address dst, int imm8);
1037 
1038   void cmpl(Address dst, int32_t imm32);
1039 
1040   void cmpl(Register dst, int32_t imm32);
1041   void cmpl(Register dst, Register src);
1042   void cmpl(Register dst, Address src);
1043 
1044   void cmpq(Address dst, int32_t imm32);
1045   void cmpq(Address dst, Register src);
1046 
1047   void cmpq(Register dst, int32_t imm32);


1384       // cache line, as this will also avoid possible second-order effects
1385       // with locked ops against the cache line. Our choice of offset
1386       // is bounded by x86 operand encoding, which should stay within
1387       // [-128; +127] to have the 8-byte displacement encoding.
1388       //
1389       // Any change to this code may need to revisit other places in
1390       // the code where this idiom is used, in particular the
1391       // orderAccess code.
1392 
1393       int offset = -VM_Version::L1_line_size();
1394       if (offset < -128) {
1395         offset = -128;
1396       }
1397 
1398       lock();
1399       addl(Address(rsp, offset), 0);// Assert the lock# signal here
1400     }
1401   }
1402 
1403   void mfence();

1404 
1405   // Moves
1406 
1407   void mov64(Register dst, int64_t imm64);
1408 
1409   void movb(Address dst, Register src);
1410   void movb(Address dst, int imm8);
1411   void movb(Register dst, Address src);
1412 
1413   void movddup(XMMRegister dst, XMMRegister src);
1414 
1415   void kmovbl(KRegister dst, Register src);
1416   void kmovbl(Register dst, KRegister src);
1417   void kmovwl(KRegister dst, Register src);
1418   void kmovwl(KRegister dst, Address src);
1419   void kmovwl(Register dst, KRegister src);
1420   void kmovdl(KRegister dst, Register src);
1421   void kmovdl(Register dst, KRegister src);
1422   void kmovql(KRegister dst, KRegister src);
1423   void kmovql(Address dst, KRegister src);


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