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src/hotspot/cpu/x86/vm_version_x86.cpp

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  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "logging/log.hpp"
  30 #include "logging/logStream.hpp"
  31 #include "memory/resourceArea.hpp"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "utilities/virtualizationSupport.hpp"
  36 #include "vm_version_x86.hpp"
  37 
  38 #include OS_HEADER_INLINE(os)
  39 
  40 int VM_Version::_cpu;
  41 int VM_Version::_model;
  42 int VM_Version::_stepping;
  43 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
  44 
  45 // Address of instruction which causes SEGV
  46 address VM_Version::_cpuinfo_segv_addr = 0;
  47 // Address of instruction after the one which causes SEGV
  48 address VM_Version::_cpuinfo_cont_addr = 0;
  49 
  50 static BufferBlob* stub_blob;
  51 static const int stub_size = 1100;
  52 
  53 extern "C" {
  54   typedef void (*get_cpu_info_stub_t)(void*);
  55 }
  56 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
  57 
  58 


 592     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
 593   }
 594   // in 64 bit the use of SSE2 is the minimum
 595   if (UseSSE < 2) UseSSE = 2;
 596 #endif
 597 
 598 #ifdef AMD64
 599   // flush_icache_stub have to be generated first.
 600   // That is why Icache line size is hard coded in ICache class,
 601   // see icache_x86.hpp. It is also the reason why we can't use
 602   // clflush instruction in 32-bit VM since it could be running
 603   // on CPU which does not support it.
 604   //
 605   // The only thing we can do is to verify that flushed
 606   // ICache::line_size has correct value.
 607   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
 608   // clflush_size is size in quadwords (8 bytes).
 609   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
 610 #endif
 611 
 612 #ifdef _LP64
 613   // assigning this field effectively enables Unsafe.writebackMemory()
 614   // by initing UnsafeConstant.DATA_CACHE_LINE_FLUSH_SIZE to non-zero
 615   // that is only implemented on x86_64 and only if the OS plays ball
 616   if (os::supports_map_sync()) {
 617     // publish data cache line flush size to generic field, otherwise
 618     // let if default to zero thereby disabling writeback
 619     _data_cache_line_flush_size = _cpuid_info.std_cpuid1_ebx.bits.clflush_size * 8;
 620   }
 621 #endif
 622   // If the OS doesn't support SSE, we can't use this feature even if the HW does
 623   if (!os::supports_sse())
 624     _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
 625 
 626   if (UseSSE < 4) {
 627     _features &= ~CPU_SSE4_1;
 628     _features &= ~CPU_SSE4_2;
 629   }
 630 
 631   if (UseSSE < 3) {
 632     _features &= ~CPU_SSE3;
 633     _features &= ~CPU_SSSE3;
 634     _features &= ~CPU_SSE4A;
 635   }
 636 
 637   if (UseSSE < 2)
 638     _features &= ~CPU_SSE2;
 639 
 640   if (UseSSE < 1)
 641     _features &= ~CPU_SSE;




  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "logging/log.hpp"
  30 #include "logging/logStream.hpp"
  31 #include "memory/resourceArea.hpp"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "utilities/virtualizationSupport.hpp"
  36 #include "vm_version_x86.hpp"
  37 

  38 
  39 int VM_Version::_cpu;
  40 int VM_Version::_model;
  41 int VM_Version::_stepping;
  42 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
  43 
  44 // Address of instruction which causes SEGV
  45 address VM_Version::_cpuinfo_segv_addr = 0;
  46 // Address of instruction after the one which causes SEGV
  47 address VM_Version::_cpuinfo_cont_addr = 0;
  48 
  49 static BufferBlob* stub_blob;
  50 static const int stub_size = 1100;
  51 
  52 extern "C" {
  53   typedef void (*get_cpu_info_stub_t)(void*);
  54 }
  55 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
  56 
  57 


 591     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
 592   }
 593   // in 64 bit the use of SSE2 is the minimum
 594   if (UseSSE < 2) UseSSE = 2;
 595 #endif
 596 
 597 #ifdef AMD64
 598   // flush_icache_stub have to be generated first.
 599   // That is why Icache line size is hard coded in ICache class,
 600   // see icache_x86.hpp. It is also the reason why we can't use
 601   // clflush instruction in 32-bit VM since it could be running
 602   // on CPU which does not support it.
 603   //
 604   // The only thing we can do is to verify that flushed
 605   // ICache::line_size has correct value.
 606   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
 607   // clflush_size is size in quadwords (8 bytes).
 608   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
 609 #endif
 610 










 611   // If the OS doesn't support SSE, we can't use this feature even if the HW does
 612   if (!os::supports_sse())
 613     _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
 614 
 615   if (UseSSE < 4) {
 616     _features &= ~CPU_SSE4_1;
 617     _features &= ~CPU_SSE4_2;
 618   }
 619 
 620   if (UseSSE < 3) {
 621     _features &= ~CPU_SSE3;
 622     _features &= ~CPU_SSSE3;
 623     _features &= ~CPU_SSE4A;
 624   }
 625 
 626   if (UseSSE < 2)
 627     _features &= ~CPU_SSE2;
 628 
 629   if (UseSSE < 1)
 630     _features &= ~CPU_SSE;


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