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src/hotspot/cpu/x86/x86.ad

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*** 8356,8366 **** instruct vshift4B(vecS dst, vecS src, vecS shift, vecS tmp, rRegI scratch) %{ predicate(UseSSE > 3 && n->as_Vector()->length() == 4); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); format %{"vextendbw $tmp,$src\n\t" "vshiftw $tmp,$shift\n\t" "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" "pand $dst,$tmp\n\t" "packuswb $dst,$dst\n\t ! packed4B shift" %} --- 8356,8366 ---- instruct vshift4B(vecS dst, vecS src, vecS shift, vecS tmp, rRegI scratch) %{ predicate(UseSSE > 3 && n->as_Vector()->length() == 4); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, TEMP tmp, TEMP scratch); format %{"vextendbw $tmp,$src\n\t" "vshiftw $tmp,$shift\n\t" "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" "pand $dst,$tmp\n\t" "packuswb $dst,$dst\n\t ! packed4B shift" %}
*** 8379,8389 **** instruct vshift8B(vecD dst, vecD src, vecS shift, vecD tmp, rRegI scratch) %{ predicate(UseSSE > 3 && n->as_Vector()->length() == 8); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); format %{"vextendbw $tmp,$src\n\t" "vshiftw $tmp,$shift\n\t" "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" "pand $dst,$tmp\n\t" "packuswb $dst,$dst\n\t ! packed8B shift" %} --- 8379,8389 ---- instruct vshift8B(vecD dst, vecD src, vecS shift, vecD tmp, rRegI scratch) %{ predicate(UseSSE > 3 && n->as_Vector()->length() == 8); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, TEMP tmp, TEMP scratch); format %{"vextendbw $tmp,$src\n\t" "vshiftw $tmp,$shift\n\t" "movdqu $dst,[0x00ff00ff0x00ff00ff]\n\t" "pand $dst,$tmp\n\t" "packuswb $dst,$dst\n\t ! packed8B shift" %}
*** 8402,8412 **** instruct vshift16B(vecX dst, vecX src, vecS shift, vecX tmp1, vecX tmp2, rRegI scratch) %{ predicate(UseSSE > 3 && UseAVX <= 1 && n->as_Vector()->length() == 16); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, USE src, USE shift, TEMP tmp1, TEMP tmp2, TEMP scratch); format %{"vextendbw $tmp1,$src\n\t" "vshiftw $tmp1,$shift\n\t" "pshufd $tmp2,$src\n\t" "vextendbw $tmp2,$tmp2\n\t" "vshiftw $tmp2,$shift\n\t" --- 8402,8412 ---- instruct vshift16B(vecX dst, vecX src, vecS shift, vecX tmp1, vecX tmp2, rRegI scratch) %{ predicate(UseSSE > 3 && UseAVX <= 1 && n->as_Vector()->length() == 16); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, TEMP tmp1, TEMP tmp2, TEMP scratch); format %{"vextendbw $tmp1,$src\n\t" "vshiftw $tmp1,$shift\n\t" "pshufd $tmp2,$src\n\t" "vextendbw $tmp2,$tmp2\n\t" "vshiftw $tmp2,$shift\n\t"
*** 8433,8443 **** instruct vshift16B_avx(vecX dst, vecX src, vecS shift, vecX tmp, rRegI scratch) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 16); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); format %{"vextendbw $tmp,$src\n\t" "vshiftw $tmp,$tmp,$shift\n\t" "vpand $tmp,$tmp,[0x00ff00ff0x00ff00ff]\n\t" "vextracti128_high $dst,$tmp\n\t" "vpackuswb $dst,$tmp,$dst\n\t! packed16B shift" %} --- 8433,8443 ---- instruct vshift16B_avx(vecX dst, vecX src, vecS shift, vecX tmp, rRegI scratch) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 16); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, TEMP tmp, TEMP scratch); format %{"vextendbw $tmp,$src\n\t" "vshiftw $tmp,$tmp,$shift\n\t" "vpand $tmp,$tmp,[0x00ff00ff0x00ff00ff]\n\t" "vextracti128_high $dst,$tmp\n\t" "vpackuswb $dst,$tmp,$dst\n\t! packed16B shift" %}
*** 8457,8467 **** instruct vshift32B_avx(vecY dst, vecY src, vecS shift, vecY tmp, rRegI scratch) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 32); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, USE src, USE shift, TEMP tmp, TEMP scratch); format %{"vextracti128_high $tmp,$src\n\t" "vextendbw $tmp,$tmp\n\t" "vextendbw $dst,$src\n\t" "vshiftw $tmp,$tmp,$shift\n\t" "vshiftw $dst,$dst,$shift\n\t" --- 8457,8467 ---- instruct vshift32B_avx(vecY dst, vecY src, vecS shift, vecY tmp, rRegI scratch) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 32); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, TEMP tmp, TEMP scratch); format %{"vextracti128_high $tmp,$src\n\t" "vextendbw $tmp,$tmp\n\t" "vextendbw $dst,$src\n\t" "vshiftw $tmp,$tmp,$shift\n\t" "vshiftw $dst,$dst,$shift\n\t"
*** 8489,8499 **** instruct vshift64B_avx(vecZ dst, vecZ src, vecS shift, vecZ tmp1, vecZ tmp2, rRegI scratch) %{ predicate(UseAVX > 2 && n->as_Vector()->length() == 64); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, USE src, USE shift, TEMP tmp1, TEMP tmp2, TEMP scratch); format %{"vextracti64x4 $tmp1,$src\n\t" "vextendbw $tmp1,$tmp1\n\t" "vextendbw $tmp2,$src\n\t" "vshiftw $tmp1,$tmp1,$shift\n\t" "vshiftw $tmp2,$tmp2,$shift\n\t" --- 8489,8499 ---- instruct vshift64B_avx(vecZ dst, vecZ src, vecS shift, vecZ tmp1, vecZ tmp2, rRegI scratch) %{ predicate(UseAVX > 2 && n->as_Vector()->length() == 64); match(Set dst (LShiftVB src shift)); match(Set dst (RShiftVB src shift)); match(Set dst (URShiftVB src shift)); ! effect(TEMP dst, TEMP tmp1, TEMP tmp2, TEMP scratch); format %{"vextracti64x4 $tmp1,$src\n\t" "vextendbw $tmp1,$tmp1\n\t" "vextendbw $tmp2,$src\n\t" "vshiftw $tmp1,$tmp1,$shift\n\t" "vshiftw $tmp2,$tmp2,$shift\n\t"
*** 8532,8542 **** instruct vshist2S(vecS dst, vecS src, vecS shift) %{ predicate(n->as_Vector()->length() == 2); match(Set dst (LShiftVS src shift)); match(Set dst (RShiftVS src shift)); match(Set dst (URShiftVS src shift)); - effect(TEMP dst, USE src, USE shift); format %{ "vshiftw $dst,$src,$shift\t! shift packed2S" %} ins_encode %{ int opcode = this->as_Mach()->ideal_Opcode(); if (UseAVX == 0) { if ($dst$$XMMRegister != $src$$XMMRegister) --- 8532,8541 ----
*** 8553,8563 **** instruct vshift4S(vecD dst, vecD src, vecS shift) %{ predicate(n->as_Vector()->length() == 4); match(Set dst (LShiftVS src shift)); match(Set dst (RShiftVS src shift)); match(Set dst (URShiftVS src shift)); - effect(TEMP dst, USE src, USE shift); format %{ "vshiftw $dst,$src,$shift\t! shift packed4S" %} ins_encode %{ int opcode = this->as_Mach()->ideal_Opcode(); if (UseAVX == 0) { if ($dst$$XMMRegister != $src$$XMMRegister) --- 8552,8561 ----
*** 8575,8585 **** instruct vshift8S(vecX dst, vecX src, vecS shift) %{ predicate(n->as_Vector()->length() == 8); match(Set dst (LShiftVS src shift)); match(Set dst (RShiftVS src shift)); match(Set dst (URShiftVS src shift)); - effect(TEMP dst, USE src, USE shift); format %{ "vshiftw $dst,$src,$shift\t! shift packed8S" %} ins_encode %{ int opcode = this->as_Mach()->ideal_Opcode(); if (UseAVX == 0) { if ($dst$$XMMRegister != $src$$XMMRegister) --- 8573,8582 ----
*** 8596,8606 **** instruct vshift16S(vecY dst, vecY src, vecS shift) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 16); match(Set dst (LShiftVS src shift)); match(Set dst (RShiftVS src shift)); match(Set dst (URShiftVS src shift)); - effect(DEF dst, USE src, USE shift); format %{ "vshiftw $dst,$src,$shift\t! shift packed16S" %} ins_encode %{ int vector_len = 1; int opcode = this->as_Mach()->ideal_Opcode(); __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); --- 8593,8602 ----
*** 8611,8621 **** instruct vshift32S(vecZ dst, vecZ src, vecS shift) %{ predicate(UseAVX > 2 && VM_Version::supports_avx512bw() && n->as_Vector()->length() == 32); match(Set dst (LShiftVS src shift)); match(Set dst (RShiftVS src shift)); match(Set dst (URShiftVS src shift)); - effect(DEF dst, USE src, USE shift); format %{ "vshiftw $dst,$src,$shift\t! shift packed32S" %} ins_encode %{ int vector_len = 2; int opcode = this->as_Mach()->ideal_Opcode(); __ vshiftw(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); --- 8607,8616 ----
*** 8627,8637 **** instruct vshift2I(vecD dst, vecD src, vecS shift) %{ predicate(n->as_Vector()->length() == 2); match(Set dst (LShiftVI src shift)); match(Set dst (RShiftVI src shift)); match(Set dst (URShiftVI src shift)); - effect(TEMP dst, USE src, USE shift); format %{ "vshiftd $dst,$src,$shift\t! shift packed2I" %} ins_encode %{ int opcode = this->as_Mach()->ideal_Opcode(); if (UseAVX == 0) { if ($dst$$XMMRegister != $src$$XMMRegister) --- 8622,8631 ----
*** 8648,8658 **** instruct vshift4I(vecX dst, vecX src, vecS shift) %{ predicate(n->as_Vector()->length() == 4); match(Set dst (LShiftVI src shift)); match(Set dst (RShiftVI src shift)); match(Set dst (URShiftVI src shift)); - effect(TEMP dst, USE src, USE shift); format %{ "vshiftd $dst,$src,$shift\t! shift packed4I" %} ins_encode %{ int opcode = this->as_Mach()->ideal_Opcode(); if (UseAVX == 0) { if ($dst$$XMMRegister != $src$$XMMRegister) --- 8642,8651 ----
*** 8669,8679 **** instruct vshift8I(vecY dst, vecY src, vecS shift) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 8); match(Set dst (LShiftVI src shift)); match(Set dst (RShiftVI src shift)); match(Set dst (URShiftVI src shift)); - effect(DEF dst, USE src, USE shift); format %{ "vshiftd $dst,$src,$shift\t! shift packed8I" %} ins_encode %{ int vector_len = 1; int opcode = this->as_Mach()->ideal_Opcode(); __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); --- 8662,8671 ----
*** 8684,8694 **** instruct vshift16I(vecZ dst, vecZ src, vecS shift) %{ predicate(UseAVX > 2 && n->as_Vector()->length() == 16); match(Set dst (LShiftVI src shift)); match(Set dst (RShiftVI src shift)); match(Set dst (URShiftVI src shift)); - effect(DEF dst, USE src, USE shift); format %{ "vshiftd $dst,$src,$shift\t! shift packed16I" %} ins_encode %{ int vector_len = 2; int opcode = this->as_Mach()->ideal_Opcode(); __ vshiftd(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); --- 8676,8685 ----
*** 8699,8709 **** // Longs vector shift instruct vshift2L(vecX dst, vecX src, vecS shift) %{ predicate(n->as_Vector()->length() == 2); match(Set dst (LShiftVL src shift)); match(Set dst (URShiftVL src shift)); - effect(TEMP dst, USE src, USE shift); format %{ "vshiftq $dst,$src,$shift\t! shift packed2L" %} ins_encode %{ int opcode = this->as_Mach()->ideal_Opcode(); if (UseAVX == 0) { if ($dst$$XMMRegister != $src$$XMMRegister) --- 8690,8699 ----
*** 8719,8729 **** instruct vshift4L(vecY dst, vecY src, vecS shift) %{ predicate(UseAVX > 1 && n->as_Vector()->length() == 4); match(Set dst (LShiftVL src shift)); match(Set dst (URShiftVL src shift)); - effect(DEF dst, USE src, USE shift); format %{ "vshiftq $dst,$src,$shift\t! left shift packed4L" %} ins_encode %{ int vector_len = 1; int opcode = this->as_Mach()->ideal_Opcode(); __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); --- 8709,8718 ----
*** 8734,8744 **** instruct vshift8L(vecZ dst, vecZ src, vecS shift) %{ predicate(UseAVX > 2 && n->as_Vector()->length() == 8); match(Set dst (LShiftVL src shift)); match(Set dst (RShiftVL src shift)); match(Set dst (URShiftVL src shift)); - effect(DEF dst, USE src, USE shift); format %{ "vshiftq $dst,$src,$shift\t! shift packed8L" %} ins_encode %{ int vector_len = 2; int opcode = this->as_Mach()->ideal_Opcode(); __ vshiftq(opcode, $dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len); --- 8723,8732 ----
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