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src/hotspot/share/opto/vectornode.cpp

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 281   case Op_ReplicateS:
 282   case Op_ReplicateI:
 283   case Op_ReplicateL:
 284   case Op_ReplicateF:
 285   case Op_ReplicateD:
 286     return true;
 287   default:
 288     return false;
 289   }
 290 }
 291 
 292 // [Start, end) half-open range defining which operands are vectors
 293 void VectorNode::vector_operands(Node* n, uint* start, uint* end) {
 294   switch (n->Opcode()) {
 295   case Op_LoadB:   case Op_LoadUB:
 296   case Op_LoadS:   case Op_LoadUS:
 297   case Op_LoadI:   case Op_LoadL:
 298   case Op_LoadF:   case Op_LoadD:
 299   case Op_LoadP:   case Op_LoadN:
 300   case Op_LoadBarrierSlowReg:

 301     *start = 0;
 302     *end   = 0; // no vector operands
 303     break;
 304   case Op_StoreB:  case Op_StoreC:
 305   case Op_StoreI:  case Op_StoreL:
 306   case Op_StoreF:  case Op_StoreD:
 307   case Op_StoreP:  case Op_StoreN:
 308     *start = MemNode::ValueIn;
 309     *end   = MemNode::ValueIn + 1; // 1 vector operand
 310     break;
 311   case Op_LShiftI:  case Op_LShiftL:
 312   case Op_RShiftI:  case Op_RShiftL:
 313   case Op_URShiftI: case Op_URShiftL:
 314     *start = 1;
 315     *end   = 2; // 1 vector operand
 316     break;
 317   case Op_AddI: case Op_AddL: case Op_AddF: case Op_AddD:
 318   case Op_SubI: case Op_SubL: case Op_SubF: case Op_SubD:
 319   case Op_MulI: case Op_MulL: case Op_MulF: case Op_MulD:
 320   case Op_DivF: case Op_DivD:




 281   case Op_ReplicateS:
 282   case Op_ReplicateI:
 283   case Op_ReplicateL:
 284   case Op_ReplicateF:
 285   case Op_ReplicateD:
 286     return true;
 287   default:
 288     return false;
 289   }
 290 }
 291 
 292 // [Start, end) half-open range defining which operands are vectors
 293 void VectorNode::vector_operands(Node* n, uint* start, uint* end) {
 294   switch (n->Opcode()) {
 295   case Op_LoadB:   case Op_LoadUB:
 296   case Op_LoadS:   case Op_LoadUS:
 297   case Op_LoadI:   case Op_LoadL:
 298   case Op_LoadF:   case Op_LoadD:
 299   case Op_LoadP:   case Op_LoadN:
 300   case Op_LoadBarrierSlowReg:
 301   case Op_LoadBarrierWeakSlowReg:
 302     *start = 0;
 303     *end   = 0; // no vector operands
 304     break;
 305   case Op_StoreB:  case Op_StoreC:
 306   case Op_StoreI:  case Op_StoreL:
 307   case Op_StoreF:  case Op_StoreD:
 308   case Op_StoreP:  case Op_StoreN:
 309     *start = MemNode::ValueIn;
 310     *end   = MemNode::ValueIn + 1; // 1 vector operand
 311     break;
 312   case Op_LShiftI:  case Op_LShiftL:
 313   case Op_RShiftI:  case Op_RShiftL:
 314   case Op_URShiftI: case Op_URShiftL:
 315     *start = 1;
 316     *end   = 2; // 1 vector operand
 317     break;
 318   case Op_AddI: case Op_AddL: case Op_AddF: case Op_AddD:
 319   case Op_SubI: case Op_SubL: case Op_SubF: case Op_SubD:
 320   case Op_MulI: case Op_MulL: case Op_MulF: case Op_MulD:
 321   case Op_DivF: case Op_DivD:


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