1 /*
   2  * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 // This file is a derivative work resulting from (and including) modifications
  26 // made by Azul Systems, Inc.  The dates of such changes are 2013-2016.
  27 // Copyright 2013-2016 Azul Systems, Inc.  All Rights Reserved.
  28 //
  29 // Please contact Azul Systems, 385 Moffett Park Drive, Suite 115, Sunnyvale,
  30 // CA 94089 USA or visit www.azul.com if you need additional information or
  31 // have any questions.
  32 
  33 #include "precompiled.hpp"
  34 #include "c1/c1_FrameMap.hpp"
  35 #include "c1/c1_LIR.hpp"
  36 #include "runtime/sharedRuntime.hpp"
  37 #include "vmreg_aarch32.inline.hpp"
  38 
  39 LIR_Opr FrameMap::r0_opr;
  40 LIR_Opr FrameMap::r1_opr;
  41 LIR_Opr FrameMap::r2_opr;
  42 LIR_Opr FrameMap::r3_opr;
  43 LIR_Opr FrameMap::r4_opr;
  44 LIR_Opr FrameMap::r5_opr;
  45 LIR_Opr FrameMap::r6_opr;
  46 LIR_Opr FrameMap::r7_opr;
  47 LIR_Opr FrameMap::r8_opr;
  48 LIR_Opr FrameMap::r9_opr;
  49 LIR_Opr FrameMap::r10_opr;
  50 LIR_Opr FrameMap::r11_opr;
  51 LIR_Opr FrameMap::r12_opr;
  52 LIR_Opr FrameMap::r13_opr;
  53 LIR_Opr FrameMap::r14_opr;
  54 LIR_Opr FrameMap::r15_opr;
  55 
  56 LIR_Opr FrameMap::r0_oop_opr;
  57 LIR_Opr FrameMap::r1_oop_opr;
  58 LIR_Opr FrameMap::r2_oop_opr;
  59 LIR_Opr FrameMap::r3_oop_opr;
  60 LIR_Opr FrameMap::r4_oop_opr;
  61 LIR_Opr FrameMap::r5_oop_opr;
  62 LIR_Opr FrameMap::r6_oop_opr;
  63 LIR_Opr FrameMap::r7_oop_opr;
  64 LIR_Opr FrameMap::r8_oop_opr;
  65 LIR_Opr FrameMap::r9_oop_opr;
  66 LIR_Opr FrameMap::r10_oop_opr;
  67 LIR_Opr FrameMap::r11_oop_opr;
  68 LIR_Opr FrameMap::r12_oop_opr;
  69 LIR_Opr FrameMap::r13_oop_opr;
  70 LIR_Opr FrameMap::r14_oop_opr;
  71 LIR_Opr FrameMap::r15_oop_opr;
  72 
  73 LIR_Opr FrameMap::r0_metadata_opr;
  74 LIR_Opr FrameMap::r1_metadata_opr;
  75 LIR_Opr FrameMap::r2_metadata_opr;
  76 LIR_Opr FrameMap::r3_metadata_opr;
  77 LIR_Opr FrameMap::r4_metadata_opr;
  78 LIR_Opr FrameMap::r5_metadata_opr;
  79 
  80 LIR_Opr FrameMap::sp_opr;
  81 LIR_Opr FrameMap::receiver_opr;
  82 
  83 LIR_Opr FrameMap::rscratch1_opr;
  84 LIR_Opr FrameMap::rscratch2_opr;
  85 LIR_Opr FrameMap::rscratch_long_opr;
  86 
  87 LIR_Opr FrameMap::long0_opr;
  88 LIR_Opr FrameMap::long1_opr;
  89 LIR_Opr FrameMap::long2_opr;
  90 LIR_Opr FrameMap::fpu0_float_opr;
  91 LIR_Opr FrameMap::fpu0_double_opr;
  92 
  93 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, };
  94 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, };
  95 
  96 void FrameMap::initialize() {
  97   assert(!_init_done, "must be called once");
  98 
  99   int i = 0;
 100   map_register(i, r0); r0_opr = LIR_OprFact::single_cpu(i); i++;
 101   map_register(i, r1); r1_opr = LIR_OprFact::single_cpu(i); i++;
 102   map_register(i, r2); r2_opr = LIR_OprFact::single_cpu(i); i++;
 103   map_register(i, r3); r3_opr = LIR_OprFact::single_cpu(i); i++;
 104   map_register(i, r4); r4_opr = LIR_OprFact::single_cpu(i); i++;
 105   map_register(i, r5); r5_opr = LIR_OprFact::single_cpu(i); i++;
 106   map_register(i, r6); r6_opr = LIR_OprFact::single_cpu(i); i++;
 107   map_register(i, r7); r7_opr = LIR_OprFact::single_cpu(i); i++;
 108   // Mapping lines in this block may be arbitrarily mixed, but all allocatable
 109   // registers should go above this comment, and unallocatable registers -
 110   // below.
 111   map_register(i, r8); r8_opr = LIR_OprFact::single_cpu(i); i++;   // rthread
 112   map_register(i, r9); r9_opr = LIR_OprFact::single_cpu(i); i++;   // rscratch1
 113   map_register(i, r10); r10_opr = LIR_OprFact::single_cpu(i); i++; // rmethod
 114   map_register(i, r11); r11_opr = LIR_OprFact::single_cpu(i); i++; // rfp
 115   map_register(i, r12); r12_opr = LIR_OprFact::single_cpu(i); i++; // rscratch2
 116   map_register(i, r13); r13_opr = LIR_OprFact::single_cpu(i); i++; // sp
 117   map_register(i, r14); r14_opr = LIR_OprFact::single_cpu(i); i++; // lr
 118   map_register(i, r15); r15_opr = LIR_OprFact::single_cpu(i); i++; // r15_pc
 119 
 120   // This flag must be set after all integer registers are mapped but before
 121   // the first use of as_*_opr() methods.
 122   _init_done = true;
 123 
 124   r0_oop_opr = as_oop_opr(r0);
 125   r1_oop_opr = as_oop_opr(r1);
 126   r2_oop_opr = as_oop_opr(r2);
 127   r3_oop_opr = as_oop_opr(r3);
 128   r4_oop_opr = as_oop_opr(r4);
 129   r5_oop_opr = as_oop_opr(r5);
 130   r6_oop_opr = as_oop_opr(r6);
 131   r7_oop_opr = as_oop_opr(r7);
 132   r8_oop_opr = as_oop_opr(r8);
 133   r9_oop_opr = as_oop_opr(r9);
 134   r10_oop_opr = as_oop_opr(r10);
 135   r11_oop_opr = as_oop_opr(r11);
 136   r12_oop_opr = as_oop_opr(r12);
 137   r13_oop_opr = as_oop_opr(r13);
 138   r14_oop_opr = as_oop_opr(r14);
 139   r15_oop_opr = as_oop_opr(r15);
 140 
 141   r0_metadata_opr = as_metadata_opr(r0);
 142   r1_metadata_opr = as_metadata_opr(r1);
 143   r2_metadata_opr = as_metadata_opr(r2);
 144   r3_metadata_opr = as_metadata_opr(r3);
 145   r4_metadata_opr = as_metadata_opr(r4);
 146   r5_metadata_opr = as_metadata_opr(r5);
 147 
 148   sp_opr = as_pointer_opr(sp);
 149 
 150   VMRegPair regs;
 151   BasicType sig_bt = T_OBJECT;
 152   SharedRuntime::java_calling_convention(&sig_bt, &regs, 1, true);
 153   receiver_opr = as_oop_opr(regs.first()->as_Register());
 154 
 155   rscratch1_opr = as_opr(rscratch1);
 156   rscratch2_opr = as_opr(rscratch2);
 157   rscratch_long_opr = as_long_opr(rscratch1, rscratch2);
 158 
 159   long0_opr = as_long_opr(r0, r1);
 160   long1_opr = as_long_opr(r2, r3);
 161   long2_opr = as_long_opr(r4, r5);
 162   fpu0_float_opr = LIR_OprFact::single_fpu(0);
 163   fpu0_double_opr = LIR_OprFact::double_fpu(0, 1);
 164 
 165   _caller_save_cpu_regs[0] = r0_opr;
 166   _caller_save_cpu_regs[1] = r1_opr;
 167   _caller_save_cpu_regs[2] = r2_opr;
 168   _caller_save_cpu_regs[3] = r3_opr;
 169   _caller_save_cpu_regs[4] = r4_opr;
 170   _caller_save_cpu_regs[5] = r5_opr;
 171   _caller_save_cpu_regs[6] = r6_opr;
 172   _caller_save_cpu_regs[7] = r7_opr;
 173 
 174   for (i = 0; i < nof_caller_save_fpu_regs; i++) {
 175     _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i);
 176   }
 177 }
 178 
 179 LIR_Opr FrameMap::stack_pointer() {
 180   return sp_opr;
 181 }
 182 
 183 // TODO: Make sure that neither method handle intrinsics nor compiled lambda
 184 // forms modify sp register (i.e., vmIntrinsics::{_invokeBasic, _linkToVirtual,
 185 // _linkToStatic, _linkToSpecial, _linkToInterface, _compiledLambdaForm})
 186 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() {
 187   return LIR_OprFact::illegalOpr;
 188 }
 189 
 190 // Return LIR_Opr corresponding to the given VMRegPair and data type
 191 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool) {
 192   LIR_Opr opr = LIR_OprFact::illegalOpr;
 193   VMReg r_1 = reg->first();
 194   VMReg r_2 = reg->second();
 195   if (r_1->is_stack()) {
 196     // Convert stack slot to sp-based address. The calling convention does not
 197     // count the SharedRuntime::out_preserve_stack_slots() value, so we must
 198     // add it in here.
 199     int st_off =
 200         (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) *
 201         VMRegImpl::stack_slot_size;
 202     opr = LIR_OprFact::address(new LIR_Address(sp_opr, st_off, type));
 203   } else if (r_1->is_Register()) {
 204     Register reg1 = r_1->as_Register();
 205 #ifdef HARD_FLOAT_CC
 206     if (type == T_DOUBLE || type == T_FLOAT) {
 207         ShouldNotReachHere();
 208     } else
 209 #endif
 210     if (type == T_LONG || type == T_DOUBLE) {
 211       assert(r_2->is_Register(), "wrong VMReg");
 212       Register reg2 = r_2->as_Register();
 213       opr = as_long_opr(reg1, reg2);
 214     } else if (type == T_OBJECT || type == T_ARRAY) {
 215       opr = as_oop_opr(reg1);
 216     } else if (type == T_METADATA) {
 217       opr = as_metadata_opr(reg1);
 218     } else {
 219       opr = as_opr(reg1);
 220     }
 221   } else if (r_1->is_FloatRegister()) {
 222     int num = r_1->as_FloatRegister()->encoding();
 223     if (type == T_FLOAT) {
 224       opr = LIR_OprFact::single_fpu(num);
 225     } else {
 226       assert(is_even(num) && r_2->as_FloatRegister()->encoding() == (num + 1),
 227              "wrong VMReg");
 228       opr = LIR_OprFact::double_fpu(num, num + 1);
 229     }
 230   } else {
 231     ShouldNotReachHere();
 232   }
 233   return opr;
 234 }
 235 
 236 // Return VMReg corresponding to the given FPU register number as it is
 237 // encoded in LIR_Opr. The conversion is straightforward because in this
 238 // implementation the encoding of FPU registers in LIR_Opr's is the same as
 239 // in FloatRegister's.
 240 VMReg FrameMap::fpu_regname(int n) {
 241   return as_FloatRegister(n)->as_VMReg();
 242 }
 243 
 244 // Check that the frame is properly addressable on the platform. The sp-based
 245 // address of every frame slot must have the offset expressible as AArch32's
 246 // imm12 with the separately stored sign.
 247 bool FrameMap::validate_frame() {
 248   int max_offset = in_bytes(framesize_in_bytes());
 249   int java_index = 0;
 250   for (int i = 0; i < _incoming_arguments->length(); i++) {
 251     LIR_Opr opr = _incoming_arguments->at(i);
 252     if (opr->is_stack()) {
 253       max_offset = MAX2(_argument_locations->at(java_index), max_offset);
 254     }
 255     java_index += type2size[opr->type()];
 256   }
 257   return Assembler::is_valid_for_offset_imm(max_offset, 12);
 258 }
 259 
 260 Address FrameMap::make_new_address(ByteSize sp_offset) const {
 261   return Address(sp, in_bytes(sp_offset));
 262 }