1 /*
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   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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  25 // This file is a derivative work resulting from (and including) modifications
  26 // made by Azul Systems, Inc.  The dates of such changes are 2013-2016.
  27 // Copyright 2013-2016 Azul Systems, Inc.  All Rights Reserved.
  28 //
  29 // Please contact Azul Systems, 385 Moffett Park Drive, Suite 115, Sunnyvale,
  30 // CA 94089 USA or visit www.azul.com if you need additional information or
  31 // have any questions.
  32 
  33 #ifndef CPU_X86_VM_C1_LIRASSEMBLER_AARCH32_HPP
  34 #define CPU_X86_VM_C1_LIRASSEMBLER_AARCH32_HPP
  35 
  36 #include "assembler_aarch32.hpp"
  37 
  38 
  39  private:
  40 
  41   int array_element_size(BasicType type) const;
  42 
  43   // helper functions which checks for overflow and sets bailout if it
  44   // occurs.  Always returns a valid embeddable pointer but in the
  45   // bailout case the pointer won't be to unique storage.
  46   address float_constant(float f);
  47   address double_constant(double d);
  48 
  49   Address as_Address(LIR_Address* addr, Register tmp, Address::InsnDataType type);
  50   Address as_Address_hi(LIR_Address* addr, Address::InsnDataType type);
  51   Address as_Address_lo(LIR_Address* addr, Address::InsnDataType type);
  52 
  53   Address as_Address(LIR_Address* addr, Address::InsnDataType type) {
  54     return as_Address(addr, rscratch1, type);
  55   }
  56 
  57 
  58   // Record the type of the receiver in ReceiverTypeData
  59   void type_profile_helper(Register mdo,
  60                            ciMethodData *md, ciProfileData *data,
  61                            Register recv, Label* update_done);
  62   void add_debug_info_for_branch(address adr, CodeEmitInfo* info);
  63 
  64   void casw(Register addr, Register newval, Register cmpval, Register result);
  65   void casl(Register addr, Register newval_lo, Register newval_hi,
  66             Register cmpval_lo,  Register cmpval_hi,
  67             Register tmp_lo, Register tmp_hi, Register result);
  68 
  69   FloatRegister as_float_reg(LIR_Opr doubleReg);
  70 
  71   static const int max_tableswitches = 20;
  72   struct tableswitch switches[max_tableswitches];
  73   int tableswitch_count;
  74 
  75   void init() { tableswitch_count = 0; }
  76 
  77   void deoptimize_trap(CodeEmitInfo *info);
  78 
  79   // remap input register (*s1 or *s2) to a temp one if it is at the same time
  80   // used a result register (d) of a preceeding operation (so otherwise its
  81   // contents gets effectively corrupt)
  82   void check_register_collision(Register d, Register *s1, Register *s2 = NULL, Register tmp = rscratch1);
  83 
  84 public:
  85 
  86   void store_parameter(Register r, int offset_from_sp_in_words);
  87   void store_parameter(jint c,     int offset_from_sp_in_words);
  88   void store_parameter(jobject c,  int offset_from_sp_in_words);
  89 
  90 enum { call_stub_size = 12 * NativeInstruction::arm_insn_sz,
  91        exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(175),
  92        deopt_handler_size = 7 * NativeInstruction::arm_insn_sz };
  93 
  94 #endif // CPU_X86_VM_C1_LIRASSEMBLER_AARCH32_HPP