1 /*
   2  * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * Copyright (c) 2015, Linaro Ltd. All rights reserved.
   5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   6  *
   7  * This code is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 only, as
   9  * published by the Free Software Foundation.
  10  *
  11  * This code is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * version 2 for more details (a copy is included in the LICENSE file that
  15  * accompanied this code).
  16  *
  17  * You should have received a copy of the GNU General Public License version
  18  * 2 along with this work; if not, write to the Free Software Foundation,
  19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  20  *
  21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  22  * or visit www.oracle.com if you need additional information or have any
  23  * questions.
  24  *
  25  */
  26 
  27 #ifndef CPU_AARCH32_VM_GLOBALDEFINITIONS_AARCH32_HPP
  28 #define CPU_AARCH32_VM_GLOBALDEFINITIONS_AARCH32_HPP
  29 
  30 // __ARM_PCS_VFP indicates that gcc runs with "-mfloat-abi=hard" option.
  31 // This option allows generation of floating point instructions and enforces
  32 // usage of FPU-specific calling conventions.
  33 #ifdef __ARM_PCS_VFP
  34 #define HARD_FLOAT_CC
  35 #endif // __ARM_PCS_VFP
  36 
  37 // If changing this please be sure to review all code which saves the registers
  38 // and the corresponding register maps to ensure that the respective frame
  39 // sizes are multiple of this new value
  40 const int StackAlignmentInBytes = 8;
  41 
  42 // Indicates whether the C calling conventions require that
  43 // 32-bit integer argument values are properly extended to 64 bits.
  44 // If set, SharedRuntime::c_calling_convention() must adapt
  45 // signatures accordingly.
  46 const bool CCallingConventionRequiresIntsAsLongs = false;
  47 
  48 #define SUPPORTS_NATIVE_CX8
  49 
  50 // The maximum B/BL offset range on AArch32 is 32MB.
  51 #undef CODE_CACHE_DEFAULT_LIMIT
  52 #define CODE_CACHE_DEFAULT_LIMIT (32*M)
  53 
  54 // According to the ARMv8 ARM, "Concurrent modification and execution
  55 // of instructions can lead to the resulting instruction performing
  56 // any behavior that can be achieved by executing any sequence of
  57 // instructions that can be executed from the same Exception level,
  58 // except where the instruction before modification and the
  59 // instruction after modification is a B, BL, NOP, BKPT, SVC, HVC, or
  60 // SMC instruction."
  61 //
  62 // This makes the games we play when patching difficult, so when we
  63 // come across an access that needs patching we deoptimize.  There are
  64 // ways we can avoid this, but these would slow down C1-compiled code
  65 // in the default case.  We could revisit this decision if we get any
  66 // evidence that it's worth doing.
  67 #define DEOPTIMIZE_WHEN_PATCHING
  68 
  69 #endif // CPU_AARCH32_VM_GLOBALDEFINITIONS_AARCH32_HPP