1 /*
   2  * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * Copyright (c) 2015, Linaro Ltd. All rights reserved.
   5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   6  *
   7  * This code is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 only, as
   9  * published by the Free Software Foundation.
  10  *
  11  * This code is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * version 2 for more details (a copy is included in the LICENSE file that
  15  * accompanied this code).
  16  *
  17  * You should have received a copy of the GNU General Public License version
  18  * 2 along with this work; if not, write to the Free Software Foundation,
  19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  20  *
  21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  22  * or visit www.oracle.com if you need additional information or have any
  23  * questions.
  24  *
  25  */
  26 
  27 #ifndef CPU_AARCH32_VM_MACROASSEMBLER_AARCH32_HPP
  28 #define CPU_AARCH32_VM_MACROASSEMBLER_AARCH32_HPP
  29 
  30 #include "asm/assembler.hpp"
  31 #include "nativeInst_aarch32.hpp"
  32 
  33 // MacroAssembler extends Assembler by frequently used macros.
  34 //
  35 // Instructions for which a 'better' code sequence exists depending
  36 // on arguments should also go in here.
  37 
  38 class MacroAssembler: public Assembler {
  39   friend class LIR_Assembler;
  40 
  41   using Assembler::mov;
  42 
  43  protected:
  44 
  45   // Support for VM calls
  46   //
  47   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  48   // may customize this version by overriding it for its purposes (e.g., to save/restore
  49   // additional registers when doing a VM call).
  50 #ifdef CC_INTERP
  51   // c++ interpreter never wants to use interp_masm version of call_VM
  52   #define VIRTUAL
  53 #else
  54   #define VIRTUAL virtual
  55 #endif
  56 
  57   VIRTUAL void call_VM_leaf_base(
  58     address entry_point,               // the entry point
  59     int     number_of_arguments,        // the number of arguments to pop after the call
  60     Label *retaddr = NULL
  61   );
  62 
  63   VIRTUAL void call_VM_leaf_base(
  64     address entry_point,               // the entry point
  65     int     number_of_arguments,        // the number of arguments to pop after the call
  66     Label &retaddr) {
  67     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  68   }
  69 
  70   // This is the base routine called by the different versions of call_VM. The interpreter
  71   // may customize this version by overriding it for its purposes (e.g., to save/restore
  72   // additional registers when doing a VM call).
  73   //
  74   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  75   // returns the register which contains the thread upon return. If a thread register has been
  76   // specified, the return value will correspond to that register. If no last_java_sp is specified
  77   // (noreg) than rsp will be used instead.
  78   VIRTUAL void call_VM_base(           // returns the register containing the thread upon return
  79     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  80     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  81     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  82     address  entry_point,              // the entry point
  83     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  84     bool     check_exceptions          // whether to check for pending exceptions after return
  85   );
  86 
  87   // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  88   // The implementation is only non-empty for the InterpreterMacroAssembler,
  89   // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  90   virtual void check_and_handle_popframe(Register java_thread);
  91   virtual void check_and_handle_earlyret(Register java_thread);
  92 
  93   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  94 
  95  public:
  96   void init_unseen_bytecodes();
  97   MacroAssembler(CodeBuffer* code) : Assembler(code) { init_unseen_bytecodes();}
  98 
  99   // Biased locking support
 100   // lock_reg and obj_reg must be loaded up with the appropriate values.
 101   // swap_reg is killed.
 102   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 103   // be killed; if not supplied, push/pop will be used internally to
 104   // allocate a temporary (inefficient, avoid if possible).
 105   // Optional slow case is for implementations (interpreter and C1) which branch to
 106   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 107   // Returns offset of first potentially-faulting instruction for null
 108   // check info (currently consumed only by C1). If
 109   // swap_reg_contains_mark is true then returns -1 as it is assumed
 110   // the calling code has already passed any potential faults.
 111   int biased_locking_enter(Register lock_reg, Register obj_reg,
 112                            Register swap_reg, Register tmp_reg,
 113                            bool swap_reg_contains_mark,
 114                            Label& done, Label* slow_case = NULL,
 115                            BiasedLockingCounters* counters = NULL);
 116   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 117 
 118 
 119   // Helper functions for statistics gathering.
 120   // Unconditional atomic increment.
 121   void atomic_inc(Register counter_addr, Register tmp);
 122   void atomic_inc(Address counter_addr, Register tmp1, Register tmp2) {
 123     lea(tmp1, counter_addr);
 124     atomic_inc(tmp1, tmp2);
 125   }
 126   // Load Effective Address
 127   void lea(Register r, const Address &a) {
 128     InstructionMark im(this);
 129     code_section()->relocate(inst_mark(), a.rspec());
 130     a.lea(this, r);
 131   }
 132 
 133   virtual void _call_Unimplemented(address call_site) {
 134     mov(rscratch2, call_site);
 135     stop("HALT");
 136   }
 137 
 138 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 139 
 140 // macro assembly operations needed for aarch32
 141 
 142 // first two private routines for loading 32 bit constants
 143 //TODO Probably add back the 64-bit one as it will be useful for longs
 144 private:
 145 
 146   int push(unsigned int bitset, Register stack);
 147   int pop(unsigned int bitset, Register stack);
 148 
 149 public:
 150 
 151   void mov(Register dst, Address a, Condition cond = C_DFLT);
 152 
 153 
 154   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 155   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 156 
 157   // now mov instructions for loading absolute addresses and 32bit immediates
 158 
 159   inline void mov(Register dst, address addr, Condition cond = C_DFLT) {
 160     // TODO: Do Address end up as address and then passing through this method, after
 161     // being marked for relocation elsewhere? If not (as I suspect) then this can
 162     // be relaxed to mov_immediate to potentially produce shorter code sequences.
 163     mov_immediate32(dst, (uint32_t)addr, cond, false);
 164   }
 165 
 166   inline void mov(Register dst, long l, Condition cond = C_DFLT) {
 167     mov(dst, (uint32_t)l, cond);
 168   }
 169   inline void mov(Register dst, unsigned long l, Condition cond = C_DFLT) {
 170     mov(dst, (uint32_t)l, cond);
 171   }
 172   inline void mov(Register dst, int i, Condition cond = C_DFLT) {
 173     mov(dst, (uint32_t)i, cond);
 174   }
 175   inline void mov(Register dst, uint32_t i, Condition cond = C_DFLT) {
 176     mov_immediate(dst, i, cond, false);
 177   }
 178 
 179   inline void mov(Register dst, Register src, Condition cond = C_DFLT) {
 180     Assembler::mov(dst, src, cond);
 181   }
 182   inline void mov(Register dst, Register src, shift_op shift,
 183                   Condition cond = C_DFLT) {
 184     Assembler::mov(dst, src, shift, cond);
 185   }
 186   // TODO add sflag compatibility
 187   void movptr(Register r, uintptr_t imm32, Condition cond = C_DFLT);
 188 
 189   void ret(Register reg);
 190 
 191   // Both of these are aarch64 instructions that can easily be emulated
 192   // Note that this does not quite have the same semantics as aarch64
 193   // version as this updates the s flag.
 194   void cbz(Register r, Label& l) {
 195     cmp(r, 0);
 196     b(l, EQ);
 197   }
 198   void cbnz(Register r, Label& l) {
 199     cmp(r, 0);
 200     b(l, NE);
 201   }
 202   void tbz(Register r, unsigned bit, Label& l) {
 203     tst(r, 1 << bit);
 204     b(l, EQ);
 205   }
 206   void tbnz(Register r, unsigned bit, Label& l) {
 207     tst(r, 1 << bit);
 208     b(l, NE);
 209   }
 210 
 211   void addmw(Address a, Register incr, Register scratch) {
 212     ldr(scratch, a);
 213     add(scratch, scratch, incr);
 214     str(scratch, a);
 215   }
 216 
 217   // Add constant to memory word
 218   void addmw(Address a, int imm, Register scratch) {
 219     ldr(scratch, a);
 220     if (imm > 0)
 221       add(scratch, scratch, (unsigned)imm);
 222     else
 223       sub(scratch, scratch, (unsigned)-imm);
 224     str(scratch, a);
 225   }
 226 
 227 // XXX stubs
 228 
 229   Register tlab_refill(Label& retry, Label& try_eden, Label& slow_case);
 230 
 231   // macro instructions for accessing and updating floating point
 232   // status register
 233   //
 234   // FPSR : op1 == 011
 235   //        CRn == 0100
 236   //        CRm == 0100
 237   //        op2 == 001
 238 
 239   inline void get_fpsr(Register reg = as_Register(0xf)) {
 240     vmrs(reg);
 241   }
 242 
 243   inline void set_fpsr(Register reg) {
 244     vmsr(reg);
 245   }
 246 
 247   inline void clear_fpsr() {
 248     mov(rscratch1, 0);
 249     set_fpsr(rscratch1);
 250   }
 251 
 252   // Support for NULL-checks
 253   //
 254   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 255   // If the accessed location is M[reg + offset] and the offset is known, provide the
 256   // offset. No explicit code generation is needed if the offset is within a certain
 257   // range (0 <= offset <= page_size).
 258 
 259   virtual void null_check(Register reg, int offset = -1);
 260   static bool needs_explicit_null_check(intptr_t offset);
 261 
 262   static address target_addr_for_insn(address insn_addr, unsigned insn);
 263   static address target_addr_for_insn(address insn_addr) {
 264     unsigned insn = *(unsigned*)insn_addr;
 265     return target_addr_for_insn(insn_addr, insn);
 266   }
 267 
 268   // Required platform-specific helpers for Label::patch_instructions.
 269   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 270   static int pd_patch_instruction_size(address branch, address target);
 271   static void pd_patch_instruction(address branch, address target) {
 272     pd_patch_instruction_size(branch, target);
 273   }
 274 
 275 #ifndef PRODUCT
 276   static void pd_print_patched_instruction(address branch);
 277 #endif
 278 
 279   static int patch_oop(address insn_addr, address o);
 280 
 281   // The following 4 methods return the offset of the appropriate move instruction
 282 
 283   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 284   int load_unsigned_byte(Register dst, Address src);
 285   int load_unsigned_short(Register dst, Address src);
 286 
 287   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 288   int load_signed_byte(Register dst, Address src);
 289   int load_signed_short(Register dst, Address src);
 290 
 291   // Support for sign-extension (hi:lo = extend_sign(lo))
 292   void extend_sign(Register hi, Register lo);
 293 
 294   // Load and store values by size and signed-ness
 295   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 296   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 297 
 298   // Support for inc/dec with optimal instruction selection depending on value.
 299   // increment()/decrement() calls with an address destination will need to use
 300   // rscratch1 to load the value to be incremented. increment()/decrement()
 301   // calls which add or subtract a constant value greater than 2^12 will need
 302   // to use rscratch2 to hold the constant. So, a register increment()/
 303   // decrement() may trash rscratch2, and an address increment()/decrement()
 304   // may trash rscratch1 and rscratch2.
 305   void decrement(Register reg, int value = 1);
 306   void decrement(Address dst, int value = 1);
 307   void increment(Register reg, int value = 1);
 308   void increment(Address dst, int value = 1);
 309 
 310   // Alignment
 311   void align(int modulus);
 312 
 313   // Stack frame creation/removal
 314   void enter()
 315   {
 316     stmdb(sp, RegSet::of(rfp, lr).bits());
 317     add(rfp, sp, wordSize);
 318   }
 319 
 320   void leave()
 321   {
 322     sub(sp, rfp, wordSize);
 323     ldmia(sp, RegSet::of(rfp, lr).bits());
 324   }
 325 
 326   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 327   // The pointer will be loaded into the thread register.
 328   void get_thread(Register thread);
 329 
 330   enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
 331   // Support for VM calls
 332   //
 333   // It is imperative that all calls into the VM are handled via the call_VM macros.
 334   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 335   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 336 
 337 
 338   void call_VM(Register oop_result,
 339                address entry_point,
 340                bool check_exceptions = true);
 341   void call_VM(Register oop_result,
 342                address entry_point,
 343                Register arg_1,
 344                bool check_exceptions = true);
 345   void call_VM(Register oop_result,
 346                address entry_point,
 347                Register arg_1, Register arg_2,
 348                bool check_exceptions = true);
 349   void call_VM(Register oop_result,
 350                address entry_point,
 351                Register arg_1, Register arg_2, Register arg_3,
 352                bool check_exceptions = true);
 353 
 354   // Overloadings with last_Java_sp
 355   void call_VM(Register oop_result,
 356                Register last_java_sp,
 357                address entry_point,
 358                int number_of_arguments = 0,
 359                bool check_exceptions = true);
 360   void call_VM(Register oop_result,
 361                Register last_java_sp,
 362                address entry_point,
 363                Register arg_1, bool
 364                check_exceptions = true);
 365   void call_VM(Register oop_result,
 366                Register last_java_sp,
 367                address entry_point,
 368                Register arg_1, Register arg_2,
 369                bool check_exceptions = true);
 370   void call_VM(Register oop_result,
 371                Register last_java_sp,
 372                address entry_point,
 373                Register arg_1, Register arg_2, Register arg_3,
 374                bool check_exceptions = true);
 375 
 376   void get_vm_result  (Register oop_result, Register thread);
 377   void get_vm_result_2(Register metadata_result, Register thread);
 378 
 379   // These always tightly bind to MacroAssembler::call_VM_base
 380   // bypassing the virtual implementation
 381   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 382   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 383   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 384   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 385   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 386 
 387   void call_VM_leaf(address entry_point,
 388                     int number_of_arguments = 0);
 389   void call_VM_leaf(address entry_point,
 390                     Register arg_1);
 391   void call_VM_leaf(address entry_point,
 392                     Register arg_1, Register arg_2);
 393   void call_VM_leaf(address entry_point,
 394                     Register arg_1, Register arg_2, Register arg_3);
 395 
 396   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 397   // bypassing the virtual implementation
 398   void super_call_VM_leaf(address entry_point);
 399   void super_call_VM_leaf(address entry_point, Register arg_1);
 400   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 401   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 402   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 403 
 404   // last Java Frame (fills frame anchor)
 405   void set_last_Java_frame(Register last_java_sp,
 406                            Register last_java_fp,
 407                            address last_java_pc,
 408                            Register scratch);
 409 
 410   void set_last_Java_frame(Register last_java_sp,
 411                            Register last_java_fp,
 412                            Label &last_java_pc,
 413                            Register scratch);
 414 
 415   void set_last_Java_frame(Register last_java_sp,
 416                            Register last_java_fp,
 417                            Register last_java_pc,
 418                            Register scratch);
 419 
 420   void reset_last_Java_frame(Register thread);
 421 
 422   // thread in the default location (rthread)
 423   void reset_last_Java_frame(bool clear_fp);
 424 
 425   // Stores
 426   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 427   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 428 
 429   void resolve_jobject(Register value, Register thread, Register tmp);
 430   void clear_jweak_tag(Register possibly_jweak);
 431 
 432 #if INCLUDE_ALL_GCS
 433 
 434   void g1_write_barrier_pre(Register obj,
 435                             Register pre_val,
 436                             Register thread,
 437                             Register tmp,
 438                             bool tosca_live,
 439                             bool expand_call);
 440 
 441   void g1_write_barrier_post(Register store_addr,
 442                              Register new_val,
 443                              Register thread,
 444                              Register tmp,
 445                              Register tmp2);
 446 
 447 #endif // INCLUDE_ALL_GCS
 448 
 449   // split store_check(Register obj) to enhance instruction interleaving
 450   void store_check_part_1(Register obj);
 451   void store_check_part_2(Register obj);
 452 
 453   // oop manipulations
 454   void load_klass(Register dst, Register src);
 455   void store_klass(Register dst, Register src);
 456   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 457 
 458   void load_heap_oop(Register dst, Address src);
 459 
 460   void load_heap_oop_not_null(Register dst, Address src);
 461   void store_heap_oop(Address dst, Register src);
 462 
 463   // Used for storing NULL. All other oop constants should be
 464   // stored using routines that take a jobject.
 465   void store_heap_oop_null(Address dst);
 466 
 467   void load_prototype_header(Register dst, Register src);
 468 
 469   void store_klass_gap(Register dst, Register src);
 470 
 471   // This dummy is to prevent a call to store_heap_oop from
 472   // converting a zero (like NULL) into a Register by giving
 473   // the compiler two choices it can't resolve
 474 
 475   void store_heap_oop(Address dst, void* dummy);
 476 
 477   void push_CPU_state();
 478   void pop_CPU_state() ;
 479 
 480   // Round up to a power of two
 481   void round_to(Register reg, int modulus);
 482 
 483   // allocation
 484   void eden_allocate(
 485     Register obj,                      // result: pointer to object after successful allocation
 486     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 487     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 488     Register t1,                       // temp register
 489     Label&   slow_case                 // continuation point if fast allocation fails
 490   );
 491   void tlab_allocate(
 492     Register obj,                      // result: pointer to object after successful allocation
 493     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 494     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 495     Register t1,                       // temp register
 496     Register t2,                       // temp register
 497     Label&   slow_case                 // continuation point if fast allocation fails
 498   );
 499 
 500   void verify_tlab();
 501 
 502   void incr_allocated_bytes(Register thread,
 503                             Register var_size_in_bytes, int con_size_in_bytes,
 504                             Register t1 = noreg);
 505 
 506   // interface method calling
 507   void lookup_interface_method(Register recv_klass,
 508                                Register intf_klass,
 509                                RegisterOrConstant itable_index,
 510                                Register method_result,
 511                                Register scan_temp,
 512                                Label& no_such_interface,
 513                                bool return_method = true);
 514 
 515   // virtual method calling
 516   // n.b. x86 allows RegisterOrConstant for vtable_index
 517   void lookup_virtual_method(Register recv_klass,
 518                              RegisterOrConstant vtable_index,
 519                              Register method_result);
 520 
 521   // Test sub_klass against super_klass, with fast and slow paths.
 522 
 523   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 524   // One of the three labels can be NULL, meaning take the fall-through.
 525   // If super_check_offset is -1, the value is loaded up from super_klass.
 526   // No registers are killed, except temp_reg.
 527   void check_klass_subtype_fast_path(Register sub_klass,
 528                                      Register super_klass,
 529                                      Register temp_reg,
 530                                      Label* L_success,
 531                                      Label* L_failure,
 532                                      Label* L_slow_path,
 533                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 534 
 535   // The rest of the type check; must be wired to a corresponding fast path.
 536   // It does not repeat the fast path logic, so don't use it standalone.
 537   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 538   // Updates the sub's secondary super cache as necessary.
 539   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 540   void check_klass_subtype_slow_path(Register sub_klass,
 541                                      Register super_klass,
 542                                      Register temp_reg,
 543                                      Register temp2_reg,
 544                                      Label* L_success,
 545                                      Label* L_failure,
 546                                      bool set_cond_codes = false);
 547 
 548   // Simplified, combined version, good for typical uses.
 549   // Falls through on failure.
 550   void check_klass_subtype(Register sub_klass,
 551                            Register super_klass,
 552                            Register temp_reg,
 553                            Label& L_success);
 554 
 555   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 556 
 557 
 558   // Debugging
 559 
 560   // only if +VerifyOops
 561   void verify_oop(Register reg, const char* s = "broken oop");
 562   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 563 
 564 // TODO: verify method and klass metadata (compare against vptr?)
 565   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 566   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 567 
 568 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 569 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 570 
 571   // only if +VerifyFPU
 572   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 573 
 574   // prints msg, dumps registers and stops execution
 575   void stop(const char* msg);
 576 
 577   // prints msg and continues
 578   void warn(const char* msg);
 579 
 580   static void debug32(char* msg, int32_t pc, int32_t regs[]);
 581 
 582   void untested()                                { stop("untested"); }
 583 
 584   void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
 585 
 586 #define should_not_reach_here() should_not_reach_here_line(__FILE__, __LINE__)
 587   void should_not_reach_here_line(const char *file, int line) {
 588 #ifdef ASSERT
 589     mov(rscratch1, line);
 590     reg_printf_important(file);
 591     reg_printf_important(": %d", rscratch1);
 592 #endif
 593     stop("should_not_reach_here");
 594   }
 595 
 596   // Stack overflow checking
 597   void bang_stack_with_offset(int offset) {
 598     // stack grows down, caller passes positive offset
 599     assert(offset > 0, "must bang with negative offset");
 600     // bang with random value from r0
 601     if (operand_valid_for_add_sub_immediate(offset)) {
 602       sub(rscratch2, sp, offset);
 603       strb(r0, Address(rscratch2));
 604     } else {
 605       mov(rscratch2, offset);
 606       strb(r0, Address(sp, rscratch2, Assembler::lsl(), Address::SUB));
 607     }
 608   }
 609 
 610   // Writes to stack successive pages until offset reached to check for
 611   // stack overflow + shadow pages.  Also, clobbers tmp
 612   void bang_stack_size(Register size, Register tmp);
 613 
 614   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 615                                                 Register tmp,
 616                                                 int offset);
 617 
 618   // Support for serializing memory accesses between threads
 619   void serialize_memory(Register thread, Register tmp);
 620 
 621   // Arithmetics
 622 
 623   void addptr(Address dst, int32_t src) {
 624     lea(rscratch2, dst);
 625     ldr(rscratch1, Address(rscratch2));
 626     add(rscratch1, rscratch1, src);
 627     str(rscratch1, Address(rscratch2));
 628   }
 629 
 630   void cmpptr(Register src1, Address src2);
 631 
 632   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
 633                   Label &suceed, Label *fail);
 634 
 635   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
 636                   Label &suceed, Label *fail);
 637 
 638   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
 639   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
 640 
 641   void atomic_xchg(Register prev, Register newv, Register addr);
 642   void atomic_xchgw(Register prev, Register newv, Register addr);
 643 
 644   void orptr(Address adr, RegisterOrConstant src) {
 645     ldr(rscratch2, adr);
 646     if (src.is_register())
 647       orr(rscratch2, rscratch2, src.as_register());
 648     else
 649       orr(rscratch2, rscratch2, src.as_constant());
 650     str(rscratch2, adr);
 651   }
 652 
 653   // Calls
 654 
 655   void trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
 656 
 657   static bool far_branches() {
 658     return ReservedCodeCacheSize > branch_range;
 659   }
 660 
 661   // Jumps that can reach anywhere in the code cache.
 662   // Trashes tmp.
 663   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
 664   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
 665 
 666   static int far_branch_size() {
 667     // TODO performance issue: always generate real far jumps
 668     if (far_branches()) {
 669       if (VM_Version::features() & (FT_ARMV7 | FT_ARMV6T2))  {
 670         return 3 * NativeInstruction::arm_insn_sz;  // movw, movt, br
 671       } else {
 672         return 5 * NativeInstruction::arm_insn_sz;  // mov, 3 orr, br
 673       }
 674     } else {
 675       return NativeInstruction::arm_insn_sz; // br
 676     }
 677   }
 678 
 679   // Emit the CompiledIC call idiom
 680   void ic_call(address entry);
 681 
 682   // Data
 683   void mov_metadata(Register dst, Metadata* obj);
 684   Address allocate_metadata_address(Metadata* obj);
 685   Address constant_oop_address(jobject obj);
 686 
 687   void movoop(Register dst, jobject obj, bool immediate = false);
 688 
 689   void far_load(Register dst, address addr);
 690   void far_load_oop(Register dst, int oop_index);
 691   void far_load_metadata(Register dst, int metadata_index);
 692   void far_load_const(Register dst, address const);
 693 
 694 
 695   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
 696   void kernel_crc32(Register crc, Register buf, Register len,
 697         Register table0, Register table1, Register table2, Register table3,
 698         Register tmp, Register tmp2, Register tmp3);
 699 
 700 #undef VIRTUAL
 701 
 702   // Stack push and pop individual 64 bit registers
 703   void push(Register src);
 704   void pop(Register dst);
 705 
 706   // push all registers onto the stack
 707   void pusha();
 708   void popa();
 709 
 710   void repne_scan(Register addr, Register value, Register count,
 711                   Register scratch);
 712   void repne_scanw(Register addr, Register value, Register count,
 713                    Register scratch);
 714 
 715   // Form an address from base + offset in Rd. Rd may or may not actually be
 716   // used: you must use the Address that is returned. It is up to you to ensure
 717   // that the shift provided matches the size of your data.
 718   Address form_address(Register Rd, Register base, long byte_offset, int shift);
 719 
 720  public:
 721 
 722   void ldr_constant(Register dest, const Address &const_addr) {
 723     if (NearCpool) {
 724       ldr(dest, const_addr);
 725     } else {
 726       mov(dest, InternalAddress(const_addr.target()));
 727       ldr(dest, dest);
 728     }
 729   }
 730 
 731   address read_polling_page(Register r, address page, relocInfo::relocType rtype);
 732   address read_polling_page(Register r, relocInfo::relocType rtype);
 733 
 734   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
 735   void update_byte_crc32(Register crc, Register val, Register table);
 736   void update_word_crc32(Register crc, Register v, Register tmp, Register tmp2,
 737         Register table0, Register table1, Register table2, Register table3);
 738 
 739   // Auto dispatch for barriers isb, dmb & dsb.
 740   void isb() {
 741     if(VM_Version::features() & FT_ARMV7) {
 742       Assembler::isb();
 743     } else {
 744       cp15isb();
 745     }
 746   }
 747 
 748   void dsb(enum barrier option) {
 749     if(VM_Version::features() & FT_ARMV7) {
 750       Assembler::dsb(option);
 751     } else {
 752       cp15dsb();
 753     }
 754   }
 755 
 756   void dmb(enum barrier option) {
 757     if(VM_Version::features() & FT_ARMV7) {
 758       Assembler::dmb(option);
 759     } else {
 760       cp15dmb();
 761     }
 762   }
 763 
 764   void membar(Membar_mask_bits order_constraint) {
 765     dmb(Assembler::barrier(order_constraint));
 766   }
 767 
 768   // ISB may be needed because of a safepoint
 769   void maybe_isb() { MacroAssembler::isb(); }
 770 
 771   // Helper functions for 64-bit multipliction, division and remainder
 772   // does <Rd+1:Rd> = <Rn+1:Rn> * <Rm+1:Rm>
 773   void mult_long(Register Rd, Register Rn, Register Rm);
 774   // does <Rdh:Rd> = <Rnh:Rn> * <Rmh:Rm>
 775   void mult_long(Register Rd, Register Rdh, Register Rn, Register Rnh, Register Rm, Register Rmh);
 776 
 777  private:
 778   void divide32(Register res, Register num, Register den, bool want_mod);
 779  public:
 780   // <Rd+1:Rd> = <Rn+1:Rn> / <Rm+1:Rm>
 781   // <Rd+1:Rd> = <Rn+1:Rn> % <Rm+1:Rm>
 782   // <Rd> = <Rn> / <Rm>
 783   // <Rd> = <Rn> % <Rm>
 784   void divide(Register Rd, Register Rn, Register Rm, int width, bool want_remainder);
 785 
 786   void extract_bits(Register dest, Register source, int lsb, int width);
 787 
 788   // These functions require that the src/dst register is an even register
 789   // and will emit LDREXD/STREXD if there are multiple cores and the procesor
 790   // supports it. If there's only one core then LDRD/STRD will be emit instead.
 791   // If the processor has multiple cores and doesn't support LDREXD/STREXD then
 792   // LDRD/STRD will be emitted and a warning message printed.
 793   void atomic_ldrd(Register Rt, Register RtII, Register Rbase);
 794   void atomic_strd(Register Rt, Register RtII, Register Rbase,
 795                    Register temp, Register tempII);
 796 
 797  private:
 798   // generic fallback ldrd generator. may need to use temporary register
 799   // when register collisions are found
 800   //
 801   // since double_ld_failed_dispatch can introduce address manipulation instructions
 802   // it should return offset of first load/store instruction that will be used
 803   // while constructing implicit null check table
 804   int double_ld_failed_dispatch(Register Rt, Register Rt2, const Address& adr,
 805                             void (Assembler::* mul)(unsigned, const Address&, Condition),
 806                             void (Assembler::* sgl)(Register, const Address&, Condition),
 807                             Register Rtmp, Condition cond);
 808   // ldrd/strd generator. can handle all strd cases and those ldrd where there
 809   // are no register collisions
 810   void double_ldst_failed_dispatch(Register Rt, Register Rt2, const Address& adr,
 811                             void (Assembler::* mul)(unsigned, const Address&, Condition),
 812                             void (Assembler::* sgl)(Register, const Address&, Condition),
 813                             Condition cond);
 814 public:
 815   // override ldrd/strd to perform a magic for when Rt + 1 != Rt2 or any other
 816   // conditions which prevent to use single ldrd/strd insn. a pair of ldr/str
 817   // is used instead then
 818   //
 819   // Since ldrd/strd macro can introduce address manipulation instructions
 820   // it should return offset of first load/store instruction that will be used
 821   // while constructing implicit null check table
 822   using Assembler::ldrd;
 823   int ldrd(Register Rt, Register Rt2, const Address& adr, Register Rmp = rscratch1, Condition cond = C_DFLT);
 824   using Assembler::strd;
 825   int strd(Register Rt, Register Rt2, const Address& adr, Condition cond = C_DFLT);
 826 
 827 private:
 828   void bfc_impl(Register rd, int lsb, int width, Condition cond);
 829 public:
 830   void bfc(Register Rd, int lsb, int width, Condition cond = C_DFLT) {
 831     if (VM_Version::features() & (FT_ARMV6T2 | FT_ARMV7))
 832       Assembler::bfc(Rd, lsb, width, cond);
 833     else
 834       bfc_impl(Rd, lsb, width, cond);
 835   }
 836 
 837   void align_stack() {
 838     if (StackAlignmentInBytes > 4)
 839       bic(sp, sp, StackAlignmentInBytes-1);
 840   }
 841 
 842 #ifdef ASSERT
 843   void verify_stack_alignment();
 844 #endif
 845 
 846   // Debug helper
 847   void save_machine_state();
 848   void restore_machine_state();
 849 
 850   static uint32_t bytecodes_until_print;
 851   static uint32_t bytecodes_executed;
 852   static int enable_debug;
 853   static int enable_method_debug;
 854   static int enable_debugging_static;
 855 
 856 
 857   void bytecode_seen(Register bc_reg, Register scratch);
 858   static void print_unseen_bytecodes();
 859   void reg_printf_internal(bool important, const char *fmt, Register a = r0, Register b = r0, Register c = r0);
 860   void reg_printf_important(const char *fmt, Register a = r0, Register b = r0, Register c = r0);
 861   void reg_printf(const char *fmt, Register a = r0, Register b = r0, Register c = r0);
 862   void print_method_entry(Register rmethod, bool native);
 863   void print_method_exit(bool normal = true);
 864   void get_bytecode(Register bc, Register dst);
 865   static void print_cpool(InstanceKlass *klass);
 866 
 867   void create_breakpoint();
 868 };
 869 
 870 
 871 #ifdef ASSERT
 872 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
 873 #endif
 874 
 875 /**
 876  * class SkipIfEqual:
 877  *
 878  * Instantiating this class will result in assembly code being output that will
 879  * jump around any code emitted between the creation of the instance and it's
 880  * automatic destruction at the end of a scope block, depending on the value of
 881  * the flag passed to the constructor, which will be checked at run-time.
 882  */
 883 class SkipIfEqual {
 884  private:
 885   MacroAssembler* _masm;
 886   Label _label;
 887 
 888  public:
 889    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
 890    ~SkipIfEqual();
 891 };
 892 
 893 struct tableswitch {
 894   Register _reg;
 895   int _insn_index;
 896   jint _first_key;
 897   jint _last_key;
 898   Label _after;
 899   Label _branches;
 900 };
 901 
 902 #endif // CPU_AARCH32_VM_MACROASSEMBLER_AARCH32_HPP