1 /*
   2  * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * Copyright (c) 2015, Linaro Ltd. All rights reserved.
   5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   6  *
   7  * This code is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 only, as
   9  * published by the Free Software Foundation.
  10  *
  11  * This code is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * version 2 for more details (a copy is included in the LICENSE file that
  15  * accompanied this code).
  16  *
  17  * You should have received a copy of the GNU General Public License version
  18  * 2 along with this work; if not, write to the Free Software Foundation,
  19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  20  *
  21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  22  * or visit www.oracle.com if you need additional information or have any
  23  * questions.
  24  *
  25  */
  26 
  27 #ifndef CPU_AARCH32_VM_REGISTER_AARCH32_HPP
  28 #define CPU_AARCH32_VM_REGISTER_AARCH32_HPP
  29 
  30 #include "asm/register.hpp"
  31 
  32 class VMRegImpl;
  33 typedef VMRegImpl* VMReg;
  34 
  35 // Implementation of integer registers for AArch32 architecture
  36 
  37 class RegisterImpl;
  38 typedef RegisterImpl* Register;
  39 
  40 inline Register as_Register(int encoding) {
  41   return (Register)(intptr_t) encoding;
  42 }
  43 
  44 class RegisterImpl : public AbstractRegisterImpl {
  45  public:
  46   enum {
  47     number_of_registers = 16
  48   };
  49 
  50   // Construction
  51   inline friend Register as_Register(int encoding);
  52 
  53   // Accessors
  54   int encoding() const {
  55     assert(is_valid(), "invalid register");
  56     return (intptr_t) this;
  57   }
  58   int encoding_nocheck() const {
  59     return (intptr_t) this;
  60   }
  61   VMReg as_VMReg();
  62   Register successor() const {
  63     return as_Register(encoding() + 1);
  64   }
  65 
  66   // Testers
  67   bool is_valid() const {
  68     return 0 <= (intptr_t) this && (intptr_t) this < number_of_registers;
  69   }
  70 
  71   // Return the bit which represents this register. This is intended to be
  72   // used in bitmasks. See RegSet class below.
  73   unsigned long bit(bool should_set = true) const {
  74     return should_set ? 1 << encoding() : 0;
  75   }
  76 
  77   // Return the name of this register
  78   const char* name() const;
  79 };
  80 
  81 // Integer registers of AArch32 architecture
  82 
  83 CONSTANT_REGISTER_DECLARATION(Register, noreg, -1);
  84 
  85 CONSTANT_REGISTER_DECLARATION(Register, r0,     0);
  86 CONSTANT_REGISTER_DECLARATION(Register, r1,     1);
  87 CONSTANT_REGISTER_DECLARATION(Register, r2,     2);
  88 CONSTANT_REGISTER_DECLARATION(Register, r3,     3);
  89 CONSTANT_REGISTER_DECLARATION(Register, r4,     4);
  90 CONSTANT_REGISTER_DECLARATION(Register, r5,     5);
  91 CONSTANT_REGISTER_DECLARATION(Register, r6,     6);
  92 CONSTANT_REGISTER_DECLARATION(Register, r7,     7);
  93 CONSTANT_REGISTER_DECLARATION(Register, r8,     8);
  94 CONSTANT_REGISTER_DECLARATION(Register, r9,     9);
  95 CONSTANT_REGISTER_DECLARATION(Register, r10,   10);
  96 CONSTANT_REGISTER_DECLARATION(Register, r11,   11);
  97 CONSTANT_REGISTER_DECLARATION(Register, r12,   12);
  98 CONSTANT_REGISTER_DECLARATION(Register, r13,   13);
  99 CONSTANT_REGISTER_DECLARATION(Register, r14,   14);
 100 CONSTANT_REGISTER_DECLARATION(Register, r15,   15);
 101 
 102 // Implementation of floating point registers for AArch32 (VFPv3-D16)
 103 // architecture
 104 
 105 class FloatRegisterImpl;
 106 typedef FloatRegisterImpl* FloatRegister;
 107 
 108 // Return FloatRegister corresponding to the given s-type (aka f-type in this
 109 // port) register number
 110 inline FloatRegister as_FloatRegister(int encoding) {
 111   return (FloatRegister)(intptr_t) encoding;
 112 }
 113 
 114 // Return FloatRegister corresponding to the given d-type register number
 115 inline FloatRegister as_DoubleFloatRegister(int encoding) {
 116   return as_FloatRegister(2 * encoding);
 117 }
 118 
 119 class FloatRegisterImpl : public AbstractRegisterImpl {
 120  public:
 121   enum {
 122     // VFPv3-D16 architecture includes 16 doubleword registers, which can be
 123     // also observed as 32 singleword registers. We count the singleword
 124     // registers here.
 125     number_of_registers = 32
 126   };
 127 
 128   enum FloatRegisterSize {
 129     SINGLE = 1,
 130     DOUBLE = 2,
 131     QUAD = 4
 132   };
 133 
 134   // Construction
 135   inline friend FloatRegister as_FloatRegister(int encoding);
 136   inline friend FloatRegister as_DoubleFloatRegister(int encoding);
 137 
 138   // Accessors
 139   int encoding() const {
 140     assert(is_valid(), "invalid register");
 141     return (intptr_t) this;
 142   }
 143   int encoding_nocheck() const {
 144     return (intptr_t) this;
 145   }
 146   VMReg as_VMReg();
 147   FloatRegister successor(enum FloatRegisterSize size) const {
 148     return (as_FloatRegister((encoding() + (int)size) % number_of_registers |
 149             (encoding() + (int)size) / number_of_registers));
 150   }
 151 
 152   // Testers
 153   bool is_valid() const {
 154     return 0 <= (intptr_t) this && (intptr_t) this < number_of_registers;
 155   }
 156 
 157   // Return the bit which represents this register. This is intended to be
 158   // used in bitmasks. See FloatRegSet class below.
 159   unsigned long bit(bool should_set = true) const {
 160     return should_set ? 1 << encoding() : 0;
 161   }
 162 
 163   // Return the name of this register
 164   const char* name() const;
 165 };
 166 
 167 // Floating point registers of AArch32 (VFPv3-D16, D32 and SIMD) architecture
 168 
 169 // Only the first 8 doubleword registers can be used for parameter passing
 170 // and thus are caller-saved. The rest 8 registers are callee-saved.
 171 // In VFPv3-D32 there are additional 16 doubleword registers that are
 172 // caller-saved again.
 173 
 174 // Here we introduce the symbolic names for doubleword registers and the
 175 // corresponding singleword views for the first 16 of them. The instruction
 176 // set allows us to encode the doubleword register numbers directly using
 177 // the constants below.
 178 
 179 // The respective names are as well defined for quad-word registers with
 180 // encoding set by the same principles.
 181 
 182 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg, -1);
 183 
 184 CONSTANT_REGISTER_DECLARATION(FloatRegister, d0,      0);
 185 CONSTANT_REGISTER_DECLARATION(FloatRegister, d1,      2);
 186 CONSTANT_REGISTER_DECLARATION(FloatRegister, d2,      4);
 187 CONSTANT_REGISTER_DECLARATION(FloatRegister, d3,      6);
 188 CONSTANT_REGISTER_DECLARATION(FloatRegister, d4,      8);
 189 CONSTANT_REGISTER_DECLARATION(FloatRegister, d5,     10);
 190 CONSTANT_REGISTER_DECLARATION(FloatRegister, d6,     12);
 191 CONSTANT_REGISTER_DECLARATION(FloatRegister, d7,     14);
 192 CONSTANT_REGISTER_DECLARATION(FloatRegister, d8,     16);
 193 CONSTANT_REGISTER_DECLARATION(FloatRegister, d9,     18);
 194 CONSTANT_REGISTER_DECLARATION(FloatRegister, d10,    20);
 195 CONSTANT_REGISTER_DECLARATION(FloatRegister, d11,    22);
 196 CONSTANT_REGISTER_DECLARATION(FloatRegister, d12,    24);
 197 CONSTANT_REGISTER_DECLARATION(FloatRegister, d13,    26);
 198 CONSTANT_REGISTER_DECLARATION(FloatRegister, d14,    28);
 199 CONSTANT_REGISTER_DECLARATION(FloatRegister, d15,    30);
 200 CONSTANT_REGISTER_DECLARATION(FloatRegister, d16,     1);
 201 CONSTANT_REGISTER_DECLARATION(FloatRegister, d17,     3);
 202 CONSTANT_REGISTER_DECLARATION(FloatRegister, d18,     5);
 203 CONSTANT_REGISTER_DECLARATION(FloatRegister, d19,     7);
 204 CONSTANT_REGISTER_DECLARATION(FloatRegister, d20,     9);
 205 CONSTANT_REGISTER_DECLARATION(FloatRegister, d21,    11);
 206 CONSTANT_REGISTER_DECLARATION(FloatRegister, d22,    13);
 207 CONSTANT_REGISTER_DECLARATION(FloatRegister, d23,    15);
 208 CONSTANT_REGISTER_DECLARATION(FloatRegister, d24,    17);
 209 CONSTANT_REGISTER_DECLARATION(FloatRegister, d25,    19);
 210 CONSTANT_REGISTER_DECLARATION(FloatRegister, d26,    21);
 211 CONSTANT_REGISTER_DECLARATION(FloatRegister, d27,    23);
 212 CONSTANT_REGISTER_DECLARATION(FloatRegister, d28,    25);
 213 CONSTANT_REGISTER_DECLARATION(FloatRegister, d29,    27);
 214 CONSTANT_REGISTER_DECLARATION(FloatRegister, d30,    29);
 215 CONSTANT_REGISTER_DECLARATION(FloatRegister, d31,    31);
 216 
 217 CONSTANT_REGISTER_DECLARATION(FloatRegister, q0,      0);
 218 CONSTANT_REGISTER_DECLARATION(FloatRegister, q1,      4);
 219 CONSTANT_REGISTER_DECLARATION(FloatRegister, q2,      8);
 220 CONSTANT_REGISTER_DECLARATION(FloatRegister, q3,     12);
 221 CONSTANT_REGISTER_DECLARATION(FloatRegister, q4,     16);
 222 CONSTANT_REGISTER_DECLARATION(FloatRegister, q5,     20);
 223 CONSTANT_REGISTER_DECLARATION(FloatRegister, q6,     24);
 224 CONSTANT_REGISTER_DECLARATION(FloatRegister, q7,     28);
 225 CONSTANT_REGISTER_DECLARATION(FloatRegister, q8,      1);
 226 CONSTANT_REGISTER_DECLARATION(FloatRegister, q9,      5);
 227 CONSTANT_REGISTER_DECLARATION(FloatRegister, q10,     9);
 228 CONSTANT_REGISTER_DECLARATION(FloatRegister, q11,    13);
 229 CONSTANT_REGISTER_DECLARATION(FloatRegister, q12,    17);
 230 CONSTANT_REGISTER_DECLARATION(FloatRegister, q13,    21);
 231 CONSTANT_REGISTER_DECLARATION(FloatRegister, q14,    25);
 232 CONSTANT_REGISTER_DECLARATION(FloatRegister, q15,    29);
 233 
 234 CONSTANT_REGISTER_DECLARATION(FloatRegister, f0,      0);
 235 CONSTANT_REGISTER_DECLARATION(FloatRegister, f1,      1);
 236 CONSTANT_REGISTER_DECLARATION(FloatRegister, f2,      2);
 237 CONSTANT_REGISTER_DECLARATION(FloatRegister, f3,      3);
 238 CONSTANT_REGISTER_DECLARATION(FloatRegister, f4,      4);
 239 CONSTANT_REGISTER_DECLARATION(FloatRegister, f5,      5);
 240 CONSTANT_REGISTER_DECLARATION(FloatRegister, f6,      6);
 241 CONSTANT_REGISTER_DECLARATION(FloatRegister, f7,      7);
 242 CONSTANT_REGISTER_DECLARATION(FloatRegister, f8,      8);
 243 CONSTANT_REGISTER_DECLARATION(FloatRegister, f9,      9);
 244 CONSTANT_REGISTER_DECLARATION(FloatRegister, f10,    10);
 245 CONSTANT_REGISTER_DECLARATION(FloatRegister, f11,    11);
 246 CONSTANT_REGISTER_DECLARATION(FloatRegister, f12,    12);
 247 CONSTANT_REGISTER_DECLARATION(FloatRegister, f13,    13);
 248 CONSTANT_REGISTER_DECLARATION(FloatRegister, f14,    14);
 249 CONSTANT_REGISTER_DECLARATION(FloatRegister, f15,    15);
 250 
 251 // Total number of registers of all sorts
 252 
 253 class ConcreteRegisterImpl : public AbstractRegisterImpl {
 254  public:
 255   enum {
 256     // Here we count the total number of 32-bit slots available in registers.
 257     // This number must be large enough to cover REG_COUNT (defined by C2)
 258     // registers. There is no requirement that any ordering here matches
 259     // any ordering C2 gives its OptoReg's.
 260     number_of_registers = RegisterImpl::number_of_registers +
 261                           FloatRegisterImpl::number_of_registers
 262   };
 263 
 264   static const int max_gpr;
 265   static const int max_fpr;
 266 };
 267 
 268 // Set of integer registers
 269 
 270 class RegSet {
 271  private:
 272   uint32_t _bitset;
 273 
 274   RegSet(uint32_t bitset) : _bitset(bitset) { }
 275 
 276  public:
 277   RegSet() : _bitset(0) { }
 278 
 279   RegSet(Register r1) : _bitset(r1->bit()) { }
 280 
 281   RegSet operator+(const RegSet aSet) const {
 282     RegSet result(_bitset | aSet._bitset);
 283     return result;
 284   }
 285 
 286   RegSet operator-(const RegSet aSet) const {
 287     RegSet result(_bitset & ~aSet._bitset);
 288     return result;
 289   }
 290 
 291   RegSet& operator+=(const RegSet aSet) {
 292     *this = *this + aSet;
 293     return *this;
 294   }
 295 
 296   static RegSet of(Register r1) {
 297     return RegSet(r1);
 298   }
 299 
 300   static RegSet of(Register r1, Register r2) {
 301     return of(r1) + r2;
 302   }
 303 
 304   static RegSet of(Register r1, Register r2, Register r3) {
 305     return of(r1, r2) + r3;
 306   }
 307 
 308   static RegSet of(Register r1, Register r2, Register r3, Register r4) {
 309     return of(r1, r2, r3) + r4;
 310   }
 311 
 312   static RegSet of(Register r1, Register r2, Register r3, Register r4, Register r5) {
 313     return of(r1, r2, r3, r4) + r5;
 314   }
 315 
 316   static RegSet range(Register start, Register end) {
 317     uint32_t bits = ~0;
 318     bits <<= start->encoding();
 319     bits <<= 31 - end->encoding();
 320     bits >>= 31 - end->encoding();
 321     return RegSet(bits);
 322   }
 323 
 324   uint32_t bits() const {
 325     return _bitset;
 326   }
 327 };
 328 
 329 // Set of singleword floating point registers
 330 
 331 class FloatRegSet {
 332  private:
 333   uint32_t _bitset;
 334 
 335   FloatRegSet(uint32_t bitset) : _bitset(bitset) { }
 336 
 337  public:
 338   FloatRegSet() : _bitset(0) { }
 339 
 340   FloatRegSet(FloatRegister r1) : _bitset(r1->bit()) { }
 341 
 342   FloatRegSet operator+(const FloatRegSet aSet) const {
 343     FloatRegSet result(_bitset | aSet._bitset);
 344     return result;
 345   }
 346 
 347   FloatRegSet operator-(const FloatRegSet aSet) const {
 348     FloatRegSet result(_bitset & ~aSet._bitset);
 349     return result;
 350   }
 351 
 352   FloatRegSet& operator+=(const FloatRegSet aSet) {
 353     *this = *this + aSet;
 354     return *this;
 355   }
 356 
 357   static FloatRegSet of(FloatRegister r1) {
 358     return FloatRegSet(r1);
 359   }
 360 
 361   static FloatRegSet of(FloatRegister r1, FloatRegister r2) {
 362     return of(r1) + r2;
 363   }
 364 
 365   static FloatRegSet of(FloatRegister r1, FloatRegister r2, FloatRegister r3) {
 366     return of(r1, r2) + r3;
 367   }
 368 
 369   static FloatRegSet of(FloatRegister r1, FloatRegister r2, FloatRegister r3,
 370                         FloatRegister r4) {
 371     return of(r1, r2, r3) + r4;
 372   }
 373 
 374   static FloatRegSet range(FloatRegister start, FloatRegister end) {
 375     uint32_t bits = ~0;
 376     bits <<= start->encoding();
 377     bits <<= 31 - end->encoding();
 378     bits >>= 31 - end->encoding();
 379     return FloatRegSet(bits);
 380   }
 381 
 382   uint32_t bits() const {
 383     return _bitset;
 384   }
 385 };
 386 
 387 // Set of doubleword floating point registers
 388 
 389 class DoubleFloatRegSet {
 390  private:
 391   uint32_t _bitset;
 392 
 393   DoubleFloatRegSet(uint32_t bitset) : _bitset(bitset) { }
 394 
 395  public:
 396   DoubleFloatRegSet() : _bitset(0) { }
 397 
 398   DoubleFloatRegSet(FloatRegister r1) : _bitset(1 << (r1->encoding() >> 1)) { }
 399 
 400   DoubleFloatRegSet operator+(const DoubleFloatRegSet aSet) const {
 401     DoubleFloatRegSet result(_bitset | aSet._bitset);
 402     return result;
 403   }
 404 
 405   DoubleFloatRegSet operator-(const DoubleFloatRegSet aSet) const {
 406     DoubleFloatRegSet result(_bitset & ~aSet._bitset);
 407     return result;
 408   }
 409 
 410   DoubleFloatRegSet& operator+=(const DoubleFloatRegSet aSet) {
 411     *this = *this + aSet;
 412     return *this;
 413   }
 414 
 415   static DoubleFloatRegSet of(FloatRegister r1) {
 416     return DoubleFloatRegSet(r1);
 417   }
 418 
 419   static DoubleFloatRegSet of(FloatRegister r1, FloatRegister r2) {
 420     return of(r1) + r2;
 421   }
 422 
 423   static DoubleFloatRegSet of(FloatRegister r1, FloatRegister r2,
 424                               FloatRegister r3) {
 425     return of(r1, r2) + r3;
 426   }
 427 
 428   static DoubleFloatRegSet of(FloatRegister r1, FloatRegister r2,
 429                               FloatRegister r3, FloatRegister r4) {
 430     return of(r1, r2, r3) + r4;
 431   }
 432 
 433   static DoubleFloatRegSet range(FloatRegister start, FloatRegister end) {
 434     uint32_t bits = ~0;
 435     bits <<= start->encoding() >> 1;
 436     bits <<= 31 - (end->encoding() >> 1);
 437     bits >>= 31 - (end->encoding() >> 1);
 438     return DoubleFloatRegSet(bits);
 439   }
 440 
 441   uint32_t bits() const {
 442     return _bitset;
 443   }
 444 };
 445 
 446 #endif // CPU_AARCH32_VM_REGISTER_AARCH32_HPP