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src/share/vm/c1/c1_LIR.hpp

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 602     return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 603                                LIR_OprDesc::metadata_type        |
 604                                LIR_OprDesc::cpu_register         |
 605                                LIR_OprDesc::single_size);
 606   }
 607   static LIR_Opr double_cpu(int reg1, int reg2) {
 608     LP64_ONLY(assert(reg1 == reg2, "must be identical"));
 609     return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
 610                                (reg2 << LIR_OprDesc::reg2_shift) |
 611                                LIR_OprDesc::long_type            |
 612                                LIR_OprDesc::cpu_register         |
 613                                LIR_OprDesc::double_size);
 614   }
 615 
 616   static LIR_Opr single_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 617                                                                              LIR_OprDesc::float_type           |
 618                                                                              LIR_OprDesc::fpu_register         |
 619                                                                              LIR_OprDesc::single_size); }
 620 #if defined(C1_LIR_MD_HPP)
 621 # include C1_LIR_MD_HPP
 622 #elif defined(SPARC)
 623   static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
 624                                                                              (reg2 << LIR_OprDesc::reg2_shift) |
 625                                                                              LIR_OprDesc::double_type          |
 626                                                                              LIR_OprDesc::fpu_register         |
 627                                                                              LIR_OprDesc::double_size); }
 628 #elif defined(X86)
 629   static LIR_Opr double_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 630                                                                              (reg  << LIR_OprDesc::reg2_shift) |
 631                                                                              LIR_OprDesc::double_type          |
 632                                                                              LIR_OprDesc::fpu_register         |
 633                                                                              LIR_OprDesc::double_size); }
 634 
 635   static LIR_Opr single_xmm(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 636                                                                              LIR_OprDesc::float_type           |
 637                                                                              LIR_OprDesc::fpu_register         |
 638                                                                              LIR_OprDesc::single_size          |
 639                                                                              LIR_OprDesc::is_xmm_mask); }
 640   static LIR_Opr double_xmm(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 641                                                                              (reg  << LIR_OprDesc::reg2_shift) |
 642                                                                              LIR_OprDesc::double_type          |


 689         break;
 690 
 691       case T_ADDRESS:
 692         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 693                                   LIR_OprDesc::address_type          |
 694                                   LIR_OprDesc::cpu_register          |
 695                                   LIR_OprDesc::single_size           |
 696                                   LIR_OprDesc::virtual_mask);
 697         break;
 698 
 699       case T_LONG:
 700         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 701                                   LIR_OprDesc::long_type             |
 702                                   LIR_OprDesc::cpu_register          |
 703                                   LIR_OprDesc::double_size           |
 704                                   LIR_OprDesc::virtual_mask);
 705         break;
 706 
 707 #ifdef __SOFTFP__
 708       case T_FLOAT:


 709         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 710                                   LIR_OprDesc::float_type  |








 711                                   LIR_OprDesc::cpu_register |
 712                                   LIR_OprDesc::single_size |
 713                                   LIR_OprDesc::virtual_mask);

 714         break;
 715       case T_DOUBLE:


 716         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 717                                   LIR_OprDesc::double_type |








 718                                   LIR_OprDesc::cpu_register |
 719                                   LIR_OprDesc::double_size |
 720                                   LIR_OprDesc::virtual_mask);

 721         break;
 722 #else // __SOFTFP__
 723       case T_FLOAT:
 724         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 725                                   LIR_OprDesc::float_type           |
 726                                   LIR_OprDesc::fpu_register         |
 727                                   LIR_OprDesc::single_size          |
 728                                   LIR_OprDesc::virtual_mask);
 729         break;
 730 
 731       case
 732         T_DOUBLE: res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 733                                             LIR_OprDesc::double_type           |
 734                                             LIR_OprDesc::fpu_register          |
 735                                             LIR_OprDesc::double_size           |
 736                                             LIR_OprDesc::virtual_mask);
 737         break;
 738 #endif // __SOFTFP__
 739       default:       ShouldNotReachHere(); res = illegalOpr;
 740     }




 602     return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 603                                LIR_OprDesc::metadata_type        |
 604                                LIR_OprDesc::cpu_register         |
 605                                LIR_OprDesc::single_size);
 606   }
 607   static LIR_Opr double_cpu(int reg1, int reg2) {
 608     LP64_ONLY(assert(reg1 == reg2, "must be identical"));
 609     return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
 610                                (reg2 << LIR_OprDesc::reg2_shift) |
 611                                LIR_OprDesc::long_type            |
 612                                LIR_OprDesc::cpu_register         |
 613                                LIR_OprDesc::double_size);
 614   }
 615 
 616   static LIR_Opr single_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 617                                                                              LIR_OprDesc::float_type           |
 618                                                                              LIR_OprDesc::fpu_register         |
 619                                                                              LIR_OprDesc::single_size); }
 620 #if defined(C1_LIR_MD_HPP)
 621 # include C1_LIR_MD_HPP
 622 #elif defined(SPARC) || defined(AARCH32)
 623   static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
 624                                                                              (reg2 << LIR_OprDesc::reg2_shift) |
 625                                                                              LIR_OprDesc::double_type          |
 626                                                                              LIR_OprDesc::fpu_register         |
 627                                                                              LIR_OprDesc::double_size); }
 628 #elif defined(X86)
 629   static LIR_Opr double_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 630                                                                              (reg  << LIR_OprDesc::reg2_shift) |
 631                                                                              LIR_OprDesc::double_type          |
 632                                                                              LIR_OprDesc::fpu_register         |
 633                                                                              LIR_OprDesc::double_size); }
 634 
 635   static LIR_Opr single_xmm(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 636                                                                              LIR_OprDesc::float_type           |
 637                                                                              LIR_OprDesc::fpu_register         |
 638                                                                              LIR_OprDesc::single_size          |
 639                                                                              LIR_OprDesc::is_xmm_mask); }
 640   static LIR_Opr double_xmm(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 641                                                                              (reg  << LIR_OprDesc::reg2_shift) |
 642                                                                              LIR_OprDesc::double_type          |


 689         break;
 690 
 691       case T_ADDRESS:
 692         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 693                                   LIR_OprDesc::address_type          |
 694                                   LIR_OprDesc::cpu_register          |
 695                                   LIR_OprDesc::single_size           |
 696                                   LIR_OprDesc::virtual_mask);
 697         break;
 698 
 699       case T_LONG:
 700         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 701                                   LIR_OprDesc::long_type             |
 702                                   LIR_OprDesc::cpu_register          |
 703                                   LIR_OprDesc::double_size           |
 704                                   LIR_OprDesc::virtual_mask);
 705         break;
 706 
 707 #ifdef __SOFTFP__
 708       case T_FLOAT:
 709 #ifdef AARCH32
 710         if (hasFPU()) {
 711         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 712                                   LIR_OprDesc::float_type  |
 713                                       LIR_OprDesc::fpu_register         |
 714                                       LIR_OprDesc::single_size          |
 715                                       LIR_OprDesc::virtual_mask);
 716         } else
 717 #endif // AARCH32
 718         {
 719             res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 720                                       LIR_OprDesc::float_type  |
 721                                   LIR_OprDesc::cpu_register |
 722                                   LIR_OprDesc::single_size |
 723                                   LIR_OprDesc::virtual_mask);
 724         }
 725         break;
 726       case T_DOUBLE:
 727 #ifdef AARCH32
 728         if(hasFPU()) {
 729         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 730                                   LIR_OprDesc::double_type |
 731                                                 LIR_OprDesc::fpu_register          |
 732                                                 LIR_OprDesc::double_size           |
 733                                                 LIR_OprDesc::virtual_mask);
 734         } else
 735 #endif
 736         {
 737             res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 738                                       LIR_OprDesc::double_type |
 739                                   LIR_OprDesc::cpu_register |
 740                                   LIR_OprDesc::double_size |
 741                                   LIR_OprDesc::virtual_mask);
 742         }
 743         break;
 744 #else // __SOFTFP__
 745       case T_FLOAT:
 746         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 747                                   LIR_OprDesc::float_type           |
 748                                   LIR_OprDesc::fpu_register         |
 749                                   LIR_OprDesc::single_size          |
 750                                   LIR_OprDesc::virtual_mask);
 751         break;
 752 
 753       case
 754         T_DOUBLE: res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
 755                                             LIR_OprDesc::double_type           |
 756                                             LIR_OprDesc::fpu_register          |
 757                                             LIR_OprDesc::double_size           |
 758                                             LIR_OprDesc::virtual_mask);
 759         break;
 760 #endif // __SOFTFP__
 761       default:       ShouldNotReachHere(); res = illegalOpr;
 762     }


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