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src/share/vm/c1/c1_LIR.hpp

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@@ -617,11 +617,11 @@
                                                                              LIR_OprDesc::float_type           |
                                                                              LIR_OprDesc::fpu_register         |
                                                                              LIR_OprDesc::single_size); }
 #if defined(C1_LIR_MD_HPP)
 # include C1_LIR_MD_HPP
-#elif defined(SPARC)
+#elif defined(SPARC) || defined(AARCH32)
   static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
                                                                              (reg2 << LIR_OprDesc::reg2_shift) |
                                                                              LIR_OprDesc::double_type          |
                                                                              LIR_OprDesc::fpu_register         |
                                                                              LIR_OprDesc::double_size); }

@@ -704,22 +704,44 @@
                                   LIR_OprDesc::virtual_mask);
         break;
 
 #ifdef __SOFTFP__
       case T_FLOAT:
+#ifdef AARCH32
+        if (hasFPU()) {
         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
                                   LIR_OprDesc::float_type  |
+                                      LIR_OprDesc::fpu_register         |
+                                      LIR_OprDesc::single_size          |
+                                      LIR_OprDesc::virtual_mask);
+        } else
+#endif // AARCH32
+        {
+            res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                      LIR_OprDesc::float_type  |
                                   LIR_OprDesc::cpu_register |
                                   LIR_OprDesc::single_size |
                                   LIR_OprDesc::virtual_mask);
+        }
         break;
       case T_DOUBLE:
+#ifdef AARCH32
+        if(hasFPU()) {
         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
                                   LIR_OprDesc::double_type |
+                                                LIR_OprDesc::fpu_register          |
+                                                LIR_OprDesc::double_size           |
+                                                LIR_OprDesc::virtual_mask);
+        } else
+#endif
+        {
+            res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
+                                      LIR_OprDesc::double_type |
                                   LIR_OprDesc::cpu_register |
                                   LIR_OprDesc::double_size |
                                   LIR_OprDesc::virtual_mask);
+        }
         break;
 #else // __SOFTFP__
       case T_FLOAT:
         res = (LIR_Opr)(intptr_t)((index << LIR_OprDesc::data_shift) |
                                   LIR_OprDesc::float_type           |
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