1 /*
   2  * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_Compilation.hpp"
  27 #include "c1/c1_Instruction.hpp"
  28 #include "c1/c1_InstructionPrinter.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_ValueStack.hpp"
  32 #include "ci/ciInstance.hpp"
  33 #ifdef TARGET_ARCH_x86
  34 # include "nativeInst_x86.hpp"
  35 # include "vmreg_x86.inline.hpp"
  36 #endif
  37 #ifdef TARGET_ARCH_sparc
  38 # include "nativeInst_sparc.hpp"
  39 # include "vmreg_sparc.inline.hpp"
  40 #endif
  41 #ifdef TARGET_ARCH_zero
  42 # include "nativeInst_zero.hpp"
  43 # include "vmreg_zero.inline.hpp"
  44 #endif
  45 #ifdef TARGET_ARCH_arm
  46 # include "nativeInst_arm.hpp"
  47 # include "vmreg_arm.inline.hpp"
  48 #endif
  49 #ifdef TARGET_ARCH_ppc
  50 # include "nativeInst_ppc.hpp"
  51 # include "vmreg_ppc.inline.hpp"
  52 #endif
  53 #ifdef TARGET_ARCH_aarch32
  54 # include "nativeInst_aarch32.hpp"
  55 # include "vmreg_aarch32.inline.hpp"
  56 #endif
  57 
  58 
  59 void LIR_Assembler::patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) {
  60   // we must have enough patching space so that call can be inserted
  61   while ((intx) _masm->pc() - (intx) patch->pc_start() < NativeCall::instruction_size) {
  62     _masm->nop();
  63   }
  64   patch->install(_masm, patch_code, obj, info);
  65   append_code_stub(patch);
  66 
  67 #ifdef ASSERT
  68   Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
  69   if (patch->id() == PatchingStub::access_field_id) {
  70     switch (code) {
  71       case Bytecodes::_putstatic:
  72       case Bytecodes::_getstatic:
  73       case Bytecodes::_putfield:
  74       case Bytecodes::_getfield:
  75         break;
  76       default:
  77         ShouldNotReachHere();
  78     }
  79   } else if (patch->id() == PatchingStub::load_klass_id) {
  80     switch (code) {
  81       case Bytecodes::_new:
  82       case Bytecodes::_anewarray:
  83       case Bytecodes::_multianewarray:
  84       case Bytecodes::_instanceof:
  85       case Bytecodes::_checkcast:
  86         break;
  87       default:
  88         ShouldNotReachHere();
  89     }
  90   } else if (patch->id() == PatchingStub::load_mirror_id) {
  91     switch (code) {
  92       case Bytecodes::_putstatic:
  93       case Bytecodes::_getstatic:
  94       case Bytecodes::_ldc:
  95       case Bytecodes::_ldc_w:
  96         break;
  97       default:
  98         ShouldNotReachHere();
  99     }
 100   } else if (patch->id() == PatchingStub::load_appendix_id) {
 101     Bytecodes::Code bc_raw = info->scope()->method()->raw_code_at_bci(info->stack()->bci());
 102     assert(Bytecodes::has_optional_appendix(bc_raw), "unexpected appendix resolution");
 103   } else {
 104     ShouldNotReachHere();
 105   }
 106 #endif
 107 }
 108 
 109 PatchingStub::PatchID LIR_Assembler::patching_id(CodeEmitInfo* info) {
 110   IRScope* scope = info->scope();
 111   Bytecodes::Code bc_raw = scope->method()->raw_code_at_bci(info->stack()->bci());
 112   if (Bytecodes::has_optional_appendix(bc_raw)) {
 113     return PatchingStub::load_appendix_id;
 114   }
 115   return PatchingStub::load_mirror_id;
 116 }
 117 
 118 //---------------------------------------------------------------
 119 
 120 
 121 LIR_Assembler::LIR_Assembler(Compilation* c):
 122    _compilation(c)
 123  , _masm(c->masm())
 124  , _bs(Universe::heap()->barrier_set())
 125  , _frame_map(c->frame_map())
 126  , _current_block(NULL)
 127  , _pending_non_safepoint(NULL)
 128  , _pending_non_safepoint_offset(0)
 129 {
 130   _slow_case_stubs = new CodeStubList();
 131 }
 132 
 133 
 134 LIR_Assembler::~LIR_Assembler() {
 135   // The unwind handler label may be unbound if this destructor is invoked because of a bail-out.
 136   // Reset it here to avoid an assertion.
 137   _unwind_handler_entry.reset();
 138 }
 139 
 140 
 141 void LIR_Assembler::check_codespace() {
 142   CodeSection* cs = _masm->code_section();
 143   if (cs->remaining() < (int)(NOT_LP64(1*K)LP64_ONLY(2*K))) {
 144     BAILOUT("CodeBuffer overflow");
 145   }
 146 }
 147 
 148 
 149 void LIR_Assembler::append_code_stub(CodeStub* stub) {
 150   _slow_case_stubs->append(stub);
 151 }
 152 
 153 void LIR_Assembler::emit_stubs(CodeStubList* stub_list) {
 154   for (int m = 0; m < stub_list->length(); m++) {
 155     CodeStub* s = (*stub_list)[m];
 156 
 157     check_codespace();
 158     CHECK_BAILOUT();
 159 
 160 #ifndef PRODUCT
 161     if (CommentedAssembly) {
 162       stringStream st;
 163       s->print_name(&st);
 164       st.print(" slow case");
 165       _masm->block_comment(st.as_string());
 166     }
 167 #endif
 168     s->emit_code(this);
 169 #ifdef ASSERT
 170     s->assert_no_unbound_labels();
 171 #endif
 172   }
 173 }
 174 
 175 
 176 void LIR_Assembler::emit_slow_case_stubs() {
 177   emit_stubs(_slow_case_stubs);
 178 }
 179 
 180 
 181 bool LIR_Assembler::needs_icache(ciMethod* method) const {
 182   return !method->is_static();
 183 }
 184 
 185 
 186 int LIR_Assembler::code_offset() const {
 187   return _masm->offset();
 188 }
 189 
 190 
 191 address LIR_Assembler::pc() const {
 192   return _masm->pc();
 193 }
 194 
 195 // To bang the stack of this compiled method we use the stack size
 196 // that the interpreter would need in case of a deoptimization. This
 197 // removes the need to bang the stack in the deoptimization blob which
 198 // in turn simplifies stack overflow handling.
 199 int LIR_Assembler::bang_size_in_bytes() const {
 200   return MAX2(initial_frame_size_in_bytes(), _compilation->interpreter_frame_size());
 201 }
 202 
 203 void LIR_Assembler::emit_exception_entries(ExceptionInfoList* info_list) {
 204   for (int i = 0; i < info_list->length(); i++) {
 205     XHandlers* handlers = info_list->at(i)->exception_handlers();
 206 
 207     for (int j = 0; j < handlers->length(); j++) {
 208       XHandler* handler = handlers->handler_at(j);
 209       assert(handler->lir_op_id() != -1, "handler not processed by LinearScan");
 210       assert(handler->entry_code() == NULL ||
 211              handler->entry_code()->instructions_list()->last()->code() == lir_branch ||
 212              handler->entry_code()->instructions_list()->last()->code() == lir_delay_slot, "last operation must be branch");
 213 
 214       if (handler->entry_pco() == -1) {
 215         // entry code not emitted yet
 216         if (handler->entry_code() != NULL && handler->entry_code()->instructions_list()->length() > 1) {
 217           handler->set_entry_pco(code_offset());
 218           if (CommentedAssembly) {
 219             _masm->block_comment("Exception adapter block");
 220           }
 221           emit_lir_list(handler->entry_code());
 222         } else {
 223           handler->set_entry_pco(handler->entry_block()->exception_handler_pco());
 224         }
 225 
 226         assert(handler->entry_pco() != -1, "must be set now");
 227       }
 228     }
 229   }
 230 }
 231 
 232 
 233 void LIR_Assembler::emit_code(BlockList* hir) {
 234   if (PrintLIR) {
 235     print_LIR(hir);
 236   }
 237 
 238   int n = hir->length();
 239   for (int i = 0; i < n; i++) {
 240     emit_block(hir->at(i));
 241     CHECK_BAILOUT();
 242   }
 243 
 244   flush_debug_info(code_offset());
 245 
 246   DEBUG_ONLY(check_no_unbound_labels());
 247 }
 248 
 249 
 250 void LIR_Assembler::emit_block(BlockBegin* block) {
 251   if (block->is_set(BlockBegin::backward_branch_target_flag)) {
 252     align_backward_branch_target();
 253   }
 254 
 255   // if this block is the start of an exception handler, record the
 256   // PC offset of the first instruction for later construction of
 257   // the ExceptionHandlerTable
 258   if (block->is_set(BlockBegin::exception_entry_flag)) {
 259     block->set_exception_handler_pco(code_offset());
 260   }
 261 
 262 #ifndef PRODUCT
 263   if (PrintLIRWithAssembly) {
 264     // don't print Phi's
 265     InstructionPrinter ip(false);
 266     block->print(ip);
 267   }
 268 #endif /* PRODUCT */
 269 
 270   assert(block->lir() != NULL, "must have LIR");
 271   X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
 272 
 273 #ifndef PRODUCT
 274   if (CommentedAssembly) {
 275     stringStream st;
 276     st.print_cr(" block B%d [%d, %d]", block->block_id(), block->bci(), block->end()->printable_bci());
 277     _masm->block_comment(st.as_string());
 278   }
 279 #endif
 280 
 281   emit_lir_list(block->lir());
 282 
 283   X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
 284 }
 285 
 286 
 287 void LIR_Assembler::emit_lir_list(LIR_List* list) {
 288   peephole(list);
 289 
 290   int n = list->length();
 291   for (int i = 0; i < n; i++) {
 292     LIR_Op* op = list->at(i);
 293 
 294     check_codespace();
 295     CHECK_BAILOUT();
 296 
 297 #ifndef PRODUCT
 298     if (CommentedAssembly) {
 299       // Don't record out every op since that's too verbose.  Print
 300       // branches since they include block and stub names.  Also print
 301       // patching moves since they generate funny looking code.
 302       if (op->code() == lir_branch ||
 303           (op->code() == lir_move && op->as_Op1()->patch_code() != lir_patch_none)) {
 304         stringStream st;
 305         op->print_on(&st);
 306         _masm->block_comment(st.as_string());
 307       }
 308     }
 309     if (PrintLIRWithAssembly) {
 310       // print out the LIR operation followed by the resulting assembly
 311       list->at(i)->print(); tty->cr();
 312     }
 313 #endif /* PRODUCT */
 314 
 315     op->emit_code(this);
 316 
 317     if (compilation()->debug_info_recorder()->recording_non_safepoints()) {
 318       process_debug_info(op);
 319     }
 320 
 321 #ifndef PRODUCT
 322     if (PrintLIRWithAssembly) {
 323       _masm->code()->decode();
 324     }
 325 #endif /* PRODUCT */
 326   }
 327 }
 328 
 329 #ifdef ASSERT
 330 void LIR_Assembler::check_no_unbound_labels() {
 331   CHECK_BAILOUT();
 332 
 333   for (int i = 0; i < _branch_target_blocks.length() - 1; i++) {
 334     if (!_branch_target_blocks.at(i)->label()->is_bound()) {
 335       tty->print_cr("label of block B%d is not bound", _branch_target_blocks.at(i)->block_id());
 336       assert(false, "unbound label");
 337     }
 338   }
 339 }
 340 #endif
 341 
 342 //----------------------------------debug info--------------------------------
 343 
 344 
 345 void LIR_Assembler::add_debug_info_for_branch(CodeEmitInfo* info) {
 346   _masm->code_section()->relocate(pc(), relocInfo::poll_type);
 347   int pc_offset = code_offset();
 348   flush_debug_info(pc_offset);
 349   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 350   if (info->exception_handlers() != NULL) {
 351     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
 352   }
 353 }
 354 
 355 
 356 void LIR_Assembler::add_call_info(int pc_offset, CodeEmitInfo* cinfo) {
 357   flush_debug_info(pc_offset);
 358   cinfo->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 359   if (cinfo->exception_handlers() != NULL) {
 360     compilation()->add_exception_handlers_for_pco(pc_offset, cinfo->exception_handlers());
 361   }
 362 }
 363 
 364 static ValueStack* debug_info(Instruction* ins) {
 365   StateSplit* ss = ins->as_StateSplit();
 366   if (ss != NULL) return ss->state();
 367   return ins->state_before();
 368 }
 369 
 370 void LIR_Assembler::process_debug_info(LIR_Op* op) {
 371   Instruction* src = op->source();
 372   if (src == NULL)  return;
 373   int pc_offset = code_offset();
 374   if (_pending_non_safepoint == src) {
 375     _pending_non_safepoint_offset = pc_offset;
 376     return;
 377   }
 378   ValueStack* vstack = debug_info(src);
 379   if (vstack == NULL)  return;
 380   if (_pending_non_safepoint != NULL) {
 381     // Got some old debug info.  Get rid of it.
 382     if (debug_info(_pending_non_safepoint) == vstack) {
 383       _pending_non_safepoint_offset = pc_offset;
 384       return;
 385     }
 386     if (_pending_non_safepoint_offset < pc_offset) {
 387       record_non_safepoint_debug_info();
 388     }
 389     _pending_non_safepoint = NULL;
 390   }
 391   // Remember the debug info.
 392   if (pc_offset > compilation()->debug_info_recorder()->last_pc_offset()) {
 393     _pending_non_safepoint = src;
 394     _pending_non_safepoint_offset = pc_offset;
 395   }
 396 }
 397 
 398 // Index caller states in s, where 0 is the oldest, 1 its callee, etc.
 399 // Return NULL if n is too large.
 400 // Returns the caller_bci for the next-younger state, also.
 401 static ValueStack* nth_oldest(ValueStack* s, int n, int& bci_result) {
 402   ValueStack* t = s;
 403   for (int i = 0; i < n; i++) {
 404     if (t == NULL)  break;
 405     t = t->caller_state();
 406   }
 407   if (t == NULL)  return NULL;
 408   for (;;) {
 409     ValueStack* tc = t->caller_state();
 410     if (tc == NULL)  return s;
 411     t = tc;
 412     bci_result = tc->bci();
 413     s = s->caller_state();
 414   }
 415 }
 416 
 417 void LIR_Assembler::record_non_safepoint_debug_info() {
 418   int         pc_offset = _pending_non_safepoint_offset;
 419   ValueStack* vstack    = debug_info(_pending_non_safepoint);
 420   int         bci       = vstack->bci();
 421 
 422   DebugInformationRecorder* debug_info = compilation()->debug_info_recorder();
 423   assert(debug_info->recording_non_safepoints(), "sanity");
 424 
 425   debug_info->add_non_safepoint(pc_offset);
 426 
 427   // Visit scopes from oldest to youngest.
 428   for (int n = 0; ; n++) {
 429     int s_bci = bci;
 430     ValueStack* s = nth_oldest(vstack, n, s_bci);
 431     if (s == NULL)  break;
 432     IRScope* scope = s->scope();
 433     //Always pass false for reexecute since these ScopeDescs are never used for deopt
 434     debug_info->describe_scope(pc_offset, scope->method(), s->bci(), false/*reexecute*/);
 435   }
 436 
 437   debug_info->end_non_safepoint(pc_offset);
 438 }
 439 
 440 
 441 void LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) {
 442   add_debug_info_for_null_check(code_offset(), cinfo);
 443 }
 444 
 445 void LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) {
 446   ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo);
 447   append_code_stub(stub);
 448 }
 449 
 450 void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) {
 451   add_debug_info_for_div0(code_offset(), info);
 452 }
 453 
 454 void LIR_Assembler::add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo) {
 455   DivByZeroStub* stub = new DivByZeroStub(pc_offset, cinfo);
 456   append_code_stub(stub);
 457 }
 458 
 459 void LIR_Assembler::emit_rtcall(LIR_OpRTCall* op) {
 460   rt_call(op->result_opr(), op->addr(), op->arguments(), op->tmp(), op->info());
 461 }
 462 
 463 
 464 void LIR_Assembler::emit_call(LIR_OpJavaCall* op) {
 465   verify_oop_map(op->info());
 466 
 467   if (os::is_MP()) {
 468     // must align calls sites, otherwise they can't be updated atomically on MP hardware
 469     align_call(op->code());
 470   }
 471 
 472   // emit the static call stub stuff out of line
 473   emit_static_call_stub();
 474   CHECK_BAILOUT();
 475 
 476   switch (op->code()) {
 477   case lir_static_call:
 478   case lir_dynamic_call:
 479     call(op, relocInfo::static_call_type);
 480     break;
 481   case lir_optvirtual_call:
 482     call(op, relocInfo::opt_virtual_call_type);
 483     break;
 484   case lir_icvirtual_call:
 485     ic_call(op);
 486     break;
 487   case lir_virtual_call:
 488     vtable_call(op);
 489     break;
 490   default:
 491     fatal(err_msg_res("unexpected op code: %s", op->name()));
 492     break;
 493   }
 494 
 495   // JSR 292
 496   // Record if this method has MethodHandle invokes.
 497   if (op->is_method_handle_invoke()) {
 498     compilation()->set_has_method_handle_invokes(true);
 499   }
 500 
 501 #if defined(X86) && defined(TIERED)
 502   // C2 leave fpu stack dirty clean it
 503   if (UseSSE < 2) {
 504     int i;
 505     for ( i = 1; i <= 7 ; i++ ) {
 506       ffree(i);
 507     }
 508     if (!op->result_opr()->is_float_kind()) {
 509       ffree(0);
 510     }
 511   }
 512 #endif // X86 && TIERED
 513 }
 514 
 515 
 516 void LIR_Assembler::emit_opLabel(LIR_OpLabel* op) {
 517   _masm->bind (*(op->label()));
 518 }
 519 
 520 
 521 void LIR_Assembler::emit_op1(LIR_Op1* op) {
 522   switch (op->code()) {
 523     case lir_move:
 524       if (op->move_kind() == lir_move_volatile) {
 525         assert(op->patch_code() == lir_patch_none, "can't patch volatiles");
 526         volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info());
 527       } else {
 528         move_op(op->in_opr(), op->result_opr(), op->type(),
 529                 op->patch_code(), op->info(), op->pop_fpu_stack(),
 530                 op->move_kind() == lir_move_unaligned,
 531                 op->move_kind() == lir_move_wide);
 532       }
 533       break;
 534 
 535     case lir_prefetchr:
 536       prefetchr(op->in_opr());
 537       break;
 538 
 539     case lir_prefetchw:
 540       prefetchw(op->in_opr());
 541       break;
 542 
 543     case lir_roundfp: {
 544       LIR_OpRoundFP* round_op = op->as_OpRoundFP();
 545       roundfp_op(round_op->in_opr(), round_op->tmp(), round_op->result_opr(), round_op->pop_fpu_stack());
 546       break;
 547     }
 548 
 549     case lir_return:
 550       return_op(op->in_opr());
 551       break;
 552 
 553     case lir_safepoint:
 554       if (compilation()->debug_info_recorder()->last_pc_offset() == code_offset()) {
 555         _masm->nop();
 556       }
 557       safepoint_poll(op->in_opr(), op->info());
 558       break;
 559 
 560     case lir_fxch:
 561       fxch(op->in_opr()->as_jint());
 562       break;
 563 
 564     case lir_fld:
 565       fld(op->in_opr()->as_jint());
 566       break;
 567 
 568     case lir_ffree:
 569       ffree(op->in_opr()->as_jint());
 570       break;
 571 
 572     case lir_branch:
 573       break;
 574 
 575     case lir_push:
 576       push(op->in_opr());
 577       break;
 578 
 579     case lir_pop:
 580       pop(op->in_opr());
 581       break;
 582 
 583     case lir_neg:
 584       negate(op->in_opr(), op->result_opr());
 585       break;
 586 
 587     case lir_leal:
 588       leal(op->in_opr(), op->result_opr());
 589       break;
 590 
 591     case lir_null_check:
 592       if (GenerateCompilerNullChecks) {
 593         add_debug_info_for_null_check_here(op->info());
 594 
 595         if (op->in_opr()->is_single_cpu()) {
 596           _masm->null_check(op->in_opr()->as_register());
 597         } else {
 598           Unimplemented();
 599         }
 600       }
 601       break;
 602 
 603     case lir_monaddr:
 604       monitor_address(op->in_opr()->as_constant_ptr()->as_jint(), op->result_opr());
 605       break;
 606 
 607 #ifdef SPARC
 608     case lir_pack64:
 609       pack64(op->in_opr(), op->result_opr());
 610       break;
 611 
 612     case lir_unpack64:
 613       unpack64(op->in_opr(), op->result_opr());
 614       break;
 615 #endif
 616 
 617     case lir_unwind:
 618       unwind_op(op->in_opr());
 619       break;
 620 
 621     default:
 622       Unimplemented();
 623       break;
 624   }
 625 }
 626 
 627 
 628 void LIR_Assembler::emit_op0(LIR_Op0* op) {
 629   switch (op->code()) {
 630     case lir_word_align: {
 631       while (code_offset() % BytesPerWord != 0) {
 632         _masm->nop();
 633       }
 634       break;
 635     }
 636 
 637     case lir_nop:
 638       assert(op->info() == NULL, "not supported");
 639       _masm->nop();
 640       break;
 641 
 642     case lir_label:
 643       Unimplemented();
 644       break;
 645 
 646     case lir_build_frame:
 647       build_frame();
 648       break;
 649 
 650     case lir_std_entry:
 651       // init offsets
 652       offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
 653       _masm->align(CodeEntryAlignment);
 654       if (needs_icache(compilation()->method())) {
 655         check_icache();
 656       }
 657       offsets()->set_value(CodeOffsets::Verified_Entry, _masm->offset());
 658       _masm->verified_entry();
 659       build_frame();
 660       offsets()->set_value(CodeOffsets::Frame_Complete, _masm->offset());
 661       break;
 662 
 663     case lir_osr_entry:
 664       offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
 665       osr_entry();
 666       break;
 667 
 668     case lir_24bit_FPU:
 669       set_24bit_FPU();
 670       break;
 671 
 672     case lir_reset_FPU:
 673       reset_FPU();
 674       break;
 675 
 676     case lir_breakpoint:
 677       breakpoint();
 678       break;
 679 
 680     case lir_fpop_raw:
 681       fpop();
 682       break;
 683 
 684     case lir_membar:
 685       membar();
 686       break;
 687 
 688     case lir_membar_acquire:
 689       membar_acquire();
 690       break;
 691 
 692     case lir_membar_release:
 693       membar_release();
 694       break;
 695 
 696     case lir_membar_loadload:
 697       membar_loadload();
 698       break;
 699 
 700     case lir_membar_storestore:
 701       membar_storestore();
 702       break;
 703 
 704     case lir_membar_loadstore:
 705       membar_loadstore();
 706       break;
 707 
 708     case lir_membar_storeload:
 709       membar_storeload();
 710       break;
 711 
 712     case lir_get_thread:
 713       get_thread(op->result_opr());
 714       break;
 715 
 716     default:
 717       ShouldNotReachHere();
 718       break;
 719   }
 720 }
 721 
 722 
 723 void LIR_Assembler::emit_op2(LIR_Op2* op) {
 724   switch (op->code()) {
 725     case lir_cmp:
 726       if (op->info() != NULL) {
 727         assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(),
 728                "shouldn't be codeemitinfo for non-address operands");
 729         add_debug_info_for_null_check_here(op->info()); // exception possible
 730       }
 731       comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
 732       break;
 733 
 734     case lir_cmp_l2i:
 735     case lir_cmp_fd2i:
 736     case lir_ucmp_fd2i:
 737       comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
 738       break;
 739 
 740     case lir_cmove:
 741       cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type());
 742       break;
 743 
 744     case lir_shl:
 745     case lir_shr:
 746     case lir_ushr:
 747       if (op->in_opr2()->is_constant()) {
 748         shift_op(op->code(), op->in_opr1(), op->in_opr2()->as_constant_ptr()->as_jint(), op->result_opr());
 749       } else {
 750         shift_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
 751       }
 752       break;
 753 
 754     case lir_add:
 755     case lir_sub:
 756     case lir_mul:
 757     case lir_mul_strictfp:
 758     case lir_div:
 759     case lir_div_strictfp:
 760     case lir_rem:
 761       assert(op->fpu_pop_count() < 2, "");
 762       arith_op(
 763         op->code(),
 764         op->in_opr1(),
 765         op->in_opr2(),
 766         op->result_opr(),
 767         op->info(),
 768         op->fpu_pop_count() == 1);
 769       break;
 770 
 771     case lir_abs:
 772     case lir_sqrt:
 773     case lir_sin:
 774     case lir_tan:
 775     case lir_cos:
 776     case lir_log:
 777     case lir_log10:
 778     case lir_exp:
 779     case lir_pow:
 780       intrinsic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
 781       break;
 782 
 783     case lir_logic_and:
 784     case lir_logic_or:
 785     case lir_logic_xor:
 786       logic_op(
 787         op->code(),
 788         op->in_opr1(),
 789         op->in_opr2(),
 790         op->result_opr());
 791       break;
 792 
 793     case lir_throw:
 794       throw_op(op->in_opr1(), op->in_opr2(), op->info());
 795       break;
 796 
 797     case lir_xadd:
 798     case lir_xchg:
 799       atomic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
 800       break;
 801 
 802     default:
 803       Unimplemented();
 804       break;
 805   }
 806 }
 807 
 808 
 809 void LIR_Assembler::build_frame() {
 810   _masm->build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 811 }
 812 
 813 
 814 void LIR_Assembler::roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack) {
 815   assert((src->is_single_fpu() && dest->is_single_stack()) ||
 816          (src->is_double_fpu() && dest->is_double_stack()),
 817          "round_fp: rounds register -> stack location");
 818 
 819   reg2stack (src, dest, src->type(), pop_fpu_stack);
 820 }
 821 
 822 
 823 void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide) {
 824   if (src->is_register()) {
 825     if (dest->is_register()) {
 826       assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
 827       reg2reg(src,  dest);
 828     } else if (dest->is_stack()) {
 829       assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
 830       reg2stack(src, dest, type, pop_fpu_stack);
 831     } else if (dest->is_address()) {
 832       reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, wide, unaligned);
 833     } else {
 834       ShouldNotReachHere();
 835     }
 836 
 837   } else if (src->is_stack()) {
 838     assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
 839     if (dest->is_register()) {
 840       stack2reg(src, dest, type);
 841     } else if (dest->is_stack()) {
 842       stack2stack(src, dest, type);
 843     } else {
 844       ShouldNotReachHere();
 845     }
 846 
 847   } else if (src->is_constant()) {
 848     if (dest->is_register()) {
 849       const2reg(src, dest, patch_code, info); // patching is possible
 850     } else if (dest->is_stack()) {
 851       assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
 852       const2stack(src, dest);
 853     } else if (dest->is_address()) {
 854       assert(patch_code == lir_patch_none, "no patching allowed here");
 855       const2mem(src, dest, type, info, wide);
 856     } else {
 857       ShouldNotReachHere();
 858     }
 859 
 860   } else if (src->is_address()) {
 861     mem2reg(src, dest, type, patch_code, info, wide, unaligned);
 862 
 863   } else {
 864     ShouldNotReachHere();
 865   }
 866 }
 867 
 868 
 869 void LIR_Assembler::verify_oop_map(CodeEmitInfo* info) {
 870 #ifndef PRODUCT
 871   if (VerifyOops) {
 872     OopMapStream s(info->oop_map());
 873     while (!s.is_done()) {
 874       OopMapValue v = s.current();
 875       if (v.is_oop()) {
 876         VMReg r = v.reg();
 877         if (!r->is_stack()) {
 878           stringStream st;
 879           st.print("bad oop %s at %d", r->as_Register()->name(), _masm->offset());
 880 #ifdef SPARC
 881           _masm->_verify_oop(r->as_Register(), strdup(st.as_string()), __FILE__, __LINE__);
 882 #else
 883           _masm->verify_oop(r->as_Register());
 884 #endif
 885         } else {
 886           _masm->verify_stack_oop(r->reg2stack() * VMRegImpl::stack_slot_size);
 887         }
 888       }
 889       check_codespace();
 890       CHECK_BAILOUT();
 891 
 892       s.next();
 893     }
 894   }
 895 #endif
 896 }