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src/share/vm/c1/c1_LinearScan.cpp

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*** 45,54 **** --- 45,58 ---- # include "vmreg_arm.inline.hpp" #endif #ifdef TARGET_ARCH_ppc # include "vmreg_ppc.inline.hpp" #endif + #ifdef TARGET_ARCH_aarch32 + # include "vmreg_aarch32.inline.hpp" + # include "vm_version_aarch32.hpp" + #endif #ifndef PRODUCT static LinearScanStatistic _stat_before_alloc;
*** 191,216 **** bool LinearScan::is_precolored_cpu_interval(const Interval* i) { return i->reg_num() < LinearScan::nof_cpu_regs; } bool LinearScan::is_virtual_cpu_interval(const Interval* i) { ! #if defined(__SOFTFP__) || defined(E500V2) return i->reg_num() >= LIR_OprDesc::vreg_base; #else ! return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE); #endif // __SOFTFP__ or E500V2 } bool LinearScan::is_precolored_fpu_interval(const Interval* i) { return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs; } bool LinearScan::is_virtual_fpu_interval(const Interval* i) { ! #if defined(__SOFTFP__) || defined(E500V2) return false; #else ! return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE); #endif // __SOFTFP__ or E500V2 } bool LinearScan::is_in_fpu_register(const Interval* i) { // fixed intervals not needed for FPU stack allocation --- 195,220 ---- bool LinearScan::is_precolored_cpu_interval(const Interval* i) { return i->reg_num() < LinearScan::nof_cpu_regs; } bool LinearScan::is_virtual_cpu_interval(const Interval* i) { ! #if !defined(AARCH32) && (defined(__SOFTFP__) || defined(E500V2)) return i->reg_num() >= LIR_OprDesc::vreg_base; #else ! return i->reg_num() >= LIR_OprDesc::vreg_base && (AARCH32_ONLY(!hasFPU() ||) (i->type() != T_FLOAT && i->type() != T_DOUBLE)); #endif // __SOFTFP__ or E500V2 } bool LinearScan::is_precolored_fpu_interval(const Interval* i) { return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs; } bool LinearScan::is_virtual_fpu_interval(const Interval* i) { ! #if !defined(AARCH32) && (defined(__SOFTFP__) || defined(E500V2)) return false; #else ! return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE) AARCH32_ONLY(&& hasFPU()); #endif // __SOFTFP__ or E500V2 } bool LinearScan::is_in_fpu_register(const Interval* i) { // fixed intervals not needed for FPU stack allocation
*** 2072,2091 **** return LIR_OprFact::single_cpu_metadata(assigned_reg); } #ifdef __SOFTFP__ case T_FLOAT: // fall through ! #endif // __SOFTFP__ case T_INT: { assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); assert(interval->assigned_regHi() == any_reg, "must not have hi register"); return LIR_OprFact::single_cpu(assigned_reg); } #ifdef __SOFTFP__ case T_DOUBLE: // fall through ! #endif // __SOFTFP__ case T_LONG: { int assigned_regHi = interval->assigned_regHi(); assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); assert(num_physical_regs(T_LONG) == 1 || (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register"); --- 2076,2110 ---- return LIR_OprFact::single_cpu_metadata(assigned_reg); } #ifdef __SOFTFP__ case T_FLOAT: // fall through ! #if defined(AARCH32) ! if(hasFPU()) { ! assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); ! assert(interval->assigned_regHi() == any_reg, "must not have hi register"); ! return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg); ! } ! #endif ! #endif case T_INT: { assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); assert(interval->assigned_regHi() == any_reg, "must not have hi register"); return LIR_OprFact::single_cpu(assigned_reg); } #ifdef __SOFTFP__ case T_DOUBLE: // fall through ! #if defined(AARCH32) ! if(hasFPU()) { ! assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); ! assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); ! assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); ! return LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg); ! } ! #endif ! #endif case T_LONG: { int assigned_regHi = interval->assigned_regHi(); assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); assert(num_physical_regs(T_LONG) == 1 || (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
*** 2136,2146 **** #ifdef SPARC assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg); ! #elif defined(ARM32) assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg); #else --- 2155,2165 ---- #ifdef SPARC assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg); ! #elif defined(ARM32) || defined(AARCH32) assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg); #else
*** 2725,2737 **** assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)"); #endif #ifdef SPARC assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)"); #endif ! #ifdef ARM32 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)"); ! #endif #ifdef PPC assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); #endif #ifdef VM_LITTLE_ENDIAN --- 2744,2756 ---- assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)"); #endif #ifdef SPARC assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)"); #endif ! #if defined(ARM32) || defined(AARCH32) assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)"); ! #endif // ARM32 || AARCH32 #ifdef PPC assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); #endif #ifdef VM_LITTLE_ENDIAN
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