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src/share/vm/utilities/globalDefinitions.hpp

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 417   NoRTM      = 0x2, // Don't use RTM
 418   UseRTM     = 0x1, // Use RTM
 419   ProfileRTM = 0x0  // Use RTM with abort ratio calculation
 420 };
 421 
 422 #ifdef TARGET_ARCH_x86
 423 # include "globalDefinitions_x86.hpp"
 424 #endif
 425 #ifdef TARGET_ARCH_sparc
 426 # include "globalDefinitions_sparc.hpp"
 427 #endif
 428 #ifdef TARGET_ARCH_zero
 429 # include "globalDefinitions_zero.hpp"
 430 #endif
 431 #ifdef TARGET_ARCH_arm
 432 # include "globalDefinitions_arm.hpp"
 433 #endif
 434 #ifdef TARGET_ARCH_ppc
 435 # include "globalDefinitions_ppc.hpp"
 436 #endif



 437 
 438 /*
 439  * If a platform does not support native stack walking
 440  * the platform specific globalDefinitions (above)
 441  * can set PLATFORM_NATIVE_STACK_WALKING_SUPPORTED to 0
 442  */
 443 #ifndef PLATFORM_NATIVE_STACK_WALKING_SUPPORTED
 444 #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1
 445 #endif
 446 
 447 // To assure the IRIW property on processors that are not multiple copy
 448 // atomic, sync instructions must be issued between volatile reads to
 449 // assure their ordering, instead of after volatile stores.
 450 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
 451 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
 452 #ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC
 453 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true;
 454 #else
 455 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
 456 #endif




 417   NoRTM      = 0x2, // Don't use RTM
 418   UseRTM     = 0x1, // Use RTM
 419   ProfileRTM = 0x0  // Use RTM with abort ratio calculation
 420 };
 421 
 422 #ifdef TARGET_ARCH_x86
 423 # include "globalDefinitions_x86.hpp"
 424 #endif
 425 #ifdef TARGET_ARCH_sparc
 426 # include "globalDefinitions_sparc.hpp"
 427 #endif
 428 #ifdef TARGET_ARCH_zero
 429 # include "globalDefinitions_zero.hpp"
 430 #endif
 431 #ifdef TARGET_ARCH_arm
 432 # include "globalDefinitions_arm.hpp"
 433 #endif
 434 #ifdef TARGET_ARCH_ppc
 435 # include "globalDefinitions_ppc.hpp"
 436 #endif
 437 #ifdef TARGET_ARCH_aarch32
 438 # include "globalDefinitions_aarch32.hpp"
 439 #endif
 440 
 441 /*
 442  * If a platform does not support native stack walking
 443  * the platform specific globalDefinitions (above)
 444  * can set PLATFORM_NATIVE_STACK_WALKING_SUPPORTED to 0
 445  */
 446 #ifndef PLATFORM_NATIVE_STACK_WALKING_SUPPORTED
 447 #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1
 448 #endif
 449 
 450 // To assure the IRIW property on processors that are not multiple copy
 451 // atomic, sync instructions must be issued between volatile reads to
 452 // assure their ordering, instead of after volatile stores.
 453 // (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models"
 454 // by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge)
 455 #ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC
 456 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true;
 457 #else
 458 const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false;
 459 #endif


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