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src/cpu/aarch64/vm/macroAssembler_aarch64.cpp

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*** 1,7 **** /* - /* * Copyright (c) 2013, Red Hat Inc. * Copyright (c) 1997, 2012, Oracle and/or its affiliates. * All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * --- 1,6 ----
*** 31,40 **** --- 30,40 ---- #include "asm/assembler.hpp" #include "asm/assembler.inline.hpp" #include "interpreter/interpreter.hpp" #include "compiler/disassembler.hpp" + #include "gc_interface/collectedHeap.inline.hpp" #include "memory/resourceArea.hpp" #include "runtime/biasedLocking.hpp" #include "runtime/interfaceSupport.hpp" #include "runtime/sharedRuntime.hpp"
*** 51,60 **** --- 51,61 ---- #if INCLUDE_ALL_GCS #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" #include "gc_implementation/g1/heapRegion.hpp" + #include "shenandoahBarrierSetAssembler_aarch64.hpp" #endif #ifdef COMPILER2 #include "opto/node.hpp" #include "opto/compile.hpp"
*** 1642,1651 **** --- 1643,1658 ---- movkw(dst, imm_h[1], 16); } } } + void MacroAssembler::mov(Register dst, address addr) { + assert(Universe::heap() == NULL + || !Universe::heap()->is_in(addr), "use movptr for oop pointers"); + mov_immediate64(dst, (uintptr_t)addr); + } + // Form an address from base + offset in Rd. Rd may or may // not actually be used: you must use the Address that is returned. // It is up to you to ensure that the shift provided matches the size // of your data. Address MacroAssembler::form_address(Register Rd, Register base, long byte_offset, int shift) {
*** 2365,2394 **** msg); assert(false, err_msg("DEBUG MESSAGE: %s", msg)); } } ! void MacroAssembler::push_call_clobbered_registers() { ! push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); ! // Push v0-v7, v16-v31. for (int i = 30; i >= 0; i -= 2) { if (i <= v7->encoding() || i >= v16->encoding()) { stpd(as_FloatRegister(i), as_FloatRegister(i+1), Address(pre(sp, -2 * wordSize))); } } } ! void MacroAssembler::pop_call_clobbered_registers() { for (int i = 0; i < 32; i += 2) { if (i <= v7->encoding() || i >= v16->encoding()) { ldpd(as_FloatRegister(i), as_FloatRegister(i+1), Address(post(sp, 2 * wordSize))); } } pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); } void MacroAssembler::push_CPU_state(bool save_vectors) { --- 2372,2410 ---- msg); assert(false, err_msg("DEBUG MESSAGE: %s", msg)); } } ! void MacroAssembler::push_call_clobbered_fp_registers() { // Push v0-v7, v16-v31. for (int i = 30; i >= 0; i -= 2) { if (i <= v7->encoding() || i >= v16->encoding()) { stpd(as_FloatRegister(i), as_FloatRegister(i+1), Address(pre(sp, -2 * wordSize))); } } } ! void MacroAssembler::pop_call_clobbered_fp_registers() { for (int i = 0; i < 32; i += 2) { if (i <= v7->encoding() || i >= v16->encoding()) { ldpd(as_FloatRegister(i), as_FloatRegister(i+1), Address(post(sp, 2 * wordSize))); } } + } + + void MacroAssembler::push_call_clobbered_registers() { + push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); + + push_call_clobbered_fp_registers(); + } + + void MacroAssembler::pop_call_clobbered_registers() { + + pop_call_clobbered_fp_registers(); pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2), sp); } void MacroAssembler::push_CPU_state(bool save_vectors) {
*** 3459,3478 **** --- 3475,3508 ---- movk(dst, nk & 0xffff); } void MacroAssembler::load_heap_oop(Register dst, Address src) { + #if INCLUDE_ALL_GCS + if (UseShenandoahGC) { + ShenandoahBarrierSetAssembler::bsasm()->load_heap_oop(this, dst, src); + return; + } + #endif + if (UseCompressedOops) { ldrw(dst, src); decode_heap_oop(dst); } else { ldr(dst, src); } } void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { + #if INCLUDE_ALL_GCS + if (UseShenandoahGC) { + ShenandoahBarrierSetAssembler::bsasm()->load_heap_oop(this, dst, src); + return; + } + #endif + if (UseCompressedOops) { ldrw(dst, src); decode_heap_oop_not_null(dst); } else { ldr(dst, src);
*** 3612,3621 **** --- 3642,3658 ---- assert_different_registers(store_addr, new_val, thread, tmp, tmp2, rscratch1); assert(store_addr != noreg && new_val != noreg && tmp != noreg && tmp2 != noreg, "expecting a register"); + if (UseShenandoahGC) { + // No need for this in Shenandoah. + return; + } + + assert(UseG1GC, "expect G1 GC"); + Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_index())); Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + PtrQueue::byte_offset_of_buf()));
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