666 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
667 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
668 default: ShouldNotReachHere();
669 };
670
671 // sparc has different condition codes for testing 32-bit
672 // vs. 64-bit values. We could always test xcc is we could
673 // guarantee that 32-bit loads always sign extended but that isn't
674 // true and since sign extension isn't free, it would impose a
675 // slight cost.
676 #ifdef _LP64
677 if (op->type() == T_INT) {
678 __ br(acond, false, Assembler::pn, *(op->label()));
679 } else
680 #endif
681 __ brx(acond, false, Assembler::pn, *(op->label()));
682 }
683 // The peephole pass fills the delay slot
684 }
685
686
687 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
688 Bytecodes::Code code = op->bytecode();
689 LIR_Opr dst = op->result_opr();
690
691 switch(code) {
692 case Bytecodes::_i2l: {
693 Register rlo = dst->as_register_lo();
694 Register rhi = dst->as_register_hi();
695 Register rval = op->in_opr()->as_register();
696 #ifdef _LP64
697 __ sra(rval, 0, rlo);
698 #else
699 __ mov(rval, rlo);
700 __ sra(rval, BitsPerInt-1, rhi);
701 #endif
702 break;
703 }
704 case Bytecodes::_i2d:
705 case Bytecodes::_i2f: {
3466 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3467 Register rs = src->as_register();
3468 Register rd = dst->as_register_lo();
3469 __ sllx(rs, 32, rs);
3470 __ srl(rs->successor(), 0, rs->successor());
3471 __ or3(rs, rs->successor(), rd);
3472 }
3473
3474 // Unpack a 64 bit value in a register into
3475 // two sequential registers.
3476 // src is unpacked into dst and dst->successor()
3477 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3478 Register rs = src->as_register_lo();
3479 Register rd = dst->as_register_hi();
3480 assert_different_registers(rs, rd, rd->successor());
3481 __ srlx(rs, 32, rd);
3482 __ srl (rs, 0, rd->successor());
3483 }
3484
3485
3486 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3487 LIR_Address* addr = addr_opr->as_address_ptr();
3488 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3489
3490 if (Assembler::is_simm13(addr->disp())) {
3491 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3492 } else {
3493 __ set(addr->disp(), G3_scratch);
3494 __ add(addr->base()->as_pointer_register(), G3_scratch, dest->as_pointer_register());
3495 }
3496 }
3497
3498
3499 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3500 assert(result_reg->is_register(), "check");
3501 __ mov(G2_thread, result_reg->as_register());
3502 }
3503
3504 #ifdef ASSERT
3505 // emit run-time assertion
3506 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
|
666 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
667 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
668 default: ShouldNotReachHere();
669 };
670
671 // sparc has different condition codes for testing 32-bit
672 // vs. 64-bit values. We could always test xcc is we could
673 // guarantee that 32-bit loads always sign extended but that isn't
674 // true and since sign extension isn't free, it would impose a
675 // slight cost.
676 #ifdef _LP64
677 if (op->type() == T_INT) {
678 __ br(acond, false, Assembler::pn, *(op->label()));
679 } else
680 #endif
681 __ brx(acond, false, Assembler::pn, *(op->label()));
682 }
683 // The peephole pass fills the delay slot
684 }
685
686 void LIR_Assembler::emit_opShenandoahWriteBarrier(LIR_OpShenandoahWriteBarrier* op) {
687 Unimplemented();
688 }
689
690 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
691 Bytecodes::Code code = op->bytecode();
692 LIR_Opr dst = op->result_opr();
693
694 switch(code) {
695 case Bytecodes::_i2l: {
696 Register rlo = dst->as_register_lo();
697 Register rhi = dst->as_register_hi();
698 Register rval = op->in_opr()->as_register();
699 #ifdef _LP64
700 __ sra(rval, 0, rlo);
701 #else
702 __ mov(rval, rlo);
703 __ sra(rval, BitsPerInt-1, rhi);
704 #endif
705 break;
706 }
707 case Bytecodes::_i2d:
708 case Bytecodes::_i2f: {
3469 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) {
3470 Register rs = src->as_register();
3471 Register rd = dst->as_register_lo();
3472 __ sllx(rs, 32, rs);
3473 __ srl(rs->successor(), 0, rs->successor());
3474 __ or3(rs, rs->successor(), rd);
3475 }
3476
3477 // Unpack a 64 bit value in a register into
3478 // two sequential registers.
3479 // src is unpacked into dst and dst->successor()
3480 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) {
3481 Register rs = src->as_register_lo();
3482 Register rd = dst->as_register_hi();
3483 assert_different_registers(rs, rd, rd->successor());
3484 __ srlx(rs, 32, rd);
3485 __ srl (rs, 0, rd->successor());
3486 }
3487
3488
3489 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3490 LIR_Address* addr = addr_opr->as_address_ptr();
3491 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet");
3492
3493 if (Assembler::is_simm13(addr->disp())) {
3494 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register());
3495 } else {
3496 __ set(addr->disp(), G3_scratch);
3497 __ add(addr->base()->as_pointer_register(), G3_scratch, dest->as_pointer_register());
3498 }
3499 }
3500
3501
3502 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3503 assert(result_reg->is_register(), "check");
3504 __ mov(G2_thread, result_reg->as_register());
3505 }
3506
3507 #ifdef ASSERT
3508 // emit run-time assertion
3509 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
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