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src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp

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 661       case lir_cond_aboveEqual:   acond = Assembler::greaterEqualUnsigned; break;
 662       case lir_cond_belowEqual:   acond = Assembler::lessEqualUnsigned;    break;
 663       default:                         ShouldNotReachHere();
 664     };
 665 
 666     // sparc has different condition codes for testing 32-bit
 667     // vs. 64-bit values.  We could always test xcc is we could
 668     // guarantee that 32-bit loads always sign extended but that isn't
 669     // true and since sign extension isn't free, it would impose a
 670     // slight cost.
 671 #ifdef _LP64
 672     if  (op->type() == T_INT) {
 673       __ br(acond, false, Assembler::pn, *(op->label()));
 674     } else
 675 #endif
 676       __ brx(acond, false, Assembler::pn, *(op->label()));
 677   }
 678   // The peephole pass fills the delay slot
 679 }
 680 



 681 
 682 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 683   Bytecodes::Code code = op->bytecode();
 684   LIR_Opr dst = op->result_opr();
 685 
 686   switch(code) {
 687     case Bytecodes::_i2l: {
 688       Register rlo  = dst->as_register_lo();
 689       Register rhi  = dst->as_register_hi();
 690       Register rval = op->in_opr()->as_register();
 691 #ifdef _LP64
 692       __ sra(rval, 0, rlo);
 693 #else
 694       __ mov(rval, rlo);
 695       __ sra(rval, BitsPerInt-1, rhi);
 696 #endif
 697       break;
 698     }
 699     case Bytecodes::_i2d:
 700     case Bytecodes::_i2f: {




 661       case lir_cond_aboveEqual:   acond = Assembler::greaterEqualUnsigned; break;
 662       case lir_cond_belowEqual:   acond = Assembler::lessEqualUnsigned;    break;
 663       default:                         ShouldNotReachHere();
 664     };
 665 
 666     // sparc has different condition codes for testing 32-bit
 667     // vs. 64-bit values.  We could always test xcc is we could
 668     // guarantee that 32-bit loads always sign extended but that isn't
 669     // true and since sign extension isn't free, it would impose a
 670     // slight cost.
 671 #ifdef _LP64
 672     if  (op->type() == T_INT) {
 673       __ br(acond, false, Assembler::pn, *(op->label()));
 674     } else
 675 #endif
 676       __ brx(acond, false, Assembler::pn, *(op->label()));
 677   }
 678   // The peephole pass fills the delay slot
 679 }
 680 
 681 void LIR_Assembler::emit_opShenandoahWriteBarrier(LIR_OpShenandoahWriteBarrier* op) {
 682   Unimplemented();
 683 }
 684 
 685 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 686   Bytecodes::Code code = op->bytecode();
 687   LIR_Opr dst = op->result_opr();
 688 
 689   switch(code) {
 690     case Bytecodes::_i2l: {
 691       Register rlo  = dst->as_register_lo();
 692       Register rhi  = dst->as_register_hi();
 693       Register rval = op->in_opr()->as_register();
 694 #ifdef _LP64
 695       __ sra(rval, 0, rlo);
 696 #else
 697       __ mov(rval, rlo);
 698       __ sra(rval, BitsPerInt-1, rhi);
 699 #endif
 700       break;
 701     }
 702     case Bytecodes::_i2d:
 703     case Bytecodes::_i2f: {


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