666 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
667 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
668 default: ShouldNotReachHere();
669 };
670
671 // sparc has different condition codes for testing 32-bit
672 // vs. 64-bit values. We could always test xcc is we could
673 // guarantee that 32-bit loads always sign extended but that isn't
674 // true and since sign extension isn't free, it would impose a
675 // slight cost.
676 #ifdef _LP64
677 if (op->type() == T_INT) {
678 __ br(acond, false, Assembler::pn, *(op->label()));
679 } else
680 #endif
681 __ brx(acond, false, Assembler::pn, *(op->label()));
682 }
683 // The peephole pass fills the delay slot
684 }
685
686
687 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
688 Bytecodes::Code code = op->bytecode();
689 LIR_Opr dst = op->result_opr();
690
691 switch(code) {
692 case Bytecodes::_i2l: {
693 Register rlo = dst->as_register_lo();
694 Register rhi = dst->as_register_hi();
695 Register rval = op->in_opr()->as_register();
696 #ifdef _LP64
697 __ sra(rval, 0, rlo);
698 #else
699 __ mov(rval, rlo);
700 __ sra(rval, BitsPerInt-1, rhi);
701 #endif
702 break;
703 }
704 case Bytecodes::_i2d:
705 case Bytecodes::_i2f: {
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666 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
667 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
668 default: ShouldNotReachHere();
669 };
670
671 // sparc has different condition codes for testing 32-bit
672 // vs. 64-bit values. We could always test xcc is we could
673 // guarantee that 32-bit loads always sign extended but that isn't
674 // true and since sign extension isn't free, it would impose a
675 // slight cost.
676 #ifdef _LP64
677 if (op->type() == T_INT) {
678 __ br(acond, false, Assembler::pn, *(op->label()));
679 } else
680 #endif
681 __ brx(acond, false, Assembler::pn, *(op->label()));
682 }
683 // The peephole pass fills the delay slot
684 }
685
686 void LIR_Assembler::emit_opShenandoahWriteBarrier(LIR_OpShenandoahWriteBarrier* op) {
687 Unimplemented();
688 }
689
690 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
691 Bytecodes::Code code = op->bytecode();
692 LIR_Opr dst = op->result_opr();
693
694 switch(code) {
695 case Bytecodes::_i2l: {
696 Register rlo = dst->as_register_lo();
697 Register rhi = dst->as_register_hi();
698 Register rval = op->in_opr()->as_register();
699 #ifdef _LP64
700 __ sra(rval, 0, rlo);
701 #else
702 __ mov(rval, rlo);
703 __ sra(rval, BitsPerInt-1, rhi);
704 #endif
705 break;
706 }
707 case Bytecodes::_i2d:
708 case Bytecodes::_i2f: {
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