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src/cpu/x86/vm/c1_LIRGenerator_x86.cpp

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*** 41,50 **** --- 41,54 ---- #define __ gen()->lir(__FILE__, __LINE__)-> #else #define __ gen()->lir()-> #endif + #if INCLUDE_ALL_GCS + #include "gc_implementation/shenandoah/shenandoahBarrierSetC1.hpp" + #endif + // Item will be loaded into a byte register; Intel only void LIRItem::load_byte_item() { load_item(); LIR_Opr res = result();
*** 784,795 **** pre_barrier(addr, LIR_OprFact::illegalOpr /* pre_val */, true /* do_load */, false /* patch */, NULL); } LIR_Opr ill = LIR_OprFact::illegalOpr; // for convenience ! if (type == objectType) __ cas_obj(addr, cmp.result(), val.result(), ill, ill); else if (type == intType) __ cas_int(addr, cmp.result(), val.result(), ill, ill); else if (type == longType) __ cas_long(addr, cmp.result(), val.result(), ill, ill); else { --- 788,807 ---- pre_barrier(addr, LIR_OprFact::illegalOpr /* pre_val */, true /* do_load */, false /* patch */, NULL); } LIR_Opr ill = LIR_OprFact::illegalOpr; // for convenience ! if (type == objectType) { ! #if INCLUDE_ALL_GCS ! if (UseShenandoahGC) { ! __ cas_obj(addr, cmp.result(), val.result(), new_register(T_OBJECT), new_register(T_OBJECT)); ! } else ! #endif ! { __ cas_obj(addr, cmp.result(), val.result(), ill, ill); + } + } else if (type == intType) __ cas_int(addr, cmp.result(), val.result(), ill, ill); else if (type == longType) __ cas_long(addr, cmp.result(), val.result(), ill, ill); else {
*** 1483,1492 **** --- 1495,1514 ---- // Do the pre-write barrier, if any. pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */, true /* do_load */, false /* patch */, NULL); } __ xchg(LIR_OprFact::address(addr), dst, dst, LIR_OprFact::illegalOpr); + + #if INCLUDE_ALL_GCS + if (UseShenandoahGC && is_obj) { + dst = ShenandoahBarrierSet::barrier_set()->bsc1()->load_reference_barrier(this, dst, NULL, true); + LIR_Opr tmp = new_register(type); + __ move(dst, tmp); + dst = tmp; + } + #endif + if (is_obj) { // Seems to be a precise address post_barrier(LIR_OprFact::address(addr), data); } }
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