26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_FrameMap.hpp"
28 #include "c1/c1_Instruction.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_LIRGenerator.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArray.hpp"
34 #include "ci/ciObjArrayKlass.hpp"
35 #include "ci/ciTypeArrayKlass.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "vmreg_x86.inline.hpp"
39
40 #ifdef ASSERT
41 #define __ gen()->lir(__FILE__, __LINE__)->
42 #else
43 #define __ gen()->lir()->
44 #endif
45
46 // Item will be loaded into a byte register; Intel only
47 void LIRItem::load_byte_item() {
48 load_item();
49 LIR_Opr res = result();
50
51 if (!res->is_virtual() || !_gen->is_vreg_flag_set(res, LIRGenerator::byte_reg)) {
52 // make sure that it is a byte register
53 assert(!value()->type()->is_float() && !value()->type()->is_double(),
54 "can't load floats in byte register");
55 LIR_Opr reg = _gen->rlock_byte(T_BYTE);
56 __ move(res, reg);
57
58 _result = reg;
59 }
60 }
61
62
63 void LIRItem::load_nonconstant() {
64 LIR_Opr r = value()->operand();
65 if (r->is_constant()) {
769 a = new LIR_Address(obj.result(),
770 offset.result()->as_jint(),
771 as_BasicType(type));
772 #endif
773 } else {
774 a = new LIR_Address(obj.result(),
775 offset.result(),
776 LIR_Address::times_1,
777 0,
778 as_BasicType(type));
779 }
780 __ leal(LIR_OprFact::address(a), addr);
781
782 if (type == objectType) { // Write-barrier needed for Object fields.
783 // Do the pre-write barrier, if any.
784 pre_barrier(addr, LIR_OprFact::illegalOpr /* pre_val */,
785 true /* do_load */, false /* patch */, NULL);
786 }
787
788 LIR_Opr ill = LIR_OprFact::illegalOpr; // for convenience
789 if (type == objectType)
790 __ cas_obj(addr, cmp.result(), val.result(), ill, ill);
791 else if (type == intType)
792 __ cas_int(addr, cmp.result(), val.result(), ill, ill);
793 else if (type == longType)
794 __ cas_long(addr, cmp.result(), val.result(), ill, ill);
795 else {
796 ShouldNotReachHere();
797 }
798
799 // generate conditional move of boolean result
800 LIR_Opr result = rlock_result(x);
801 __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
802 result, as_BasicType(type));
803 if (type == objectType) { // Write-barrier needed for Object fields.
804 // Seems to be precise
805 post_barrier(addr, val.result());
806 }
807 }
808
809
810 void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
1468 }
1469 #else
1470 addr = new LIR_Address(src.result(), offset->as_jint(), type);
1471 #endif
1472 } else {
1473 addr = new LIR_Address(src.result(), offset, type);
1474 }
1475
1476 // Because we want a 2-arg form of xchg and xadd
1477 __ move(data, dst);
1478
1479 if (x->is_add()) {
1480 __ xadd(LIR_OprFact::address(addr), dst, dst, LIR_OprFact::illegalOpr);
1481 } else {
1482 if (is_obj) {
1483 // Do the pre-write barrier, if any.
1484 pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */,
1485 true /* do_load */, false /* patch */, NULL);
1486 }
1487 __ xchg(LIR_OprFact::address(addr), dst, dst, LIR_OprFact::illegalOpr);
1488 if (is_obj) {
1489 // Seems to be a precise address
1490 post_barrier(LIR_OprFact::address(addr), data);
1491 }
1492 }
1493 }
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26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_FrameMap.hpp"
28 #include "c1/c1_Instruction.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_LIRGenerator.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArray.hpp"
34 #include "ci/ciObjArrayKlass.hpp"
35 #include "ci/ciTypeArrayKlass.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "vmreg_x86.inline.hpp"
39
40 #ifdef ASSERT
41 #define __ gen()->lir(__FILE__, __LINE__)->
42 #else
43 #define __ gen()->lir()->
44 #endif
45
46 #if INCLUDE_ALL_GCS
47 #include "gc_implementation/shenandoah/c1/shenandoahBarrierSetC1.hpp"
48 #endif
49
50 // Item will be loaded into a byte register; Intel only
51 void LIRItem::load_byte_item() {
52 load_item();
53 LIR_Opr res = result();
54
55 if (!res->is_virtual() || !_gen->is_vreg_flag_set(res, LIRGenerator::byte_reg)) {
56 // make sure that it is a byte register
57 assert(!value()->type()->is_float() && !value()->type()->is_double(),
58 "can't load floats in byte register");
59 LIR_Opr reg = _gen->rlock_byte(T_BYTE);
60 __ move(res, reg);
61
62 _result = reg;
63 }
64 }
65
66
67 void LIRItem::load_nonconstant() {
68 LIR_Opr r = value()->operand();
69 if (r->is_constant()) {
773 a = new LIR_Address(obj.result(),
774 offset.result()->as_jint(),
775 as_BasicType(type));
776 #endif
777 } else {
778 a = new LIR_Address(obj.result(),
779 offset.result(),
780 LIR_Address::times_1,
781 0,
782 as_BasicType(type));
783 }
784 __ leal(LIR_OprFact::address(a), addr);
785
786 if (type == objectType) { // Write-barrier needed for Object fields.
787 // Do the pre-write barrier, if any.
788 pre_barrier(addr, LIR_OprFact::illegalOpr /* pre_val */,
789 true /* do_load */, false /* patch */, NULL);
790 }
791
792 LIR_Opr ill = LIR_OprFact::illegalOpr; // for convenience
793 if (type == objectType) {
794 #if INCLUDE_ALL_GCS
795 if (UseShenandoahGC && ShenandoahCASBarrier) {
796 LIR_Opr result = rlock_result(x);
797 __ cas_obj(addr, cmp.result(), val.result(), new_register(T_OBJECT), new_register(T_OBJECT), result);
798 // Shenandoah C1 barrier would do all result management itself, shortcut here.
799 return;
800 } else
801 #endif
802 {
803 __ cas_obj(addr, cmp.result(), val.result(), ill, ill);
804 }
805 }
806 else if (type == intType)
807 __ cas_int(addr, cmp.result(), val.result(), ill, ill);
808 else if (type == longType)
809 __ cas_long(addr, cmp.result(), val.result(), ill, ill);
810 else {
811 ShouldNotReachHere();
812 }
813
814 // generate conditional move of boolean result
815 LIR_Opr result = rlock_result(x);
816 __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
817 result, as_BasicType(type));
818 if (type == objectType) { // Write-barrier needed for Object fields.
819 // Seems to be precise
820 post_barrier(addr, val.result());
821 }
822 }
823
824
825 void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
1483 }
1484 #else
1485 addr = new LIR_Address(src.result(), offset->as_jint(), type);
1486 #endif
1487 } else {
1488 addr = new LIR_Address(src.result(), offset, type);
1489 }
1490
1491 // Because we want a 2-arg form of xchg and xadd
1492 __ move(data, dst);
1493
1494 if (x->is_add()) {
1495 __ xadd(LIR_OprFact::address(addr), dst, dst, LIR_OprFact::illegalOpr);
1496 } else {
1497 if (is_obj) {
1498 // Do the pre-write barrier, if any.
1499 pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */,
1500 true /* do_load */, false /* patch */, NULL);
1501 }
1502 __ xchg(LIR_OprFact::address(addr), dst, dst, LIR_OprFact::illegalOpr);
1503
1504 #if INCLUDE_ALL_GCS
1505 if (UseShenandoahGC && is_obj) {
1506 LIR_Opr tmp = ShenandoahBarrierSet::barrier_set()->bsc1()->load_reference_barrier(this, dst, LIR_OprFact::addressConst(0));
1507 __ move(tmp, dst);
1508 }
1509 #endif
1510
1511 if (is_obj) {
1512 // Seems to be a precise address
1513 post_barrier(LIR_OprFact::address(addr), data);
1514 }
1515 }
1516 }
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