1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "memory/resourceArea.hpp"
  28 #include "nativeInst_x86.hpp"
  29 #include "oops/oop.inline.hpp"
  30 #include "runtime/handles.hpp"
  31 #include "runtime/sharedRuntime.hpp"
  32 #include "runtime/stubRoutines.hpp"
  33 #include "utilities/ostream.hpp"
  34 #ifdef COMPILER1
  35 #include "c1/c1_Runtime1.hpp"
  36 #endif
  37 
  38 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
  39 
  40 void NativeInstruction::wrote(int offset) {
  41   ICache::invalidate_word(addr_at(offset));
  42 }
  43 
  44 
  45 void NativeCall::verify() {
  46   // Make sure code pattern is actually a call imm32 instruction.
  47   int inst = ubyte_at(0);
  48   if (inst != instruction_code) {
  49     tty->print_cr("Addr: " INTPTR_FORMAT " Code: 0x%x", instruction_address(),
  50                                                         inst);
  51     fatal("not a call disp32");
  52   }
  53 }
  54 
  55 address NativeCall::destination() const {
  56   // Getting the destination of a call isn't safe because that call can
  57   // be getting patched while you're calling this.  There's only special
  58   // places where this can be called but not automatically verifiable by
  59   // checking which locks are held.  The solution is true atomic patching
  60   // on x86, nyi.
  61   return return_address() + displacement();
  62 }
  63 
  64 void NativeCall::print() {
  65   tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT,
  66                 instruction_address(), destination());
  67 }
  68 
  69 // Inserts a native call instruction at a given pc
  70 void NativeCall::insert(address code_pos, address entry) {
  71   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
  72 #ifdef AMD64
  73   guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
  74 #endif // AMD64
  75   *code_pos = instruction_code;
  76   *((int32_t *)(code_pos+1)) = (int32_t) disp;
  77   ICache::invalidate_range(code_pos, instruction_size);
  78 }
  79 
  80 // MT-safe patching of a call instruction.
  81 // First patches first word of instruction to two jmp's that jmps to them
  82 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
  83 // the jmp's with the first 4 byte of the new instruction.
  84 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
  85   assert(Patching_lock->is_locked() ||
  86          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
  87   assert (instr_addr != NULL, "illegal address for code patching");
  88 
  89   NativeCall* n_call =  nativeCall_at (instr_addr); // checking that it is a call
  90   if (os::is_MP()) {
  91     guarantee((intptr_t)instr_addr % BytesPerWord == 0, "must be aligned");
  92   }
  93 
  94   // First patch dummy jmp in place
  95   unsigned char patch[4];
  96   assert(sizeof(patch)==sizeof(jint), "sanity check");
  97   patch[0] = 0xEB;       // jmp rel8
  98   patch[1] = 0xFE;       // jmp to self
  99   patch[2] = 0xEB;
 100   patch[3] = 0xFE;
 101 
 102   // First patch dummy jmp in place
 103   *(jint*)instr_addr = *(jint *)patch;
 104 
 105   // Invalidate.  Opteron requires a flush after every write.
 106   n_call->wrote(0);
 107 
 108   // Patch 4th byte
 109   instr_addr[4] = code_buffer[4];
 110 
 111   n_call->wrote(4);
 112 
 113   // Patch bytes 0-3
 114   *(jint*)instr_addr = *(jint *)code_buffer;
 115 
 116   n_call->wrote(0);
 117 
 118 #ifdef ASSERT
 119    // verify patching
 120    for ( int i = 0; i < instruction_size; i++) {
 121      address ptr = (address)((intptr_t)code_buffer + i);
 122      int a_byte = (*ptr) & 0xFF;
 123      assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
 124    }
 125 #endif
 126 
 127 }
 128 
 129 
 130 // Similar to replace_mt_safe, but just changes the destination.  The
 131 // important thing is that free-running threads are able to execute this
 132 // call instruction at all times.  If the displacement field is aligned
 133 // we can simply rely on atomicity of 32-bit writes to make sure other threads
 134 // will see no intermediate states.  Otherwise, the first two bytes of the
 135 // call are guaranteed to be aligned, and can be atomically patched to a
 136 // self-loop to guard the instruction while we change the other bytes.
 137 
 138 // We cannot rely on locks here, since the free-running threads must run at
 139 // full speed.
 140 //
 141 // Used in the runtime linkage of calls; see class CompiledIC.
 142 // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
 143 void NativeCall::set_destination_mt_safe(address dest) {
 144   debug_only(verify());
 145   // Make sure patching code is locked.  No two threads can patch at the same
 146   // time but one may be executing this code.
 147   assert(Patching_lock->is_locked() ||
 148          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
 149   // Both C1 and C2 should now be generating code which aligns the patched address
 150   // to be within a single cache line except that C1 does not do the alignment on
 151   // uniprocessor systems.
 152   bool is_aligned = ((uintptr_t)displacement_address() + 0) / cache_line_size ==
 153                     ((uintptr_t)displacement_address() + 3) / cache_line_size;
 154 
 155   guarantee(!os::is_MP() || is_aligned, "destination must be aligned");
 156 
 157   if (is_aligned) {
 158     // Simple case:  The destination lies within a single cache line.
 159     set_destination(dest);
 160   } else if ((uintptr_t)instruction_address() / cache_line_size ==
 161              ((uintptr_t)instruction_address()+1) / cache_line_size) {
 162     // Tricky case:  The instruction prefix lies within a single cache line.
 163     intptr_t disp = dest - return_address();
 164 #ifdef AMD64
 165     guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
 166 #endif // AMD64
 167 
 168     int call_opcode = instruction_address()[0];
 169 
 170     // First patch dummy jump in place:
 171     {
 172       u_char patch_jump[2];
 173       patch_jump[0] = 0xEB;       // jmp rel8
 174       patch_jump[1] = 0xFE;       // jmp to self
 175 
 176       assert(sizeof(patch_jump)==sizeof(short), "sanity check");
 177       *(short*)instruction_address() = *(short*)patch_jump;
 178     }
 179     // Invalidate.  Opteron requires a flush after every write.
 180     wrote(0);
 181 
 182     // (Note: We assume any reader which has already started to read
 183     // the unpatched call will completely read the whole unpatched call
 184     // without seeing the next writes we are about to make.)
 185 
 186     // Next, patch the last three bytes:
 187     u_char patch_disp[5];
 188     patch_disp[0] = call_opcode;
 189     *(int32_t*)&patch_disp[1] = (int32_t)disp;
 190     assert(sizeof(patch_disp)==instruction_size, "sanity check");
 191     for (int i = sizeof(short); i < instruction_size; i++)
 192       instruction_address()[i] = patch_disp[i];
 193 
 194     // Invalidate.  Opteron requires a flush after every write.
 195     wrote(sizeof(short));
 196 
 197     // (Note: We assume that any reader which reads the opcode we are
 198     // about to repatch will also read the writes we just made.)
 199 
 200     // Finally, overwrite the jump:
 201     *(short*)instruction_address() = *(short*)patch_disp;
 202     // Invalidate.  Opteron requires a flush after every write.
 203     wrote(0);
 204 
 205     debug_only(verify());
 206     guarantee(destination() == dest, "patch succeeded");
 207   } else {
 208     // Impossible:  One or the other must be atomically writable.
 209     ShouldNotReachHere();
 210   }
 211 }
 212 
 213 
 214 void NativeMovConstReg::verify() {
 215 #ifdef AMD64
 216   // make sure code pattern is actually a mov reg64, imm64 instruction
 217   if ((ubyte_at(0) != Assembler::REX_W && ubyte_at(0) != Assembler::REX_WB) ||
 218       (ubyte_at(1) & (0xff ^ register_mask)) != 0xB8) {
 219     print();
 220     fatal("not a REX.W[B] mov reg64, imm64");
 221   }
 222 #else
 223   // make sure code pattern is actually a mov reg, imm32 instruction
 224   u_char test_byte = *(u_char*)instruction_address();
 225   u_char test_byte_2 = test_byte & ( 0xff ^ register_mask);
 226   if (test_byte_2 != instruction_code) fatal("not a mov reg, imm32");
 227 #endif // AMD64
 228 }
 229 
 230 
 231 void NativeMovConstReg::print() {
 232   tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
 233                 instruction_address(), data());
 234 }
 235 
 236 //-------------------------------------------------------------------
 237 
 238 int NativeMovRegMem::instruction_start() const {
 239   int off = 0;
 240   u_char instr_0 = ubyte_at(off);
 241 
 242   // See comment in Assembler::locate_operand() about VEX prefixes.
 243   if (instr_0 == instruction_VEX_prefix_2bytes) {
 244     assert((UseAVX > 0), "shouldn't have VEX prefix");
 245     NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions"));
 246     return 2;
 247   }
 248   if (instr_0 == instruction_VEX_prefix_3bytes) {
 249     assert((UseAVX > 0), "shouldn't have VEX prefix");
 250     NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions"));
 251     return 3;
 252   }
 253 
 254   // First check to see if we have a (prefixed or not) xor
 255   if (instr_0 >= instruction_prefix_wide_lo && // 0x40
 256       instr_0 <= instruction_prefix_wide_hi) { // 0x4f
 257     off++;
 258     instr_0 = ubyte_at(off);
 259   }
 260 
 261   if (instr_0 == instruction_code_xor) {
 262     off += 2;
 263     instr_0 = ubyte_at(off);
 264   }
 265 
 266   // Now look for the real instruction and the many prefix/size specifiers.
 267 
 268   if (instr_0 == instruction_operandsize_prefix ) {  // 0x66
 269     off++; // Not SSE instructions
 270     instr_0 = ubyte_at(off);
 271   }
 272 
 273   if ( instr_0 == instruction_code_xmm_ss_prefix || // 0xf3
 274        instr_0 == instruction_code_xmm_sd_prefix) { // 0xf2
 275     off++;
 276     instr_0 = ubyte_at(off);
 277   }
 278 
 279   if ( instr_0 >= instruction_prefix_wide_lo && // 0x40
 280        instr_0 <= instruction_prefix_wide_hi) { // 0x4f
 281     off++;
 282     instr_0 = ubyte_at(off);
 283   }
 284 
 285 
 286   if (instr_0 == instruction_extended_prefix ) {  // 0x0f
 287     off++;
 288   }
 289 
 290   return off;
 291 }
 292 
 293 address NativeMovRegMem::instruction_address() const {
 294   return addr_at(instruction_start());
 295 }
 296 
 297 address NativeMovRegMem::next_instruction_address() const {
 298   address ret = instruction_address() + instruction_size;
 299   u_char instr_0 =  *(u_char*) instruction_address();
 300   switch (instr_0) {
 301   case instruction_operandsize_prefix:
 302 
 303     fatal("should have skipped instruction_operandsize_prefix");
 304     break;
 305 
 306   case instruction_extended_prefix:
 307     fatal("should have skipped instruction_extended_prefix");
 308     break;
 309 
 310   case instruction_code_mem2reg_movslq: // 0x63
 311   case instruction_code_mem2reg_movzxb: // 0xB6
 312   case instruction_code_mem2reg_movsxb: // 0xBE
 313   case instruction_code_mem2reg_movzxw: // 0xB7
 314   case instruction_code_mem2reg_movsxw: // 0xBF
 315   case instruction_code_reg2mem:        // 0x89 (q/l)
 316   case instruction_code_mem2reg:        // 0x8B (q/l)
 317   case instruction_code_reg2memb:       // 0x88
 318   case instruction_code_mem2regb:       // 0x8a
 319 
 320   case instruction_code_lea:            // 0x8d
 321 
 322   case instruction_code_float_s:        // 0xd9 fld_s a
 323   case instruction_code_float_d:        // 0xdd fld_d a
 324 
 325   case instruction_code_xmm_load:       // 0x10
 326   case instruction_code_xmm_store:      // 0x11
 327   case instruction_code_xmm_lpd:        // 0x12
 328     {
 329       // If there is an SIB then instruction is longer than expected
 330       u_char mod_rm = *(u_char*)(instruction_address() + 1);
 331       if ((mod_rm & 7) == 0x4) {
 332         ret++;
 333       }
 334     }
 335   case instruction_code_xor:
 336     fatal("should have skipped xor lead in");
 337     break;
 338 
 339   default:
 340     fatal("not a NativeMovRegMem");
 341   }
 342   return ret;
 343 
 344 }
 345 
 346 int NativeMovRegMem::offset() const{
 347   int off = data_offset + instruction_start();
 348   u_char mod_rm = *(u_char*)(instruction_address() + 1);
 349   // nnnn(r12|rsp) isn't coded as simple mod/rm since that is
 350   // the encoding to use an SIB byte. Which will have the nnnn
 351   // field off by one byte
 352   if ((mod_rm & 7) == 0x4) {
 353     off++;
 354   }
 355   return int_at(off);
 356 }
 357 
 358 void NativeMovRegMem::set_offset(int x) {
 359   int off = data_offset + instruction_start();
 360   u_char mod_rm = *(u_char*)(instruction_address() + 1);
 361   // nnnn(r12|rsp) isn't coded as simple mod/rm since that is
 362   // the encoding to use an SIB byte. Which will have the nnnn
 363   // field off by one byte
 364   if ((mod_rm & 7) == 0x4) {
 365     off++;
 366   }
 367   set_int_at(off, x);
 368 }
 369 
 370 void NativeMovRegMem::verify() {
 371   // make sure code pattern is actually a mov [reg+offset], reg instruction
 372   u_char test_byte = *(u_char*)instruction_address();
 373   switch (test_byte) {
 374     case instruction_code_reg2memb:  // 0x88 movb a, r
 375     case instruction_code_reg2mem:   // 0x89 movl a, r (can be movq in 64bit)
 376     case instruction_code_mem2regb:  // 0x8a movb r, a
 377     case instruction_code_mem2reg:   // 0x8b movl r, a (can be movq in 64bit)
 378       break;
 379 
 380     case instruction_code_mem2reg_movslq: // 0x63 movsql r, a
 381     case instruction_code_mem2reg_movzxb: // 0xb6 movzbl r, a (movzxb)
 382     case instruction_code_mem2reg_movzxw: // 0xb7 movzwl r, a (movzxw)
 383     case instruction_code_mem2reg_movsxb: // 0xbe movsbl r, a (movsxb)
 384     case instruction_code_mem2reg_movsxw: // 0xbf  movswl r, a (movsxw)
 385       break;
 386 
 387     case instruction_code_float_s:   // 0xd9 fld_s a
 388     case instruction_code_float_d:   // 0xdd fld_d a
 389     case instruction_code_xmm_load:  // 0x10 movsd xmm, a
 390     case instruction_code_xmm_store: // 0x11 movsd a, xmm
 391     case instruction_code_xmm_lpd:   // 0x12 movlpd xmm, a
 392       break;
 393 
 394     case instruction_code_lea:       // 0x8d lea r, a
 395       break;
 396 
 397     default:
 398           fatal ("not a mov [reg+offs], reg instruction");
 399   }
 400 }
 401 
 402 
 403 void NativeMovRegMem::print() {
 404   tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
 405 }
 406 
 407 //-------------------------------------------------------------------
 408 
 409 void NativeLoadAddress::verify() {
 410   // make sure code pattern is actually a mov [reg+offset], reg instruction
 411   u_char test_byte = *(u_char*)instruction_address();
 412 #ifdef _LP64
 413   if ( (test_byte == instruction_prefix_wide ||
 414         test_byte == instruction_prefix_wide_extended) ) {
 415     test_byte = *(u_char*)(instruction_address() + 1);
 416   }
 417 #endif // _LP64
 418   if ( ! ((test_byte == lea_instruction_code)
 419           LP64_ONLY(|| (test_byte == mov64_instruction_code) ))) {
 420     fatal ("not a lea reg, [reg+offs] instruction");
 421   }
 422 }
 423 
 424 
 425 void NativeLoadAddress::print() {
 426   tty->print_cr("0x%x: lea [reg + %x], reg", instruction_address(), offset());
 427 }
 428 
 429 //--------------------------------------------------------------------------------
 430 
 431 void NativeJump::verify() {
 432   if (*(u_char*)instruction_address() != instruction_code) {
 433     fatal("not a jump instruction");
 434   }
 435 }
 436 
 437 
 438 void NativeJump::insert(address code_pos, address entry) {
 439   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
 440 #ifdef AMD64
 441   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
 442 #endif // AMD64
 443 
 444   *code_pos = instruction_code;
 445   *((int32_t*)(code_pos + 1)) = (int32_t)disp;
 446 
 447   ICache::invalidate_range(code_pos, instruction_size);
 448 }
 449 
 450 void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) {
 451   // Patching to not_entrant can happen while activations of the method are
 452   // in use. The patching in that instance must happen only when certain
 453   // alignment restrictions are true. These guarantees check those
 454   // conditions.
 455 #ifdef AMD64
 456   const int linesize = 64;
 457 #else
 458   const int linesize = 32;
 459 #endif // AMD64
 460 
 461   // Must be wordSize aligned
 462   guarantee(((uintptr_t) verified_entry & (wordSize -1)) == 0,
 463             "illegal address for code patching 2");
 464   // First 5 bytes must be within the same cache line - 4827828
 465   guarantee((uintptr_t) verified_entry / linesize ==
 466             ((uintptr_t) verified_entry + 4) / linesize,
 467             "illegal address for code patching 3");
 468 }
 469 
 470 
 471 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
 472 // The problem: jmp <dest> is a 5-byte instruction. Atomical write can be only with 4 bytes.
 473 // First patches the first word atomically to be a jump to itself.
 474 // Then patches the last byte  and then atomically patches the first word (4-bytes),
 475 // thus inserting the desired jump
 476 // This code is mt-safe with the following conditions: entry point is 4 byte aligned,
 477 // entry point is in same cache line as unverified entry point, and the instruction being
 478 // patched is >= 5 byte (size of patch).
 479 //
 480 // In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit.
 481 // In C1 the restriction is enforced by CodeEmitter::method_entry
 482 //
 483 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
 484   // complete jump instruction (to be inserted) is in code_buffer;
 485   unsigned char code_buffer[5];
 486   code_buffer[0] = instruction_code;
 487   intptr_t disp = (intptr_t)dest - ((intptr_t)verified_entry + 1 + 4);
 488 #ifdef AMD64
 489   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
 490 #endif // AMD64
 491   *(int32_t*)(code_buffer + 1) = (int32_t)disp;
 492 
 493   check_verified_entry_alignment(entry, verified_entry);
 494 
 495   // Can't call nativeJump_at() because it's asserts jump exists
 496   NativeJump* n_jump = (NativeJump*) verified_entry;
 497 
 498   //First patch dummy jmp in place
 499 
 500   unsigned char patch[4];
 501   assert(sizeof(patch)==sizeof(int32_t), "sanity check");
 502   patch[0] = 0xEB;       // jmp rel8
 503   patch[1] = 0xFE;       // jmp to self
 504   patch[2] = 0xEB;
 505   patch[3] = 0xFE;
 506 
 507   // First patch dummy jmp in place
 508   *(int32_t*)verified_entry = *(int32_t *)patch;
 509 
 510   n_jump->wrote(0);
 511 
 512   // Patch 5th byte (from jump instruction)
 513   verified_entry[4] = code_buffer[4];
 514 
 515   n_jump->wrote(4);
 516 
 517   // Patch bytes 0-3 (from jump instruction)
 518   *(int32_t*)verified_entry = *(int32_t *)code_buffer;
 519   // Invalidate.  Opteron requires a flush after every write.
 520   n_jump->wrote(0);
 521 
 522 }
 523 
 524 void NativePopReg::insert(address code_pos, Register reg) {
 525   assert(reg->encoding() < 8, "no space for REX");
 526   assert(NativePopReg::instruction_size == sizeof(char), "right address unit for update");
 527   *code_pos = (u_char)(instruction_code | reg->encoding());
 528   ICache::invalidate_range(code_pos, instruction_size);
 529 }
 530 
 531 
 532 void NativeIllegalInstruction::insert(address code_pos) {
 533   assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update");
 534   *(short *)code_pos = instruction_code;
 535   ICache::invalidate_range(code_pos, instruction_size);
 536 }
 537 
 538 void NativeGeneralJump::verify() {
 539   assert(((NativeInstruction *)this)->is_jump() ||
 540          ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
 541 }
 542 
 543 
 544 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
 545   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
 546 #ifdef AMD64
 547   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
 548 #endif // AMD64
 549 
 550   *code_pos = unconditional_long_jump;
 551   *((int32_t *)(code_pos+1)) = (int32_t) disp;
 552   ICache::invalidate_range(code_pos, instruction_size);
 553 }
 554 
 555 
 556 // MT-safe patching of a long jump instruction.
 557 // First patches first word of instruction to two jmp's that jmps to them
 558 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
 559 // the jmp's with the first 4 byte of the new instruction.
 560 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
 561    assert (instr_addr != NULL, "illegal address for code patching (4)");
 562    NativeGeneralJump* n_jump =  nativeGeneralJump_at (instr_addr); // checking that it is a jump
 563 
 564    // Temporary code
 565    unsigned char patch[4];
 566    assert(sizeof(patch)==sizeof(int32_t), "sanity check");
 567    patch[0] = 0xEB;       // jmp rel8
 568    patch[1] = 0xFE;       // jmp to self
 569    patch[2] = 0xEB;
 570    patch[3] = 0xFE;
 571 
 572    // First patch dummy jmp in place
 573    *(int32_t*)instr_addr = *(int32_t *)patch;
 574     n_jump->wrote(0);
 575 
 576    // Patch 4th byte
 577    instr_addr[4] = code_buffer[4];
 578 
 579     n_jump->wrote(4);
 580 
 581    // Patch bytes 0-3
 582    *(jint*)instr_addr = *(jint *)code_buffer;
 583 
 584     n_jump->wrote(0);
 585 
 586 #ifdef ASSERT
 587    // verify patching
 588    for ( int i = 0; i < instruction_size; i++) {
 589      address ptr = (address)((intptr_t)code_buffer + i);
 590      int a_byte = (*ptr) & 0xFF;
 591      assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
 592    }
 593 #endif
 594 
 595 }
 596 
 597 
 598 
 599 address NativeGeneralJump::jump_destination() const {
 600   int op_code = ubyte_at(0);
 601   bool is_rel32off = (op_code == 0xE9 || op_code == 0x0F);
 602   int  offset  = (op_code == 0x0F)  ? 2 : 1;
 603   int  length  = offset + ((is_rel32off) ? 4 : 1);
 604 
 605   if (is_rel32off)
 606     return addr_at(0) + length + int_at(offset);
 607   else
 608     return addr_at(0) + length + sbyte_at(offset);
 609 }
 610 
 611 bool NativeInstruction::is_dtrace_trap() {
 612   return (*(int32_t*)this & 0xff) == 0xcc;
 613 }