1 /*
   2  * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_InstructionPrinter.hpp"
  27 #include "c1/c1_LIR.hpp"
  28 #include "c1/c1_LIRAssembler.hpp"
  29 #include "c1/c1_ValueStack.hpp"
  30 #include "ci/ciInstance.hpp"
  31 #include "runtime/sharedRuntime.hpp"
  32 
  33 Register LIR_OprDesc::as_register() const {
  34   return FrameMap::cpu_rnr2reg(cpu_regnr());
  35 }
  36 
  37 Register LIR_OprDesc::as_register_lo() const {
  38   return FrameMap::cpu_rnr2reg(cpu_regnrLo());
  39 }
  40 
  41 Register LIR_OprDesc::as_register_hi() const {
  42   return FrameMap::cpu_rnr2reg(cpu_regnrHi());
  43 }
  44 
  45 #if defined(X86)
  46 
  47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
  48   return FrameMap::nr2xmmreg(xmm_regnr());
  49 }
  50 
  51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
  52   assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
  53   return FrameMap::nr2xmmreg(xmm_regnrLo());
  54 }
  55 
  56 #endif // X86
  57 
  58 #if defined(SPARC) || defined(PPC)
  59 
  60 FloatRegister LIR_OprDesc::as_float_reg() const {
  61   return FrameMap::nr2floatreg(fpu_regnr());
  62 }
  63 
  64 FloatRegister LIR_OprDesc::as_double_reg() const {
  65   return FrameMap::nr2floatreg(fpu_regnrHi());
  66 }
  67 
  68 #endif
  69 
  70 #if defined(ARM) || defined (TARGET_ARCH_aarch64)
  71 
  72 FloatRegister LIR_OprDesc::as_float_reg() const {
  73   return as_FloatRegister(fpu_regnr());
  74 }
  75 
  76 FloatRegister LIR_OprDesc::as_double_reg() const {
  77   return as_FloatRegister(fpu_regnrLo());
  78 }
  79 
  80 #endif
  81 
  82 
  83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
  84 
  85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
  86   ValueTag tag = type->tag();
  87   switch (tag) {
  88   case metaDataTag : {
  89     ClassConstant* c = type->as_ClassConstant();
  90     if (c != NULL && !c->value()->is_loaded()) {
  91       return LIR_OprFact::metadataConst(NULL);
  92     } else if (c != NULL) {
  93       return LIR_OprFact::metadataConst(c->value()->constant_encoding());
  94     } else {
  95       MethodConstant* m = type->as_MethodConstant();
  96       assert (m != NULL, "not a class or a method?");
  97       return LIR_OprFact::metadataConst(m->value()->constant_encoding());
  98     }
  99   }
 100   case objectTag : {
 101       return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
 102     }
 103   case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
 104   case intTag    : return LIR_OprFact::intConst(type->as_IntConstant()->value());
 105   case floatTag  : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
 106   case longTag   : return LIR_OprFact::longConst(type->as_LongConstant()->value());
 107   case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
 108   default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
 109   }
 110 }
 111 
 112 
 113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
 114   switch (type->tag()) {
 115     case objectTag: return LIR_OprFact::oopConst(NULL);
 116     case addressTag:return LIR_OprFact::addressConst(0);
 117     case intTag:    return LIR_OprFact::intConst(0);
 118     case floatTag:  return LIR_OprFact::floatConst(0.0);
 119     case longTag:   return LIR_OprFact::longConst(0);
 120     case doubleTag: return LIR_OprFact::doubleConst(0.0);
 121     default:        ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
 122   }
 123   return illegalOpr;
 124 }
 125 
 126 
 127 
 128 //---------------------------------------------------
 129 
 130 
 131 LIR_Address::Scale LIR_Address::scale(BasicType type) {
 132   int elem_size = type2aelembytes(type);
 133   switch (elem_size) {
 134   case 1: return LIR_Address::times_1;
 135   case 2: return LIR_Address::times_2;
 136   case 4: return LIR_Address::times_4;
 137   case 8: return LIR_Address::times_8;
 138   }
 139   ShouldNotReachHere();
 140   return LIR_Address::times_1;
 141 }
 142 
 143 
 144 #ifndef PRODUCT
 145 void LIR_Address::verify0() const {
 146 #if defined(SPARC) || defined(PPC)
 147   assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
 148   assert(disp() == 0 || index()->is_illegal(), "can't have both");
 149 #endif
 150 #ifdef _LP64
 151   assert(base()->is_cpu_register(), "wrong base operand");
 152 #ifndef TARGET_ARCH_aarch64
 153   assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
 154 #else
 155   assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
 156 #endif
 157   assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
 158          "wrong type for addresses");
 159 #else
 160   assert(base()->is_single_cpu(), "wrong base operand");
 161   assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
 162   assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
 163          "wrong type for addresses");
 164 #endif
 165 }
 166 #endif
 167 
 168 
 169 //---------------------------------------------------
 170 
 171 char LIR_OprDesc::type_char(BasicType t) {
 172   switch (t) {
 173     case T_ARRAY:
 174       t = T_OBJECT;
 175     case T_BOOLEAN:
 176     case T_CHAR:
 177     case T_FLOAT:
 178     case T_DOUBLE:
 179     case T_BYTE:
 180     case T_SHORT:
 181     case T_INT:
 182     case T_LONG:
 183     case T_OBJECT:
 184     case T_ADDRESS:
 185     case T_VOID:
 186       return ::type2char(t);
 187     case T_METADATA:
 188       return 'M';
 189     case T_ILLEGAL:
 190       return '?';
 191 
 192     default:
 193       ShouldNotReachHere();
 194       return '?';
 195   }
 196 }
 197 
 198 #ifndef PRODUCT
 199 void LIR_OprDesc::validate_type() const {
 200 
 201 #ifdef ASSERT
 202   if (!is_pointer() && !is_illegal()) {
 203     OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
 204     switch (as_BasicType(type_field())) {
 205     case T_LONG:
 206       assert((kindfield == cpu_register || kindfield == stack_value) &&
 207              size_field() == double_size, "must match");
 208       break;
 209     case T_FLOAT:
 210       // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
 211       assert((kindfield == fpu_register || kindfield == stack_value
 212              ARM_ONLY(|| kindfield == cpu_register)
 213              PPC_ONLY(|| kindfield == cpu_register) ) &&
 214              size_field() == single_size, "must match");
 215       break;
 216     case T_DOUBLE:
 217       // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
 218       assert((kindfield == fpu_register || kindfield == stack_value
 219              ARM_ONLY(|| kindfield == cpu_register)
 220              PPC_ONLY(|| kindfield == cpu_register) ) &&
 221              size_field() == double_size, "must match");
 222       break;
 223     case T_BOOLEAN:
 224     case T_CHAR:
 225     case T_BYTE:
 226     case T_SHORT:
 227     case T_INT:
 228     case T_ADDRESS:
 229     case T_OBJECT:
 230     case T_METADATA:
 231     case T_ARRAY:
 232       assert((kindfield == cpu_register || kindfield == stack_value) &&
 233              size_field() == single_size, "must match");
 234       break;
 235 
 236     case T_ILLEGAL:
 237       // XXX TKR also means unknown right now
 238       // assert(is_illegal(), "must match");
 239       break;
 240 
 241     default:
 242       ShouldNotReachHere();
 243     }
 244   }
 245 #endif
 246 
 247 }
 248 #endif // PRODUCT
 249 
 250 
 251 bool LIR_OprDesc::is_oop() const {
 252   if (is_pointer()) {
 253     return pointer()->is_oop_pointer();
 254   } else {
 255     OprType t= type_field();
 256     assert(t != unknown_type, "not set");
 257     return t == object_type;
 258   }
 259 }
 260 
 261 
 262 
 263 void LIR_Op2::verify() const {
 264 #ifdef ASSERT
 265   switch (code()) {
 266     case lir_cmove:
 267     case lir_xchg:
 268       break;
 269 
 270     default:
 271       assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
 272              "can't produce oops from arith");
 273   }
 274 
 275   if (TwoOperandLIRForm) {
 276     switch (code()) {
 277     case lir_add:
 278     case lir_sub:
 279     case lir_mul:
 280     case lir_mul_strictfp:
 281     case lir_div:
 282     case lir_div_strictfp:
 283     case lir_rem:
 284     case lir_logic_and:
 285     case lir_logic_or:
 286     case lir_logic_xor:
 287     case lir_shl:
 288     case lir_shr:
 289       assert(in_opr1() == result_opr(), "opr1 and result must match");
 290       assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
 291       break;
 292 
 293     // special handling for lir_ushr because of write barriers
 294     case lir_ushr:
 295       assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
 296       assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
 297       break;
 298 
 299     }
 300   }
 301 #endif
 302 }
 303 
 304 
 305 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
 306   : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 307   , _cond(cond)
 308   , _type(type)
 309   , _label(block->label())
 310   , _block(block)
 311   , _ublock(NULL)
 312   , _stub(NULL) {
 313 }
 314 
 315 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
 316   LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 317   , _cond(cond)
 318   , _type(type)
 319   , _label(stub->entry())
 320   , _block(NULL)
 321   , _ublock(NULL)
 322   , _stub(stub) {
 323 }
 324 
 325 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
 326   : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
 327   , _cond(cond)
 328   , _type(type)
 329   , _label(block->label())
 330   , _block(block)
 331   , _ublock(ublock)
 332   , _stub(NULL)
 333 {
 334 }
 335 
 336 void LIR_OpBranch::change_block(BlockBegin* b) {
 337   assert(_block != NULL, "must have old block");
 338   assert(_block->label() == label(), "must be equal");
 339 
 340   _block = b;
 341   _label = b->label();
 342 }
 343 
 344 void LIR_OpBranch::change_ublock(BlockBegin* b) {
 345   assert(_ublock != NULL, "must have old block");
 346   _ublock = b;
 347 }
 348 
 349 void LIR_OpBranch::negate_cond() {
 350   switch (_cond) {
 351     case lir_cond_equal:        _cond = lir_cond_notEqual;     break;
 352     case lir_cond_notEqual:     _cond = lir_cond_equal;        break;
 353     case lir_cond_less:         _cond = lir_cond_greaterEqual; break;
 354     case lir_cond_lessEqual:    _cond = lir_cond_greater;      break;
 355     case lir_cond_greaterEqual: _cond = lir_cond_less;         break;
 356     case lir_cond_greater:      _cond = lir_cond_lessEqual;    break;
 357     default: ShouldNotReachHere();
 358   }
 359 }
 360 
 361 
 362 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
 363                                  LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
 364                                  bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
 365                                  CodeStub* stub)
 366 
 367   : LIR_Op(code, result, NULL)
 368   , _object(object)
 369   , _array(LIR_OprFact::illegalOpr)
 370   , _klass(klass)
 371   , _tmp1(tmp1)
 372   , _tmp2(tmp2)
 373   , _tmp3(tmp3)
 374   , _fast_check(fast_check)
 375   , _stub(stub)
 376   , _info_for_patch(info_for_patch)
 377   , _info_for_exception(info_for_exception)
 378   , _profiled_method(NULL)
 379   , _profiled_bci(-1)
 380   , _should_profile(false)
 381 {
 382   if (code == lir_checkcast) {
 383     assert(info_for_exception != NULL, "checkcast throws exceptions");
 384   } else if (code == lir_instanceof) {
 385     assert(info_for_exception == NULL, "instanceof throws no exceptions");
 386   } else {
 387     ShouldNotReachHere();
 388   }
 389 }
 390 
 391 
 392 
 393 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
 394   : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
 395   , _object(object)
 396   , _array(array)
 397   , _klass(NULL)
 398   , _tmp1(tmp1)
 399   , _tmp2(tmp2)
 400   , _tmp3(tmp3)
 401   , _fast_check(false)
 402   , _stub(NULL)
 403   , _info_for_patch(NULL)
 404   , _info_for_exception(info_for_exception)
 405   , _profiled_method(NULL)
 406   , _profiled_bci(-1)
 407   , _should_profile(false)
 408 {
 409   if (code == lir_store_check) {
 410     _stub = new ArrayStoreExceptionStub(object, info_for_exception);
 411     assert(info_for_exception != NULL, "store_check throws exceptions");
 412   } else {
 413     ShouldNotReachHere();
 414   }
 415 }
 416 
 417 
 418 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
 419                                  LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
 420   : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
 421   , _tmp(tmp)
 422   , _src(src)
 423   , _src_pos(src_pos)
 424   , _dst(dst)
 425   , _dst_pos(dst_pos)
 426   , _flags(flags)
 427   , _expected_type(expected_type)
 428   , _length(length) {
 429   _stub = new ArrayCopyStub(this);
 430 }
 431 
 432 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
 433   : LIR_Op(lir_updatecrc32, res, NULL)
 434   , _crc(crc)
 435   , _val(val) {
 436 }
 437 
 438 //-------------------verify--------------------------
 439 
 440 void LIR_Op1::verify() const {
 441   switch(code()) {
 442   case lir_move:
 443     assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
 444     break;
 445   case lir_null_check:
 446     assert(in_opr()->is_register(), "must be");
 447     break;
 448   case lir_return:
 449     assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
 450     break;
 451   }
 452 }
 453 
 454 void LIR_OpRTCall::verify() const {
 455   assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
 456 }
 457 
 458 //-------------------visits--------------------------
 459 
 460 // complete rework of LIR instruction visitor.
 461 // The virtual call for each instruction type is replaced by a big
 462 // switch that adds the operands for each instruction
 463 
 464 void LIR_OpVisitState::visit(LIR_Op* op) {
 465   // copy information from the LIR_Op
 466   reset();
 467   set_op(op);
 468 
 469   switch (op->code()) {
 470 
 471 // LIR_Op0
 472     case lir_word_align:               // result and info always invalid
 473     case lir_backwardbranch_target:    // result and info always invalid
 474     case lir_build_frame:              // result and info always invalid
 475     case lir_fpop_raw:                 // result and info always invalid
 476     case lir_24bit_FPU:                // result and info always invalid
 477     case lir_reset_FPU:                // result and info always invalid
 478     case lir_breakpoint:               // result and info always invalid
 479     case lir_membar:                   // result and info always invalid
 480     case lir_membar_acquire:           // result and info always invalid
 481     case lir_membar_release:           // result and info always invalid
 482     case lir_membar_loadload:          // result and info always invalid
 483     case lir_membar_storestore:        // result and info always invalid
 484     case lir_membar_loadstore:         // result and info always invalid
 485     case lir_membar_storeload:         // result and info always invalid
 486     {
 487       assert(op->as_Op0() != NULL, "must be");
 488       assert(op->_info == NULL, "info not used by this instruction");
 489       assert(op->_result->is_illegal(), "not used");
 490       break;
 491     }
 492 
 493     case lir_nop:                      // may have info, result always invalid
 494     case lir_std_entry:                // may have result, info always invalid
 495     case lir_osr_entry:                // may have result, info always invalid
 496     case lir_get_thread:               // may have result, info always invalid
 497     {
 498       assert(op->as_Op0() != NULL, "must be");
 499       if (op->_info != NULL)           do_info(op->_info);
 500       if (op->_result->is_valid())     do_output(op->_result);
 501       break;
 502     }
 503 
 504 
 505 // LIR_OpLabel
 506     case lir_label:                    // result and info always invalid
 507     {
 508       assert(op->as_OpLabel() != NULL, "must be");
 509       assert(op->_info == NULL, "info not used by this instruction");
 510       assert(op->_result->is_illegal(), "not used");
 511       break;
 512     }
 513 
 514 
 515 // LIR_Op1
 516     case lir_fxch:           // input always valid, result and info always invalid
 517     case lir_fld:            // input always valid, result and info always invalid
 518     case lir_ffree:          // input always valid, result and info always invalid
 519     case lir_push:           // input always valid, result and info always invalid
 520     case lir_pop:            // input always valid, result and info always invalid
 521     case lir_return:         // input always valid, result and info always invalid
 522     case lir_leal:           // input and result always valid, info always invalid
 523     case lir_neg:            // input and result always valid, info always invalid
 524     case lir_monaddr:        // input and result always valid, info always invalid
 525     case lir_null_check:     // input and info always valid, result always invalid
 526     case lir_move:           // input and result always valid, may have info
 527     case lir_pack64:         // input and result always valid
 528     case lir_unpack64:       // input and result always valid
 529     case lir_prefetchr:      // input always valid, result and info always invalid
 530     case lir_prefetchw:      // input always valid, result and info always invalid
 531     {
 532       assert(op->as_Op1() != NULL, "must be");
 533       LIR_Op1* op1 = (LIR_Op1*)op;
 534 
 535       if (op1->_info)                  do_info(op1->_info);
 536       if (op1->_opr->is_valid())       do_input(op1->_opr);
 537       if (op1->_result->is_valid())    do_output(op1->_result);
 538 
 539       break;
 540     }
 541 
 542     case lir_safepoint:
 543     {
 544       assert(op->as_Op1() != NULL, "must be");
 545       LIR_Op1* op1 = (LIR_Op1*)op;
 546 
 547       assert(op1->_info != NULL, "");  do_info(op1->_info);
 548       if (op1->_opr->is_valid())       do_temp(op1->_opr); // safepoints on SPARC need temporary register
 549       assert(op1->_result->is_illegal(), "safepoint does not produce value");
 550 
 551       break;
 552     }
 553 
 554 // LIR_OpConvert;
 555     case lir_convert:        // input and result always valid, info always invalid
 556     {
 557       assert(op->as_OpConvert() != NULL, "must be");
 558       LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
 559 
 560       assert(opConvert->_info == NULL, "must be");
 561       if (opConvert->_opr->is_valid())       do_input(opConvert->_opr);
 562       if (opConvert->_result->is_valid())    do_output(opConvert->_result);
 563 #if defined(PPC) || defined(TARGET_ARCH_aarch64)
 564       if (opConvert->_tmp1->is_valid())      do_temp(opConvert->_tmp1);
 565       if (opConvert->_tmp2->is_valid())      do_temp(opConvert->_tmp2);
 566 #endif
 567       do_stub(opConvert->_stub);
 568 
 569       break;
 570     }
 571 
 572 // LIR_OpBranch;
 573     case lir_branch:                   // may have info, input and result register always invalid
 574     case lir_cond_float_branch:        // may have info, input and result register always invalid
 575     {
 576       assert(op->as_OpBranch() != NULL, "must be");
 577       LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
 578 
 579       if (opBranch->_info != NULL)     do_info(opBranch->_info);
 580       assert(opBranch->_result->is_illegal(), "not used");
 581       if (opBranch->_stub != NULL)     opBranch->stub()->visit(this);
 582 
 583       break;
 584     }
 585 
 586 
 587 // LIR_OpAllocObj
 588     case lir_alloc_object:
 589     {
 590       assert(op->as_OpAllocObj() != NULL, "must be");
 591       LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
 592 
 593       if (opAllocObj->_info)                     do_info(opAllocObj->_info);
 594       if (opAllocObj->_opr->is_valid()) {        do_input(opAllocObj->_opr);
 595                                                  do_temp(opAllocObj->_opr);
 596                                         }
 597       if (opAllocObj->_tmp1->is_valid())         do_temp(opAllocObj->_tmp1);
 598       if (opAllocObj->_tmp2->is_valid())         do_temp(opAllocObj->_tmp2);
 599       if (opAllocObj->_tmp3->is_valid())         do_temp(opAllocObj->_tmp3);
 600       if (opAllocObj->_tmp4->is_valid())         do_temp(opAllocObj->_tmp4);
 601       if (opAllocObj->_result->is_valid())       do_output(opAllocObj->_result);
 602                                                  do_stub(opAllocObj->_stub);
 603       break;
 604     }
 605 
 606 
 607 // LIR_OpRoundFP;
 608     case lir_roundfp: {
 609       assert(op->as_OpRoundFP() != NULL, "must be");
 610       LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
 611 
 612       assert(op->_info == NULL, "info not used by this instruction");
 613       assert(opRoundFP->_tmp->is_illegal(), "not used");
 614       do_input(opRoundFP->_opr);
 615       do_output(opRoundFP->_result);
 616 
 617       break;
 618     }
 619 
 620 
 621 // LIR_Op2
 622     case lir_cmp:
 623     case lir_cmp_l2i:
 624     case lir_ucmp_fd2i:
 625     case lir_cmp_fd2i:
 626     case lir_add:
 627     case lir_sub:
 628     case lir_mul:
 629     case lir_div:
 630     case lir_rem:
 631     case lir_sqrt:
 632     case lir_abs:
 633     case lir_logic_and:
 634     case lir_logic_or:
 635     case lir_logic_xor:
 636     case lir_shl:
 637     case lir_shr:
 638     case lir_ushr:
 639     case lir_xadd:
 640     case lir_xchg:
 641     case lir_assert:
 642     {
 643       assert(op->as_Op2() != NULL, "must be");
 644       LIR_Op2* op2 = (LIR_Op2*)op;
 645       assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
 646              op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 647 
 648       if (op2->_info)                     do_info(op2->_info);
 649       if (op2->_opr1->is_valid())         do_input(op2->_opr1);
 650       if (op2->_opr2->is_valid())         do_input(op2->_opr2);
 651       if (op2->_tmp1->is_valid())         do_temp(op2->_tmp1);
 652       if (op2->_result->is_valid())       do_output(op2->_result);
 653       if (op->code() == lir_xchg || op->code() == lir_xadd) {
 654         // on ARM and PPC, return value is loaded first so could
 655         // destroy inputs. On other platforms that implement those
 656         // (x86, sparc), the extra constrainsts are harmless.
 657         if (op2->_opr1->is_valid())       do_temp(op2->_opr1);
 658         if (op2->_opr2->is_valid())       do_temp(op2->_opr2);
 659       }
 660 
 661       break;
 662     }
 663 
 664     // special handling for cmove: right input operand must not be equal
 665     // to the result operand, otherwise the backend fails
 666     case lir_cmove:
 667     {
 668       assert(op->as_Op2() != NULL, "must be");
 669       LIR_Op2* op2 = (LIR_Op2*)op;
 670 
 671       assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
 672              op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 673       assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
 674 
 675       do_input(op2->_opr1);
 676       do_input(op2->_opr2);
 677       do_temp(op2->_opr2);
 678       do_output(op2->_result);
 679 
 680       break;
 681     }
 682 
 683     // vspecial handling for strict operations: register input operands
 684     // as temp to guarantee that they do not overlap with other
 685     // registers
 686     case lir_mul_strictfp:
 687     case lir_div_strictfp:
 688     {
 689       assert(op->as_Op2() != NULL, "must be");
 690       LIR_Op2* op2 = (LIR_Op2*)op;
 691 
 692       assert(op2->_info == NULL, "not used");
 693       assert(op2->_opr1->is_valid(), "used");
 694       assert(op2->_opr2->is_valid(), "used");
 695       assert(op2->_result->is_valid(), "used");
 696       assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
 697              op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 698 
 699       do_input(op2->_opr1); do_temp(op2->_opr1);
 700       do_input(op2->_opr2); do_temp(op2->_opr2);
 701       if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
 702       do_output(op2->_result);
 703 
 704       break;
 705     }
 706 
 707     case lir_throw: {
 708       assert(op->as_Op2() != NULL, "must be");
 709       LIR_Op2* op2 = (LIR_Op2*)op;
 710 
 711       if (op2->_info)                     do_info(op2->_info);
 712       if (op2->_opr1->is_valid())         do_temp(op2->_opr1);
 713       if (op2->_opr2->is_valid())         do_input(op2->_opr2); // exception object is input parameter
 714       assert(op2->_result->is_illegal(), "no result");
 715       assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
 716              op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
 717 
 718       break;
 719     }
 720 
 721     case lir_unwind: {
 722       assert(op->as_Op1() != NULL, "must be");
 723       LIR_Op1* op1 = (LIR_Op1*)op;
 724 
 725       assert(op1->_info == NULL, "no info");
 726       assert(op1->_opr->is_valid(), "exception oop");         do_input(op1->_opr);
 727       assert(op1->_result->is_illegal(), "no result");
 728 
 729       break;
 730     }
 731 
 732 
 733     case lir_tan:
 734     case lir_sin:
 735     case lir_cos:
 736     case lir_log:
 737     case lir_log10:
 738     case lir_exp: {
 739       assert(op->as_Op2() != NULL, "must be");
 740       LIR_Op2* op2 = (LIR_Op2*)op;
 741 
 742       // On x86 tan/sin/cos need two temporary fpu stack slots and
 743       // log/log10 need one so handle opr2 and tmp as temp inputs.
 744       // Register input operand as temp to guarantee that it doesn't
 745       // overlap with the input.
 746       assert(op2->_info == NULL, "not used");
 747       assert(op2->_tmp5->is_illegal(), "not used");
 748       assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used");
 749       assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used");
 750       assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used");
 751       assert(op2->_opr1->is_valid(), "used");
 752       do_input(op2->_opr1); do_temp(op2->_opr1);
 753 
 754       if (op2->_opr2->is_valid())         do_temp(op2->_opr2);
 755       if (op2->_tmp1->is_valid())         do_temp(op2->_tmp1);
 756       if (op2->_tmp2->is_valid())         do_temp(op2->_tmp2);
 757       if (op2->_tmp3->is_valid())         do_temp(op2->_tmp3);
 758       if (op2->_tmp4->is_valid())         do_temp(op2->_tmp4);
 759       if (op2->_result->is_valid())       do_output(op2->_result);
 760 
 761       break;
 762     }
 763 
 764     case lir_pow: {
 765       assert(op->as_Op2() != NULL, "must be");
 766       LIR_Op2* op2 = (LIR_Op2*)op;
 767 
 768       // On x86 pow needs two temporary fpu stack slots: tmp1 and
 769       // tmp2. Register input operands as temps to guarantee that it
 770       // doesn't overlap with the temporary slots.
 771       assert(op2->_info == NULL, "not used");
 772       assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
 773       assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
 774              && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
 775       assert(op2->_result->is_valid(), "used");
 776 
 777       do_input(op2->_opr1); do_temp(op2->_opr1);
 778       do_input(op2->_opr2); do_temp(op2->_opr2);
 779       do_temp(op2->_tmp1);
 780       do_temp(op2->_tmp2);
 781       do_temp(op2->_tmp3);
 782       do_temp(op2->_tmp4);
 783       do_temp(op2->_tmp5);
 784       do_output(op2->_result);
 785 
 786       break;
 787     }
 788 
 789 // LIR_Op3
 790     case lir_idiv:
 791     case lir_irem: {
 792       assert(op->as_Op3() != NULL, "must be");
 793       LIR_Op3* op3= (LIR_Op3*)op;
 794 
 795       if (op3->_info)                     do_info(op3->_info);
 796       if (op3->_opr1->is_valid())         do_input(op3->_opr1);
 797 
 798       // second operand is input and temp, so ensure that second operand
 799       // and third operand get not the same register
 800       if (op3->_opr2->is_valid())         do_input(op3->_opr2);
 801       if (op3->_opr2->is_valid())         do_temp(op3->_opr2);
 802       if (op3->_opr3->is_valid())         do_temp(op3->_opr3);
 803 
 804       if (op3->_result->is_valid())       do_output(op3->_result);
 805 
 806       break;
 807     }
 808 
 809 
 810 // LIR_OpJavaCall
 811     case lir_static_call:
 812     case lir_optvirtual_call:
 813     case lir_icvirtual_call:
 814     case lir_virtual_call:
 815     case lir_dynamic_call: {
 816       LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
 817       assert(opJavaCall != NULL, "must be");
 818 
 819       if (opJavaCall->_receiver->is_valid())     do_input(opJavaCall->_receiver);
 820 
 821       // only visit register parameters
 822       int n = opJavaCall->_arguments->length();
 823       for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
 824         if (!opJavaCall->_arguments->at(i)->is_pointer()) {
 825           do_input(*opJavaCall->_arguments->adr_at(i));
 826         }
 827       }
 828 
 829       if (opJavaCall->_info)                     do_info(opJavaCall->_info);
 830       if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
 831           opJavaCall->is_method_handle_invoke()) {
 832         opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
 833         do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
 834       }
 835       do_call();
 836       if (opJavaCall->_result->is_valid())       do_output(opJavaCall->_result);
 837 
 838       break;
 839     }
 840 
 841 
 842 // LIR_OpRTCall
 843     case lir_rtcall: {
 844       assert(op->as_OpRTCall() != NULL, "must be");
 845       LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
 846 
 847       // only visit register parameters
 848       int n = opRTCall->_arguments->length();
 849       for (int i = 0; i < n; i++) {
 850         if (!opRTCall->_arguments->at(i)->is_pointer()) {
 851           do_input(*opRTCall->_arguments->adr_at(i));
 852         }
 853       }
 854       if (opRTCall->_info)                     do_info(opRTCall->_info);
 855       if (opRTCall->_tmp->is_valid())          do_temp(opRTCall->_tmp);
 856       do_call();
 857       if (opRTCall->_result->is_valid())       do_output(opRTCall->_result);
 858 
 859       break;
 860     }
 861 
 862 
 863 // LIR_OpArrayCopy
 864     case lir_arraycopy: {
 865       assert(op->as_OpArrayCopy() != NULL, "must be");
 866       LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
 867 
 868       assert(opArrayCopy->_result->is_illegal(), "unused");
 869       assert(opArrayCopy->_src->is_valid(), "used");          do_input(opArrayCopy->_src);     do_temp(opArrayCopy->_src);
 870       assert(opArrayCopy->_src_pos->is_valid(), "used");      do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
 871       assert(opArrayCopy->_dst->is_valid(), "used");          do_input(opArrayCopy->_dst);     do_temp(opArrayCopy->_dst);
 872       assert(opArrayCopy->_dst_pos->is_valid(), "used");      do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
 873       assert(opArrayCopy->_length->is_valid(), "used");       do_input(opArrayCopy->_length);  do_temp(opArrayCopy->_length);
 874       assert(opArrayCopy->_tmp->is_valid(), "used");          do_temp(opArrayCopy->_tmp);
 875       if (opArrayCopy->_info)                     do_info(opArrayCopy->_info);
 876 
 877       // the implementation of arraycopy always has a call into the runtime
 878       do_call();
 879 
 880       break;
 881     }
 882 
 883 
 884 // LIR_OpUpdateCRC32
 885     case lir_updatecrc32: {
 886       assert(op->as_OpUpdateCRC32() != NULL, "must be");
 887       LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
 888 
 889       assert(opUp->_crc->is_valid(), "used");          do_input(opUp->_crc);     do_temp(opUp->_crc);
 890       assert(opUp->_val->is_valid(), "used");          do_input(opUp->_val);     do_temp(opUp->_val);
 891       assert(opUp->_result->is_valid(), "used");       do_output(opUp->_result);
 892       assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
 893 
 894       break;
 895     }
 896 
 897 
 898 // LIR_OpLock
 899     case lir_lock:
 900     case lir_unlock: {
 901       assert(op->as_OpLock() != NULL, "must be");
 902       LIR_OpLock* opLock = (LIR_OpLock*)op;
 903 
 904       if (opLock->_info)                          do_info(opLock->_info);
 905 
 906       // TODO: check if these operands really have to be temp
 907       // (or if input is sufficient). This may have influence on the oop map!
 908       assert(opLock->_lock->is_valid(), "used");  do_temp(opLock->_lock);
 909       assert(opLock->_hdr->is_valid(),  "used");  do_temp(opLock->_hdr);
 910       assert(opLock->_obj->is_valid(),  "used");  do_temp(opLock->_obj);
 911 
 912       if (opLock->_scratch->is_valid())           do_temp(opLock->_scratch);
 913       assert(opLock->_result->is_illegal(), "unused");
 914 
 915       do_stub(opLock->_stub);
 916 
 917       break;
 918     }
 919 
 920 
 921 // LIR_OpDelay
 922     case lir_delay_slot: {
 923       assert(op->as_OpDelay() != NULL, "must be");
 924       LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
 925 
 926       visit(opDelay->delay_op());
 927       break;
 928     }
 929 
 930 // LIR_OpTypeCheck
 931     case lir_instanceof:
 932     case lir_checkcast:
 933     case lir_store_check: {
 934       assert(op->as_OpTypeCheck() != NULL, "must be");
 935       LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
 936 
 937       if (opTypeCheck->_info_for_exception)       do_info(opTypeCheck->_info_for_exception);
 938       if (opTypeCheck->_info_for_patch)           do_info(opTypeCheck->_info_for_patch);
 939       if (opTypeCheck->_object->is_valid())       do_input(opTypeCheck->_object);
 940       if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
 941         do_temp(opTypeCheck->_object);
 942       }
 943       if (opTypeCheck->_array->is_valid())        do_input(opTypeCheck->_array);
 944       if (opTypeCheck->_tmp1->is_valid())         do_temp(opTypeCheck->_tmp1);
 945       if (opTypeCheck->_tmp2->is_valid())         do_temp(opTypeCheck->_tmp2);
 946       if (opTypeCheck->_tmp3->is_valid())         do_temp(opTypeCheck->_tmp3);
 947       if (opTypeCheck->_result->is_valid())       do_output(opTypeCheck->_result);
 948                                                   do_stub(opTypeCheck->_stub);
 949       break;
 950     }
 951 
 952 // LIR_OpCompareAndSwap
 953     case lir_cas_long:
 954     case lir_cas_obj:
 955     case lir_cas_int: {
 956       assert(op->as_OpCompareAndSwap() != NULL, "must be");
 957       LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
 958 
 959       assert(opCompareAndSwap->_addr->is_valid(),      "used");
 960       assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
 961       assert(opCompareAndSwap->_new_value->is_valid(), "used");
 962       if (opCompareAndSwap->_info)                    do_info(opCompareAndSwap->_info);
 963                                                       do_input(opCompareAndSwap->_addr);
 964                                                       do_temp(opCompareAndSwap->_addr);
 965                                                       do_input(opCompareAndSwap->_cmp_value);
 966                                                       do_temp(opCompareAndSwap->_cmp_value);
 967                                                       do_input(opCompareAndSwap->_new_value);
 968                                                       do_temp(opCompareAndSwap->_new_value);
 969       if (opCompareAndSwap->_tmp1->is_valid())        do_temp(opCompareAndSwap->_tmp1);
 970       if (opCompareAndSwap->_tmp2->is_valid())        do_temp(opCompareAndSwap->_tmp2);
 971       if (opCompareAndSwap->_result->is_valid())      do_output(opCompareAndSwap->_result);
 972 
 973       break;
 974     }
 975 
 976 
 977 // LIR_OpAllocArray;
 978     case lir_alloc_array: {
 979       assert(op->as_OpAllocArray() != NULL, "must be");
 980       LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
 981 
 982       if (opAllocArray->_info)                        do_info(opAllocArray->_info);
 983       if (opAllocArray->_klass->is_valid())           do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
 984       if (opAllocArray->_len->is_valid())             do_input(opAllocArray->_len);   do_temp(opAllocArray->_len);
 985       if (opAllocArray->_tmp1->is_valid())            do_temp(opAllocArray->_tmp1);
 986       if (opAllocArray->_tmp2->is_valid())            do_temp(opAllocArray->_tmp2);
 987       if (opAllocArray->_tmp3->is_valid())            do_temp(opAllocArray->_tmp3);
 988       if (opAllocArray->_tmp4->is_valid())            do_temp(opAllocArray->_tmp4);
 989       if (opAllocArray->_result->is_valid())          do_output(opAllocArray->_result);
 990                                                       do_stub(opAllocArray->_stub);
 991       break;
 992     }
 993 
 994 // LIR_OpProfileCall:
 995     case lir_profile_call: {
 996       assert(op->as_OpProfileCall() != NULL, "must be");
 997       LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
 998 
 999       if (opProfileCall->_recv->is_valid())              do_temp(opProfileCall->_recv);
1000       assert(opProfileCall->_mdo->is_valid(), "used");   do_temp(opProfileCall->_mdo);
1001       assert(opProfileCall->_tmp1->is_valid(), "used");  do_temp(opProfileCall->_tmp1);
1002       break;
1003     }
1004 
1005 // LIR_OpProfileType:
1006     case lir_profile_type: {
1007       assert(op->as_OpProfileType() != NULL, "must be");
1008       LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1009 
1010       do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1011       do_input(opProfileType->_obj);
1012       do_temp(opProfileType->_tmp);
1013       break;
1014     }
1015   default:
1016     ShouldNotReachHere();
1017   }
1018 }
1019 
1020 
1021 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1022   if (stub != NULL) {
1023     stub->visit(this);
1024   }
1025 }
1026 
1027 XHandlers* LIR_OpVisitState::all_xhandler() {
1028   XHandlers* result = NULL;
1029 
1030   int i;
1031   for (i = 0; i < info_count(); i++) {
1032     if (info_at(i)->exception_handlers() != NULL) {
1033       result = info_at(i)->exception_handlers();
1034       break;
1035     }
1036   }
1037 
1038 #ifdef ASSERT
1039   for (i = 0; i < info_count(); i++) {
1040     assert(info_at(i)->exception_handlers() == NULL ||
1041            info_at(i)->exception_handlers() == result,
1042            "only one xhandler list allowed per LIR-operation");
1043   }
1044 #endif
1045 
1046   if (result != NULL) {
1047     return result;
1048   } else {
1049     return new XHandlers();
1050   }
1051 
1052   return result;
1053 }
1054 
1055 
1056 #ifdef ASSERT
1057 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1058   visit(op);
1059 
1060   return opr_count(inputMode) == 0 &&
1061          opr_count(outputMode) == 0 &&
1062          opr_count(tempMode) == 0 &&
1063          info_count() == 0 &&
1064          !has_call() &&
1065          !has_slow_case();
1066 }
1067 #endif
1068 
1069 //---------------------------------------------------
1070 
1071 
1072 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1073   masm->emit_call(this);
1074 }
1075 
1076 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1077   masm->emit_rtcall(this);
1078 }
1079 
1080 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1081   masm->emit_opLabel(this);
1082 }
1083 
1084 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1085   masm->emit_arraycopy(this);
1086   masm->append_code_stub(stub());
1087 }
1088 
1089 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1090   masm->emit_updatecrc32(this);
1091 }
1092 
1093 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1094   masm->emit_op0(this);
1095 }
1096 
1097 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1098   masm->emit_op1(this);
1099 }
1100 
1101 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1102   masm->emit_alloc_obj(this);
1103   masm->append_code_stub(stub());
1104 }
1105 
1106 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1107   masm->emit_opBranch(this);
1108   if (stub()) {
1109     masm->append_code_stub(stub());
1110   }
1111 }
1112 
1113 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1114   masm->emit_opConvert(this);
1115   if (stub() != NULL) {
1116     masm->append_code_stub(stub());
1117   }
1118 }
1119 
1120 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1121   masm->emit_op2(this);
1122 }
1123 
1124 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1125   masm->emit_alloc_array(this);
1126   masm->append_code_stub(stub());
1127 }
1128 
1129 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1130   masm->emit_opTypeCheck(this);
1131   if (stub()) {
1132     masm->append_code_stub(stub());
1133   }
1134 }
1135 
1136 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1137   masm->emit_compare_and_swap(this);
1138 }
1139 
1140 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1141   masm->emit_op3(this);
1142 }
1143 
1144 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1145   masm->emit_lock(this);
1146   if (stub()) {
1147     masm->append_code_stub(stub());
1148   }
1149 }
1150 
1151 #ifdef ASSERT
1152 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1153   masm->emit_assert(this);
1154 }
1155 #endif
1156 
1157 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1158   masm->emit_delay(this);
1159 }
1160 
1161 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1162   masm->emit_profile_call(this);
1163 }
1164 
1165 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1166   masm->emit_profile_type(this);
1167 }
1168 
1169 // LIR_List
1170 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1171   : _operations(8)
1172   , _compilation(compilation)
1173 #ifndef PRODUCT
1174   , _block(block)
1175 #endif
1176 #ifdef ASSERT
1177   , _file(NULL)
1178   , _line(0)
1179 #endif
1180 { }
1181 
1182 
1183 #ifdef ASSERT
1184 void LIR_List::set_file_and_line(const char * file, int line) {
1185   const char * f = strrchr(file, '/');
1186   if (f == NULL) f = strrchr(file, '\\');
1187   if (f == NULL) {
1188     f = file;
1189   } else {
1190     f++;
1191   }
1192   _file = f;
1193   _line = line;
1194 }
1195 #endif
1196 
1197 
1198 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1199   assert(this == buffer->lir_list(), "wrong lir list");
1200   const int n = _operations.length();
1201 
1202   if (buffer->number_of_ops() > 0) {
1203     // increase size of instructions list
1204     _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1205     // insert ops from buffer into instructions list
1206     int op_index = buffer->number_of_ops() - 1;
1207     int ip_index = buffer->number_of_insertion_points() - 1;
1208     int from_index = n - 1;
1209     int to_index = _operations.length() - 1;
1210     for (; ip_index >= 0; ip_index --) {
1211       int index = buffer->index_at(ip_index);
1212       // make room after insertion point
1213       while (index < from_index) {
1214         _operations.at_put(to_index --, _operations.at(from_index --));
1215       }
1216       // insert ops from buffer
1217       for (int i = buffer->count_at(ip_index); i > 0; i --) {
1218         _operations.at_put(to_index --, buffer->op_at(op_index --));
1219       }
1220     }
1221   }
1222 
1223   buffer->finish();
1224 }
1225 
1226 
1227 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1228   assert(reg->type() == T_OBJECT, "bad reg");
1229   append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o),  reg, T_OBJECT, lir_patch_normal, info));
1230 }
1231 
1232 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1233   assert(reg->type() == T_METADATA, "bad reg");
1234   append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1235 }
1236 
1237 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1238   append(new LIR_Op1(
1239             lir_move,
1240             LIR_OprFact::address(addr),
1241             src,
1242             addr->type(),
1243             patch_code,
1244             info));
1245 }
1246 
1247 
1248 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1249   append(new LIR_Op1(
1250             lir_move,
1251             LIR_OprFact::address(address),
1252             dst,
1253             address->type(),
1254             patch_code,
1255             info, lir_move_volatile));
1256 }
1257 
1258 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1259   append(new LIR_Op1(
1260             lir_move,
1261             LIR_OprFact::address(new LIR_Address(base, offset, type)),
1262             dst,
1263             type,
1264             patch_code,
1265             info, lir_move_volatile));
1266 }
1267 
1268 
1269 void LIR_List::prefetch(LIR_Address* addr, bool is_store) {
1270   append(new LIR_Op1(
1271             is_store ? lir_prefetchw : lir_prefetchr,
1272             LIR_OprFact::address(addr)));
1273 }
1274 
1275 
1276 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1277   append(new LIR_Op1(
1278             lir_move,
1279             LIR_OprFact::intConst(v),
1280             LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1281             type,
1282             patch_code,
1283             info));
1284 }
1285 
1286 
1287 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1288   append(new LIR_Op1(
1289             lir_move,
1290             LIR_OprFact::oopConst(o),
1291             LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1292             type,
1293             patch_code,
1294             info));
1295 }
1296 
1297 
1298 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1299   append(new LIR_Op1(
1300             lir_move,
1301             src,
1302             LIR_OprFact::address(addr),
1303             addr->type(),
1304             patch_code,
1305             info));
1306 }
1307 
1308 
1309 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1310   append(new LIR_Op1(
1311             lir_move,
1312             src,
1313             LIR_OprFact::address(addr),
1314             addr->type(),
1315             patch_code,
1316             info,
1317             lir_move_volatile));
1318 }
1319 
1320 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1321   append(new LIR_Op1(
1322             lir_move,
1323             src,
1324             LIR_OprFact::address(new LIR_Address(base, offset, type)),
1325             type,
1326             patch_code,
1327             info, lir_move_volatile));
1328 }
1329 
1330 
1331 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1332   append(new LIR_Op3(
1333                     lir_idiv,
1334                     left,
1335                     right,
1336                     tmp,
1337                     res,
1338                     info));
1339 }
1340 
1341 
1342 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1343   append(new LIR_Op3(
1344                     lir_idiv,
1345                     left,
1346                     LIR_OprFact::intConst(right),
1347                     tmp,
1348                     res,
1349                     info));
1350 }
1351 
1352 
1353 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1354   append(new LIR_Op3(
1355                     lir_irem,
1356                     left,
1357                     right,
1358                     tmp,
1359                     res,
1360                     info));
1361 }
1362 
1363 
1364 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1365   append(new LIR_Op3(
1366                     lir_irem,
1367                     left,
1368                     LIR_OprFact::intConst(right),
1369                     tmp,
1370                     res,
1371                     info));
1372 }
1373 
1374 
1375 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1376   append(new LIR_Op2(
1377                     lir_cmp,
1378                     condition,
1379                     LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1380                     LIR_OprFact::intConst(c),
1381                     info));
1382 }
1383 
1384 
1385 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1386   append(new LIR_Op2(
1387                     lir_cmp,
1388                     condition,
1389                     reg,
1390                     LIR_OprFact::address(addr),
1391                     info));
1392 }
1393 
1394 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1395                                int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1396   append(new LIR_OpAllocObj(
1397                            klass,
1398                            dst,
1399                            t1,
1400                            t2,
1401                            t3,
1402                            t4,
1403                            header_size,
1404                            object_size,
1405                            init_check,
1406                            stub));
1407 }
1408 
1409 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1410   append(new LIR_OpAllocArray(
1411                            klass,
1412                            len,
1413                            dst,
1414                            t1,
1415                            t2,
1416                            t3,
1417                            t4,
1418                            type,
1419                            stub));
1420 }
1421 
1422 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1423  append(new LIR_Op2(
1424                     lir_shl,
1425                     value,
1426                     count,
1427                     dst,
1428                     tmp));
1429 }
1430 
1431 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1432  append(new LIR_Op2(
1433                     lir_shr,
1434                     value,
1435                     count,
1436                     dst,
1437                     tmp));
1438 }
1439 
1440 
1441 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1442  append(new LIR_Op2(
1443                     lir_ushr,
1444                     value,
1445                     count,
1446                     dst,
1447                     tmp));
1448 }
1449 
1450 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1451   append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1452                      left,
1453                      right,
1454                      dst));
1455 }
1456 
1457 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1458   append(new LIR_OpLock(
1459                     lir_lock,
1460                     hdr,
1461                     obj,
1462                     lock,
1463                     scratch,
1464                     stub,
1465                     info));
1466 }
1467 
1468 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1469   append(new LIR_OpLock(
1470                     lir_unlock,
1471                     hdr,
1472                     obj,
1473                     lock,
1474                     scratch,
1475                     stub,
1476                     NULL));
1477 }
1478 
1479 
1480 void check_LIR() {
1481   // cannot do the proper checking as PRODUCT and other modes return different results
1482   // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1483 }
1484 
1485 
1486 
1487 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1488                           LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1489                           CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1490                           ciMethod* profiled_method, int profiled_bci) {
1491   LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1492                                            tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1493   if (profiled_method != NULL) {
1494     c->set_profiled_method(profiled_method);
1495     c->set_profiled_bci(profiled_bci);
1496     c->set_should_profile(true);
1497   }
1498   append(c);
1499 }
1500 
1501 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1502   LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1503   if (profiled_method != NULL) {
1504     c->set_profiled_method(profiled_method);
1505     c->set_profiled_bci(profiled_bci);
1506     c->set_should_profile(true);
1507   }
1508   append(c);
1509 }
1510 
1511 
1512 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1513                            CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1514   LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1515   if (profiled_method != NULL) {
1516     c->set_profiled_method(profiled_method);
1517     c->set_profiled_bci(profiled_bci);
1518     c->set_should_profile(true);
1519   }
1520   append(c);
1521 }
1522 
1523 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) {
1524   if (deoptimize_on_null) {
1525     // Emit an explicit null check and deoptimize if opr is null
1526     CodeStub* deopt = new DeoptimizeStub(info);
1527     cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL));
1528     branch(lir_cond_equal, T_OBJECT, deopt);
1529   } else {
1530     // Emit an implicit null check
1531     append(new LIR_Op1(lir_null_check, opr, info));
1532   }
1533 }
1534 
1535 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1536                         LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1537   append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1538 }
1539 
1540 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1541                        LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1542   append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1543 }
1544 
1545 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1546                        LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1547   append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1548 }
1549 
1550 
1551 #ifdef PRODUCT
1552 
1553 void print_LIR(BlockList* blocks) {
1554 }
1555 
1556 #else
1557 // LIR_OprDesc
1558 void LIR_OprDesc::print() const {
1559   print(tty);
1560 }
1561 
1562 void LIR_OprDesc::print(outputStream* out) const {
1563   if (is_illegal()) {
1564     return;
1565   }
1566 
1567   out->print("[");
1568   if (is_pointer()) {
1569     pointer()->print_value_on(out);
1570   } else if (is_single_stack()) {
1571     out->print("stack:%d", single_stack_ix());
1572   } else if (is_double_stack()) {
1573     out->print("dbl_stack:%d",double_stack_ix());
1574   } else if (is_virtual()) {
1575     out->print("R%d", vreg_number());
1576   } else if (is_single_cpu()) {
1577     out->print("%s", as_register()->name());
1578   } else if (is_double_cpu()) {
1579     out->print("%s", as_register_hi()->name());
1580     out->print("%s", as_register_lo()->name());
1581 #if defined(AARCH64)
1582   } else if (is_single_fpu()) {
1583     out->print("fpu%d", fpu_regnr());
1584   } else if (is_double_fpu()) {
1585     out->print("fpu%d", fpu_regnrLo());
1586 #elif defined(X86)
1587   } else if (is_single_xmm()) {
1588     out->print("%s", as_xmm_float_reg()->name());
1589   } else if (is_double_xmm()) {
1590     out->print("%s", as_xmm_double_reg()->name());
1591   } else if (is_single_fpu()) {
1592     out->print("fpu%d", fpu_regnr());
1593   } else if (is_double_fpu()) {
1594     out->print("fpu%d", fpu_regnrLo());
1595 #elif defined(ARM)
1596   } else if (is_single_fpu()) {
1597     out->print("s%d", fpu_regnr());
1598   } else if (is_double_fpu()) {
1599     out->print("d%d", fpu_regnrLo() >> 1);
1600 #else
1601   } else if (is_single_fpu()) {
1602     out->print("%s", as_float_reg()->name());
1603   } else if (is_double_fpu()) {
1604     out->print("%s", as_double_reg()->name());
1605 #endif
1606 
1607   } else if (is_illegal()) {
1608     out->print("-");
1609   } else {
1610     out->print("Unknown Operand");
1611   }
1612   if (!is_illegal()) {
1613     out->print("|%c", type_char());
1614   }
1615   if (is_register() && is_last_use()) {
1616     out->print("(last_use)");
1617   }
1618   out->print("]");
1619 }
1620 
1621 
1622 // LIR_Address
1623 void LIR_Const::print_value_on(outputStream* out) const {
1624   switch (type()) {
1625     case T_ADDRESS:out->print("address:%d",as_jint());          break;
1626     case T_INT:    out->print("int:%d",   as_jint());           break;
1627     case T_LONG:   out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1628     case T_FLOAT:  out->print("flt:%f",   as_jfloat());         break;
1629     case T_DOUBLE: out->print("dbl:%f",   as_jdouble());        break;
1630     case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject()));        break;
1631     case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1632     default:       out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1633   }
1634 }
1635 
1636 // LIR_Address
1637 void LIR_Address::print_value_on(outputStream* out) const {
1638   out->print("Base:"); _base->print(out);
1639   if (!_index->is_illegal()) {
1640     out->print(" Index:"); _index->print(out);
1641     switch (scale()) {
1642     case times_1: break;
1643     case times_2: out->print(" * 2"); break;
1644     case times_4: out->print(" * 4"); break;
1645     case times_8: out->print(" * 8"); break;
1646     }
1647   }
1648   out->print(" Disp: " INTX_FORMAT, _disp);
1649 }
1650 
1651 // debug output of block header without InstructionPrinter
1652 //       (because phi functions are not necessary for LIR)
1653 static void print_block(BlockBegin* x) {
1654   // print block id
1655   BlockEnd* end = x->end();
1656   tty->print("B%d ", x->block_id());
1657 
1658   // print flags
1659   if (x->is_set(BlockBegin::std_entry_flag))               tty->print("std ");
1660   if (x->is_set(BlockBegin::osr_entry_flag))               tty->print("osr ");
1661   if (x->is_set(BlockBegin::exception_entry_flag))         tty->print("ex ");
1662   if (x->is_set(BlockBegin::subroutine_entry_flag))        tty->print("jsr ");
1663   if (x->is_set(BlockBegin::backward_branch_target_flag))  tty->print("bb ");
1664   if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1665   if (x->is_set(BlockBegin::linear_scan_loop_end_flag))    tty->print("le ");
1666 
1667   // print block bci range
1668   tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1669 
1670   // print predecessors and successors
1671   if (x->number_of_preds() > 0) {
1672     tty->print("preds: ");
1673     for (int i = 0; i < x->number_of_preds(); i ++) {
1674       tty->print("B%d ", x->pred_at(i)->block_id());
1675     }
1676   }
1677 
1678   if (x->number_of_sux() > 0) {
1679     tty->print("sux: ");
1680     for (int i = 0; i < x->number_of_sux(); i ++) {
1681       tty->print("B%d ", x->sux_at(i)->block_id());
1682     }
1683   }
1684 
1685   // print exception handlers
1686   if (x->number_of_exception_handlers() > 0) {
1687     tty->print("xhandler: ");
1688     for (int i = 0; i < x->number_of_exception_handlers();  i++) {
1689       tty->print("B%d ", x->exception_handler_at(i)->block_id());
1690     }
1691   }
1692 
1693   tty->cr();
1694 }
1695 
1696 void print_LIR(BlockList* blocks) {
1697   tty->print_cr("LIR:");
1698   int i;
1699   for (i = 0; i < blocks->length(); i++) {
1700     BlockBegin* bb = blocks->at(i);
1701     print_block(bb);
1702     tty->print("__id_Instruction___________________________________________"); tty->cr();
1703     bb->lir()->print_instructions();
1704   }
1705 }
1706 
1707 void LIR_List::print_instructions() {
1708   for (int i = 0; i < _operations.length(); i++) {
1709     _operations.at(i)->print(); tty->cr();
1710   }
1711   tty->cr();
1712 }
1713 
1714 // LIR_Ops printing routines
1715 // LIR_Op
1716 void LIR_Op::print_on(outputStream* out) const {
1717   if (id() != -1 || PrintCFGToFile) {
1718     out->print("%4d ", id());
1719   } else {
1720     out->print("     ");
1721   }
1722   out->print("%s ", name());
1723   print_instr(out);
1724   if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1725 #ifdef ASSERT
1726   if (Verbose && _file != NULL) {
1727     out->print(" (%s:%d)", _file, _line);
1728   }
1729 #endif
1730 }
1731 
1732 const char * LIR_Op::name() const {
1733   const char* s = NULL;
1734   switch(code()) {
1735      // LIR_Op0
1736      case lir_membar:                s = "membar";        break;
1737      case lir_membar_acquire:        s = "membar_acquire"; break;
1738      case lir_membar_release:        s = "membar_release"; break;
1739      case lir_membar_loadload:       s = "membar_loadload";   break;
1740      case lir_membar_storestore:     s = "membar_storestore"; break;
1741      case lir_membar_loadstore:      s = "membar_loadstore";  break;
1742      case lir_membar_storeload:      s = "membar_storeload";  break;
1743      case lir_word_align:            s = "word_align";    break;
1744      case lir_label:                 s = "label";         break;
1745      case lir_nop:                   s = "nop";           break;
1746      case lir_backwardbranch_target: s = "backbranch";    break;
1747      case lir_std_entry:             s = "std_entry";     break;
1748      case lir_osr_entry:             s = "osr_entry";     break;
1749      case lir_build_frame:           s = "build_frm";     break;
1750      case lir_fpop_raw:              s = "fpop_raw";      break;
1751      case lir_24bit_FPU:             s = "24bit_FPU";     break;
1752      case lir_reset_FPU:             s = "reset_FPU";     break;
1753      case lir_breakpoint:            s = "breakpoint";    break;
1754      case lir_get_thread:            s = "get_thread";    break;
1755      // LIR_Op1
1756      case lir_fxch:                  s = "fxch";          break;
1757      case lir_fld:                   s = "fld";           break;
1758      case lir_ffree:                 s = "ffree";         break;
1759      case lir_push:                  s = "push";          break;
1760      case lir_pop:                   s = "pop";           break;
1761      case lir_null_check:            s = "null_check";    break;
1762      case lir_return:                s = "return";        break;
1763      case lir_safepoint:             s = "safepoint";     break;
1764      case lir_neg:                   s = "neg";           break;
1765      case lir_leal:                  s = "leal";          break;
1766      case lir_branch:                s = "branch";        break;
1767      case lir_cond_float_branch:     s = "flt_cond_br";   break;
1768      case lir_move:                  s = "move";          break;
1769      case lir_roundfp:               s = "roundfp";       break;
1770      case lir_rtcall:                s = "rtcall";        break;
1771      case lir_throw:                 s = "throw";         break;
1772      case lir_unwind:                s = "unwind";        break;
1773      case lir_convert:               s = "convert";       break;
1774      case lir_alloc_object:          s = "alloc_obj";     break;
1775      case lir_monaddr:               s = "mon_addr";      break;
1776      case lir_pack64:                s = "pack64";        break;
1777      case lir_unpack64:              s = "unpack64";      break;
1778      // LIR_Op2
1779      case lir_cmp:                   s = "cmp";           break;
1780      case lir_cmp_l2i:               s = "cmp_l2i";       break;
1781      case lir_ucmp_fd2i:             s = "ucomp_fd2i";    break;
1782      case lir_cmp_fd2i:              s = "comp_fd2i";     break;
1783      case lir_cmove:                 s = "cmove";         break;
1784      case lir_add:                   s = "add";           break;
1785      case lir_sub:                   s = "sub";           break;
1786      case lir_mul:                   s = "mul";           break;
1787      case lir_mul_strictfp:          s = "mul_strictfp";  break;
1788      case lir_div:                   s = "div";           break;
1789      case lir_div_strictfp:          s = "div_strictfp";  break;
1790      case lir_rem:                   s = "rem";           break;
1791      case lir_abs:                   s = "abs";           break;
1792      case lir_sqrt:                  s = "sqrt";          break;
1793      case lir_sin:                   s = "sin";           break;
1794      case lir_cos:                   s = "cos";           break;
1795      case lir_tan:                   s = "tan";           break;
1796      case lir_log:                   s = "log";           break;
1797      case lir_log10:                 s = "log10";         break;
1798      case lir_exp:                   s = "exp";           break;
1799      case lir_pow:                   s = "pow";           break;
1800      case lir_logic_and:             s = "logic_and";     break;
1801      case lir_logic_or:              s = "logic_or";      break;
1802      case lir_logic_xor:             s = "logic_xor";     break;
1803      case lir_shl:                   s = "shift_left";    break;
1804      case lir_shr:                   s = "shift_right";   break;
1805      case lir_ushr:                  s = "ushift_right";  break;
1806      case lir_alloc_array:           s = "alloc_array";   break;
1807      case lir_xadd:                  s = "xadd";          break;
1808      case lir_xchg:                  s = "xchg";          break;
1809      // LIR_Op3
1810      case lir_idiv:                  s = "idiv";          break;
1811      case lir_irem:                  s = "irem";          break;
1812      // LIR_OpJavaCall
1813      case lir_static_call:           s = "static";        break;
1814      case lir_optvirtual_call:       s = "optvirtual";    break;
1815      case lir_icvirtual_call:        s = "icvirtual";     break;
1816      case lir_virtual_call:          s = "virtual";       break;
1817      case lir_dynamic_call:          s = "dynamic";       break;
1818      // LIR_OpArrayCopy
1819      case lir_arraycopy:             s = "arraycopy";     break;
1820      // LIR_OpUpdateCRC32
1821      case lir_updatecrc32:           s = "updatecrc32";   break;
1822      // LIR_OpLock
1823      case lir_lock:                  s = "lock";          break;
1824      case lir_unlock:                s = "unlock";        break;
1825      // LIR_OpDelay
1826      case lir_delay_slot:            s = "delay";         break;
1827      // LIR_OpTypeCheck
1828      case lir_instanceof:            s = "instanceof";    break;
1829      case lir_checkcast:             s = "checkcast";     break;
1830      case lir_store_check:           s = "store_check";   break;
1831      // LIR_OpCompareAndSwap
1832      case lir_cas_long:              s = "cas_long";      break;
1833      case lir_cas_obj:               s = "cas_obj";      break;
1834      case lir_cas_int:               s = "cas_int";      break;
1835      // LIR_OpProfileCall
1836      case lir_profile_call:          s = "profile_call";  break;
1837      // LIR_OpProfileType
1838      case lir_profile_type:          s = "profile_type";  break;
1839      // LIR_OpAssert
1840 #ifdef ASSERT
1841      case lir_assert:                s = "assert";        break;
1842 #endif
1843      case lir_none:                  ShouldNotReachHere();break;
1844     default:                         s = "illegal_op";    break;
1845   }
1846   return s;
1847 }
1848 
1849 // LIR_OpJavaCall
1850 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1851   out->print("call: ");
1852   out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
1853   if (receiver()->is_valid()) {
1854     out->print(" [recv: ");   receiver()->print(out);   out->print("]");
1855   }
1856   if (result_opr()->is_valid()) {
1857     out->print(" [result: "); result_opr()->print(out); out->print("]");
1858   }
1859 }
1860 
1861 // LIR_OpLabel
1862 void LIR_OpLabel::print_instr(outputStream* out) const {
1863   out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
1864 }
1865 
1866 // LIR_OpArrayCopy
1867 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1868   src()->print(out);     out->print(" ");
1869   src_pos()->print(out); out->print(" ");
1870   dst()->print(out);     out->print(" ");
1871   dst_pos()->print(out); out->print(" ");
1872   length()->print(out);  out->print(" ");
1873   tmp()->print(out);     out->print(" ");
1874 }
1875 
1876 // LIR_OpUpdateCRC32
1877 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
1878   crc()->print(out);     out->print(" ");
1879   val()->print(out);     out->print(" ");
1880   result_opr()->print(out); out->print(" ");
1881 }
1882 
1883 // LIR_OpCompareAndSwap
1884 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1885   addr()->print(out);      out->print(" ");
1886   cmp_value()->print(out); out->print(" ");
1887   new_value()->print(out); out->print(" ");
1888   tmp1()->print(out);      out->print(" ");
1889   tmp2()->print(out);      out->print(" ");
1890 
1891 }
1892 
1893 // LIR_Op0
1894 void LIR_Op0::print_instr(outputStream* out) const {
1895   result_opr()->print(out);
1896 }
1897 
1898 // LIR_Op1
1899 const char * LIR_Op1::name() const {
1900   if (code() == lir_move) {
1901     switch (move_kind()) {
1902     case lir_move_normal:
1903       return "move";
1904     case lir_move_unaligned:
1905       return "unaligned move";
1906     case lir_move_volatile:
1907       return "volatile_move";
1908     case lir_move_wide:
1909       return "wide_move";
1910     default:
1911       ShouldNotReachHere();
1912     return "illegal_op";
1913     }
1914   } else {
1915     return LIR_Op::name();
1916   }
1917 }
1918 
1919 
1920 void LIR_Op1::print_instr(outputStream* out) const {
1921   _opr->print(out);         out->print(" ");
1922   result_opr()->print(out); out->print(" ");
1923   print_patch_code(out, patch_code());
1924 }
1925 
1926 
1927 // LIR_Op1
1928 void LIR_OpRTCall::print_instr(outputStream* out) const {
1929   intx a = (intx)addr();
1930   out->print("%s", Runtime1::name_for_address(addr()));
1931   out->print(" ");
1932   tmp()->print(out);
1933 }
1934 
1935 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1936   switch(code) {
1937     case lir_patch_none:                                 break;
1938     case lir_patch_low:    out->print("[patch_low]");    break;
1939     case lir_patch_high:   out->print("[patch_high]");   break;
1940     case lir_patch_normal: out->print("[patch_normal]"); break;
1941     default: ShouldNotReachHere();
1942   }
1943 }
1944 
1945 // LIR_OpBranch
1946 void LIR_OpBranch::print_instr(outputStream* out) const {
1947   print_condition(out, cond());             out->print(" ");
1948   if (block() != NULL) {
1949     out->print("[B%d] ", block()->block_id());
1950   } else if (stub() != NULL) {
1951     out->print("[");
1952     stub()->print_name(out);
1953     out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1954     if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1955   } else {
1956     out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1957   }
1958   if (ublock() != NULL) {
1959     out->print("unordered: [B%d] ", ublock()->block_id());
1960   }
1961 }
1962 
1963 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1964   switch(cond) {
1965     case lir_cond_equal:           out->print("[EQ]");      break;
1966     case lir_cond_notEqual:        out->print("[NE]");      break;
1967     case lir_cond_less:            out->print("[LT]");      break;
1968     case lir_cond_lessEqual:       out->print("[LE]");      break;
1969     case lir_cond_greaterEqual:    out->print("[GE]");      break;
1970     case lir_cond_greater:         out->print("[GT]");      break;
1971     case lir_cond_belowEqual:      out->print("[BE]");      break;
1972     case lir_cond_aboveEqual:      out->print("[AE]");      break;
1973     case lir_cond_always:          out->print("[AL]");      break;
1974     default:                       out->print("[%d]",cond); break;
1975   }
1976 }
1977 
1978 // LIR_OpConvert
1979 void LIR_OpConvert::print_instr(outputStream* out) const {
1980   print_bytecode(out, bytecode());
1981   in_opr()->print(out);                  out->print(" ");
1982   result_opr()->print(out);              out->print(" ");
1983 #if defined(PPC) || defined(TARGET_ARCH_aarch64)
1984   if(tmp1()->is_valid()) {
1985     tmp1()->print(out); out->print(" ");
1986     tmp2()->print(out); out->print(" ");
1987   }
1988 #endif
1989 }
1990 
1991 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1992   switch(code) {
1993     case Bytecodes::_d2f: out->print("[d2f] "); break;
1994     case Bytecodes::_d2i: out->print("[d2i] "); break;
1995     case Bytecodes::_d2l: out->print("[d2l] "); break;
1996     case Bytecodes::_f2d: out->print("[f2d] "); break;
1997     case Bytecodes::_f2i: out->print("[f2i] "); break;
1998     case Bytecodes::_f2l: out->print("[f2l] "); break;
1999     case Bytecodes::_i2b: out->print("[i2b] "); break;
2000     case Bytecodes::_i2c: out->print("[i2c] "); break;
2001     case Bytecodes::_i2d: out->print("[i2d] "); break;
2002     case Bytecodes::_i2f: out->print("[i2f] "); break;
2003     case Bytecodes::_i2l: out->print("[i2l] "); break;
2004     case Bytecodes::_i2s: out->print("[i2s] "); break;
2005     case Bytecodes::_l2i: out->print("[l2i] "); break;
2006     case Bytecodes::_l2f: out->print("[l2f] "); break;
2007     case Bytecodes::_l2d: out->print("[l2d] "); break;
2008     default:
2009       out->print("[?%d]",code);
2010     break;
2011   }
2012 }
2013 
2014 void LIR_OpAllocObj::print_instr(outputStream* out) const {
2015   klass()->print(out);                      out->print(" ");
2016   obj()->print(out);                        out->print(" ");
2017   tmp1()->print(out);                       out->print(" ");
2018   tmp2()->print(out);                       out->print(" ");
2019   tmp3()->print(out);                       out->print(" ");
2020   tmp4()->print(out);                       out->print(" ");
2021   out->print("[hdr:%d]", header_size()); out->print(" ");
2022   out->print("[obj:%d]", object_size()); out->print(" ");
2023   out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2024 }
2025 
2026 void LIR_OpRoundFP::print_instr(outputStream* out) const {
2027   _opr->print(out);         out->print(" ");
2028   tmp()->print(out);        out->print(" ");
2029   result_opr()->print(out); out->print(" ");
2030 }
2031 
2032 // LIR_Op2
2033 void LIR_Op2::print_instr(outputStream* out) const {
2034   if (code() == lir_cmove) {
2035     print_condition(out, condition());         out->print(" ");
2036   }
2037   in_opr1()->print(out);    out->print(" ");
2038   in_opr2()->print(out);    out->print(" ");
2039   if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out);    out->print(" "); }
2040   if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out);    out->print(" "); }
2041   if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out);    out->print(" "); }
2042   if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out);    out->print(" "); }
2043   if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out);    out->print(" "); }
2044   result_opr()->print(out);
2045 }
2046 
2047 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2048   klass()->print(out);                   out->print(" ");
2049   len()->print(out);                     out->print(" ");
2050   obj()->print(out);                     out->print(" ");
2051   tmp1()->print(out);                    out->print(" ");
2052   tmp2()->print(out);                    out->print(" ");
2053   tmp3()->print(out);                    out->print(" ");
2054   tmp4()->print(out);                    out->print(" ");
2055   out->print("[type:0x%x]", type());     out->print(" ");
2056   out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2057 }
2058 
2059 
2060 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2061   object()->print(out);                  out->print(" ");
2062   if (code() == lir_store_check) {
2063     array()->print(out);                 out->print(" ");
2064   }
2065   if (code() != lir_store_check) {
2066     klass()->print_name_on(out);         out->print(" ");
2067     if (fast_check())                 out->print("fast_check ");
2068   }
2069   tmp1()->print(out);                    out->print(" ");
2070   tmp2()->print(out);                    out->print(" ");
2071   tmp3()->print(out);                    out->print(" ");
2072   result_opr()->print(out);              out->print(" ");
2073   if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2074 }
2075 
2076 
2077 // LIR_Op3
2078 void LIR_Op3::print_instr(outputStream* out) const {
2079   in_opr1()->print(out);    out->print(" ");
2080   in_opr2()->print(out);    out->print(" ");
2081   in_opr3()->print(out);    out->print(" ");
2082   result_opr()->print(out);
2083 }
2084 
2085 
2086 void LIR_OpLock::print_instr(outputStream* out) const {
2087   hdr_opr()->print(out);   out->print(" ");
2088   obj_opr()->print(out);   out->print(" ");
2089   lock_opr()->print(out);  out->print(" ");
2090   if (_scratch->is_valid()) {
2091     _scratch->print(out);  out->print(" ");
2092   }
2093   out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2094 }
2095 
2096 #ifdef ASSERT
2097 void LIR_OpAssert::print_instr(outputStream* out) const {
2098   print_condition(out, condition()); out->print(" ");
2099   in_opr1()->print(out);             out->print(" ");
2100   in_opr2()->print(out);             out->print(", \"");
2101   out->print("%s", msg());          out->print("\"");
2102 }
2103 #endif
2104 
2105 
2106 void LIR_OpDelay::print_instr(outputStream* out) const {
2107   _op->print_on(out);
2108 }
2109 
2110 
2111 // LIR_OpProfileCall
2112 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2113   profiled_method()->name()->print_symbol_on(out);
2114   out->print(".");
2115   profiled_method()->holder()->name()->print_symbol_on(out);
2116   out->print(" @ %d ", profiled_bci());
2117   mdo()->print(out);           out->print(" ");
2118   recv()->print(out);          out->print(" ");
2119   tmp1()->print(out);          out->print(" ");
2120 }
2121 
2122 // LIR_OpProfileType
2123 void LIR_OpProfileType::print_instr(outputStream* out) const {
2124   out->print("exact = ");
2125   if  (exact_klass() == NULL) {
2126     out->print("unknown");
2127   } else {
2128     exact_klass()->print_name_on(out);
2129   }
2130   out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2131   out->print(" ");
2132   mdp()->print(out);          out->print(" ");
2133   obj()->print(out);          out->print(" ");
2134   tmp()->print(out);          out->print(" ");
2135 }
2136 
2137 #endif // PRODUCT
2138 
2139 // Implementation of LIR_InsertionBuffer
2140 
2141 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2142   assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2143 
2144   int i = number_of_insertion_points() - 1;
2145   if (i < 0 || index_at(i) < index) {
2146     append_new(index, 1);
2147   } else {
2148     assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2149     assert(count_at(i) > 0, "check");
2150     set_count_at(i, count_at(i) + 1);
2151   }
2152   _ops.push(op);
2153 
2154   DEBUG_ONLY(verify());
2155 }
2156 
2157 #ifdef ASSERT
2158 void LIR_InsertionBuffer::verify() {
2159   int sum = 0;
2160   int prev_idx = -1;
2161 
2162   for (int i = 0; i < number_of_insertion_points(); i++) {
2163     assert(prev_idx < index_at(i), "index must be ordered ascending");
2164     sum += count_at(i);
2165   }
2166   assert(sum == number_of_ops(), "wrong total sum");
2167 }
2168 #endif