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src/share/vm/c1/c1_LIR.cpp

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  50 
  51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
  52   assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
  53   return FrameMap::nr2xmmreg(xmm_regnrLo());
  54 }
  55 
  56 #endif // X86
  57 
  58 #if defined(SPARC) || defined(PPC)
  59 
  60 FloatRegister LIR_OprDesc::as_float_reg() const {
  61   return FrameMap::nr2floatreg(fpu_regnr());
  62 }
  63 
  64 FloatRegister LIR_OprDesc::as_double_reg() const {
  65   return FrameMap::nr2floatreg(fpu_regnrHi());
  66 }
  67 
  68 #endif
  69 
  70 #ifdef ARM
  71 
  72 FloatRegister LIR_OprDesc::as_float_reg() const {
  73   return as_FloatRegister(fpu_regnr());
  74 }
  75 
  76 FloatRegister LIR_OprDesc::as_double_reg() const {
  77   return as_FloatRegister(fpu_regnrLo());
  78 }
  79 
  80 #endif
  81 
  82 
  83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
  84 
  85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
  86   ValueTag tag = type->tag();
  87   switch (tag) {
  88   case metaDataTag : {
  89     ClassConstant* c = type->as_ClassConstant();
  90     if (c != NULL && !c->value()->is_loaded()) {


 132   int elem_size = type2aelembytes(type);
 133   switch (elem_size) {
 134   case 1: return LIR_Address::times_1;
 135   case 2: return LIR_Address::times_2;
 136   case 4: return LIR_Address::times_4;
 137   case 8: return LIR_Address::times_8;
 138   }
 139   ShouldNotReachHere();
 140   return LIR_Address::times_1;
 141 }
 142 
 143 
 144 #ifndef PRODUCT
 145 void LIR_Address::verify0() const {
 146 #if defined(SPARC) || defined(PPC)
 147   assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
 148   assert(disp() == 0 || index()->is_illegal(), "can't have both");
 149 #endif
 150 #ifdef _LP64
 151   assert(base()->is_cpu_register(), "wrong base operand");

 152   assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");



 153   assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
 154          "wrong type for addresses");
 155 #else
 156   assert(base()->is_single_cpu(), "wrong base operand");
 157   assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
 158   assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
 159          "wrong type for addresses");
 160 #endif
 161 }
 162 #endif
 163 
 164 
 165 //---------------------------------------------------
 166 
 167 char LIR_OprDesc::type_char(BasicType t) {
 168   switch (t) {
 169     case T_ARRAY:
 170       t = T_OBJECT;
 171     case T_BOOLEAN:
 172     case T_CHAR:


 539     {
 540       assert(op->as_Op1() != NULL, "must be");
 541       LIR_Op1* op1 = (LIR_Op1*)op;
 542 
 543       assert(op1->_info != NULL, "");  do_info(op1->_info);
 544       if (op1->_opr->is_valid())       do_temp(op1->_opr); // safepoints on SPARC need temporary register
 545       assert(op1->_result->is_illegal(), "safepoint does not produce value");
 546 
 547       break;
 548     }
 549 
 550 // LIR_OpConvert;
 551     case lir_convert:        // input and result always valid, info always invalid
 552     {
 553       assert(op->as_OpConvert() != NULL, "must be");
 554       LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
 555 
 556       assert(opConvert->_info == NULL, "must be");
 557       if (opConvert->_opr->is_valid())       do_input(opConvert->_opr);
 558       if (opConvert->_result->is_valid())    do_output(opConvert->_result);
 559 #ifdef PPC
 560       if (opConvert->_tmp1->is_valid())      do_temp(opConvert->_tmp1);
 561       if (opConvert->_tmp2->is_valid())      do_temp(opConvert->_tmp2);
 562 #endif
 563       do_stub(opConvert->_stub);
 564 
 565       break;
 566     }
 567 
 568 // LIR_OpBranch;
 569     case lir_branch:                   // may have info, input and result register always invalid
 570     case lir_cond_float_branch:        // may have info, input and result register always invalid
 571     {
 572       assert(op->as_OpBranch() != NULL, "must be");
 573       LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
 574 
 575       if (opBranch->_info != NULL)     do_info(opBranch->_info);
 576       assert(opBranch->_result->is_illegal(), "not used");
 577       if (opBranch->_stub != NULL)     opBranch->stub()->visit(this);
 578 
 579       break;


1557 
1558 void LIR_OprDesc::print(outputStream* out) const {
1559   if (is_illegal()) {
1560     return;
1561   }
1562 
1563   out->print("[");
1564   if (is_pointer()) {
1565     pointer()->print_value_on(out);
1566   } else if (is_single_stack()) {
1567     out->print("stack:%d", single_stack_ix());
1568   } else if (is_double_stack()) {
1569     out->print("dbl_stack:%d",double_stack_ix());
1570   } else if (is_virtual()) {
1571     out->print("R%d", vreg_number());
1572   } else if (is_single_cpu()) {
1573     out->print("%s", as_register()->name());
1574   } else if (is_double_cpu()) {
1575     out->print("%s", as_register_hi()->name());
1576     out->print("%s", as_register_lo()->name());
1577 #if defined(X86)





1578   } else if (is_single_xmm()) {
1579     out->print("%s", as_xmm_float_reg()->name());
1580   } else if (is_double_xmm()) {
1581     out->print("%s", as_xmm_double_reg()->name());
1582   } else if (is_single_fpu()) {
1583     out->print("fpu%d", fpu_regnr());
1584   } else if (is_double_fpu()) {
1585     out->print("fpu%d", fpu_regnrLo());
1586 #elif defined(ARM)
1587   } else if (is_single_fpu()) {
1588     out->print("s%d", fpu_regnr());
1589   } else if (is_double_fpu()) {
1590     out->print("d%d", fpu_regnrLo() >> 1);
1591 #else
1592   } else if (is_single_fpu()) {
1593     out->print("%s", as_float_reg()->name());
1594   } else if (is_double_fpu()) {
1595     out->print("%s", as_double_reg()->name());
1596 #endif
1597 


1954 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1955   switch(cond) {
1956     case lir_cond_equal:           out->print("[EQ]");      break;
1957     case lir_cond_notEqual:        out->print("[NE]");      break;
1958     case lir_cond_less:            out->print("[LT]");      break;
1959     case lir_cond_lessEqual:       out->print("[LE]");      break;
1960     case lir_cond_greaterEqual:    out->print("[GE]");      break;
1961     case lir_cond_greater:         out->print("[GT]");      break;
1962     case lir_cond_belowEqual:      out->print("[BE]");      break;
1963     case lir_cond_aboveEqual:      out->print("[AE]");      break;
1964     case lir_cond_always:          out->print("[AL]");      break;
1965     default:                       out->print("[%d]",cond); break;
1966   }
1967 }
1968 
1969 // LIR_OpConvert
1970 void LIR_OpConvert::print_instr(outputStream* out) const {
1971   print_bytecode(out, bytecode());
1972   in_opr()->print(out);                  out->print(" ");
1973   result_opr()->print(out);              out->print(" ");
1974 #ifdef PPC
1975   if(tmp1()->is_valid()) {
1976     tmp1()->print(out); out->print(" ");
1977     tmp2()->print(out); out->print(" ");
1978   }
1979 #endif
1980 }
1981 
1982 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1983   switch(code) {
1984     case Bytecodes::_d2f: out->print("[d2f] "); break;
1985     case Bytecodes::_d2i: out->print("[d2i] "); break;
1986     case Bytecodes::_d2l: out->print("[d2l] "); break;
1987     case Bytecodes::_f2d: out->print("[f2d] "); break;
1988     case Bytecodes::_f2i: out->print("[f2i] "); break;
1989     case Bytecodes::_f2l: out->print("[f2l] "); break;
1990     case Bytecodes::_i2b: out->print("[i2b] "); break;
1991     case Bytecodes::_i2c: out->print("[i2c] "); break;
1992     case Bytecodes::_i2d: out->print("[i2d] "); break;
1993     case Bytecodes::_i2f: out->print("[i2f] "); break;
1994     case Bytecodes::_i2l: out->print("[i2l] "); break;




  50 
  51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
  52   assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
  53   return FrameMap::nr2xmmreg(xmm_regnrLo());
  54 }
  55 
  56 #endif // X86
  57 
  58 #if defined(SPARC) || defined(PPC)
  59 
  60 FloatRegister LIR_OprDesc::as_float_reg() const {
  61   return FrameMap::nr2floatreg(fpu_regnr());
  62 }
  63 
  64 FloatRegister LIR_OprDesc::as_double_reg() const {
  65   return FrameMap::nr2floatreg(fpu_regnrHi());
  66 }
  67 
  68 #endif
  69 
  70 #if defined(ARM) || defined (TARGET_ARCH_aarch64)
  71 
  72 FloatRegister LIR_OprDesc::as_float_reg() const {
  73   return as_FloatRegister(fpu_regnr());
  74 }
  75 
  76 FloatRegister LIR_OprDesc::as_double_reg() const {
  77   return as_FloatRegister(fpu_regnrLo());
  78 }
  79 
  80 #endif
  81 
  82 
  83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
  84 
  85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
  86   ValueTag tag = type->tag();
  87   switch (tag) {
  88   case metaDataTag : {
  89     ClassConstant* c = type->as_ClassConstant();
  90     if (c != NULL && !c->value()->is_loaded()) {


 132   int elem_size = type2aelembytes(type);
 133   switch (elem_size) {
 134   case 1: return LIR_Address::times_1;
 135   case 2: return LIR_Address::times_2;
 136   case 4: return LIR_Address::times_4;
 137   case 8: return LIR_Address::times_8;
 138   }
 139   ShouldNotReachHere();
 140   return LIR_Address::times_1;
 141 }
 142 
 143 
 144 #ifndef PRODUCT
 145 void LIR_Address::verify0() const {
 146 #if defined(SPARC) || defined(PPC)
 147   assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
 148   assert(disp() == 0 || index()->is_illegal(), "can't have both");
 149 #endif
 150 #ifdef _LP64
 151   assert(base()->is_cpu_register(), "wrong base operand");
 152 #ifndef TARGET_ARCH_aarch64
 153   assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
 154 #else
 155   assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
 156 #endif
 157   assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
 158          "wrong type for addresses");
 159 #else
 160   assert(base()->is_single_cpu(), "wrong base operand");
 161   assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
 162   assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
 163          "wrong type for addresses");
 164 #endif
 165 }
 166 #endif
 167 
 168 
 169 //---------------------------------------------------
 170 
 171 char LIR_OprDesc::type_char(BasicType t) {
 172   switch (t) {
 173     case T_ARRAY:
 174       t = T_OBJECT;
 175     case T_BOOLEAN:
 176     case T_CHAR:


 543     {
 544       assert(op->as_Op1() != NULL, "must be");
 545       LIR_Op1* op1 = (LIR_Op1*)op;
 546 
 547       assert(op1->_info != NULL, "");  do_info(op1->_info);
 548       if (op1->_opr->is_valid())       do_temp(op1->_opr); // safepoints on SPARC need temporary register
 549       assert(op1->_result->is_illegal(), "safepoint does not produce value");
 550 
 551       break;
 552     }
 553 
 554 // LIR_OpConvert;
 555     case lir_convert:        // input and result always valid, info always invalid
 556     {
 557       assert(op->as_OpConvert() != NULL, "must be");
 558       LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
 559 
 560       assert(opConvert->_info == NULL, "must be");
 561       if (opConvert->_opr->is_valid())       do_input(opConvert->_opr);
 562       if (opConvert->_result->is_valid())    do_output(opConvert->_result);
 563 #if defined(PPC) || defined(TARGET_ARCH_aarch64)
 564       if (opConvert->_tmp1->is_valid())      do_temp(opConvert->_tmp1);
 565       if (opConvert->_tmp2->is_valid())      do_temp(opConvert->_tmp2);
 566 #endif
 567       do_stub(opConvert->_stub);
 568 
 569       break;
 570     }
 571 
 572 // LIR_OpBranch;
 573     case lir_branch:                   // may have info, input and result register always invalid
 574     case lir_cond_float_branch:        // may have info, input and result register always invalid
 575     {
 576       assert(op->as_OpBranch() != NULL, "must be");
 577       LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
 578 
 579       if (opBranch->_info != NULL)     do_info(opBranch->_info);
 580       assert(opBranch->_result->is_illegal(), "not used");
 581       if (opBranch->_stub != NULL)     opBranch->stub()->visit(this);
 582 
 583       break;


1561 
1562 void LIR_OprDesc::print(outputStream* out) const {
1563   if (is_illegal()) {
1564     return;
1565   }
1566 
1567   out->print("[");
1568   if (is_pointer()) {
1569     pointer()->print_value_on(out);
1570   } else if (is_single_stack()) {
1571     out->print("stack:%d", single_stack_ix());
1572   } else if (is_double_stack()) {
1573     out->print("dbl_stack:%d",double_stack_ix());
1574   } else if (is_virtual()) {
1575     out->print("R%d", vreg_number());
1576   } else if (is_single_cpu()) {
1577     out->print("%s", as_register()->name());
1578   } else if (is_double_cpu()) {
1579     out->print("%s", as_register_hi()->name());
1580     out->print("%s", as_register_lo()->name());
1581 #if defined(AARCH64)
1582   } else if (is_single_fpu()) {
1583     out->print("fpu%d", fpu_regnr());
1584   } else if (is_double_fpu()) {
1585     out->print("fpu%d", fpu_regnrLo());
1586 #elif defined(X86)
1587   } else if (is_single_xmm()) {
1588     out->print("%s", as_xmm_float_reg()->name());
1589   } else if (is_double_xmm()) {
1590     out->print("%s", as_xmm_double_reg()->name());
1591   } else if (is_single_fpu()) {
1592     out->print("fpu%d", fpu_regnr());
1593   } else if (is_double_fpu()) {
1594     out->print("fpu%d", fpu_regnrLo());
1595 #elif defined(ARM)
1596   } else if (is_single_fpu()) {
1597     out->print("s%d", fpu_regnr());
1598   } else if (is_double_fpu()) {
1599     out->print("d%d", fpu_regnrLo() >> 1);
1600 #else
1601   } else if (is_single_fpu()) {
1602     out->print("%s", as_float_reg()->name());
1603   } else if (is_double_fpu()) {
1604     out->print("%s", as_double_reg()->name());
1605 #endif
1606 


1963 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1964   switch(cond) {
1965     case lir_cond_equal:           out->print("[EQ]");      break;
1966     case lir_cond_notEqual:        out->print("[NE]");      break;
1967     case lir_cond_less:            out->print("[LT]");      break;
1968     case lir_cond_lessEqual:       out->print("[LE]");      break;
1969     case lir_cond_greaterEqual:    out->print("[GE]");      break;
1970     case lir_cond_greater:         out->print("[GT]");      break;
1971     case lir_cond_belowEqual:      out->print("[BE]");      break;
1972     case lir_cond_aboveEqual:      out->print("[AE]");      break;
1973     case lir_cond_always:          out->print("[AL]");      break;
1974     default:                       out->print("[%d]",cond); break;
1975   }
1976 }
1977 
1978 // LIR_OpConvert
1979 void LIR_OpConvert::print_instr(outputStream* out) const {
1980   print_bytecode(out, bytecode());
1981   in_opr()->print(out);                  out->print(" ");
1982   result_opr()->print(out);              out->print(" ");
1983 #if defined(PPC) || defined(TARGET_ARCH_aarch64)
1984   if(tmp1()->is_valid()) {
1985     tmp1()->print(out); out->print(" ");
1986     tmp2()->print(out); out->print(" ");
1987   }
1988 #endif
1989 }
1990 
1991 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1992   switch(code) {
1993     case Bytecodes::_d2f: out->print("[d2f] "); break;
1994     case Bytecodes::_d2i: out->print("[d2i] "); break;
1995     case Bytecodes::_d2l: out->print("[d2l] "); break;
1996     case Bytecodes::_f2d: out->print("[f2d] "); break;
1997     case Bytecodes::_f2i: out->print("[f2i] "); break;
1998     case Bytecodes::_f2l: out->print("[f2l] "); break;
1999     case Bytecodes::_i2b: out->print("[i2b] "); break;
2000     case Bytecodes::_i2c: out->print("[i2c] "); break;
2001     case Bytecodes::_i2d: out->print("[i2d] "); break;
2002     case Bytecodes::_i2f: out->print("[i2f] "); break;
2003     case Bytecodes::_i2l: out->print("[i2l] "); break;


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