< prev index next >

src/share/vm/c1/c1_LIR.hpp

Print this page




 429   int   vreg_number() const    { assert(is_virtual(),                       "type check"); return (RegNr)data(); }
 430 
 431   LIR_OprPtr* pointer()  const                   { assert(is_pointer(), "type check");      return (LIR_OprPtr*)this; }
 432   LIR_Const* as_constant_ptr() const             { return pointer()->as_constant(); }
 433   LIR_Address* as_address_ptr() const            { return pointer()->as_address(); }
 434 
 435   Register as_register()    const;
 436   Register as_register_lo() const;
 437   Register as_register_hi() const;
 438 
 439   Register as_pointer_register() {
 440 #ifdef _LP64
 441     if (is_double_cpu()) {
 442       assert(as_register_lo() == as_register_hi(), "should be a single register");
 443       return as_register_lo();
 444     }
 445 #endif
 446     return as_register();
 447   }
 448 
 449 #ifdef X86
 450   XMMRegister as_xmm_float_reg() const;
 451   XMMRegister as_xmm_double_reg() const;
 452   // for compatibility with RInfo
 453   int fpu () const                                  { return lo_reg_half(); }
 454 #endif // X86
 455 #if defined(SPARC) || defined(ARM) || defined(PPC)
 456   FloatRegister as_float_reg   () const;
 457   FloatRegister as_double_reg  () const;
 458 #endif
 459 
 460   jint      as_jint()    const { return as_constant_ptr()->as_jint(); }
 461   jlong     as_jlong()   const { return as_constant_ptr()->as_jlong(); }
 462   jfloat    as_jfloat()  const { return as_constant_ptr()->as_jfloat(); }
 463   jdouble   as_jdouble() const { return as_constant_ptr()->as_jdouble(); }
 464   jobject   as_jobject() const { return as_constant_ptr()->as_jobject(); }
 465 
 466   void print() const PRODUCT_RETURN;
 467   void print(outputStream* out) const PRODUCT_RETURN;
 468 };
 469 
 470 
 471 inline LIR_OprDesc::OprType as_OprType(BasicType type) {
 472   switch (type) {
 473   case T_INT:      return LIR_OprDesc::int_type;
 474   case T_LONG:     return LIR_OprDesc::long_type;
 475   case T_FLOAT:    return LIR_OprDesc::float_type;


 525        _base(base)
 526      , _index(index)
 527      , _scale(times_1)
 528      , _type(type)
 529      , _disp(0) { verify(); }
 530 
 531   LIR_Address(LIR_Opr base, intx disp, BasicType type):
 532        _base(base)
 533      , _index(LIR_OprDesc::illegalOpr())
 534      , _scale(times_1)
 535      , _type(type)
 536      , _disp(disp) { verify(); }
 537 
 538   LIR_Address(LIR_Opr base, BasicType type):
 539        _base(base)
 540      , _index(LIR_OprDesc::illegalOpr())
 541      , _scale(times_1)
 542      , _type(type)
 543      , _disp(0) { verify(); }
 544 
 545 #if defined(X86) || defined(ARM)
 546   LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type):
 547        _base(base)
 548      , _index(index)
 549      , _scale(scale)
 550      , _type(type)
 551      , _disp(disp) { verify(); }
 552 #endif // X86 || ARM
 553 
 554   LIR_Opr base()  const                          { return _base;  }
 555   LIR_Opr index() const                          { return _index; }
 556   Scale   scale() const                          { return _scale; }
 557   intx    disp()  const                          { return _disp;  }
 558 
 559   bool equals(LIR_Address* other) const          { return base() == other->base() && index() == other->index() && disp() == other->disp() && scale() == other->scale(); }
 560 
 561   virtual LIR_Address* as_address()              { return this;   }
 562   virtual BasicType type() const                 { return _type; }
 563   virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
 564 
 565   void verify0() const PRODUCT_RETURN;


 608     LP64_ONLY(assert(reg1 == reg2, "must be identical"));
 609     return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
 610                                (reg2 << LIR_OprDesc::reg2_shift) |
 611                                LIR_OprDesc::long_type            |
 612                                LIR_OprDesc::cpu_register         |
 613                                LIR_OprDesc::double_size);
 614   }
 615 
 616   static LIR_Opr single_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 617                                                                              LIR_OprDesc::float_type           |
 618                                                                              LIR_OprDesc::fpu_register         |
 619                                                                              LIR_OprDesc::single_size); }
 620 #if defined(C1_LIR_MD_HPP)
 621 # include C1_LIR_MD_HPP
 622 #elif defined(SPARC)
 623   static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
 624                                                                              (reg2 << LIR_OprDesc::reg2_shift) |
 625                                                                              LIR_OprDesc::double_type          |
 626                                                                              LIR_OprDesc::fpu_register         |
 627                                                                              LIR_OprDesc::double_size); }
 628 #elif defined(X86)
 629   static LIR_Opr double_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 630                                                                              (reg  << LIR_OprDesc::reg2_shift) |
 631                                                                              LIR_OprDesc::double_type          |
 632                                                                              LIR_OprDesc::fpu_register         |
 633                                                                              LIR_OprDesc::double_size); }
 634 
 635   static LIR_Opr single_xmm(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 636                                                                              LIR_OprDesc::float_type           |
 637                                                                              LIR_OprDesc::fpu_register         |
 638                                                                              LIR_OprDesc::single_size          |
 639                                                                              LIR_OprDesc::is_xmm_mask); }
 640   static LIR_Opr double_xmm(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 641                                                                              (reg  << LIR_OprDesc::reg2_shift) |
 642                                                                              LIR_OprDesc::double_type          |
 643                                                                              LIR_OprDesc::fpu_register         |
 644                                                                              LIR_OprDesc::double_size          |
 645                                                                              LIR_OprDesc::is_xmm_mask); }
 646 #elif defined(PPC)
 647   static LIR_Opr double_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 648                                                                              (reg  << LIR_OprDesc::reg2_shift) |


1457   CodeStub*     stub()        const              { return _stub;       }
1458 
1459   void          change_block(BlockBegin* b);
1460   void          change_ublock(BlockBegin* b);
1461   void          negate_cond();
1462 
1463   virtual void emit_code(LIR_Assembler* masm);
1464   virtual LIR_OpBranch* as_OpBranch() { return this; }
1465   virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1466 };
1467 
1468 
1469 class ConversionStub;
1470 
1471 class LIR_OpConvert: public LIR_Op1 {
1472  friend class LIR_OpVisitState;
1473 
1474  private:
1475    Bytecodes::Code _bytecode;
1476    ConversionStub* _stub;
1477 #ifdef PPC
1478   LIR_Opr _tmp1;
1479   LIR_Opr _tmp2;
1480 #endif
1481 
1482  public:
1483    LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub)
1484      : LIR_Op1(lir_convert, opr, result)
1485      , _stub(stub)
1486 #ifdef PPC
1487      , _tmp1(LIR_OprDesc::illegalOpr())
1488      , _tmp2(LIR_OprDesc::illegalOpr())
1489 #endif
1490      , _bytecode(code)                           {}
1491 
1492 #ifdef PPC
1493    LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub
1494                  ,LIR_Opr tmp1, LIR_Opr tmp2)
1495      : LIR_Op1(lir_convert, opr, result)
1496      , _stub(stub)
1497      , _tmp1(tmp1)
1498      , _tmp2(tmp2)
1499      , _bytecode(code)                           {}
1500 #endif
1501 
1502   Bytecodes::Code bytecode() const               { return _bytecode; }
1503   ConversionStub* stub() const                   { return _stub; }
1504 #ifdef PPC
1505   LIR_Opr tmp1() const                           { return _tmp1; }
1506   LIR_Opr tmp2() const                           { return _tmp2; }
1507 #endif
1508 
1509   virtual void emit_code(LIR_Assembler* masm);
1510   virtual LIR_OpConvert* as_OpConvert() { return this; }
1511   virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1512 
1513   static void print_bytecode(outputStream* out, Bytecodes::Code code) PRODUCT_RETURN;
1514 };
1515 
1516 
1517 // LIR_OpAllocObj
1518 class LIR_OpAllocObj : public LIR_Op1 {
1519  friend class LIR_OpVisitState;
1520 
1521  private:
1522   LIR_Opr _tmp1;
1523   LIR_Opr _tmp2;
1524   LIR_Opr _tmp3;


2127       append(new LIR_Op1(lir_move, src, LIR_OprFact::address(dst), dst->type(), lir_patch_none, info, lir_move_wide));
2128     } else {
2129       move(src, dst, info);
2130     }
2131   }
2132   void volatile_move(LIR_Opr src, LIR_Opr dst, BasicType type, CodeEmitInfo* info = NULL, LIR_PatchCode patch_code = lir_patch_none) { append(new LIR_Op1(lir_move, src, dst, type, patch_code, info, lir_move_volatile)); }
2133 
2134   void oop2reg  (jobject o, LIR_Opr reg)         { assert(reg->type() == T_OBJECT, "bad reg"); append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o),    reg));   }
2135   void oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info);
2136 
2137   void metadata2reg  (Metadata* o, LIR_Opr reg)  { assert(reg->type() == T_METADATA, "bad reg"); append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg));   }
2138   void klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info);
2139 
2140   void return_op(LIR_Opr result)                 { append(new LIR_Op1(lir_return, result)); }
2141 
2142   void safepoint(LIR_Opr tmp, CodeEmitInfo* info)  { append(new LIR_Op1(lir_safepoint, tmp, info)); }
2143 
2144 #ifdef PPC
2145   void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); }
2146 #endif






2147   void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); }

2148 
2149   void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and,  left, right, dst)); }
2150   void logical_or  (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or,   left, right, dst)); }
2151   void logical_xor (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_xor,  left, right, dst)); }
2152 
2153   void   pack64(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_pack64,   src, dst, T_LONG, lir_patch_none, NULL)); }
2154   void unpack64(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_unpack64, src, dst, T_LONG, lir_patch_none, NULL)); }
2155 
2156   void null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null = false);
2157   void throw_exception(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2158     append(new LIR_Op2(lir_throw, exceptionPC, exceptionOop, LIR_OprFact::illegalOpr, info));
2159   }
2160   void unwind_exception(LIR_Opr exceptionOop) {
2161     append(new LIR_Op1(lir_unwind, exceptionOop));
2162   }
2163 
2164   void compare_to (LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2165     append(new LIR_Op2(lir_compare_to,  left, right, dst));
2166   }
2167 




 429   int   vreg_number() const    { assert(is_virtual(),                       "type check"); return (RegNr)data(); }
 430 
 431   LIR_OprPtr* pointer()  const                   { assert(is_pointer(), "type check");      return (LIR_OprPtr*)this; }
 432   LIR_Const* as_constant_ptr() const             { return pointer()->as_constant(); }
 433   LIR_Address* as_address_ptr() const            { return pointer()->as_address(); }
 434 
 435   Register as_register()    const;
 436   Register as_register_lo() const;
 437   Register as_register_hi() const;
 438 
 439   Register as_pointer_register() {
 440 #ifdef _LP64
 441     if (is_double_cpu()) {
 442       assert(as_register_lo() == as_register_hi(), "should be a single register");
 443       return as_register_lo();
 444     }
 445 #endif
 446     return as_register();
 447   }
 448 
 449 #if defined(X86)
 450   XMMRegister as_xmm_float_reg() const;
 451   XMMRegister as_xmm_double_reg() const;
 452   // for compatibility with RInfo
 453   int fpu () const                                  { return lo_reg_half(); }
 454 #endif
 455 #if defined(SPARC) || defined(ARM) || defined(PPC) || defined(AARCH64)
 456   FloatRegister as_float_reg   () const;
 457   FloatRegister as_double_reg  () const;
 458 #endif
 459 
 460   jint      as_jint()    const { return as_constant_ptr()->as_jint(); }
 461   jlong     as_jlong()   const { return as_constant_ptr()->as_jlong(); }
 462   jfloat    as_jfloat()  const { return as_constant_ptr()->as_jfloat(); }
 463   jdouble   as_jdouble() const { return as_constant_ptr()->as_jdouble(); }
 464   jobject   as_jobject() const { return as_constant_ptr()->as_jobject(); }
 465 
 466   void print() const PRODUCT_RETURN;
 467   void print(outputStream* out) const PRODUCT_RETURN;
 468 };
 469 
 470 
 471 inline LIR_OprDesc::OprType as_OprType(BasicType type) {
 472   switch (type) {
 473   case T_INT:      return LIR_OprDesc::int_type;
 474   case T_LONG:     return LIR_OprDesc::long_type;
 475   case T_FLOAT:    return LIR_OprDesc::float_type;


 525        _base(base)
 526      , _index(index)
 527      , _scale(times_1)
 528      , _type(type)
 529      , _disp(0) { verify(); }
 530 
 531   LIR_Address(LIR_Opr base, intx disp, BasicType type):
 532        _base(base)
 533      , _index(LIR_OprDesc::illegalOpr())
 534      , _scale(times_1)
 535      , _type(type)
 536      , _disp(disp) { verify(); }
 537 
 538   LIR_Address(LIR_Opr base, BasicType type):
 539        _base(base)
 540      , _index(LIR_OprDesc::illegalOpr())
 541      , _scale(times_1)
 542      , _type(type)
 543      , _disp(0) { verify(); }
 544 
 545 #if defined(X86) || defined(ARM) || defined(AARCH64)
 546   LIR_Address(LIR_Opr base, LIR_Opr index, Scale scale, intx disp, BasicType type):
 547        _base(base)
 548      , _index(index)
 549      , _scale(scale)
 550      , _type(type)
 551      , _disp(disp) { verify(); }
 552 #endif // X86 || ARM
 553 
 554   LIR_Opr base()  const                          { return _base;  }
 555   LIR_Opr index() const                          { return _index; }
 556   Scale   scale() const                          { return _scale; }
 557   intx    disp()  const                          { return _disp;  }
 558 
 559   bool equals(LIR_Address* other) const          { return base() == other->base() && index() == other->index() && disp() == other->disp() && scale() == other->scale(); }
 560 
 561   virtual LIR_Address* as_address()              { return this;   }
 562   virtual BasicType type() const                 { return _type; }
 563   virtual void print_value_on(outputStream* out) const PRODUCT_RETURN;
 564 
 565   void verify0() const PRODUCT_RETURN;


 608     LP64_ONLY(assert(reg1 == reg2, "must be identical"));
 609     return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
 610                                (reg2 << LIR_OprDesc::reg2_shift) |
 611                                LIR_OprDesc::long_type            |
 612                                LIR_OprDesc::cpu_register         |
 613                                LIR_OprDesc::double_size);
 614   }
 615 
 616   static LIR_Opr single_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 617                                                                              LIR_OprDesc::float_type           |
 618                                                                              LIR_OprDesc::fpu_register         |
 619                                                                              LIR_OprDesc::single_size); }
 620 #if defined(C1_LIR_MD_HPP)
 621 # include C1_LIR_MD_HPP
 622 #elif defined(SPARC)
 623   static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
 624                                                                              (reg2 << LIR_OprDesc::reg2_shift) |
 625                                                                              LIR_OprDesc::double_type          |
 626                                                                              LIR_OprDesc::fpu_register         |
 627                                                                              LIR_OprDesc::double_size); }
 628 #elif defined(X86) || defined(AARCH64)
 629   static LIR_Opr double_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 630                                                                              (reg  << LIR_OprDesc::reg2_shift) |
 631                                                                              LIR_OprDesc::double_type          |
 632                                                                              LIR_OprDesc::fpu_register         |
 633                                                                              LIR_OprDesc::double_size); }
 634 
 635   static LIR_Opr single_xmm(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 636                                                                              LIR_OprDesc::float_type           |
 637                                                                              LIR_OprDesc::fpu_register         |
 638                                                                              LIR_OprDesc::single_size          |
 639                                                                              LIR_OprDesc::is_xmm_mask); }
 640   static LIR_Opr double_xmm(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 641                                                                              (reg  << LIR_OprDesc::reg2_shift) |
 642                                                                              LIR_OprDesc::double_type          |
 643                                                                              LIR_OprDesc::fpu_register         |
 644                                                                              LIR_OprDesc::double_size          |
 645                                                                              LIR_OprDesc::is_xmm_mask); }
 646 #elif defined(PPC)
 647   static LIR_Opr double_fpu(int reg)            { return (LIR_Opr)(intptr_t)((reg  << LIR_OprDesc::reg1_shift) |
 648                                                                              (reg  << LIR_OprDesc::reg2_shift) |


1457   CodeStub*     stub()        const              { return _stub;       }
1458 
1459   void          change_block(BlockBegin* b);
1460   void          change_ublock(BlockBegin* b);
1461   void          negate_cond();
1462 
1463   virtual void emit_code(LIR_Assembler* masm);
1464   virtual LIR_OpBranch* as_OpBranch() { return this; }
1465   virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1466 };
1467 
1468 
1469 class ConversionStub;
1470 
1471 class LIR_OpConvert: public LIR_Op1 {
1472  friend class LIR_OpVisitState;
1473 
1474  private:
1475    Bytecodes::Code _bytecode;
1476    ConversionStub* _stub;
1477 #if defined(PPC) || defined(TARGET_ARCH_aarch64)
1478   LIR_Opr _tmp1;
1479   LIR_Opr _tmp2;
1480 #endif
1481 
1482  public:
1483    LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub)
1484      : LIR_Op1(lir_convert, opr, result)
1485      , _stub(stub)
1486 #ifdef PPC
1487      , _tmp1(LIR_OprDesc::illegalOpr())
1488      , _tmp2(LIR_OprDesc::illegalOpr())
1489 #endif
1490      , _bytecode(code)                           {}
1491 
1492 #if defined(PPC) || defined(TARGET_ARCH_aarch64)
1493    LIR_OpConvert(Bytecodes::Code code, LIR_Opr opr, LIR_Opr result, ConversionStub* stub
1494                  ,LIR_Opr tmp1, LIR_Opr tmp2)
1495      : LIR_Op1(lir_convert, opr, result)
1496      , _stub(stub)
1497      , _tmp1(tmp1)
1498      , _tmp2(tmp2)
1499      , _bytecode(code)                           {}
1500 #endif
1501 
1502   Bytecodes::Code bytecode() const               { return _bytecode; }
1503   ConversionStub* stub() const                   { return _stub; }
1504 #if defined(PPC) || defined(TARGET_ARCH_aarch64)
1505   LIR_Opr tmp1() const                           { return _tmp1; }
1506   LIR_Opr tmp2() const                           { return _tmp2; }
1507 #endif
1508 
1509   virtual void emit_code(LIR_Assembler* masm);
1510   virtual LIR_OpConvert* as_OpConvert() { return this; }
1511   virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
1512 
1513   static void print_bytecode(outputStream* out, Bytecodes::Code code) PRODUCT_RETURN;
1514 };
1515 
1516 
1517 // LIR_OpAllocObj
1518 class LIR_OpAllocObj : public LIR_Op1 {
1519  friend class LIR_OpVisitState;
1520 
1521  private:
1522   LIR_Opr _tmp1;
1523   LIR_Opr _tmp2;
1524   LIR_Opr _tmp3;


2127       append(new LIR_Op1(lir_move, src, LIR_OprFact::address(dst), dst->type(), lir_patch_none, info, lir_move_wide));
2128     } else {
2129       move(src, dst, info);
2130     }
2131   }
2132   void volatile_move(LIR_Opr src, LIR_Opr dst, BasicType type, CodeEmitInfo* info = NULL, LIR_PatchCode patch_code = lir_patch_none) { append(new LIR_Op1(lir_move, src, dst, type, patch_code, info, lir_move_volatile)); }
2133 
2134   void oop2reg  (jobject o, LIR_Opr reg)         { assert(reg->type() == T_OBJECT, "bad reg"); append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o),    reg));   }
2135   void oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info);
2136 
2137   void metadata2reg  (Metadata* o, LIR_Opr reg)  { assert(reg->type() == T_METADATA, "bad reg"); append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg));   }
2138   void klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info);
2139 
2140   void return_op(LIR_Opr result)                 { append(new LIR_Op1(lir_return, result)); }
2141 
2142   void safepoint(LIR_Opr tmp, CodeEmitInfo* info)  { append(new LIR_Op1(lir_safepoint, tmp, info)); }
2143 
2144 #ifdef PPC
2145   void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_OpConvert(code, left, dst, NULL, tmp1, tmp2)); }
2146 #endif
2147 #if defined (TARGET_ARCH_aarch64)
2148   void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst,
2149                ConversionStub* stub = NULL, LIR_Opr tmp1 = LIR_OprDesc::illegalOpr()) {
2150     append(new LIR_OpConvert(code, left, dst, stub, tmp1, LIR_OprDesc::illegalOpr()));
2151   }
2152 #else
2153   void convert(Bytecodes::Code code, LIR_Opr left, LIR_Opr dst, ConversionStub* stub = NULL/*, bool is_32bit = false*/) { append(new LIR_OpConvert(code, left, dst, stub)); }
2154 #endif
2155 
2156   void logical_and (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_and,  left, right, dst)); }
2157   void logical_or  (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_or,   left, right, dst)); }
2158   void logical_xor (LIR_Opr left, LIR_Opr right, LIR_Opr dst) { append(new LIR_Op2(lir_logic_xor,  left, right, dst)); }
2159 
2160   void   pack64(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_pack64,   src, dst, T_LONG, lir_patch_none, NULL)); }
2161   void unpack64(LIR_Opr src, LIR_Opr dst) { append(new LIR_Op1(lir_unpack64, src, dst, T_LONG, lir_patch_none, NULL)); }
2162 
2163   void null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null = false);
2164   void throw_exception(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2165     append(new LIR_Op2(lir_throw, exceptionPC, exceptionOop, LIR_OprFact::illegalOpr, info));
2166   }
2167   void unwind_exception(LIR_Opr exceptionOop) {
2168     append(new LIR_Op1(lir_unwind, exceptionOop));
2169   }
2170 
2171   void compare_to (LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2172     append(new LIR_Op2(lir_compare_to,  left, right, dst));
2173   }
2174 


< prev index next >