1 //
2 // Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2024, Red Hat, Inc. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 // AArch64 Architecture Description File
27
28 //----------REGISTER DEFINITION BLOCK------------------------------------------
29 // This information is used by the matcher and the register allocator to
30 // describe individual registers and classes of registers within the target
31 // architecture.
32
33 register %{
34 //----------Architecture Description Register Definitions----------------------
35 // General Registers
36 // "reg_def" name ( register save type, C convention save type,
37 // ideal register type, encoding );
38 // Register Save Types:
39 //
40 // NS = No-Save: The register allocator assumes that these registers
41 // can be used without saving upon entry to the method, &
42 // that they do not need to be saved at call sites.
43 //
44 // SOC = Save-On-Call: The register allocator assumes that these registers
45 // can be used without saving upon entry to the method,
46 // but that they must be saved at call sites.
47 //
48 // SOE = Save-On-Entry: The register allocator assumes that these registers
49 // must be saved before using them upon entry to the
50 // method, but they do not need to be saved at call
51 // sites.
52 //
53 // AS = Always-Save: The register allocator assumes that these registers
54 // must be saved before using them upon entry to the
55 // method, & that they must be saved at call sites.
56 //
57 // Ideal Register Type is used to determine how to save & restore a
58 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
59 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
60 //
61 // The encoding number is the actual bit-pattern placed into the opcodes.
62
63 // We must define the 64 bit int registers in two 32 bit halves, the
64 // real lower register and a virtual upper half register. upper halves
65 // are used by the register allocator but are not actually supplied as
66 // operands to memory ops.
67 //
68 // follow the C1 compiler in making registers
69 //
70 // r0-r7,r10-r26 volatile (caller save)
71 // r27-r32 system (no save, no allocate)
72 // r8-r9 non-allocatable (so we can use them as scratch regs)
73 //
74 // as regards Java usage. we don't use any callee save registers
75 // because this makes it difficult to de-optimise a frame (see comment
76 // in x86 implementation of Deoptimization::unwind_callee_save_values)
77 //
78
79 // General Registers
80
81 reg_def R0 ( SOC, SOC, Op_RegI, 0, r0->as_VMReg() );
82 reg_def R0_H ( SOC, SOC, Op_RegI, 0, r0->as_VMReg()->next() );
83 reg_def R1 ( SOC, SOC, Op_RegI, 1, r1->as_VMReg() );
84 reg_def R1_H ( SOC, SOC, Op_RegI, 1, r1->as_VMReg()->next() );
85 reg_def R2 ( SOC, SOC, Op_RegI, 2, r2->as_VMReg() );
86 reg_def R2_H ( SOC, SOC, Op_RegI, 2, r2->as_VMReg()->next() );
87 reg_def R3 ( SOC, SOC, Op_RegI, 3, r3->as_VMReg() );
88 reg_def R3_H ( SOC, SOC, Op_RegI, 3, r3->as_VMReg()->next() );
89 reg_def R4 ( SOC, SOC, Op_RegI, 4, r4->as_VMReg() );
90 reg_def R4_H ( SOC, SOC, Op_RegI, 4, r4->as_VMReg()->next() );
91 reg_def R5 ( SOC, SOC, Op_RegI, 5, r5->as_VMReg() );
92 reg_def R5_H ( SOC, SOC, Op_RegI, 5, r5->as_VMReg()->next() );
93 reg_def R6 ( SOC, SOC, Op_RegI, 6, r6->as_VMReg() );
94 reg_def R6_H ( SOC, SOC, Op_RegI, 6, r6->as_VMReg()->next() );
95 reg_def R7 ( SOC, SOC, Op_RegI, 7, r7->as_VMReg() );
96 reg_def R7_H ( SOC, SOC, Op_RegI, 7, r7->as_VMReg()->next() );
97 reg_def R8 ( NS, SOC, Op_RegI, 8, r8->as_VMReg() ); // rscratch1, non-allocatable
98 reg_def R8_H ( NS, SOC, Op_RegI, 8, r8->as_VMReg()->next() );
99 reg_def R9 ( NS, SOC, Op_RegI, 9, r9->as_VMReg() ); // rscratch2, non-allocatable
100 reg_def R9_H ( NS, SOC, Op_RegI, 9, r9->as_VMReg()->next() );
101 reg_def R10 ( SOC, SOC, Op_RegI, 10, r10->as_VMReg() );
102 reg_def R10_H ( SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
103 reg_def R11 ( SOC, SOC, Op_RegI, 11, r11->as_VMReg() );
104 reg_def R11_H ( SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
105 reg_def R12 ( SOC, SOC, Op_RegI, 12, r12->as_VMReg() );
106 reg_def R12_H ( SOC, SOC, Op_RegI, 12, r12->as_VMReg()->next());
107 reg_def R13 ( SOC, SOC, Op_RegI, 13, r13->as_VMReg() );
108 reg_def R13_H ( SOC, SOC, Op_RegI, 13, r13->as_VMReg()->next());
109 reg_def R14 ( SOC, SOC, Op_RegI, 14, r14->as_VMReg() );
110 reg_def R14_H ( SOC, SOC, Op_RegI, 14, r14->as_VMReg()->next());
111 reg_def R15 ( SOC, SOC, Op_RegI, 15, r15->as_VMReg() );
112 reg_def R15_H ( SOC, SOC, Op_RegI, 15, r15->as_VMReg()->next());
113 reg_def R16 ( SOC, SOC, Op_RegI, 16, r16->as_VMReg() );
114 reg_def R16_H ( SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next());
115 reg_def R17 ( SOC, SOC, Op_RegI, 17, r17->as_VMReg() );
116 reg_def R17_H ( SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next());
117 reg_def R18 ( SOC, SOC, Op_RegI, 18, r18_tls->as_VMReg() );
118 reg_def R18_H ( SOC, SOC, Op_RegI, 18, r18_tls->as_VMReg()->next());
119 reg_def R19 ( SOC, SOE, Op_RegI, 19, r19->as_VMReg() );
120 reg_def R19_H ( SOC, SOE, Op_RegI, 19, r19->as_VMReg()->next());
121 reg_def R20 ( SOC, SOE, Op_RegI, 20, r20->as_VMReg() ); // caller esp
122 reg_def R20_H ( SOC, SOE, Op_RegI, 20, r20->as_VMReg()->next());
123 reg_def R21 ( SOC, SOE, Op_RegI, 21, r21->as_VMReg() );
124 reg_def R21_H ( SOC, SOE, Op_RegI, 21, r21->as_VMReg()->next());
125 reg_def R22 ( SOC, SOE, Op_RegI, 22, r22->as_VMReg() );
126 reg_def R22_H ( SOC, SOE, Op_RegI, 22, r22->as_VMReg()->next());
127 reg_def R23 ( SOC, SOE, Op_RegI, 23, r23->as_VMReg() );
128 reg_def R23_H ( SOC, SOE, Op_RegI, 23, r23->as_VMReg()->next());
129 reg_def R24 ( SOC, SOE, Op_RegI, 24, r24->as_VMReg() );
130 reg_def R24_H ( SOC, SOE, Op_RegI, 24, r24->as_VMReg()->next());
131 reg_def R25 ( SOC, SOE, Op_RegI, 25, r25->as_VMReg() );
132 reg_def R25_H ( SOC, SOE, Op_RegI, 25, r25->as_VMReg()->next());
133 reg_def R26 ( SOC, SOE, Op_RegI, 26, r26->as_VMReg() );
134 reg_def R26_H ( SOC, SOE, Op_RegI, 26, r26->as_VMReg()->next());
135 reg_def R27 ( SOC, SOE, Op_RegI, 27, r27->as_VMReg() ); // heapbase
136 reg_def R27_H ( SOC, SOE, Op_RegI, 27, r27->as_VMReg()->next());
137 reg_def R28 ( NS, SOE, Op_RegI, 28, r28->as_VMReg() ); // thread
138 reg_def R28_H ( NS, SOE, Op_RegI, 28, r28->as_VMReg()->next());
139 reg_def R29 ( NS, NS, Op_RegI, 29, r29->as_VMReg() ); // fp
140 reg_def R29_H ( NS, NS, Op_RegI, 29, r29->as_VMReg()->next());
141 reg_def R30 ( NS, NS, Op_RegI, 30, r30->as_VMReg() ); // lr
142 reg_def R30_H ( NS, NS, Op_RegI, 30, r30->as_VMReg()->next());
143 reg_def R31 ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg() ); // sp
144 reg_def R31_H ( NS, NS, Op_RegI, 31, r31_sp->as_VMReg()->next());
145
146 // ----------------------------
147 // Float/Double/Vector Registers
148 // ----------------------------
149
150 // Double Registers
151
152 // The rules of ADL require that double registers be defined in pairs.
153 // Each pair must be two 32-bit values, but not necessarily a pair of
154 // single float registers. In each pair, ADLC-assigned register numbers
155 // must be adjacent, with the lower number even. Finally, when the
156 // CPU stores such a register pair to memory, the word associated with
157 // the lower ADLC-assigned number must be stored to the lower address.
158
159 // AArch64 has 32 floating-point registers. Each can store a vector of
160 // single or double precision floating-point values up to 8 * 32
161 // floats, 4 * 64 bit floats or 2 * 128 bit floats. We currently only
162 // use the first float or double element of the vector.
163
164 // for Java use float registers v0-v15 are always save on call whereas
165 // the platform ABI treats v8-v15 as callee save). float registers
166 // v16-v31 are SOC as per the platform spec
167
168 // For SVE vector registers, we simply extend vector register size to 8
169 // 'logical' slots. This is nominally 256 bits but it actually covers
170 // all possible 'physical' SVE vector register lengths from 128 ~ 2048
171 // bits. The 'physical' SVE vector register length is detected during
172 // startup, so the register allocator is able to identify the correct
173 // number of bytes needed for an SVE spill/unspill.
174 // Note that a vector register with 4 slots denotes a 128-bit NEON
175 // register allowing it to be distinguished from the corresponding SVE
176 // vector register when the SVE vector length is 128 bits.
177
178 reg_def V0 ( SOC, SOC, Op_RegF, 0, v0->as_VMReg() );
179 reg_def V0_H ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next() );
180 reg_def V0_J ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(2) );
181 reg_def V0_K ( SOC, SOC, Op_RegF, 0, v0->as_VMReg()->next(3) );
182
183 reg_def V1 ( SOC, SOC, Op_RegF, 1, v1->as_VMReg() );
184 reg_def V1_H ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next() );
185 reg_def V1_J ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(2) );
186 reg_def V1_K ( SOC, SOC, Op_RegF, 1, v1->as_VMReg()->next(3) );
187
188 reg_def V2 ( SOC, SOC, Op_RegF, 2, v2->as_VMReg() );
189 reg_def V2_H ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next() );
190 reg_def V2_J ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(2) );
191 reg_def V2_K ( SOC, SOC, Op_RegF, 2, v2->as_VMReg()->next(3) );
192
193 reg_def V3 ( SOC, SOC, Op_RegF, 3, v3->as_VMReg() );
194 reg_def V3_H ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next() );
195 reg_def V3_J ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(2) );
196 reg_def V3_K ( SOC, SOC, Op_RegF, 3, v3->as_VMReg()->next(3) );
197
198 reg_def V4 ( SOC, SOC, Op_RegF, 4, v4->as_VMReg() );
199 reg_def V4_H ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next() );
200 reg_def V4_J ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(2) );
201 reg_def V4_K ( SOC, SOC, Op_RegF, 4, v4->as_VMReg()->next(3) );
202
203 reg_def V5 ( SOC, SOC, Op_RegF, 5, v5->as_VMReg() );
204 reg_def V5_H ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next() );
205 reg_def V5_J ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(2) );
206 reg_def V5_K ( SOC, SOC, Op_RegF, 5, v5->as_VMReg()->next(3) );
207
208 reg_def V6 ( SOC, SOC, Op_RegF, 6, v6->as_VMReg() );
209 reg_def V6_H ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next() );
210 reg_def V6_J ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(2) );
211 reg_def V6_K ( SOC, SOC, Op_RegF, 6, v6->as_VMReg()->next(3) );
212
213 reg_def V7 ( SOC, SOC, Op_RegF, 7, v7->as_VMReg() );
214 reg_def V7_H ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next() );
215 reg_def V7_J ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(2) );
216 reg_def V7_K ( SOC, SOC, Op_RegF, 7, v7->as_VMReg()->next(3) );
217
218 reg_def V8 ( SOC, SOE, Op_RegF, 8, v8->as_VMReg() );
219 reg_def V8_H ( SOC, SOE, Op_RegF, 8, v8->as_VMReg()->next() );
220 reg_def V8_J ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(2) );
221 reg_def V8_K ( SOC, SOC, Op_RegF, 8, v8->as_VMReg()->next(3) );
222
223 reg_def V9 ( SOC, SOE, Op_RegF, 9, v9->as_VMReg() );
224 reg_def V9_H ( SOC, SOE, Op_RegF, 9, v9->as_VMReg()->next() );
225 reg_def V9_J ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(2) );
226 reg_def V9_K ( SOC, SOC, Op_RegF, 9, v9->as_VMReg()->next(3) );
227
228 reg_def V10 ( SOC, SOE, Op_RegF, 10, v10->as_VMReg() );
229 reg_def V10_H ( SOC, SOE, Op_RegF, 10, v10->as_VMReg()->next() );
230 reg_def V10_J ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(2) );
231 reg_def V10_K ( SOC, SOC, Op_RegF, 10, v10->as_VMReg()->next(3) );
232
233 reg_def V11 ( SOC, SOE, Op_RegF, 11, v11->as_VMReg() );
234 reg_def V11_H ( SOC, SOE, Op_RegF, 11, v11->as_VMReg()->next() );
235 reg_def V11_J ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(2) );
236 reg_def V11_K ( SOC, SOC, Op_RegF, 11, v11->as_VMReg()->next(3) );
237
238 reg_def V12 ( SOC, SOE, Op_RegF, 12, v12->as_VMReg() );
239 reg_def V12_H ( SOC, SOE, Op_RegF, 12, v12->as_VMReg()->next() );
240 reg_def V12_J ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(2) );
241 reg_def V12_K ( SOC, SOC, Op_RegF, 12, v12->as_VMReg()->next(3) );
242
243 reg_def V13 ( SOC, SOE, Op_RegF, 13, v13->as_VMReg() );
244 reg_def V13_H ( SOC, SOE, Op_RegF, 13, v13->as_VMReg()->next() );
245 reg_def V13_J ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(2) );
246 reg_def V13_K ( SOC, SOC, Op_RegF, 13, v13->as_VMReg()->next(3) );
247
248 reg_def V14 ( SOC, SOE, Op_RegF, 14, v14->as_VMReg() );
249 reg_def V14_H ( SOC, SOE, Op_RegF, 14, v14->as_VMReg()->next() );
250 reg_def V14_J ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(2) );
251 reg_def V14_K ( SOC, SOC, Op_RegF, 14, v14->as_VMReg()->next(3) );
252
253 reg_def V15 ( SOC, SOE, Op_RegF, 15, v15->as_VMReg() );
254 reg_def V15_H ( SOC, SOE, Op_RegF, 15, v15->as_VMReg()->next() );
255 reg_def V15_J ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(2) );
256 reg_def V15_K ( SOC, SOC, Op_RegF, 15, v15->as_VMReg()->next(3) );
257
258 reg_def V16 ( SOC, SOC, Op_RegF, 16, v16->as_VMReg() );
259 reg_def V16_H ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next() );
260 reg_def V16_J ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(2) );
261 reg_def V16_K ( SOC, SOC, Op_RegF, 16, v16->as_VMReg()->next(3) );
262
263 reg_def V17 ( SOC, SOC, Op_RegF, 17, v17->as_VMReg() );
264 reg_def V17_H ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next() );
265 reg_def V17_J ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(2) );
266 reg_def V17_K ( SOC, SOC, Op_RegF, 17, v17->as_VMReg()->next(3) );
267
268 reg_def V18 ( SOC, SOC, Op_RegF, 18, v18->as_VMReg() );
269 reg_def V18_H ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next() );
270 reg_def V18_J ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(2) );
271 reg_def V18_K ( SOC, SOC, Op_RegF, 18, v18->as_VMReg()->next(3) );
272
273 reg_def V19 ( SOC, SOC, Op_RegF, 19, v19->as_VMReg() );
274 reg_def V19_H ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next() );
275 reg_def V19_J ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(2) );
276 reg_def V19_K ( SOC, SOC, Op_RegF, 19, v19->as_VMReg()->next(3) );
277
278 reg_def V20 ( SOC, SOC, Op_RegF, 20, v20->as_VMReg() );
279 reg_def V20_H ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next() );
280 reg_def V20_J ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(2) );
281 reg_def V20_K ( SOC, SOC, Op_RegF, 20, v20->as_VMReg()->next(3) );
282
283 reg_def V21 ( SOC, SOC, Op_RegF, 21, v21->as_VMReg() );
284 reg_def V21_H ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next() );
285 reg_def V21_J ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(2) );
286 reg_def V21_K ( SOC, SOC, Op_RegF, 21, v21->as_VMReg()->next(3) );
287
288 reg_def V22 ( SOC, SOC, Op_RegF, 22, v22->as_VMReg() );
289 reg_def V22_H ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next() );
290 reg_def V22_J ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(2) );
291 reg_def V22_K ( SOC, SOC, Op_RegF, 22, v22->as_VMReg()->next(3) );
292
293 reg_def V23 ( SOC, SOC, Op_RegF, 23, v23->as_VMReg() );
294 reg_def V23_H ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next() );
295 reg_def V23_J ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(2) );
296 reg_def V23_K ( SOC, SOC, Op_RegF, 23, v23->as_VMReg()->next(3) );
297
298 reg_def V24 ( SOC, SOC, Op_RegF, 24, v24->as_VMReg() );
299 reg_def V24_H ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next() );
300 reg_def V24_J ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(2) );
301 reg_def V24_K ( SOC, SOC, Op_RegF, 24, v24->as_VMReg()->next(3) );
302
303 reg_def V25 ( SOC, SOC, Op_RegF, 25, v25->as_VMReg() );
304 reg_def V25_H ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next() );
305 reg_def V25_J ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(2) );
306 reg_def V25_K ( SOC, SOC, Op_RegF, 25, v25->as_VMReg()->next(3) );
307
308 reg_def V26 ( SOC, SOC, Op_RegF, 26, v26->as_VMReg() );
309 reg_def V26_H ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next() );
310 reg_def V26_J ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(2) );
311 reg_def V26_K ( SOC, SOC, Op_RegF, 26, v26->as_VMReg()->next(3) );
312
313 reg_def V27 ( SOC, SOC, Op_RegF, 27, v27->as_VMReg() );
314 reg_def V27_H ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next() );
315 reg_def V27_J ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(2) );
316 reg_def V27_K ( SOC, SOC, Op_RegF, 27, v27->as_VMReg()->next(3) );
317
318 reg_def V28 ( SOC, SOC, Op_RegF, 28, v28->as_VMReg() );
319 reg_def V28_H ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next() );
320 reg_def V28_J ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(2) );
321 reg_def V28_K ( SOC, SOC, Op_RegF, 28, v28->as_VMReg()->next(3) );
322
323 reg_def V29 ( SOC, SOC, Op_RegF, 29, v29->as_VMReg() );
324 reg_def V29_H ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next() );
325 reg_def V29_J ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(2) );
326 reg_def V29_K ( SOC, SOC, Op_RegF, 29, v29->as_VMReg()->next(3) );
327
328 reg_def V30 ( SOC, SOC, Op_RegF, 30, v30->as_VMReg() );
329 reg_def V30_H ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next() );
330 reg_def V30_J ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(2) );
331 reg_def V30_K ( SOC, SOC, Op_RegF, 30, v30->as_VMReg()->next(3) );
332
333 reg_def V31 ( SOC, SOC, Op_RegF, 31, v31->as_VMReg() );
334 reg_def V31_H ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next() );
335 reg_def V31_J ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(2) );
336 reg_def V31_K ( SOC, SOC, Op_RegF, 31, v31->as_VMReg()->next(3) );
337
338 // ----------------------------
339 // SVE Predicate Registers
340 // ----------------------------
341 reg_def P0 (SOC, SOC, Op_RegVectMask, 0, p0->as_VMReg());
342 reg_def P1 (SOC, SOC, Op_RegVectMask, 1, p1->as_VMReg());
343 reg_def P2 (SOC, SOC, Op_RegVectMask, 2, p2->as_VMReg());
344 reg_def P3 (SOC, SOC, Op_RegVectMask, 3, p3->as_VMReg());
345 reg_def P4 (SOC, SOC, Op_RegVectMask, 4, p4->as_VMReg());
346 reg_def P5 (SOC, SOC, Op_RegVectMask, 5, p5->as_VMReg());
347 reg_def P6 (SOC, SOC, Op_RegVectMask, 6, p6->as_VMReg());
348 reg_def P7 (SOC, SOC, Op_RegVectMask, 7, p7->as_VMReg());
349 reg_def P8 (SOC, SOC, Op_RegVectMask, 8, p8->as_VMReg());
350 reg_def P9 (SOC, SOC, Op_RegVectMask, 9, p9->as_VMReg());
351 reg_def P10 (SOC, SOC, Op_RegVectMask, 10, p10->as_VMReg());
352 reg_def P11 (SOC, SOC, Op_RegVectMask, 11, p11->as_VMReg());
353 reg_def P12 (SOC, SOC, Op_RegVectMask, 12, p12->as_VMReg());
354 reg_def P13 (SOC, SOC, Op_RegVectMask, 13, p13->as_VMReg());
355 reg_def P14 (SOC, SOC, Op_RegVectMask, 14, p14->as_VMReg());
356 reg_def P15 (SOC, SOC, Op_RegVectMask, 15, p15->as_VMReg());
357
358 // ----------------------------
359 // Special Registers
360 // ----------------------------
361
362 // the AArch64 CSPR status flag register is not directly accessible as
363 // instruction operand. the FPSR status flag register is a system
364 // register which can be written/read using MSR/MRS but again does not
365 // appear as an operand (a code identifying the FSPR occurs as an
366 // immediate value in the instruction).
367
368 reg_def RFLAGS(SOC, SOC, 0, 32, VMRegImpl::Bad());
369
370 // Specify priority of register selection within phases of register
371 // allocation. Highest priority is first. A useful heuristic is to
372 // give registers a low priority when they are required by machine
373 // instructions, like EAX and EDX on I486, and choose no-save registers
374 // before save-on-call, & save-on-call before save-on-entry. Registers
375 // which participate in fixed calling sequences should come last.
376 // Registers which are used as pairs must fall on an even boundary.
377
378 alloc_class chunk0(
379 // volatiles
380 R10, R10_H,
381 R11, R11_H,
382 R12, R12_H,
383 R13, R13_H,
384 R14, R14_H,
385 R15, R15_H,
386 R16, R16_H,
387 R17, R17_H,
388 R18, R18_H,
389
390 // arg registers
391 R0, R0_H,
392 R1, R1_H,
393 R2, R2_H,
394 R3, R3_H,
395 R4, R4_H,
396 R5, R5_H,
397 R6, R6_H,
398 R7, R7_H,
399
400 // non-volatiles
401 R19, R19_H,
402 R20, R20_H,
403 R21, R21_H,
404 R22, R22_H,
405 R23, R23_H,
406 R24, R24_H,
407 R25, R25_H,
408 R26, R26_H,
409
410 // non-allocatable registers
411
412 R27, R27_H, // heapbase
413 R28, R28_H, // thread
414 R29, R29_H, // fp
415 R30, R30_H, // lr
416 R31, R31_H, // sp
417 R8, R8_H, // rscratch1
418 R9, R9_H, // rscratch2
419 );
420
421 alloc_class chunk1(
422
423 // no save
424 V16, V16_H, V16_J, V16_K,
425 V17, V17_H, V17_J, V17_K,
426 V18, V18_H, V18_J, V18_K,
427 V19, V19_H, V19_J, V19_K,
428 V20, V20_H, V20_J, V20_K,
429 V21, V21_H, V21_J, V21_K,
430 V22, V22_H, V22_J, V22_K,
431 V23, V23_H, V23_J, V23_K,
432 V24, V24_H, V24_J, V24_K,
433 V25, V25_H, V25_J, V25_K,
434 V26, V26_H, V26_J, V26_K,
435 V27, V27_H, V27_J, V27_K,
436 V28, V28_H, V28_J, V28_K,
437 V29, V29_H, V29_J, V29_K,
438 V30, V30_H, V30_J, V30_K,
439 V31, V31_H, V31_J, V31_K,
440
441 // arg registers
442 V0, V0_H, V0_J, V0_K,
443 V1, V1_H, V1_J, V1_K,
444 V2, V2_H, V2_J, V2_K,
445 V3, V3_H, V3_J, V3_K,
446 V4, V4_H, V4_J, V4_K,
447 V5, V5_H, V5_J, V5_K,
448 V6, V6_H, V6_J, V6_K,
449 V7, V7_H, V7_J, V7_K,
450
451 // non-volatiles
452 V8, V8_H, V8_J, V8_K,
453 V9, V9_H, V9_J, V9_K,
454 V10, V10_H, V10_J, V10_K,
455 V11, V11_H, V11_J, V11_K,
456 V12, V12_H, V12_J, V12_K,
457 V13, V13_H, V13_J, V13_K,
458 V14, V14_H, V14_J, V14_K,
459 V15, V15_H, V15_J, V15_K,
460 );
461
462 alloc_class chunk2 (
463 // Governing predicates for load/store and arithmetic
464 P0,
465 P1,
466 P2,
467 P3,
468 P4,
469 P5,
470 P6,
471
472 // Extra predicates
473 P8,
474 P9,
475 P10,
476 P11,
477 P12,
478 P13,
479 P14,
480 P15,
481
482 // Preserved for all-true predicate
483 P7,
484 );
485
486 alloc_class chunk3(RFLAGS);
487
488 //----------Architecture Description Register Classes--------------------------
489 // Several register classes are automatically defined based upon information in
490 // this architecture description.
491 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
492 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
493 //
494
495 // Class for all 32 bit general purpose registers
496 reg_class all_reg32(
497 R0,
498 R1,
499 R2,
500 R3,
501 R4,
502 R5,
503 R6,
504 R7,
505 R10,
506 R11,
507 R12,
508 R13,
509 R14,
510 R15,
511 R16,
512 R17,
513 R18,
514 R19,
515 R20,
516 R21,
517 R22,
518 R23,
519 R24,
520 R25,
521 R26,
522 R27,
523 R28,
524 R29,
525 R30,
526 R31
527 );
528
529
530 // Class for all 32 bit integer registers (excluding SP which
531 // will never be used as an integer register)
532 reg_class any_reg32 %{
533 return _ANY_REG32_mask;
534 %}
535
536 // Singleton class for R0 int register
537 reg_class int_r0_reg(R0);
538
539 // Singleton class for R2 int register
540 reg_class int_r2_reg(R2);
541
542 // Singleton class for R3 int register
543 reg_class int_r3_reg(R3);
544
545 // Singleton class for R4 int register
546 reg_class int_r4_reg(R4);
547
548 // Singleton class for R31 int register
549 reg_class int_r31_reg(R31);
550
551 // Class for all 64 bit general purpose registers
552 reg_class all_reg(
553 R0, R0_H,
554 R1, R1_H,
555 R2, R2_H,
556 R3, R3_H,
557 R4, R4_H,
558 R5, R5_H,
559 R6, R6_H,
560 R7, R7_H,
561 R10, R10_H,
562 R11, R11_H,
563 R12, R12_H,
564 R13, R13_H,
565 R14, R14_H,
566 R15, R15_H,
567 R16, R16_H,
568 R17, R17_H,
569 R18, R18_H,
570 R19, R19_H,
571 R20, R20_H,
572 R21, R21_H,
573 R22, R22_H,
574 R23, R23_H,
575 R24, R24_H,
576 R25, R25_H,
577 R26, R26_H,
578 R27, R27_H,
579 R28, R28_H,
580 R29, R29_H,
581 R30, R30_H,
582 R31, R31_H
583 );
584
585 // Class for all long integer registers (including SP)
586 reg_class any_reg %{
587 return _ANY_REG_mask;
588 %}
589
590 // Class for non-allocatable 32 bit registers
591 reg_class non_allocatable_reg32(
592 #ifdef R18_RESERVED
593 // See comment in register_aarch64.hpp
594 R18, // tls on Windows
595 #endif
596 R28, // thread
597 R30, // lr
598 R31 // sp
599 );
600
601 // Class for non-allocatable 64 bit registers
602 reg_class non_allocatable_reg(
603 #ifdef R18_RESERVED
604 // See comment in register_aarch64.hpp
605 R18, R18_H, // tls on Windows, platform register on macOS
606 #endif
607 R28, R28_H, // thread
608 R30, R30_H, // lr
609 R31, R31_H // sp
610 );
611
612 // Class for all non-special integer registers
613 reg_class no_special_reg32 %{
614 return _NO_SPECIAL_REG32_mask;
615 %}
616
617 // Class for all non-special long integer registers
618 reg_class no_special_reg %{
619 return _NO_SPECIAL_REG_mask;
620 %}
621
622 // Class for 64 bit register r0
623 reg_class r0_reg(
624 R0, R0_H
625 );
626
627 // Class for 64 bit register r1
628 reg_class r1_reg(
629 R1, R1_H
630 );
631
632 // Class for 64 bit register r2
633 reg_class r2_reg(
634 R2, R2_H
635 );
636
637 // Class for 64 bit register r3
638 reg_class r3_reg(
639 R3, R3_H
640 );
641
642 // Class for 64 bit register r4
643 reg_class r4_reg(
644 R4, R4_H
645 );
646
647 // Class for 64 bit register r5
648 reg_class r5_reg(
649 R5, R5_H
650 );
651
652 // Class for 64 bit register r10
653 reg_class r10_reg(
654 R10, R10_H
655 );
656
657 // Class for 64 bit register r11
658 reg_class r11_reg(
659 R11, R11_H
660 );
661
662 // Class for method register
663 reg_class method_reg(
664 R12, R12_H
665 );
666
667 // Class for thread register
668 reg_class thread_reg(
669 R28, R28_H
670 );
671
672 // Class for frame pointer register
673 reg_class fp_reg(
674 R29, R29_H
675 );
676
677 // Class for link register
678 reg_class lr_reg(
679 R30, R30_H
680 );
681
682 // Class for long sp register
683 reg_class sp_reg(
684 R31, R31_H
685 );
686
687 // Class for all pointer registers
688 reg_class ptr_reg %{
689 return _PTR_REG_mask;
690 %}
691
692 // Class for all non_special pointer registers
693 reg_class no_special_ptr_reg %{
694 return _NO_SPECIAL_PTR_REG_mask;
695 %}
696
697 // Class for all non_special pointer registers (excluding rfp)
698 reg_class no_special_no_rfp_ptr_reg %{
699 return _NO_SPECIAL_NO_RFP_PTR_REG_mask;
700 %}
701
702 // Class for all float registers
703 reg_class float_reg(
704 V0,
705 V1,
706 V2,
707 V3,
708 V4,
709 V5,
710 V6,
711 V7,
712 V8,
713 V9,
714 V10,
715 V11,
716 V12,
717 V13,
718 V14,
719 V15,
720 V16,
721 V17,
722 V18,
723 V19,
724 V20,
725 V21,
726 V22,
727 V23,
728 V24,
729 V25,
730 V26,
731 V27,
732 V28,
733 V29,
734 V30,
735 V31
736 );
737
738 // Double precision float registers have virtual `high halves' that
739 // are needed by the allocator.
740 // Class for all double registers
741 reg_class double_reg(
742 V0, V0_H,
743 V1, V1_H,
744 V2, V2_H,
745 V3, V3_H,
746 V4, V4_H,
747 V5, V5_H,
748 V6, V6_H,
749 V7, V7_H,
750 V8, V8_H,
751 V9, V9_H,
752 V10, V10_H,
753 V11, V11_H,
754 V12, V12_H,
755 V13, V13_H,
756 V14, V14_H,
757 V15, V15_H,
758 V16, V16_H,
759 V17, V17_H,
760 V18, V18_H,
761 V19, V19_H,
762 V20, V20_H,
763 V21, V21_H,
764 V22, V22_H,
765 V23, V23_H,
766 V24, V24_H,
767 V25, V25_H,
768 V26, V26_H,
769 V27, V27_H,
770 V28, V28_H,
771 V29, V29_H,
772 V30, V30_H,
773 V31, V31_H
774 );
775
776 // Class for all SVE vector registers.
777 reg_class vectora_reg (
778 V0, V0_H, V0_J, V0_K,
779 V1, V1_H, V1_J, V1_K,
780 V2, V2_H, V2_J, V2_K,
781 V3, V3_H, V3_J, V3_K,
782 V4, V4_H, V4_J, V4_K,
783 V5, V5_H, V5_J, V5_K,
784 V6, V6_H, V6_J, V6_K,
785 V7, V7_H, V7_J, V7_K,
786 V8, V8_H, V8_J, V8_K,
787 V9, V9_H, V9_J, V9_K,
788 V10, V10_H, V10_J, V10_K,
789 V11, V11_H, V11_J, V11_K,
790 V12, V12_H, V12_J, V12_K,
791 V13, V13_H, V13_J, V13_K,
792 V14, V14_H, V14_J, V14_K,
793 V15, V15_H, V15_J, V15_K,
794 V16, V16_H, V16_J, V16_K,
795 V17, V17_H, V17_J, V17_K,
796 V18, V18_H, V18_J, V18_K,
797 V19, V19_H, V19_J, V19_K,
798 V20, V20_H, V20_J, V20_K,
799 V21, V21_H, V21_J, V21_K,
800 V22, V22_H, V22_J, V22_K,
801 V23, V23_H, V23_J, V23_K,
802 V24, V24_H, V24_J, V24_K,
803 V25, V25_H, V25_J, V25_K,
804 V26, V26_H, V26_J, V26_K,
805 V27, V27_H, V27_J, V27_K,
806 V28, V28_H, V28_J, V28_K,
807 V29, V29_H, V29_J, V29_K,
808 V30, V30_H, V30_J, V30_K,
809 V31, V31_H, V31_J, V31_K,
810 );
811
812 // Class for all 64bit vector registers
813 reg_class vectord_reg(
814 V0, V0_H,
815 V1, V1_H,
816 V2, V2_H,
817 V3, V3_H,
818 V4, V4_H,
819 V5, V5_H,
820 V6, V6_H,
821 V7, V7_H,
822 V8, V8_H,
823 V9, V9_H,
824 V10, V10_H,
825 V11, V11_H,
826 V12, V12_H,
827 V13, V13_H,
828 V14, V14_H,
829 V15, V15_H,
830 V16, V16_H,
831 V17, V17_H,
832 V18, V18_H,
833 V19, V19_H,
834 V20, V20_H,
835 V21, V21_H,
836 V22, V22_H,
837 V23, V23_H,
838 V24, V24_H,
839 V25, V25_H,
840 V26, V26_H,
841 V27, V27_H,
842 V28, V28_H,
843 V29, V29_H,
844 V30, V30_H,
845 V31, V31_H
846 );
847
848 // Class for all 128bit vector registers
849 reg_class vectorx_reg(
850 V0, V0_H, V0_J, V0_K,
851 V1, V1_H, V1_J, V1_K,
852 V2, V2_H, V2_J, V2_K,
853 V3, V3_H, V3_J, V3_K,
854 V4, V4_H, V4_J, V4_K,
855 V5, V5_H, V5_J, V5_K,
856 V6, V6_H, V6_J, V6_K,
857 V7, V7_H, V7_J, V7_K,
858 V8, V8_H, V8_J, V8_K,
859 V9, V9_H, V9_J, V9_K,
860 V10, V10_H, V10_J, V10_K,
861 V11, V11_H, V11_J, V11_K,
862 V12, V12_H, V12_J, V12_K,
863 V13, V13_H, V13_J, V13_K,
864 V14, V14_H, V14_J, V14_K,
865 V15, V15_H, V15_J, V15_K,
866 V16, V16_H, V16_J, V16_K,
867 V17, V17_H, V17_J, V17_K,
868 V18, V18_H, V18_J, V18_K,
869 V19, V19_H, V19_J, V19_K,
870 V20, V20_H, V20_J, V20_K,
871 V21, V21_H, V21_J, V21_K,
872 V22, V22_H, V22_J, V22_K,
873 V23, V23_H, V23_J, V23_K,
874 V24, V24_H, V24_J, V24_K,
875 V25, V25_H, V25_J, V25_K,
876 V26, V26_H, V26_J, V26_K,
877 V27, V27_H, V27_J, V27_K,
878 V28, V28_H, V28_J, V28_K,
879 V29, V29_H, V29_J, V29_K,
880 V30, V30_H, V30_J, V30_K,
881 V31, V31_H, V31_J, V31_K
882 );
883
884 // Class for 128 bit register v0
885 reg_class v0_reg(
886 V0, V0_H
887 );
888
889 // Class for 128 bit register v1
890 reg_class v1_reg(
891 V1, V1_H
892 );
893
894 // Class for 128 bit register v2
895 reg_class v2_reg(
896 V2, V2_H
897 );
898
899 // Class for 128 bit register v3
900 reg_class v3_reg(
901 V3, V3_H
902 );
903
904 // Class for 128 bit register v4
905 reg_class v4_reg(
906 V4, V4_H
907 );
908
909 // Class for 128 bit register v5
910 reg_class v5_reg(
911 V5, V5_H
912 );
913
914 // Class for 128 bit register v6
915 reg_class v6_reg(
916 V6, V6_H
917 );
918
919 // Class for 128 bit register v7
920 reg_class v7_reg(
921 V7, V7_H
922 );
923
924 // Class for 128 bit register v8
925 reg_class v8_reg(
926 V8, V8_H
927 );
928
929 // Class for 128 bit register v9
930 reg_class v9_reg(
931 V9, V9_H
932 );
933
934 // Class for 128 bit register v10
935 reg_class v10_reg(
936 V10, V10_H
937 );
938
939 // Class for 128 bit register v11
940 reg_class v11_reg(
941 V11, V11_H
942 );
943
944 // Class for 128 bit register v12
945 reg_class v12_reg(
946 V12, V12_H
947 );
948
949 // Class for 128 bit register v13
950 reg_class v13_reg(
951 V13, V13_H
952 );
953
954 // Class for 128 bit register v14
955 reg_class v14_reg(
956 V14, V14_H
957 );
958
959 // Class for 128 bit register v15
960 reg_class v15_reg(
961 V15, V15_H
962 );
963
964 // Class for 128 bit register v16
965 reg_class v16_reg(
966 V16, V16_H
967 );
968
969 // Class for 128 bit register v17
970 reg_class v17_reg(
971 V17, V17_H
972 );
973
974 // Class for 128 bit register v18
975 reg_class v18_reg(
976 V18, V18_H
977 );
978
979 // Class for 128 bit register v19
980 reg_class v19_reg(
981 V19, V19_H
982 );
983
984 // Class for 128 bit register v20
985 reg_class v20_reg(
986 V20, V20_H
987 );
988
989 // Class for 128 bit register v21
990 reg_class v21_reg(
991 V21, V21_H
992 );
993
994 // Class for 128 bit register v22
995 reg_class v22_reg(
996 V22, V22_H
997 );
998
999 // Class for 128 bit register v23
1000 reg_class v23_reg(
1001 V23, V23_H
1002 );
1003
1004 // Class for 128 bit register v24
1005 reg_class v24_reg(
1006 V24, V24_H
1007 );
1008
1009 // Class for 128 bit register v25
1010 reg_class v25_reg(
1011 V25, V25_H
1012 );
1013
1014 // Class for 128 bit register v26
1015 reg_class v26_reg(
1016 V26, V26_H
1017 );
1018
1019 // Class for 128 bit register v27
1020 reg_class v27_reg(
1021 V27, V27_H
1022 );
1023
1024 // Class for 128 bit register v28
1025 reg_class v28_reg(
1026 V28, V28_H
1027 );
1028
1029 // Class for 128 bit register v29
1030 reg_class v29_reg(
1031 V29, V29_H
1032 );
1033
1034 // Class for 128 bit register v30
1035 reg_class v30_reg(
1036 V30, V30_H
1037 );
1038
1039 // Class for 128 bit register v31
1040 reg_class v31_reg(
1041 V31, V31_H
1042 );
1043
1044 // Class for all SVE predicate registers.
1045 reg_class pr_reg (
1046 P0,
1047 P1,
1048 P2,
1049 P3,
1050 P4,
1051 P5,
1052 P6,
1053 // P7, non-allocatable, preserved with all elements preset to TRUE.
1054 P8,
1055 P9,
1056 P10,
1057 P11,
1058 P12,
1059 P13,
1060 P14,
1061 P15
1062 );
1063
1064 // Class for SVE governing predicate registers, which are used
1065 // to determine the active elements of a predicated instruction.
1066 reg_class gov_pr (
1067 P0,
1068 P1,
1069 P2,
1070 P3,
1071 P4,
1072 P5,
1073 P6,
1074 // P7, non-allocatable, preserved with all elements preset to TRUE.
1075 );
1076
1077 reg_class p0_reg(P0);
1078 reg_class p1_reg(P1);
1079
1080 // Singleton class for condition codes
1081 reg_class int_flags(RFLAGS);
1082
1083 %}
1084
1085 //----------DEFINITION BLOCK---------------------------------------------------
1086 // Define name --> value mappings to inform the ADLC of an integer valued name
1087 // Current support includes integer values in the range [0, 0x7FFFFFFF]
1088 // Format:
1089 // int_def <name> ( <int_value>, <expression>);
1090 // Generated Code in ad_<arch>.hpp
1091 // #define <name> (<expression>)
1092 // // value == <int_value>
1093 // Generated code in ad_<arch>.cpp adlc_verification()
1094 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
1095 //
1096
1097 // we follow the ppc-aix port in using a simple cost model which ranks
1098 // register operations as cheap, memory ops as more expensive and
1099 // branches as most expensive. the first two have a low as well as a
1100 // normal cost. huge cost appears to be a way of saying don't do
1101 // something
1102
1103 definitions %{
1104 // The default cost (of a register move instruction).
1105 int_def INSN_COST ( 100, 100);
1106 int_def BRANCH_COST ( 200, 2 * INSN_COST);
1107 int_def CALL_COST ( 200, 2 * INSN_COST);
1108 int_def VOLATILE_REF_COST ( 1000, 10 * INSN_COST);
1109 %}
1110
1111
1112 //----------SOURCE BLOCK-------------------------------------------------------
1113 // This is a block of C++ code which provides values, functions, and
1114 // definitions necessary in the rest of the architecture description
1115
1116 source_hpp %{
1117
1118 #include "asm/macroAssembler.hpp"
1119 #include "gc/shared/barrierSetAssembler.hpp"
1120 #include "gc/shared/cardTable.hpp"
1121 #include "gc/shared/cardTableBarrierSet.hpp"
1122 #include "gc/shared/collectedHeap.hpp"
1123 #include "opto/addnode.hpp"
1124 #include "opto/convertnode.hpp"
1125 #include "runtime/objectMonitor.hpp"
1126
1127 extern RegMask _ANY_REG32_mask;
1128 extern RegMask _ANY_REG_mask;
1129 extern RegMask _PTR_REG_mask;
1130 extern RegMask _NO_SPECIAL_REG32_mask;
1131 extern RegMask _NO_SPECIAL_REG_mask;
1132 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1133 extern RegMask _NO_SPECIAL_NO_RFP_PTR_REG_mask;
1134
1135 class CallStubImpl {
1136
1137 //--------------------------------------------------------------
1138 //---< Used for optimization in Compile::shorten_branches >---
1139 //--------------------------------------------------------------
1140
1141 public:
1142 // Size of call trampoline stub.
1143 static uint size_call_trampoline() {
1144 return 0; // no call trampolines on this platform
1145 }
1146
1147 // number of relocations needed by a call trampoline stub
1148 static uint reloc_call_trampoline() {
1149 return 0; // no call trampolines on this platform
1150 }
1151 };
1152
1153 class HandlerImpl {
1154
1155 public:
1156
1157 static int emit_exception_handler(C2_MacroAssembler *masm);
1158 static int emit_deopt_handler(C2_MacroAssembler* masm);
1159
1160 static uint size_exception_handler() {
1161 return MacroAssembler::far_codestub_branch_size();
1162 }
1163
1164 static uint size_deopt_handler() {
1165 // count one adr and one far branch instruction
1166 return NativeInstruction::instruction_size + MacroAssembler::far_codestub_branch_size();
1167 }
1168 };
1169
1170 class Node::PD {
1171 public:
1172 enum NodeFlags {
1173 _last_flag = Node::_last_flag
1174 };
1175 };
1176
1177 bool is_CAS(int opcode, bool maybe_volatile);
1178
1179 // predicates controlling emit of ldr<x>/ldar<x> and associated dmb
1180
1181 bool unnecessary_acquire(const Node *barrier);
1182 bool needs_acquiring_load(const Node *load);
1183
1184 // predicates controlling emit of str<x>/stlr<x> and associated dmbs
1185
1186 bool unnecessary_release(const Node *barrier);
1187 bool unnecessary_volatile(const Node *barrier);
1188 bool needs_releasing_store(const Node *store);
1189
1190 // predicate controlling translation of CompareAndSwapX
1191 bool needs_acquiring_load_exclusive(const Node *load);
1192
1193 // predicate controlling addressing modes
1194 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1195
1196 // Convert BootTest condition to Assembler condition.
1197 // Replicate the logic of cmpOpOper::ccode() and cmpOpUOper::ccode().
1198 Assembler::Condition to_assembler_cond(BoolTest::mask cond);
1199 %}
1200
1201 source %{
1202
1203 // Derived RegMask with conditionally allocatable registers
1204
1205 void PhaseOutput::pd_perform_mach_node_analysis() {
1206 }
1207
1208 int MachNode::pd_alignment_required() const {
1209 return 1;
1210 }
1211
1212 int MachNode::compute_padding(int current_offset) const {
1213 return 0;
1214 }
1215
1216 RegMask _ANY_REG32_mask;
1217 RegMask _ANY_REG_mask;
1218 RegMask _PTR_REG_mask;
1219 RegMask _NO_SPECIAL_REG32_mask;
1220 RegMask _NO_SPECIAL_REG_mask;
1221 RegMask _NO_SPECIAL_PTR_REG_mask;
1222 RegMask _NO_SPECIAL_NO_RFP_PTR_REG_mask;
1223
1224 void reg_mask_init() {
1225 // We derive below RegMask(s) from the ones which are auto-generated from
1226 // adlc register classes to make AArch64 rheapbase (r27) and rfp (r29)
1227 // registers conditionally reserved.
1228
1229 _ANY_REG32_mask = _ALL_REG32_mask;
1230 _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(r31_sp->as_VMReg()));
1231
1232 _ANY_REG_mask = _ALL_REG_mask;
1233
1234 _PTR_REG_mask = _ALL_REG_mask;
1235
1236 _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1237 _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
1238
1239 _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1240 _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1241
1242 _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1243 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1244
1245 // r27 is not allocatable when compressed oops is on and heapbase is not
1246 // zero, compressed klass pointers doesn't use r27 after JDK-8234794
1247 if (UseCompressedOops && (CompressedOops::ptrs_base() != nullptr)) {
1248 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(r27->as_VMReg()));
1249 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(r27->as_VMReg()));
1250 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(r27->as_VMReg()));
1251 }
1252
1253 // r29 is not allocatable when PreserveFramePointer is on
1254 if (PreserveFramePointer) {
1255 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(r29->as_VMReg()));
1256 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(r29->as_VMReg()));
1257 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(r29->as_VMReg()));
1258 }
1259
1260 _NO_SPECIAL_NO_RFP_PTR_REG_mask = _NO_SPECIAL_PTR_REG_mask;
1261 _NO_SPECIAL_NO_RFP_PTR_REG_mask.Remove(OptoReg::as_OptoReg(r29->as_VMReg()));
1262 }
1263
1264 // Optimizaton of volatile gets and puts
1265 // -------------------------------------
1266 //
1267 // AArch64 has ldar<x> and stlr<x> instructions which we can safely
1268 // use to implement volatile reads and writes. For a volatile read
1269 // we simply need
1270 //
1271 // ldar<x>
1272 //
1273 // and for a volatile write we need
1274 //
1275 // stlr<x>
1276 //
1277 // Alternatively, we can implement them by pairing a normal
1278 // load/store with a memory barrier. For a volatile read we need
1279 //
1280 // ldr<x>
1281 // dmb ishld
1282 //
1283 // for a volatile write
1284 //
1285 // dmb ish
1286 // str<x>
1287 // dmb ish
1288 //
1289 // We can also use ldaxr and stlxr to implement compare and swap CAS
1290 // sequences. These are normally translated to an instruction
1291 // sequence like the following
1292 //
1293 // dmb ish
1294 // retry:
1295 // ldxr<x> rval raddr
1296 // cmp rval rold
1297 // b.ne done
1298 // stlxr<x> rval, rnew, rold
1299 // cbnz rval retry
1300 // done:
1301 // cset r0, eq
1302 // dmb ishld
1303 //
1304 // Note that the exclusive store is already using an stlxr
1305 // instruction. That is required to ensure visibility to other
1306 // threads of the exclusive write (assuming it succeeds) before that
1307 // of any subsequent writes.
1308 //
1309 // The following instruction sequence is an improvement on the above
1310 //
1311 // retry:
1312 // ldaxr<x> rval raddr
1313 // cmp rval rold
1314 // b.ne done
1315 // stlxr<x> rval, rnew, rold
1316 // cbnz rval retry
1317 // done:
1318 // cset r0, eq
1319 //
1320 // We don't need the leading dmb ish since the stlxr guarantees
1321 // visibility of prior writes in the case that the swap is
1322 // successful. Crucially we don't have to worry about the case where
1323 // the swap is not successful since no valid program should be
1324 // relying on visibility of prior changes by the attempting thread
1325 // in the case where the CAS fails.
1326 //
1327 // Similarly, we don't need the trailing dmb ishld if we substitute
1328 // an ldaxr instruction since that will provide all the guarantees we
1329 // require regarding observation of changes made by other threads
1330 // before any change to the CAS address observed by the load.
1331 //
1332 // In order to generate the desired instruction sequence we need to
1333 // be able to identify specific 'signature' ideal graph node
1334 // sequences which i) occur as a translation of a volatile reads or
1335 // writes or CAS operations and ii) do not occur through any other
1336 // translation or graph transformation. We can then provide
1337 // alternative aldc matching rules which translate these node
1338 // sequences to the desired machine code sequences. Selection of the
1339 // alternative rules can be implemented by predicates which identify
1340 // the relevant node sequences.
1341 //
1342 // The ideal graph generator translates a volatile read to the node
1343 // sequence
1344 //
1345 // LoadX[mo_acquire]
1346 // MemBarAcquire
1347 //
1348 // As a special case when using the compressed oops optimization we
1349 // may also see this variant
1350 //
1351 // LoadN[mo_acquire]
1352 // DecodeN
1353 // MemBarAcquire
1354 //
1355 // A volatile write is translated to the node sequence
1356 //
1357 // MemBarRelease
1358 // StoreX[mo_release] {CardMark}-optional
1359 // MemBarVolatile
1360 //
1361 // n.b. the above node patterns are generated with a strict
1362 // 'signature' configuration of input and output dependencies (see
1363 // the predicates below for exact details). The card mark may be as
1364 // simple as a few extra nodes or, in a few GC configurations, may
1365 // include more complex control flow between the leading and
1366 // trailing memory barriers. However, whatever the card mark
1367 // configuration these signatures are unique to translated volatile
1368 // reads/stores -- they will not appear as a result of any other
1369 // bytecode translation or inlining nor as a consequence of
1370 // optimizing transforms.
1371 //
1372 // We also want to catch inlined unsafe volatile gets and puts and
1373 // be able to implement them using either ldar<x>/stlr<x> or some
1374 // combination of ldr<x>/stlr<x> and dmb instructions.
1375 //
1376 // Inlined unsafe volatiles puts manifest as a minor variant of the
1377 // normal volatile put node sequence containing an extra cpuorder
1378 // membar
1379 //
1380 // MemBarRelease
1381 // MemBarCPUOrder
1382 // StoreX[mo_release] {CardMark}-optional
1383 // MemBarCPUOrder
1384 // MemBarVolatile
1385 //
1386 // n.b. as an aside, a cpuorder membar is not itself subject to
1387 // matching and translation by adlc rules. However, the rule
1388 // predicates need to detect its presence in order to correctly
1389 // select the desired adlc rules.
1390 //
1391 // Inlined unsafe volatile gets manifest as a slightly different
1392 // node sequence to a normal volatile get because of the
1393 // introduction of some CPUOrder memory barriers to bracket the
1394 // Load. However, but the same basic skeleton of a LoadX feeding a
1395 // MemBarAcquire, possibly through an optional DecodeN, is still
1396 // present
1397 //
1398 // MemBarCPUOrder
1399 // || \\
1400 // MemBarCPUOrder LoadX[mo_acquire]
1401 // || |
1402 // || {DecodeN} optional
1403 // || /
1404 // MemBarAcquire
1405 //
1406 // In this case the acquire membar does not directly depend on the
1407 // load. However, we can be sure that the load is generated from an
1408 // inlined unsafe volatile get if we see it dependent on this unique
1409 // sequence of membar nodes. Similarly, given an acquire membar we
1410 // can know that it was added because of an inlined unsafe volatile
1411 // get if it is fed and feeds a cpuorder membar and if its feed
1412 // membar also feeds an acquiring load.
1413 //
1414 // Finally an inlined (Unsafe) CAS operation is translated to the
1415 // following ideal graph
1416 //
1417 // MemBarRelease
1418 // MemBarCPUOrder
1419 // CompareAndSwapX {CardMark}-optional
1420 // MemBarCPUOrder
1421 // MemBarAcquire
1422 //
1423 // So, where we can identify these volatile read and write
1424 // signatures we can choose to plant either of the above two code
1425 // sequences. For a volatile read we can simply plant a normal
1426 // ldr<x> and translate the MemBarAcquire to a dmb. However, we can
1427 // also choose to inhibit translation of the MemBarAcquire and
1428 // inhibit planting of the ldr<x>, instead planting an ldar<x>.
1429 //
1430 // When we recognise a volatile store signature we can choose to
1431 // plant at a dmb ish as a translation for the MemBarRelease, a
1432 // normal str<x> and then a dmb ish for the MemBarVolatile.
1433 // Alternatively, we can inhibit translation of the MemBarRelease
1434 // and MemBarVolatile and instead plant a simple stlr<x>
1435 // instruction.
1436 //
1437 // when we recognise a CAS signature we can choose to plant a dmb
1438 // ish as a translation for the MemBarRelease, the conventional
1439 // macro-instruction sequence for the CompareAndSwap node (which
1440 // uses ldxr<x>) and then a dmb ishld for the MemBarAcquire.
1441 // Alternatively, we can elide generation of the dmb instructions
1442 // and plant the alternative CompareAndSwap macro-instruction
1443 // sequence (which uses ldaxr<x>).
1444 //
1445 // Of course, the above only applies when we see these signature
1446 // configurations. We still want to plant dmb instructions in any
1447 // other cases where we may see a MemBarAcquire, MemBarRelease or
1448 // MemBarVolatile. For example, at the end of a constructor which
1449 // writes final/volatile fields we will see a MemBarRelease
1450 // instruction and this needs a 'dmb ish' lest we risk the
1451 // constructed object being visible without making the
1452 // final/volatile field writes visible.
1453 //
1454 // n.b. the translation rules below which rely on detection of the
1455 // volatile signatures and insert ldar<x> or stlr<x> are failsafe.
1456 // If we see anything other than the signature configurations we
1457 // always just translate the loads and stores to ldr<x> and str<x>
1458 // and translate acquire, release and volatile membars to the
1459 // relevant dmb instructions.
1460 //
1461
1462 // is_CAS(int opcode, bool maybe_volatile)
1463 //
1464 // return true if opcode is one of the possible CompareAndSwapX
1465 // values otherwise false.
1466
1467 bool is_CAS(int opcode, bool maybe_volatile)
1468 {
1469 switch(opcode) {
1470 // We handle these
1471 case Op_CompareAndSwapI:
1472 case Op_CompareAndSwapL:
1473 case Op_CompareAndSwapP:
1474 case Op_CompareAndSwapN:
1475 case Op_ShenandoahCompareAndSwapP:
1476 case Op_ShenandoahCompareAndSwapN:
1477 case Op_CompareAndSwapB:
1478 case Op_CompareAndSwapS:
1479 case Op_GetAndSetI:
1480 case Op_GetAndSetL:
1481 case Op_GetAndSetP:
1482 case Op_GetAndSetN:
1483 case Op_GetAndAddI:
1484 case Op_GetAndAddL:
1485 return true;
1486 case Op_CompareAndExchangeI:
1487 case Op_CompareAndExchangeN:
1488 case Op_CompareAndExchangeB:
1489 case Op_CompareAndExchangeS:
1490 case Op_CompareAndExchangeL:
1491 case Op_CompareAndExchangeP:
1492 case Op_WeakCompareAndSwapB:
1493 case Op_WeakCompareAndSwapS:
1494 case Op_WeakCompareAndSwapI:
1495 case Op_WeakCompareAndSwapL:
1496 case Op_WeakCompareAndSwapP:
1497 case Op_WeakCompareAndSwapN:
1498 case Op_ShenandoahWeakCompareAndSwapP:
1499 case Op_ShenandoahWeakCompareAndSwapN:
1500 case Op_ShenandoahCompareAndExchangeP:
1501 case Op_ShenandoahCompareAndExchangeN:
1502 return maybe_volatile;
1503 default:
1504 return false;
1505 }
1506 }
1507
1508 // helper to determine the maximum number of Phi nodes we may need to
1509 // traverse when searching from a card mark membar for the merge mem
1510 // feeding a trailing membar or vice versa
1511
1512 // predicates controlling emit of ldr<x>/ldar<x>
1513
1514 bool unnecessary_acquire(const Node *barrier)
1515 {
1516 assert(barrier->is_MemBar(), "expecting a membar");
1517
1518 MemBarNode* mb = barrier->as_MemBar();
1519
1520 if (mb->trailing_load()) {
1521 return true;
1522 }
1523
1524 if (mb->trailing_load_store()) {
1525 Node* load_store = mb->in(MemBarNode::Precedent);
1526 assert(load_store->is_LoadStore(), "unexpected graph shape");
1527 return is_CAS(load_store->Opcode(), true);
1528 }
1529
1530 return false;
1531 }
1532
1533 bool needs_acquiring_load(const Node *n)
1534 {
1535 assert(n->is_Load(), "expecting a load");
1536 LoadNode *ld = n->as_Load();
1537 return ld->is_acquire();
1538 }
1539
1540 bool unnecessary_release(const Node *n)
1541 {
1542 assert((n->is_MemBar() &&
1543 n->Opcode() == Op_MemBarRelease),
1544 "expecting a release membar");
1545
1546 MemBarNode *barrier = n->as_MemBar();
1547 if (!barrier->leading()) {
1548 return false;
1549 } else {
1550 Node* trailing = barrier->trailing_membar();
1551 MemBarNode* trailing_mb = trailing->as_MemBar();
1552 assert(trailing_mb->trailing(), "Not a trailing membar?");
1553 assert(trailing_mb->leading_membar() == n, "inconsistent leading/trailing membars");
1554
1555 Node* mem = trailing_mb->in(MemBarNode::Precedent);
1556 if (mem->is_Store()) {
1557 assert(mem->as_Store()->is_release(), "");
1558 assert(trailing_mb->Opcode() == Op_MemBarVolatile, "");
1559 return true;
1560 } else {
1561 assert(mem->is_LoadStore(), "");
1562 assert(trailing_mb->Opcode() == Op_MemBarAcquire, "");
1563 return is_CAS(mem->Opcode(), true);
1564 }
1565 }
1566 return false;
1567 }
1568
1569 bool unnecessary_volatile(const Node *n)
1570 {
1571 // assert n->is_MemBar();
1572 MemBarNode *mbvol = n->as_MemBar();
1573
1574 bool release = mbvol->trailing_store();
1575 assert(!release || (mbvol->in(MemBarNode::Precedent)->is_Store() && mbvol->in(MemBarNode::Precedent)->as_Store()->is_release()), "");
1576 #ifdef ASSERT
1577 if (release) {
1578 Node* leading = mbvol->leading_membar();
1579 assert(leading->Opcode() == Op_MemBarRelease, "");
1580 assert(leading->as_MemBar()->leading_store(), "");
1581 assert(leading->as_MemBar()->trailing_membar() == mbvol, "");
1582 }
1583 #endif
1584
1585 return release;
1586 }
1587
1588 // predicates controlling emit of str<x>/stlr<x>
1589
1590 bool needs_releasing_store(const Node *n)
1591 {
1592 // assert n->is_Store();
1593 StoreNode *st = n->as_Store();
1594 return st->trailing_membar() != nullptr;
1595 }
1596
1597 // predicate controlling translation of CAS
1598 //
1599 // returns true if CAS needs to use an acquiring load otherwise false
1600
1601 bool needs_acquiring_load_exclusive(const Node *n)
1602 {
1603 assert(is_CAS(n->Opcode(), true), "expecting a compare and swap");
1604 LoadStoreNode* ldst = n->as_LoadStore();
1605 if (is_CAS(n->Opcode(), false)) {
1606 assert(ldst->trailing_membar() != nullptr, "expected trailing membar");
1607 } else {
1608 return ldst->trailing_membar() != nullptr;
1609 }
1610
1611 // so we can just return true here
1612 return true;
1613 }
1614
1615 #define __ masm->
1616
1617 // advance declarations for helper functions to convert register
1618 // indices to register objects
1619
1620 // the ad file has to provide implementations of certain methods
1621 // expected by the generic code
1622 //
1623 // REQUIRED FUNCTIONALITY
1624
1625 //=============================================================================
1626
1627 // !!!!! Special hack to get all types of calls to specify the byte offset
1628 // from the start of the call to the point where the return address
1629 // will point.
1630
1631 int MachCallStaticJavaNode::ret_addr_offset()
1632 {
1633 // call should be a simple bl
1634 int off = 4;
1635 return off;
1636 }
1637
1638 int MachCallDynamicJavaNode::ret_addr_offset()
1639 {
1640 return 16; // movz, movk, movk, bl
1641 }
1642
1643 int MachCallRuntimeNode::ret_addr_offset() {
1644 // for generated stubs the call will be
1645 // bl(addr)
1646 // or with far branches
1647 // bl(trampoline_stub)
1648 // for real runtime callouts it will be six instructions
1649 // see aarch64_enc_java_to_runtime
1650 // adr(rscratch2, retaddr)
1651 // lea(rscratch1, RuntimeAddress(addr)
1652 // stp(zr, rscratch2, Address(__ pre(sp, -2 * wordSize)))
1653 // blr(rscratch1)
1654 CodeBlob *cb = CodeCache::find_blob(_entry_point);
1655 if (cb) {
1656 return 1 * NativeInstruction::instruction_size;
1657 } else {
1658 return 6 * NativeInstruction::instruction_size;
1659 }
1660 }
1661
1662 //=============================================================================
1663
1664 #ifndef PRODUCT
1665 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1666 st->print("BREAKPOINT");
1667 }
1668 #endif
1669
1670 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1671 __ brk(0);
1672 }
1673
1674 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1675 return MachNode::size(ra_);
1676 }
1677
1678 //=============================================================================
1679
1680 #ifndef PRODUCT
1681 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1682 st->print("nop \t# %d bytes pad for loops and calls", _count);
1683 }
1684 #endif
1685
1686 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1687 for (int i = 0; i < _count; i++) {
1688 __ nop();
1689 }
1690 }
1691
1692 uint MachNopNode::size(PhaseRegAlloc*) const {
1693 return _count * NativeInstruction::instruction_size;
1694 }
1695
1696 //=============================================================================
1697 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1698
1699 int ConstantTable::calculate_table_base_offset() const {
1700 return 0; // absolute addressing, no offset
1701 }
1702
1703 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1704 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1705 ShouldNotReachHere();
1706 }
1707
1708 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1709 // Empty encoding
1710 }
1711
1712 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1713 return 0;
1714 }
1715
1716 #ifndef PRODUCT
1717 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1718 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1719 }
1720 #endif
1721
1722 #ifndef PRODUCT
1723 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1724 Compile* C = ra_->C;
1725
1726 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1727
1728 if (C->output()->need_stack_bang(framesize))
1729 st->print("# stack bang size=%d\n\t", framesize);
1730
1731 if (VM_Version::use_rop_protection()) {
1732 st->print("ldr zr, [lr]\n\t");
1733 st->print("paciaz\n\t");
1734 }
1735 if (framesize < ((1 << 9) + 2 * wordSize)) {
1736 st->print("sub sp, sp, #%d\n\t", framesize);
1737 st->print("stp rfp, lr, [sp, #%d]", framesize - 2 * wordSize);
1738 if (PreserveFramePointer) st->print("\n\tadd rfp, sp, #%d", framesize - 2 * wordSize);
1739 } else {
1740 st->print("stp lr, rfp, [sp, #%d]!\n\t", -(2 * wordSize));
1741 if (PreserveFramePointer) st->print("mov rfp, sp\n\t");
1742 st->print("mov rscratch1, #%d\n\t", framesize - 2 * wordSize);
1743 st->print("sub sp, sp, rscratch1");
1744 }
1745 if (C->stub_function() == nullptr && BarrierSet::barrier_set()->barrier_set_nmethod() != nullptr) {
1746 st->print("\n\t");
1747 st->print("ldr rscratch1, [guard]\n\t");
1748 st->print("dmb ishld\n\t");
1749 st->print("ldr rscratch2, [rthread, #thread_disarmed_guard_value_offset]\n\t");
1750 st->print("cmp rscratch1, rscratch2\n\t");
1751 st->print("b.eq skip");
1752 st->print("\n\t");
1753 st->print("blr #nmethod_entry_barrier_stub\n\t");
1754 st->print("b skip\n\t");
1755 st->print("guard: int\n\t");
1756 st->print("\n\t");
1757 st->print("skip:\n\t");
1758 }
1759 }
1760 #endif
1761
1762 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1763 Compile* C = ra_->C;
1764
1765 // n.b. frame size includes space for return pc and rfp
1766 const int framesize = C->output()->frame_size_in_bytes();
1767
1768 // insert a nop at the start of the prolog so we can patch in a
1769 // branch if we need to invalidate the method later
1770 __ nop();
1771
1772 if (C->clinit_barrier_on_entry()) {
1773 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1774
1775 Label L_skip_barrier;
1776
1777 __ mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
1778 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
1779 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1780 __ bind(L_skip_barrier);
1781 }
1782
1783 if (C->max_vector_size() > 0) {
1784 __ reinitialize_ptrue();
1785 }
1786
1787 int bangsize = C->output()->bang_size_in_bytes();
1788 if (C->output()->need_stack_bang(bangsize))
1789 __ generate_stack_overflow_check(bangsize);
1790
1791 __ build_frame(framesize);
1792
1793 if (C->stub_function() == nullptr) {
1794 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1795 if (BarrierSet::barrier_set()->barrier_set_nmethod() != nullptr) {
1796 // Dummy labels for just measuring the code size
1797 Label dummy_slow_path;
1798 Label dummy_continuation;
1799 Label dummy_guard;
1800 Label* slow_path = &dummy_slow_path;
1801 Label* continuation = &dummy_continuation;
1802 Label* guard = &dummy_guard;
1803 if (!Compile::current()->output()->in_scratch_emit_size()) {
1804 // Use real labels from actual stub when not emitting code for the purpose of measuring its size
1805 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1806 Compile::current()->output()->add_stub(stub);
1807 slow_path = &stub->entry();
1808 continuation = &stub->continuation();
1809 guard = &stub->guard();
1810 }
1811 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1812 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1813 }
1814 }
1815
1816 if (VerifyStackAtCalls) {
1817 Unimplemented();
1818 }
1819
1820 C->output()->set_frame_complete(__ offset());
1821
1822 if (C->has_mach_constant_base_node()) {
1823 // NOTE: We set the table base offset here because users might be
1824 // emitted before MachConstantBaseNode.
1825 ConstantTable& constant_table = C->output()->constant_table();
1826 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1827 }
1828 }
1829
1830 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1831 {
1832 return MachNode::size(ra_); // too many variables; just compute it
1833 // the hard way
1834 }
1835
1836 int MachPrologNode::reloc() const
1837 {
1838 return 0;
1839 }
1840
1841 //=============================================================================
1842
1843 #ifndef PRODUCT
1844 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1845 Compile* C = ra_->C;
1846 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1847
1848 st->print("# pop frame %d\n\t",framesize);
1849
1850 if (framesize == 0) {
1851 st->print("ldp lr, rfp, [sp],#%d\n\t", (2 * wordSize));
1852 } else if (framesize < ((1 << 9) + 2 * wordSize)) {
1853 st->print("ldp lr, rfp, [sp,#%d]\n\t", framesize - 2 * wordSize);
1854 st->print("add sp, sp, #%d\n\t", framesize);
1855 } else {
1856 st->print("mov rscratch1, #%d\n\t", framesize - 2 * wordSize);
1857 st->print("add sp, sp, rscratch1\n\t");
1858 st->print("ldp lr, rfp, [sp],#%d\n\t", (2 * wordSize));
1859 }
1860 if (VM_Version::use_rop_protection()) {
1861 st->print("autiaz\n\t");
1862 st->print("ldr zr, [lr]\n\t");
1863 }
1864
1865 if (do_polling() && C->is_method_compilation()) {
1866 st->print("# test polling word\n\t");
1867 st->print("ldr rscratch1, [rthread],#%d\n\t", in_bytes(JavaThread::polling_word_offset()));
1868 st->print("cmp sp, rscratch1\n\t");
1869 st->print("bhi #slow_path");
1870 }
1871 }
1872 #endif
1873
1874 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1875 Compile* C = ra_->C;
1876 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1877
1878 __ remove_frame(framesize);
1879
1880 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1881 __ reserved_stack_check();
1882 }
1883
1884 if (do_polling() && C->is_method_compilation()) {
1885 Label dummy_label;
1886 Label* code_stub = &dummy_label;
1887 if (!C->output()->in_scratch_emit_size()) {
1888 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1889 C->output()->add_stub(stub);
1890 code_stub = &stub->entry();
1891 }
1892 __ relocate(relocInfo::poll_return_type);
1893 __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
1894 }
1895 }
1896
1897 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1898 // Variable size. Determine dynamically.
1899 return MachNode::size(ra_);
1900 }
1901
1902 int MachEpilogNode::reloc() const {
1903 // Return number of relocatable values contained in this instruction.
1904 return 1; // 1 for polling page.
1905 }
1906
1907 const Pipeline * MachEpilogNode::pipeline() const {
1908 return MachNode::pipeline_class();
1909 }
1910
1911 //=============================================================================
1912
1913 static enum RC rc_class(OptoReg::Name reg) {
1914
1915 if (reg == OptoReg::Bad) {
1916 return rc_bad;
1917 }
1918
1919 // we have 32 int registers * 2 halves
1920 int slots_of_int_registers = Register::number_of_registers * Register::max_slots_per_register;
1921
1922 if (reg < slots_of_int_registers) {
1923 return rc_int;
1924 }
1925
1926 // we have 32 float register * 8 halves
1927 int slots_of_float_registers = FloatRegister::number_of_registers * FloatRegister::max_slots_per_register;
1928 if (reg < slots_of_int_registers + slots_of_float_registers) {
1929 return rc_float;
1930 }
1931
1932 int slots_of_predicate_registers = PRegister::number_of_registers * PRegister::max_slots_per_register;
1933 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_predicate_registers) {
1934 return rc_predicate;
1935 }
1936
1937 // Between predicate regs & stack is the flags.
1938 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1939
1940 return rc_stack;
1941 }
1942
1943 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1944 Compile* C = ra_->C;
1945
1946 // Get registers to move.
1947 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1948 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1949 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1950 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1951
1952 enum RC src_hi_rc = rc_class(src_hi);
1953 enum RC src_lo_rc = rc_class(src_lo);
1954 enum RC dst_hi_rc = rc_class(dst_hi);
1955 enum RC dst_lo_rc = rc_class(dst_lo);
1956
1957 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1958
1959 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1960 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1961 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1962 "expected aligned-adjacent pairs");
1963 }
1964
1965 if (src_lo == dst_lo && src_hi == dst_hi) {
1966 return 0; // Self copy, no move.
1967 }
1968
1969 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1970 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1971 int src_offset = ra_->reg2offset(src_lo);
1972 int dst_offset = ra_->reg2offset(dst_lo);
1973
1974 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1975 uint ireg = ideal_reg();
1976 if (ireg == Op_VecA && masm) {
1977 int sve_vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1978 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1979 // stack->stack
1980 __ spill_copy_sve_vector_stack_to_stack(src_offset, dst_offset,
1981 sve_vector_reg_size_in_bytes);
1982 } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1983 __ spill_sve_vector(as_FloatRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo),
1984 sve_vector_reg_size_in_bytes);
1985 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) {
1986 __ unspill_sve_vector(as_FloatRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo),
1987 sve_vector_reg_size_in_bytes);
1988 } else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1989 __ sve_orr(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1990 as_FloatRegister(Matcher::_regEncode[src_lo]),
1991 as_FloatRegister(Matcher::_regEncode[src_lo]));
1992 } else {
1993 ShouldNotReachHere();
1994 }
1995 } else if (masm) {
1996 assert(ireg == Op_VecD || ireg == Op_VecX, "must be 64 bit or 128 bit vector");
1997 assert((src_lo_rc != rc_int && dst_lo_rc != rc_int), "sanity");
1998 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1999 // stack->stack
2000 assert((src_offset & 7) == 0 && (dst_offset & 7) == 0, "unaligned stack offset");
2001 if (ireg == Op_VecD) {
2002 __ unspill(rscratch1, true, src_offset);
2003 __ spill(rscratch1, true, dst_offset);
2004 } else {
2005 __ spill_copy128(src_offset, dst_offset);
2006 }
2007 } else if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
2008 __ mov(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2009 ireg == Op_VecD ? __ T8B : __ T16B,
2010 as_FloatRegister(Matcher::_regEncode[src_lo]));
2011 } else if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
2012 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
2013 ireg == Op_VecD ? __ D : __ Q,
2014 ra_->reg2offset(dst_lo));
2015 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_float) {
2016 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2017 ireg == Op_VecD ? __ D : __ Q,
2018 ra_->reg2offset(src_lo));
2019 } else {
2020 ShouldNotReachHere();
2021 }
2022 }
2023 } else if (masm) {
2024 switch (src_lo_rc) {
2025 case rc_int:
2026 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
2027 if (is64) {
2028 __ mov(as_Register(Matcher::_regEncode[dst_lo]),
2029 as_Register(Matcher::_regEncode[src_lo]));
2030 } else {
2031 __ movw(as_Register(Matcher::_regEncode[dst_lo]),
2032 as_Register(Matcher::_regEncode[src_lo]));
2033 }
2034 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
2035 if (is64) {
2036 __ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2037 as_Register(Matcher::_regEncode[src_lo]));
2038 } else {
2039 __ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2040 as_Register(Matcher::_regEncode[src_lo]));
2041 }
2042 } else { // gpr --> stack spill
2043 assert(dst_lo_rc == rc_stack, "spill to bad register class");
2044 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
2045 }
2046 break;
2047 case rc_float:
2048 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
2049 if (is64) {
2050 __ fmovd(as_Register(Matcher::_regEncode[dst_lo]),
2051 as_FloatRegister(Matcher::_regEncode[src_lo]));
2052 } else {
2053 __ fmovs(as_Register(Matcher::_regEncode[dst_lo]),
2054 as_FloatRegister(Matcher::_regEncode[src_lo]));
2055 }
2056 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
2057 if (is64) {
2058 __ fmovd(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2059 as_FloatRegister(Matcher::_regEncode[src_lo]));
2060 } else {
2061 __ fmovs(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2062 as_FloatRegister(Matcher::_regEncode[src_lo]));
2063 }
2064 } else { // fpr --> stack spill
2065 assert(dst_lo_rc == rc_stack, "spill to bad register class");
2066 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
2067 is64 ? __ D : __ S, dst_offset);
2068 }
2069 break;
2070 case rc_stack:
2071 if (dst_lo_rc == rc_int) { // stack --> gpr load
2072 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
2073 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
2074 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
2075 is64 ? __ D : __ S, src_offset);
2076 } else if (dst_lo_rc == rc_predicate) {
2077 __ unspill_sve_predicate(as_PRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo),
2078 Matcher::scalable_vector_reg_size(T_BYTE) >> 3);
2079 } else { // stack --> stack copy
2080 assert(dst_lo_rc == rc_stack, "spill to bad register class");
2081 if (ideal_reg() == Op_RegVectMask) {
2082 __ spill_copy_sve_predicate_stack_to_stack(src_offset, dst_offset,
2083 Matcher::scalable_vector_reg_size(T_BYTE) >> 3);
2084 } else {
2085 __ unspill(rscratch1, is64, src_offset);
2086 __ spill(rscratch1, is64, dst_offset);
2087 }
2088 }
2089 break;
2090 case rc_predicate:
2091 if (dst_lo_rc == rc_predicate) {
2092 __ sve_mov(as_PRegister(Matcher::_regEncode[dst_lo]), as_PRegister(Matcher::_regEncode[src_lo]));
2093 } else if (dst_lo_rc == rc_stack) {
2094 __ spill_sve_predicate(as_PRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo),
2095 Matcher::scalable_vector_reg_size(T_BYTE) >> 3);
2096 } else {
2097 assert(false, "bad src and dst rc_class combination.");
2098 ShouldNotReachHere();
2099 }
2100 break;
2101 default:
2102 assert(false, "bad rc_class for spill");
2103 ShouldNotReachHere();
2104 }
2105 }
2106
2107 if (st) {
2108 st->print("spill ");
2109 if (src_lo_rc == rc_stack) {
2110 st->print("[sp, #%d] -> ", ra_->reg2offset(src_lo));
2111 } else {
2112 st->print("%s -> ", Matcher::regName[src_lo]);
2113 }
2114 if (dst_lo_rc == rc_stack) {
2115 st->print("[sp, #%d]", ra_->reg2offset(dst_lo));
2116 } else {
2117 st->print("%s", Matcher::regName[dst_lo]);
2118 }
2119 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
2120 int vsize = 0;
2121 switch (ideal_reg()) {
2122 case Op_VecD:
2123 vsize = 64;
2124 break;
2125 case Op_VecX:
2126 vsize = 128;
2127 break;
2128 case Op_VecA:
2129 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
2130 break;
2131 default:
2132 assert(false, "bad register type for spill");
2133 ShouldNotReachHere();
2134 }
2135 st->print("\t# vector spill size = %d", vsize);
2136 } else if (ideal_reg() == Op_RegVectMask) {
2137 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
2138 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
2139 st->print("\t# predicate spill size = %d", vsize);
2140 } else {
2141 st->print("\t# spill size = %d", is64 ? 64 : 32);
2142 }
2143 }
2144
2145 return 0;
2146
2147 }
2148
2149 #ifndef PRODUCT
2150 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2151 if (!ra_)
2152 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
2153 else
2154 implementation(nullptr, ra_, false, st);
2155 }
2156 #endif
2157
2158 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
2159 implementation(masm, ra_, false, nullptr);
2160 }
2161
2162 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
2163 return MachNode::size(ra_);
2164 }
2165
2166 //=============================================================================
2167
2168 #ifndef PRODUCT
2169 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
2170 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2171 int reg = ra_->get_reg_first(this);
2172 st->print("add %s, rsp, #%d]\t# box lock",
2173 Matcher::regName[reg], offset);
2174 }
2175 #endif
2176
2177 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
2178 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2179 int reg = ra_->get_encode(this);
2180
2181 // This add will handle any 24-bit signed offset. 24 bits allows an
2182 // 8 megabyte stack frame.
2183 __ add(as_Register(reg), sp, offset);
2184 }
2185
2186 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
2187 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
2188 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
2189
2190 if (Assembler::operand_valid_for_add_sub_immediate(offset)) {
2191 return NativeInstruction::instruction_size;
2192 } else {
2193 return 2 * NativeInstruction::instruction_size;
2194 }
2195 }
2196
2197 //=============================================================================
2198
2199 #ifndef PRODUCT
2200 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
2201 {
2202 st->print_cr("# MachUEPNode");
2203 if (UseCompressedClassPointers) {
2204 st->print_cr("\tldrw rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
2205 st->print_cr("\tldrw r10, [rscratch2 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
2206 st->print_cr("\tcmpw rscratch1, r10");
2207 } else {
2208 st->print_cr("\tldr rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
2209 st->print_cr("\tldr r10, [rscratch2 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
2210 st->print_cr("\tcmp rscratch1, r10");
2211 }
2212 st->print_cr("\tbne, SharedRuntime::_ic_miss_stub");
2213 }
2214 #endif
2215
2216 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
2217 {
2218 __ ic_check(InteriorEntryAlignment);
2219 }
2220
2221 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
2222 {
2223 return MachNode::size(ra_);
2224 }
2225
2226 // REQUIRED EMIT CODE
2227
2228 //=============================================================================
2229
2230 // Emit exception handler code.
2231 int HandlerImpl::emit_exception_handler(C2_MacroAssembler* masm)
2232 {
2233 // mov rscratch1 #exception_blob_entry_point
2234 // br rscratch1
2235 // Note that the code buffer's insts_mark is always relative to insts.
2236 // That's why we must use the macroassembler to generate a handler.
2237 address base = __ start_a_stub(size_exception_handler());
2238 if (base == nullptr) {
2239 ciEnv::current()->record_failure("CodeCache is full");
2240 return 0; // CodeBuffer::expand failed
2241 }
2242 int offset = __ offset();
2243 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
2244 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
2245 __ end_a_stub();
2246 return offset;
2247 }
2248
2249 // Emit deopt handler code.
2250 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
2251 {
2252 // Note that the code buffer's insts_mark is always relative to insts.
2253 // That's why we must use the macroassembler to generate a handler.
2254 address base = __ start_a_stub(size_deopt_handler());
2255 if (base == nullptr) {
2256 ciEnv::current()->record_failure("CodeCache is full");
2257 return 0; // CodeBuffer::expand failed
2258 }
2259 int offset = __ offset();
2260
2261 __ adr(lr, __ pc());
2262 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
2263
2264 assert(__ offset() - offset == (int) size_deopt_handler(), "overflow");
2265 __ end_a_stub();
2266 return offset;
2267 }
2268
2269 // REQUIRED MATCHER CODE
2270
2271 //=============================================================================
2272
2273 bool Matcher::match_rule_supported(int opcode) {
2274 if (!has_match_rule(opcode))
2275 return false;
2276
2277 switch (opcode) {
2278 case Op_OnSpinWait:
2279 return VM_Version::supports_on_spin_wait();
2280 case Op_CacheWB:
2281 case Op_CacheWBPreSync:
2282 case Op_CacheWBPostSync:
2283 if (!VM_Version::supports_data_cache_line_flush()) {
2284 return false;
2285 }
2286 break;
2287 case Op_ExpandBits:
2288 case Op_CompressBits:
2289 if (!VM_Version::supports_svebitperm()) {
2290 return false;
2291 }
2292 break;
2293 case Op_FmaF:
2294 case Op_FmaD:
2295 case Op_FmaVF:
2296 case Op_FmaVD:
2297 if (!UseFMA) {
2298 return false;
2299 }
2300 break;
2301 }
2302
2303 return true; // Per default match rules are supported.
2304 }
2305
2306 const RegMask* Matcher::predicate_reg_mask(void) {
2307 return &_PR_REG_mask;
2308 }
2309
2310 const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length) {
2311 return new TypeVectMask(elemTy, length);
2312 }
2313
2314 // Vector calling convention not yet implemented.
2315 bool Matcher::supports_vector_calling_convention(void) {
2316 return false;
2317 }
2318
2319 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
2320 Unimplemented();
2321 return OptoRegPair(0, 0);
2322 }
2323
2324 // Is this branch offset short enough that a short branch can be used?
2325 //
2326 // NOTE: If the platform does not provide any short branch variants, then
2327 // this method should return false for offset 0.
2328 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2329 // The passed offset is relative to address of the branch.
2330
2331 return (-32768 <= offset && offset < 32768);
2332 }
2333
2334 // Vector width in bytes.
2335 int Matcher::vector_width_in_bytes(BasicType bt) {
2336 // The MaxVectorSize should have been set by detecting SVE max vector register size.
2337 int size = MIN2((UseSVE > 0) ? 256 : 16, (int)MaxVectorSize);
2338 // Minimum 2 values in vector
2339 if (size < 2*type2aelembytes(bt)) size = 0;
2340 // But never < 4
2341 if (size < 4) size = 0;
2342 return size;
2343 }
2344
2345 // Limits on vector size (number of elements) loaded into vector.
2346 int Matcher::max_vector_size(const BasicType bt) {
2347 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2348 }
2349
2350 int Matcher::min_vector_size(const BasicType bt) {
2351 int max_size = max_vector_size(bt);
2352 // Limit the min vector size to 8 bytes.
2353 int size = 8 / type2aelembytes(bt);
2354 if (bt == T_BYTE) {
2355 // To support vector api shuffle/rearrange.
2356 size = 4;
2357 } else if (bt == T_BOOLEAN) {
2358 // To support vector api load/store mask.
2359 size = 2;
2360 }
2361 if (size < 2) size = 2;
2362 return MIN2(size, max_size);
2363 }
2364
2365 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2366 return Matcher::max_vector_size(bt);
2367 }
2368
2369 // Actual max scalable vector register length.
2370 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2371 return Matcher::max_vector_size(bt);
2372 }
2373
2374 // Vector ideal reg.
2375 uint Matcher::vector_ideal_reg(int len) {
2376 if (UseSVE > 0 && 16 < len && len <= 256) {
2377 return Op_VecA;
2378 }
2379 switch(len) {
2380 // For 16-bit/32-bit mask vector, reuse VecD.
2381 case 2:
2382 case 4:
2383 case 8: return Op_VecD;
2384 case 16: return Op_VecX;
2385 }
2386 ShouldNotReachHere();
2387 return 0;
2388 }
2389
2390 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* generic_opnd, uint ideal_reg, bool is_temp) {
2391 assert(Matcher::is_generic_vector(generic_opnd), "not generic");
2392 switch (ideal_reg) {
2393 case Op_VecA: return new vecAOper();
2394 case Op_VecD: return new vecDOper();
2395 case Op_VecX: return new vecXOper();
2396 }
2397 ShouldNotReachHere();
2398 return nullptr;
2399 }
2400
2401 bool Matcher::is_reg2reg_move(MachNode* m) {
2402 return false;
2403 }
2404
2405 bool Matcher::is_generic_vector(MachOper* opnd) {
2406 return opnd->opcode() == VREG;
2407 }
2408
2409 // Return whether or not this register is ever used as an argument.
2410 // This function is used on startup to build the trampoline stubs in
2411 // generateOptoStub. Registers not mentioned will be killed by the VM
2412 // call in the trampoline, and arguments in those registers not be
2413 // available to the callee.
2414 bool Matcher::can_be_java_arg(int reg)
2415 {
2416 return
2417 reg == R0_num || reg == R0_H_num ||
2418 reg == R1_num || reg == R1_H_num ||
2419 reg == R2_num || reg == R2_H_num ||
2420 reg == R3_num || reg == R3_H_num ||
2421 reg == R4_num || reg == R4_H_num ||
2422 reg == R5_num || reg == R5_H_num ||
2423 reg == R6_num || reg == R6_H_num ||
2424 reg == R7_num || reg == R7_H_num ||
2425 reg == V0_num || reg == V0_H_num ||
2426 reg == V1_num || reg == V1_H_num ||
2427 reg == V2_num || reg == V2_H_num ||
2428 reg == V3_num || reg == V3_H_num ||
2429 reg == V4_num || reg == V4_H_num ||
2430 reg == V5_num || reg == V5_H_num ||
2431 reg == V6_num || reg == V6_H_num ||
2432 reg == V7_num || reg == V7_H_num;
2433 }
2434
2435 bool Matcher::is_spillable_arg(int reg)
2436 {
2437 return can_be_java_arg(reg);
2438 }
2439
2440 uint Matcher::int_pressure_limit()
2441 {
2442 // JDK-8183543: When taking the number of available registers as int
2443 // register pressure threshold, the jtreg test:
2444 // test/hotspot/jtreg/compiler/regalloc/TestC2IntPressure.java
2445 // failed due to C2 compilation failure with
2446 // "COMPILE SKIPPED: failed spill-split-recycle sanity check".
2447 //
2448 // A derived pointer is live at CallNode and then is flagged by RA
2449 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2450 // derived pointers and lastly fail to spill after reaching maximum
2451 // number of iterations. Lowering the default pressure threshold to
2452 // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
2453 // a high register pressure area of the code so that split_DEF can
2454 // generate DefinitionSpillCopy for the derived pointer.
2455 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
2456 if (!PreserveFramePointer) {
2457 // When PreserveFramePointer is off, frame pointer is allocatable,
2458 // but different from other SOC registers, it is excluded from
2459 // fatproj's mask because its save type is No-Save. Decrease 1 to
2460 // ensure high pressure at fatproj when PreserveFramePointer is off.
2461 // See check_pressure_at_fatproj().
2462 default_int_pressure_threshold--;
2463 }
2464 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2465 }
2466
2467 uint Matcher::float_pressure_limit()
2468 {
2469 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2470 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
2471 }
2472
2473 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2474 return false;
2475 }
2476
2477 RegMask Matcher::divI_proj_mask() {
2478 ShouldNotReachHere();
2479 return RegMask();
2480 }
2481
2482 // Register for MODI projection of divmodI.
2483 RegMask Matcher::modI_proj_mask() {
2484 ShouldNotReachHere();
2485 return RegMask();
2486 }
2487
2488 // Register for DIVL projection of divmodL.
2489 RegMask Matcher::divL_proj_mask() {
2490 ShouldNotReachHere();
2491 return RegMask();
2492 }
2493
2494 // Register for MODL projection of divmodL.
2495 RegMask Matcher::modL_proj_mask() {
2496 ShouldNotReachHere();
2497 return RegMask();
2498 }
2499
2500 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2501 return FP_REG_mask();
2502 }
2503
2504 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2505 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2506 Node* u = addp->fast_out(i);
2507 if (u->is_LoadStore()) {
2508 // On AArch64, LoadStoreNodes (i.e. compare and swap
2509 // instructions) only take register indirect as an operand, so
2510 // any attempt to use an AddPNode as an input to a LoadStoreNode
2511 // must fail.
2512 return false;
2513 }
2514 if (u->is_Mem()) {
2515 int opsize = u->as_Mem()->memory_size();
2516 assert(opsize > 0, "unexpected memory operand size");
2517 if (u->as_Mem()->memory_size() != (1<<shift)) {
2518 return false;
2519 }
2520 }
2521 }
2522 return true;
2523 }
2524
2525 // Convert BootTest condition to Assembler condition.
2526 // Replicate the logic of cmpOpOper::ccode() and cmpOpUOper::ccode().
2527 Assembler::Condition to_assembler_cond(BoolTest::mask cond) {
2528 Assembler::Condition result;
2529 switch(cond) {
2530 case BoolTest::eq:
2531 result = Assembler::EQ; break;
2532 case BoolTest::ne:
2533 result = Assembler::NE; break;
2534 case BoolTest::le:
2535 result = Assembler::LE; break;
2536 case BoolTest::ge:
2537 result = Assembler::GE; break;
2538 case BoolTest::lt:
2539 result = Assembler::LT; break;
2540 case BoolTest::gt:
2541 result = Assembler::GT; break;
2542 case BoolTest::ule:
2543 result = Assembler::LS; break;
2544 case BoolTest::uge:
2545 result = Assembler::HS; break;
2546 case BoolTest::ult:
2547 result = Assembler::LO; break;
2548 case BoolTest::ugt:
2549 result = Assembler::HI; break;
2550 case BoolTest::overflow:
2551 result = Assembler::VS; break;
2552 case BoolTest::no_overflow:
2553 result = Assembler::VC; break;
2554 default:
2555 ShouldNotReachHere();
2556 return Assembler::Condition(-1);
2557 }
2558
2559 // Check conversion
2560 if (cond & BoolTest::unsigned_compare) {
2561 assert(cmpOpUOper((BoolTest::mask)((int)cond & ~(BoolTest::unsigned_compare))).ccode() == result, "Invalid conversion");
2562 } else {
2563 assert(cmpOpOper(cond).ccode() == result, "Invalid conversion");
2564 }
2565
2566 return result;
2567 }
2568
2569 // Binary src (Replicate con)
2570 static bool is_valid_sve_arith_imm_pattern(Node* n, Node* m) {
2571 if (n == nullptr || m == nullptr) {
2572 return false;
2573 }
2574
2575 if (UseSVE == 0 || m->Opcode() != Op_Replicate) {
2576 return false;
2577 }
2578
2579 Node* imm_node = m->in(1);
2580 if (!imm_node->is_Con()) {
2581 return false;
2582 }
2583
2584 const Type* t = imm_node->bottom_type();
2585 if (!(t->isa_int() || t->isa_long())) {
2586 return false;
2587 }
2588
2589 switch (n->Opcode()) {
2590 case Op_AndV:
2591 case Op_OrV:
2592 case Op_XorV: {
2593 Assembler::SIMD_RegVariant T = Assembler::elemType_to_regVariant(Matcher::vector_element_basic_type(n));
2594 uint64_t value = t->isa_long() ? (uint64_t)imm_node->get_long() : (uint64_t)imm_node->get_int();
2595 return Assembler::operand_valid_for_sve_logical_immediate(Assembler::regVariant_to_elemBits(T), value);
2596 }
2597 case Op_AddVB:
2598 return (imm_node->get_int() <= 255 && imm_node->get_int() >= -255);
2599 case Op_AddVS:
2600 case Op_AddVI:
2601 return Assembler::operand_valid_for_sve_add_sub_immediate((int64_t)imm_node->get_int());
2602 case Op_AddVL:
2603 return Assembler::operand_valid_for_sve_add_sub_immediate(imm_node->get_long());
2604 default:
2605 return false;
2606 }
2607 }
2608
2609 // (XorV src (Replicate m1))
2610 // (XorVMask src (MaskAll m1))
2611 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2612 if (n != nullptr && m != nullptr) {
2613 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2614 VectorNode::is_all_ones_vector(m);
2615 }
2616 return false;
2617 }
2618
2619 // Should the matcher clone input 'm' of node 'n'?
2620 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2621 if (is_vshift_con_pattern(n, m) ||
2622 is_vector_bitwise_not_pattern(n, m) ||
2623 is_valid_sve_arith_imm_pattern(n, m)) {
2624 mstack.push(m, Visit);
2625 return true;
2626 }
2627 return false;
2628 }
2629
2630 // Should the Matcher clone shifts on addressing modes, expecting them
2631 // to be subsumed into complex addressing expressions or compute them
2632 // into registers?
2633 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2634 if (clone_base_plus_offset_address(m, mstack, address_visited)) {
2635 return true;
2636 }
2637
2638 Node *off = m->in(AddPNode::Offset);
2639 if (off->Opcode() == Op_LShiftL && off->in(2)->is_Con() &&
2640 size_fits_all_mem_uses(m, off->in(2)->get_int()) &&
2641 // Are there other uses besides address expressions?
2642 !is_visited(off)) {
2643 address_visited.set(off->_idx); // Flag as address_visited
2644 mstack.push(off->in(2), Visit);
2645 Node *conv = off->in(1);
2646 if (conv->Opcode() == Op_ConvI2L &&
2647 // Are there other uses besides address expressions?
2648 !is_visited(conv)) {
2649 address_visited.set(conv->_idx); // Flag as address_visited
2650 mstack.push(conv->in(1), Pre_Visit);
2651 } else {
2652 mstack.push(conv, Pre_Visit);
2653 }
2654 address_visited.test_set(m->_idx); // Flag as address_visited
2655 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2656 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2657 return true;
2658 } else if (off->Opcode() == Op_ConvI2L &&
2659 // Are there other uses besides address expressions?
2660 !is_visited(off)) {
2661 address_visited.test_set(m->_idx); // Flag as address_visited
2662 address_visited.set(off->_idx); // Flag as address_visited
2663 mstack.push(off->in(1), Pre_Visit);
2664 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2665 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2666 return true;
2667 }
2668 return false;
2669 }
2670
2671 #define MOV_VOLATILE(REG, BASE, INDEX, SCALE, DISP, SCRATCH, INSN) \
2672 { \
2673 guarantee(INDEX == -1, "mode not permitted for volatile"); \
2674 guarantee(DISP == 0, "mode not permitted for volatile"); \
2675 guarantee(SCALE == 0, "mode not permitted for volatile"); \
2676 __ INSN(REG, as_Register(BASE)); \
2677 }
2678
2679
2680 static Address mem2address(int opcode, Register base, int index, int size, int disp)
2681 {
2682 Address::extend scale;
2683
2684 // Hooboy, this is fugly. We need a way to communicate to the
2685 // encoder that the index needs to be sign extended, so we have to
2686 // enumerate all the cases.
2687 switch (opcode) {
2688 case INDINDEXSCALEDI2L:
2689 case INDINDEXSCALEDI2LN:
2690 case INDINDEXI2L:
2691 case INDINDEXI2LN:
2692 scale = Address::sxtw(size);
2693 break;
2694 default:
2695 scale = Address::lsl(size);
2696 }
2697
2698 if (index == -1) {
2699 return Address(base, disp);
2700 } else {
2701 assert(disp == 0, "unsupported address mode: disp = %d", disp);
2702 return Address(base, as_Register(index), scale);
2703 }
2704 }
2705
2706
2707 typedef void (MacroAssembler::* mem_insn)(Register Rt, const Address &adr);
2708 typedef void (MacroAssembler::* mem_insn2)(Register Rt, Register adr);
2709 typedef void (MacroAssembler::* mem_float_insn)(FloatRegister Rt, const Address &adr);
2710 typedef void (MacroAssembler::* mem_vector_insn)(FloatRegister Rt,
2711 MacroAssembler::SIMD_RegVariant T, const Address &adr);
2712
2713 // Used for all non-volatile memory accesses. The use of
2714 // $mem->opcode() to discover whether this pattern uses sign-extended
2715 // offsets is something of a kludge.
2716 static void loadStore(C2_MacroAssembler* masm, mem_insn insn,
2717 Register reg, int opcode,
2718 Register base, int index, int scale, int disp,
2719 int size_in_memory)
2720 {
2721 Address addr = mem2address(opcode, base, index, scale, disp);
2722 if (addr.getMode() == Address::base_plus_offset) {
2723 /* Fix up any out-of-range offsets. */
2724 assert_different_registers(rscratch1, base);
2725 assert_different_registers(rscratch1, reg);
2726 addr = __ legitimize_address(addr, size_in_memory, rscratch1);
2727 }
2728 (masm->*insn)(reg, addr);
2729 }
2730
2731 static void loadStore(C2_MacroAssembler* masm, mem_float_insn insn,
2732 FloatRegister reg, int opcode,
2733 Register base, int index, int size, int disp,
2734 int size_in_memory)
2735 {
2736 Address::extend scale;
2737
2738 switch (opcode) {
2739 case INDINDEXSCALEDI2L:
2740 case INDINDEXSCALEDI2LN:
2741 scale = Address::sxtw(size);
2742 break;
2743 default:
2744 scale = Address::lsl(size);
2745 }
2746
2747 if (index == -1) {
2748 /* If we get an out-of-range offset it is a bug in the compiler,
2749 so we assert here. */
2750 assert(Address::offset_ok_for_immed(disp, exact_log2(size_in_memory)), "c2 compiler bug");
2751 /* Fix up any out-of-range offsets. */
2752 assert_different_registers(rscratch1, base);
2753 Address addr = Address(base, disp);
2754 addr = __ legitimize_address(addr, size_in_memory, rscratch1);
2755 (masm->*insn)(reg, addr);
2756 } else {
2757 assert(disp == 0, "unsupported address mode: disp = %d", disp);
2758 (masm->*insn)(reg, Address(base, as_Register(index), scale));
2759 }
2760 }
2761
2762 static void loadStore(C2_MacroAssembler* masm, mem_vector_insn insn,
2763 FloatRegister reg, MacroAssembler::SIMD_RegVariant T,
2764 int opcode, Register base, int index, int size, int disp)
2765 {
2766 if (index == -1) {
2767 (masm->*insn)(reg, T, Address(base, disp));
2768 } else {
2769 assert(disp == 0, "unsupported address mode");
2770 (masm->*insn)(reg, T, Address(base, as_Register(index), Address::lsl(size)));
2771 }
2772 }
2773
2774 %}
2775
2776
2777
2778 //----------ENCODING BLOCK-----------------------------------------------------
2779 // This block specifies the encoding classes used by the compiler to
2780 // output byte streams. Encoding classes are parameterized macros
2781 // used by Machine Instruction Nodes in order to generate the bit
2782 // encoding of the instruction. Operands specify their base encoding
2783 // interface with the interface keyword. There are currently
2784 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2785 // COND_INTER. REG_INTER causes an operand to generate a function
2786 // which returns its register number when queried. CONST_INTER causes
2787 // an operand to generate a function which returns the value of the
2788 // constant when queried. MEMORY_INTER causes an operand to generate
2789 // four functions which return the Base Register, the Index Register,
2790 // the Scale Value, and the Offset Value of the operand when queried.
2791 // COND_INTER causes an operand to generate six functions which return
2792 // the encoding code (ie - encoding bits for the instruction)
2793 // associated with each basic boolean condition for a conditional
2794 // instruction.
2795 //
2796 // Instructions specify two basic values for encoding. Again, a
2797 // function is available to check if the constant displacement is an
2798 // oop. They use the ins_encode keyword to specify their encoding
2799 // classes (which must be a sequence of enc_class names, and their
2800 // parameters, specified in the encoding block), and they use the
2801 // opcode keyword to specify, in order, their primary, secondary, and
2802 // tertiary opcode. Only the opcode sections which a particular
2803 // instruction needs for encoding need to be specified.
2804 encode %{
2805 // Build emit functions for each basic byte or larger field in the
2806 // intel encoding scheme (opcode, rm, sib, immediate), and call them
2807 // from C++ code in the enc_class source block. Emit functions will
2808 // live in the main source block for now. In future, we can
2809 // generalize this by adding a syntax that specifies the sizes of
2810 // fields in an order, so that the adlc can build the emit functions
2811 // automagically
2812
2813 // catch all for unimplemented encodings
2814 enc_class enc_unimplemented %{
2815 __ unimplemented("C2 catch all");
2816 %}
2817
2818 // BEGIN Non-volatile memory access
2819
2820 // This encoding class is generated automatically from ad_encode.m4.
2821 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2822 enc_class aarch64_enc_ldrsbw(iRegI dst, memory1 mem) %{
2823 Register dst_reg = as_Register($dst$$reg);
2824 loadStore(masm, &MacroAssembler::ldrsbw, dst_reg, $mem->opcode(),
2825 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2826 %}
2827
2828 // This encoding class is generated automatically from ad_encode.m4.
2829 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2830 enc_class aarch64_enc_ldrsb(iRegI dst, memory1 mem) %{
2831 Register dst_reg = as_Register($dst$$reg);
2832 loadStore(masm, &MacroAssembler::ldrsb, dst_reg, $mem->opcode(),
2833 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2834 %}
2835
2836 // This encoding class is generated automatically from ad_encode.m4.
2837 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2838 enc_class aarch64_enc_ldrb(iRegI dst, memory1 mem) %{
2839 Register dst_reg = as_Register($dst$$reg);
2840 loadStore(masm, &MacroAssembler::ldrb, dst_reg, $mem->opcode(),
2841 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2842 %}
2843
2844 // This encoding class is generated automatically from ad_encode.m4.
2845 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2846 enc_class aarch64_enc_ldrb(iRegL dst, memory1 mem) %{
2847 Register dst_reg = as_Register($dst$$reg);
2848 loadStore(masm, &MacroAssembler::ldrb, dst_reg, $mem->opcode(),
2849 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2850 %}
2851
2852 // This encoding class is generated automatically from ad_encode.m4.
2853 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2854 enc_class aarch64_enc_ldrshw(iRegI dst, memory2 mem) %{
2855 Register dst_reg = as_Register($dst$$reg);
2856 loadStore(masm, &MacroAssembler::ldrshw, dst_reg, $mem->opcode(),
2857 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2858 %}
2859
2860 // This encoding class is generated automatically from ad_encode.m4.
2861 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2862 enc_class aarch64_enc_ldrsh(iRegI dst, memory2 mem) %{
2863 Register dst_reg = as_Register($dst$$reg);
2864 loadStore(masm, &MacroAssembler::ldrsh, dst_reg, $mem->opcode(),
2865 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2866 %}
2867
2868 // This encoding class is generated automatically from ad_encode.m4.
2869 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2870 enc_class aarch64_enc_ldrh(iRegI dst, memory2 mem) %{
2871 Register dst_reg = as_Register($dst$$reg);
2872 loadStore(masm, &MacroAssembler::ldrh, dst_reg, $mem->opcode(),
2873 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2874 %}
2875
2876 // This encoding class is generated automatically from ad_encode.m4.
2877 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2878 enc_class aarch64_enc_ldrh(iRegL dst, memory2 mem) %{
2879 Register dst_reg = as_Register($dst$$reg);
2880 loadStore(masm, &MacroAssembler::ldrh, dst_reg, $mem->opcode(),
2881 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2882 %}
2883
2884 // This encoding class is generated automatically from ad_encode.m4.
2885 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2886 enc_class aarch64_enc_ldrw(iRegI dst, memory4 mem) %{
2887 Register dst_reg = as_Register($dst$$reg);
2888 loadStore(masm, &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
2889 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2890 %}
2891
2892 // This encoding class is generated automatically from ad_encode.m4.
2893 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2894 enc_class aarch64_enc_ldrw(iRegL dst, memory4 mem) %{
2895 Register dst_reg = as_Register($dst$$reg);
2896 loadStore(masm, &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
2897 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2898 %}
2899
2900 // This encoding class is generated automatically from ad_encode.m4.
2901 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2902 enc_class aarch64_enc_ldrsw(iRegL dst, memory4 mem) %{
2903 Register dst_reg = as_Register($dst$$reg);
2904 loadStore(masm, &MacroAssembler::ldrsw, dst_reg, $mem->opcode(),
2905 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2906 %}
2907
2908 // This encoding class is generated automatically from ad_encode.m4.
2909 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2910 enc_class aarch64_enc_ldr(iRegL dst, memory8 mem) %{
2911 Register dst_reg = as_Register($dst$$reg);
2912 loadStore(masm, &MacroAssembler::ldr, dst_reg, $mem->opcode(),
2913 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
2914 %}
2915
2916 // This encoding class is generated automatically from ad_encode.m4.
2917 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2918 enc_class aarch64_enc_ldrs(vRegF dst, memory4 mem) %{
2919 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2920 loadStore(masm, &MacroAssembler::ldrs, dst_reg, $mem->opcode(),
2921 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2922 %}
2923
2924 // This encoding class is generated automatically from ad_encode.m4.
2925 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2926 enc_class aarch64_enc_ldrd(vRegD dst, memory8 mem) %{
2927 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2928 loadStore(masm, &MacroAssembler::ldrd, dst_reg, $mem->opcode(),
2929 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
2930 %}
2931
2932 // This encoding class is generated automatically from ad_encode.m4.
2933 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2934 enc_class aarch64_enc_strb(iRegI src, memory1 mem) %{
2935 Register src_reg = as_Register($src$$reg);
2936 loadStore(masm, &MacroAssembler::strb, src_reg, $mem->opcode(),
2937 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2938 %}
2939
2940 // This encoding class is generated automatically from ad_encode.m4.
2941 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2942 enc_class aarch64_enc_strb0(memory1 mem) %{
2943 loadStore(masm, &MacroAssembler::strb, zr, $mem->opcode(),
2944 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2945 %}
2946
2947 // This encoding class is generated automatically from ad_encode.m4.
2948 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2949 enc_class aarch64_enc_strh(iRegI src, memory2 mem) %{
2950 Register src_reg = as_Register($src$$reg);
2951 loadStore(masm, &MacroAssembler::strh, src_reg, $mem->opcode(),
2952 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2953 %}
2954
2955 // This encoding class is generated automatically from ad_encode.m4.
2956 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2957 enc_class aarch64_enc_strh0(memory2 mem) %{
2958 loadStore(masm, &MacroAssembler::strh, zr, $mem->opcode(),
2959 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 2);
2960 %}
2961
2962 // This encoding class is generated automatically from ad_encode.m4.
2963 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2964 enc_class aarch64_enc_strw(iRegI src, memory4 mem) %{
2965 Register src_reg = as_Register($src$$reg);
2966 loadStore(masm, &MacroAssembler::strw, src_reg, $mem->opcode(),
2967 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2968 %}
2969
2970 // This encoding class is generated automatically from ad_encode.m4.
2971 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2972 enc_class aarch64_enc_strw0(memory4 mem) %{
2973 loadStore(masm, &MacroAssembler::strw, zr, $mem->opcode(),
2974 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2975 %}
2976
2977 // This encoding class is generated automatically from ad_encode.m4.
2978 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2979 enc_class aarch64_enc_str(iRegL src, memory8 mem) %{
2980 Register src_reg = as_Register($src$$reg);
2981 // we sometimes get asked to store the stack pointer into the
2982 // current thread -- we cannot do that directly on AArch64
2983 if (src_reg == r31_sp) {
2984 assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
2985 __ mov(rscratch2, sp);
2986 src_reg = rscratch2;
2987 }
2988 loadStore(masm, &MacroAssembler::str, src_reg, $mem->opcode(),
2989 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
2990 %}
2991
2992 // This encoding class is generated automatically from ad_encode.m4.
2993 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2994 enc_class aarch64_enc_str0(memory8 mem) %{
2995 loadStore(masm, &MacroAssembler::str, zr, $mem->opcode(),
2996 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
2997 %}
2998
2999 // This encoding class is generated automatically from ad_encode.m4.
3000 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
3001 enc_class aarch64_enc_strs(vRegF src, memory4 mem) %{
3002 FloatRegister src_reg = as_FloatRegister($src$$reg);
3003 loadStore(masm, &MacroAssembler::strs, src_reg, $mem->opcode(),
3004 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
3005 %}
3006
3007 // This encoding class is generated automatically from ad_encode.m4.
3008 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
3009 enc_class aarch64_enc_strd(vRegD src, memory8 mem) %{
3010 FloatRegister src_reg = as_FloatRegister($src$$reg);
3011 loadStore(masm, &MacroAssembler::strd, src_reg, $mem->opcode(),
3012 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
3013 %}
3014
3015 // This encoding class is generated automatically from ad_encode.m4.
3016 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
3017 enc_class aarch64_enc_strb0_ordered(memory4 mem) %{
3018 __ membar(Assembler::StoreStore);
3019 loadStore(masm, &MacroAssembler::strb, zr, $mem->opcode(),
3020 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
3021 %}
3022
3023 // END Non-volatile memory access
3024
3025 // Vector loads and stores
3026 enc_class aarch64_enc_ldrvH(vReg dst, memory mem) %{
3027 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3028 loadStore(masm, &MacroAssembler::ldr, dst_reg, MacroAssembler::H,
3029 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3030 %}
3031
3032 enc_class aarch64_enc_ldrvS(vReg dst, memory mem) %{
3033 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3034 loadStore(masm, &MacroAssembler::ldr, dst_reg, MacroAssembler::S,
3035 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3036 %}
3037
3038 enc_class aarch64_enc_ldrvD(vReg dst, memory mem) %{
3039 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3040 loadStore(masm, &MacroAssembler::ldr, dst_reg, MacroAssembler::D,
3041 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3042 %}
3043
3044 enc_class aarch64_enc_ldrvQ(vReg dst, memory mem) %{
3045 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3046 loadStore(masm, &MacroAssembler::ldr, dst_reg, MacroAssembler::Q,
3047 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3048 %}
3049
3050 enc_class aarch64_enc_strvH(vReg src, memory mem) %{
3051 FloatRegister src_reg = as_FloatRegister($src$$reg);
3052 loadStore(masm, &MacroAssembler::str, src_reg, MacroAssembler::H,
3053 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3054 %}
3055
3056 enc_class aarch64_enc_strvS(vReg src, memory mem) %{
3057 FloatRegister src_reg = as_FloatRegister($src$$reg);
3058 loadStore(masm, &MacroAssembler::str, src_reg, MacroAssembler::S,
3059 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3060 %}
3061
3062 enc_class aarch64_enc_strvD(vReg src, memory mem) %{
3063 FloatRegister src_reg = as_FloatRegister($src$$reg);
3064 loadStore(masm, &MacroAssembler::str, src_reg, MacroAssembler::D,
3065 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3066 %}
3067
3068 enc_class aarch64_enc_strvQ(vReg src, memory mem) %{
3069 FloatRegister src_reg = as_FloatRegister($src$$reg);
3070 loadStore(masm, &MacroAssembler::str, src_reg, MacroAssembler::Q,
3071 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
3072 %}
3073
3074 // volatile loads and stores
3075
3076 enc_class aarch64_enc_stlrb(iRegI src, memory mem) %{
3077 MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3078 rscratch1, stlrb);
3079 %}
3080
3081 enc_class aarch64_enc_stlrb0(memory mem) %{
3082 MOV_VOLATILE(zr, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3083 rscratch1, stlrb);
3084 %}
3085
3086 enc_class aarch64_enc_stlrh(iRegI src, memory mem) %{
3087 MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3088 rscratch1, stlrh);
3089 %}
3090
3091 enc_class aarch64_enc_stlrh0(memory mem) %{
3092 MOV_VOLATILE(zr, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3093 rscratch1, stlrh);
3094 %}
3095
3096 enc_class aarch64_enc_stlrw(iRegI src, memory mem) %{
3097 MOV_VOLATILE(as_Register($src$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3098 rscratch1, stlrw);
3099 %}
3100
3101 enc_class aarch64_enc_stlrw0(memory mem) %{
3102 MOV_VOLATILE(zr, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3103 rscratch1, stlrw);
3104 %}
3105
3106 enc_class aarch64_enc_ldarsbw(iRegI dst, memory mem) %{
3107 Register dst_reg = as_Register($dst$$reg);
3108 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3109 rscratch1, ldarb);
3110 __ sxtbw(dst_reg, dst_reg);
3111 %}
3112
3113 enc_class aarch64_enc_ldarsb(iRegL dst, memory mem) %{
3114 Register dst_reg = as_Register($dst$$reg);
3115 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3116 rscratch1, ldarb);
3117 __ sxtb(dst_reg, dst_reg);
3118 %}
3119
3120 enc_class aarch64_enc_ldarbw(iRegI dst, memory mem) %{
3121 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3122 rscratch1, ldarb);
3123 %}
3124
3125 enc_class aarch64_enc_ldarb(iRegL dst, memory mem) %{
3126 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3127 rscratch1, ldarb);
3128 %}
3129
3130 enc_class aarch64_enc_ldarshw(iRegI dst, memory mem) %{
3131 Register dst_reg = as_Register($dst$$reg);
3132 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3133 rscratch1, ldarh);
3134 __ sxthw(dst_reg, dst_reg);
3135 %}
3136
3137 enc_class aarch64_enc_ldarsh(iRegL dst, memory mem) %{
3138 Register dst_reg = as_Register($dst$$reg);
3139 MOV_VOLATILE(dst_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3140 rscratch1, ldarh);
3141 __ sxth(dst_reg, dst_reg);
3142 %}
3143
3144 enc_class aarch64_enc_ldarhw(iRegI dst, memory mem) %{
3145 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3146 rscratch1, ldarh);
3147 %}
3148
3149 enc_class aarch64_enc_ldarh(iRegL dst, memory mem) %{
3150 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3151 rscratch1, ldarh);
3152 %}
3153
3154 enc_class aarch64_enc_ldarw(iRegI dst, memory mem) %{
3155 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3156 rscratch1, ldarw);
3157 %}
3158
3159 enc_class aarch64_enc_ldarw(iRegL dst, memory mem) %{
3160 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3161 rscratch1, ldarw);
3162 %}
3163
3164 enc_class aarch64_enc_ldar(iRegL dst, memory mem) %{
3165 MOV_VOLATILE(as_Register($dst$$reg), $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3166 rscratch1, ldar);
3167 %}
3168
3169 enc_class aarch64_enc_fldars(vRegF dst, memory mem) %{
3170 MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3171 rscratch1, ldarw);
3172 __ fmovs(as_FloatRegister($dst$$reg), rscratch1);
3173 %}
3174
3175 enc_class aarch64_enc_fldard(vRegD dst, memory mem) %{
3176 MOV_VOLATILE(rscratch1, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3177 rscratch1, ldar);
3178 __ fmovd(as_FloatRegister($dst$$reg), rscratch1);
3179 %}
3180
3181 enc_class aarch64_enc_stlr(iRegL src, memory mem) %{
3182 Register src_reg = as_Register($src$$reg);
3183 // we sometimes get asked to store the stack pointer into the
3184 // current thread -- we cannot do that directly on AArch64
3185 if (src_reg == r31_sp) {
3186 assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
3187 __ mov(rscratch2, sp);
3188 src_reg = rscratch2;
3189 }
3190 MOV_VOLATILE(src_reg, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3191 rscratch1, stlr);
3192 %}
3193
3194 enc_class aarch64_enc_stlr0(memory mem) %{
3195 MOV_VOLATILE(zr, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3196 rscratch1, stlr);
3197 %}
3198
3199 enc_class aarch64_enc_fstlrs(vRegF src, memory mem) %{
3200 {
3201 FloatRegister src_reg = as_FloatRegister($src$$reg);
3202 __ fmovs(rscratch2, src_reg);
3203 }
3204 MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3205 rscratch1, stlrw);
3206 %}
3207
3208 enc_class aarch64_enc_fstlrd(vRegD src, memory mem) %{
3209 {
3210 FloatRegister src_reg = as_FloatRegister($src$$reg);
3211 __ fmovd(rscratch2, src_reg);
3212 }
3213 MOV_VOLATILE(rscratch2, $mem$$base, $mem$$index, $mem$$scale, $mem$$disp,
3214 rscratch1, stlr);
3215 %}
3216
3217 // synchronized read/update encodings
3218
3219 enc_class aarch64_enc_ldaxr(iRegL dst, memory8 mem) %{
3220 Register dst_reg = as_Register($dst$$reg);
3221 Register base = as_Register($mem$$base);
3222 int index = $mem$$index;
3223 int scale = $mem$$scale;
3224 int disp = $mem$$disp;
3225 if (index == -1) {
3226 if (disp != 0) {
3227 __ lea(rscratch1, Address(base, disp));
3228 __ ldaxr(dst_reg, rscratch1);
3229 } else {
3230 // TODO
3231 // should we ever get anything other than this case?
3232 __ ldaxr(dst_reg, base);
3233 }
3234 } else {
3235 Register index_reg = as_Register(index);
3236 if (disp == 0) {
3237 __ lea(rscratch1, Address(base, index_reg, Address::lsl(scale)));
3238 __ ldaxr(dst_reg, rscratch1);
3239 } else {
3240 __ lea(rscratch1, Address(base, disp));
3241 __ lea(rscratch1, Address(rscratch1, index_reg, Address::lsl(scale)));
3242 __ ldaxr(dst_reg, rscratch1);
3243 }
3244 }
3245 %}
3246
3247 enc_class aarch64_enc_stlxr(iRegLNoSp src, memory8 mem) %{
3248 Register src_reg = as_Register($src$$reg);
3249 Register base = as_Register($mem$$base);
3250 int index = $mem$$index;
3251 int scale = $mem$$scale;
3252 int disp = $mem$$disp;
3253 if (index == -1) {
3254 if (disp != 0) {
3255 __ lea(rscratch2, Address(base, disp));
3256 __ stlxr(rscratch1, src_reg, rscratch2);
3257 } else {
3258 // TODO
3259 // should we ever get anything other than this case?
3260 __ stlxr(rscratch1, src_reg, base);
3261 }
3262 } else {
3263 Register index_reg = as_Register(index);
3264 if (disp == 0) {
3265 __ lea(rscratch2, Address(base, index_reg, Address::lsl(scale)));
3266 __ stlxr(rscratch1, src_reg, rscratch2);
3267 } else {
3268 __ lea(rscratch2, Address(base, disp));
3269 __ lea(rscratch2, Address(rscratch2, index_reg, Address::lsl(scale)));
3270 __ stlxr(rscratch1, src_reg, rscratch2);
3271 }
3272 }
3273 __ cmpw(rscratch1, zr);
3274 %}
3275
3276 enc_class aarch64_enc_cmpxchg(memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
3277 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3278 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3279 Assembler::xword, /*acquire*/ false, /*release*/ true,
3280 /*weak*/ false, noreg);
3281 %}
3282
3283 enc_class aarch64_enc_cmpxchgw(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3284 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3285 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3286 Assembler::word, /*acquire*/ false, /*release*/ true,
3287 /*weak*/ false, noreg);
3288 %}
3289
3290 enc_class aarch64_enc_cmpxchgs(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3291 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3292 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3293 Assembler::halfword, /*acquire*/ false, /*release*/ true,
3294 /*weak*/ false, noreg);
3295 %}
3296
3297 enc_class aarch64_enc_cmpxchgb(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3298 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3299 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3300 Assembler::byte, /*acquire*/ false, /*release*/ true,
3301 /*weak*/ false, noreg);
3302 %}
3303
3304
3305 // The only difference between aarch64_enc_cmpxchg and
3306 // aarch64_enc_cmpxchg_acq is that we use load-acquire in the
3307 // CompareAndSwap sequence to serve as a barrier on acquiring a
3308 // lock.
3309 enc_class aarch64_enc_cmpxchg_acq(memory mem, iRegLNoSp oldval, iRegLNoSp newval) %{
3310 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3311 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3312 Assembler::xword, /*acquire*/ true, /*release*/ true,
3313 /*weak*/ false, noreg);
3314 %}
3315
3316 enc_class aarch64_enc_cmpxchgw_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3317 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3318 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3319 Assembler::word, /*acquire*/ true, /*release*/ true,
3320 /*weak*/ false, noreg);
3321 %}
3322
3323 enc_class aarch64_enc_cmpxchgs_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3324 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3325 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3326 Assembler::halfword, /*acquire*/ true, /*release*/ true,
3327 /*weak*/ false, noreg);
3328 %}
3329
3330 enc_class aarch64_enc_cmpxchgb_acq(memory mem, iRegINoSp oldval, iRegINoSp newval) %{
3331 guarantee($mem$$index == -1 && $mem$$disp == 0, "impossible encoding");
3332 __ cmpxchg($mem$$base$$Register, $oldval$$Register, $newval$$Register,
3333 Assembler::byte, /*acquire*/ true, /*release*/ true,
3334 /*weak*/ false, noreg);
3335 %}
3336
3337 // auxiliary used for CompareAndSwapX to set result register
3338 enc_class aarch64_enc_cset_eq(iRegINoSp res) %{
3339 Register res_reg = as_Register($res$$reg);
3340 __ cset(res_reg, Assembler::EQ);
3341 %}
3342
3343 // prefetch encodings
3344
3345 enc_class aarch64_enc_prefetchw(memory mem) %{
3346 Register base = as_Register($mem$$base);
3347 int index = $mem$$index;
3348 int scale = $mem$$scale;
3349 int disp = $mem$$disp;
3350 if (index == -1) {
3351 __ prfm(Address(base, disp), PSTL1KEEP);
3352 } else {
3353 Register index_reg = as_Register(index);
3354 if (disp == 0) {
3355 __ prfm(Address(base, index_reg, Address::lsl(scale)), PSTL1KEEP);
3356 } else {
3357 __ lea(rscratch1, Address(base, disp));
3358 __ prfm(Address(rscratch1, index_reg, Address::lsl(scale)), PSTL1KEEP);
3359 }
3360 }
3361 %}
3362
3363 /// mov envcodings
3364
3365 enc_class aarch64_enc_movw_imm(iRegI dst, immI src) %{
3366 uint32_t con = (uint32_t)$src$$constant;
3367 Register dst_reg = as_Register($dst$$reg);
3368 if (con == 0) {
3369 __ movw(dst_reg, zr);
3370 } else {
3371 __ movw(dst_reg, con);
3372 }
3373 %}
3374
3375 enc_class aarch64_enc_mov_imm(iRegL dst, immL src) %{
3376 Register dst_reg = as_Register($dst$$reg);
3377 uint64_t con = (uint64_t)$src$$constant;
3378 if (con == 0) {
3379 __ mov(dst_reg, zr);
3380 } else {
3381 __ mov(dst_reg, con);
3382 }
3383 %}
3384
3385 enc_class aarch64_enc_mov_p(iRegP dst, immP src) %{
3386 Register dst_reg = as_Register($dst$$reg);
3387 address con = (address)$src$$constant;
3388 if (con == nullptr || con == (address)1) {
3389 ShouldNotReachHere();
3390 } else {
3391 relocInfo::relocType rtype = $src->constant_reloc();
3392 if (rtype == relocInfo::oop_type) {
3393 __ movoop(dst_reg, (jobject)con);
3394 } else if (rtype == relocInfo::metadata_type) {
3395 __ mov_metadata(dst_reg, (Metadata*)con);
3396 } else {
3397 assert(rtype == relocInfo::none, "unexpected reloc type");
3398 if (! __ is_valid_AArch64_address(con) ||
3399 con < (address)(uintptr_t)os::vm_page_size()) {
3400 __ mov(dst_reg, con);
3401 } else {
3402 uint64_t offset;
3403 __ adrp(dst_reg, con, offset);
3404 __ add(dst_reg, dst_reg, offset);
3405 }
3406 }
3407 }
3408 %}
3409
3410 enc_class aarch64_enc_mov_p0(iRegP dst, immP0 src) %{
3411 Register dst_reg = as_Register($dst$$reg);
3412 __ mov(dst_reg, zr);
3413 %}
3414
3415 enc_class aarch64_enc_mov_p1(iRegP dst, immP_1 src) %{
3416 Register dst_reg = as_Register($dst$$reg);
3417 __ mov(dst_reg, (uint64_t)1);
3418 %}
3419
3420 enc_class aarch64_enc_mov_byte_map_base(iRegP dst, immByteMapBase src) %{
3421 __ load_byte_map_base($dst$$Register);
3422 %}
3423
3424 enc_class aarch64_enc_mov_n(iRegN dst, immN src) %{
3425 Register dst_reg = as_Register($dst$$reg);
3426 address con = (address)$src$$constant;
3427 if (con == nullptr) {
3428 ShouldNotReachHere();
3429 } else {
3430 relocInfo::relocType rtype = $src->constant_reloc();
3431 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
3432 __ set_narrow_oop(dst_reg, (jobject)con);
3433 }
3434 %}
3435
3436 enc_class aarch64_enc_mov_n0(iRegN dst, immN0 src) %{
3437 Register dst_reg = as_Register($dst$$reg);
3438 __ mov(dst_reg, zr);
3439 %}
3440
3441 enc_class aarch64_enc_mov_nk(iRegN dst, immNKlass src) %{
3442 Register dst_reg = as_Register($dst$$reg);
3443 address con = (address)$src$$constant;
3444 if (con == nullptr) {
3445 ShouldNotReachHere();
3446 } else {
3447 relocInfo::relocType rtype = $src->constant_reloc();
3448 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
3449 __ set_narrow_klass(dst_reg, (Klass *)con);
3450 }
3451 %}
3452
3453 // arithmetic encodings
3454
3455 enc_class aarch64_enc_addsubw_imm(iRegI dst, iRegI src1, immIAddSub src2) %{
3456 Register dst_reg = as_Register($dst$$reg);
3457 Register src_reg = as_Register($src1$$reg);
3458 int32_t con = (int32_t)$src2$$constant;
3459 // add has primary == 0, subtract has primary == 1
3460 if ($primary) { con = -con; }
3461 if (con < 0) {
3462 __ subw(dst_reg, src_reg, -con);
3463 } else {
3464 __ addw(dst_reg, src_reg, con);
3465 }
3466 %}
3467
3468 enc_class aarch64_enc_addsub_imm(iRegL dst, iRegL src1, immLAddSub src2) %{
3469 Register dst_reg = as_Register($dst$$reg);
3470 Register src_reg = as_Register($src1$$reg);
3471 int32_t con = (int32_t)$src2$$constant;
3472 // add has primary == 0, subtract has primary == 1
3473 if ($primary) { con = -con; }
3474 if (con < 0) {
3475 __ sub(dst_reg, src_reg, -con);
3476 } else {
3477 __ add(dst_reg, src_reg, con);
3478 }
3479 %}
3480
3481 enc_class aarch64_enc_divw(iRegI dst, iRegI src1, iRegI src2) %{
3482 Register dst_reg = as_Register($dst$$reg);
3483 Register src1_reg = as_Register($src1$$reg);
3484 Register src2_reg = as_Register($src2$$reg);
3485 __ corrected_idivl(dst_reg, src1_reg, src2_reg, false, rscratch1);
3486 %}
3487
3488 enc_class aarch64_enc_div(iRegI dst, iRegI src1, iRegI src2) %{
3489 Register dst_reg = as_Register($dst$$reg);
3490 Register src1_reg = as_Register($src1$$reg);
3491 Register src2_reg = as_Register($src2$$reg);
3492 __ corrected_idivq(dst_reg, src1_reg, src2_reg, false, rscratch1);
3493 %}
3494
3495 enc_class aarch64_enc_modw(iRegI dst, iRegI src1, iRegI src2) %{
3496 Register dst_reg = as_Register($dst$$reg);
3497 Register src1_reg = as_Register($src1$$reg);
3498 Register src2_reg = as_Register($src2$$reg);
3499 __ corrected_idivl(dst_reg, src1_reg, src2_reg, true, rscratch1);
3500 %}
3501
3502 enc_class aarch64_enc_mod(iRegI dst, iRegI src1, iRegI src2) %{
3503 Register dst_reg = as_Register($dst$$reg);
3504 Register src1_reg = as_Register($src1$$reg);
3505 Register src2_reg = as_Register($src2$$reg);
3506 __ corrected_idivq(dst_reg, src1_reg, src2_reg, true, rscratch1);
3507 %}
3508
3509 // compare instruction encodings
3510
3511 enc_class aarch64_enc_cmpw(iRegI src1, iRegI src2) %{
3512 Register reg1 = as_Register($src1$$reg);
3513 Register reg2 = as_Register($src2$$reg);
3514 __ cmpw(reg1, reg2);
3515 %}
3516
3517 enc_class aarch64_enc_cmpw_imm_addsub(iRegI src1, immIAddSub src2) %{
3518 Register reg = as_Register($src1$$reg);
3519 int32_t val = $src2$$constant;
3520 if (val >= 0) {
3521 __ subsw(zr, reg, val);
3522 } else {
3523 __ addsw(zr, reg, -val);
3524 }
3525 %}
3526
3527 enc_class aarch64_enc_cmpw_imm(iRegI src1, immI src2) %{
3528 Register reg1 = as_Register($src1$$reg);
3529 uint32_t val = (uint32_t)$src2$$constant;
3530 __ movw(rscratch1, val);
3531 __ cmpw(reg1, rscratch1);
3532 %}
3533
3534 enc_class aarch64_enc_cmp(iRegL src1, iRegL src2) %{
3535 Register reg1 = as_Register($src1$$reg);
3536 Register reg2 = as_Register($src2$$reg);
3537 __ cmp(reg1, reg2);
3538 %}
3539
3540 enc_class aarch64_enc_cmp_imm_addsub(iRegL src1, immL12 src2) %{
3541 Register reg = as_Register($src1$$reg);
3542 int64_t val = $src2$$constant;
3543 if (val >= 0) {
3544 __ subs(zr, reg, val);
3545 } else if (val != -val) {
3546 __ adds(zr, reg, -val);
3547 } else {
3548 // aargh, Long.MIN_VALUE is a special case
3549 __ orr(rscratch1, zr, (uint64_t)val);
3550 __ subs(zr, reg, rscratch1);
3551 }
3552 %}
3553
3554 enc_class aarch64_enc_cmp_imm(iRegL src1, immL src2) %{
3555 Register reg1 = as_Register($src1$$reg);
3556 uint64_t val = (uint64_t)$src2$$constant;
3557 __ mov(rscratch1, val);
3558 __ cmp(reg1, rscratch1);
3559 %}
3560
3561 enc_class aarch64_enc_cmpp(iRegP src1, iRegP src2) %{
3562 Register reg1 = as_Register($src1$$reg);
3563 Register reg2 = as_Register($src2$$reg);
3564 __ cmp(reg1, reg2);
3565 %}
3566
3567 enc_class aarch64_enc_cmpn(iRegN src1, iRegN src2) %{
3568 Register reg1 = as_Register($src1$$reg);
3569 Register reg2 = as_Register($src2$$reg);
3570 __ cmpw(reg1, reg2);
3571 %}
3572
3573 enc_class aarch64_enc_testp(iRegP src) %{
3574 Register reg = as_Register($src$$reg);
3575 __ cmp(reg, zr);
3576 %}
3577
3578 enc_class aarch64_enc_testn(iRegN src) %{
3579 Register reg = as_Register($src$$reg);
3580 __ cmpw(reg, zr);
3581 %}
3582
3583 enc_class aarch64_enc_b(label lbl) %{
3584 Label *L = $lbl$$label;
3585 __ b(*L);
3586 %}
3587
3588 enc_class aarch64_enc_br_con(cmpOp cmp, label lbl) %{
3589 Label *L = $lbl$$label;
3590 __ br ((Assembler::Condition)$cmp$$cmpcode, *L);
3591 %}
3592
3593 enc_class aarch64_enc_br_conU(cmpOpU cmp, label lbl) %{
3594 Label *L = $lbl$$label;
3595 __ br ((Assembler::Condition)$cmp$$cmpcode, *L);
3596 %}
3597
3598 enc_class aarch64_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result)
3599 %{
3600 Register sub_reg = as_Register($sub$$reg);
3601 Register super_reg = as_Register($super$$reg);
3602 Register temp_reg = as_Register($temp$$reg);
3603 Register result_reg = as_Register($result$$reg);
3604
3605 Label miss;
3606 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
3607 nullptr, &miss,
3608 /*set_cond_codes:*/ true);
3609 if ($primary) {
3610 __ mov(result_reg, zr);
3611 }
3612 __ bind(miss);
3613 %}
3614
3615 enc_class aarch64_enc_java_static_call(method meth) %{
3616 address addr = (address)$meth$$method;
3617 address call;
3618 if (!_method) {
3619 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3620 call = __ trampoline_call(Address(addr, relocInfo::runtime_call_type));
3621 if (call == nullptr) {
3622 ciEnv::current()->record_failure("CodeCache is full");
3623 return;
3624 }
3625 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
3626 // The NOP here is purely to ensure that eliding a call to
3627 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
3628 __ nop();
3629 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
3630 } else {
3631 int method_index = resolved_method_index(masm);
3632 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
3633 : static_call_Relocation::spec(method_index);
3634 call = __ trampoline_call(Address(addr, rspec));
3635 if (call == nullptr) {
3636 ciEnv::current()->record_failure("CodeCache is full");
3637 return;
3638 }
3639 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
3640 // Calls of the same statically bound method can share
3641 // a stub to the interpreter.
3642 __ code()->shared_stub_to_interp_for(_method, call - __ begin());
3643 } else {
3644 // Emit stub for static call
3645 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
3646 if (stub == nullptr) {
3647 ciEnv::current()->record_failure("CodeCache is full");
3648 return;
3649 }
3650 }
3651 }
3652
3653 __ post_call_nop();
3654
3655 // Only non uncommon_trap calls need to reinitialize ptrue.
3656 if (Compile::current()->max_vector_size() > 0 && uncommon_trap_request() == 0) {
3657 __ reinitialize_ptrue();
3658 }
3659 %}
3660
3661 enc_class aarch64_enc_java_dynamic_call(method meth) %{
3662 int method_index = resolved_method_index(masm);
3663 address call = __ ic_call((address)$meth$$method, method_index);
3664 if (call == nullptr) {
3665 ciEnv::current()->record_failure("CodeCache is full");
3666 return;
3667 }
3668 __ post_call_nop();
3669 if (Compile::current()->max_vector_size() > 0) {
3670 __ reinitialize_ptrue();
3671 }
3672 %}
3673
3674 enc_class aarch64_enc_call_epilog() %{
3675 if (VerifyStackAtCalls) {
3676 // Check that stack depth is unchanged: find majik cookie on stack
3677 __ call_Unimplemented();
3678 }
3679 %}
3680
3681 enc_class aarch64_enc_java_to_runtime(method meth) %{
3682 // some calls to generated routines (arraycopy code) are scheduled
3683 // by C2 as runtime calls. if so we can call them using a br (they
3684 // will be in a reachable segment) otherwise we have to use a blr
3685 // which loads the absolute address into a register.
3686 address entry = (address)$meth$$method;
3687 CodeBlob *cb = CodeCache::find_blob(entry);
3688 if (cb) {
3689 address call = __ trampoline_call(Address(entry, relocInfo::runtime_call_type));
3690 if (call == nullptr) {
3691 ciEnv::current()->record_failure("CodeCache is full");
3692 return;
3693 }
3694 __ post_call_nop();
3695 } else {
3696 Label retaddr;
3697 __ adr(rscratch2, retaddr);
3698 __ lea(rscratch1, RuntimeAddress(entry));
3699 // Leave a breadcrumb for JavaFrameAnchor::capture_last_Java_pc()
3700 __ stp(zr, rscratch2, Address(__ pre(sp, -2 * wordSize)));
3701 __ blr(rscratch1);
3702 __ bind(retaddr);
3703 __ post_call_nop();
3704 __ add(sp, sp, 2 * wordSize);
3705 }
3706 if (Compile::current()->max_vector_size() > 0) {
3707 __ reinitialize_ptrue();
3708 }
3709 %}
3710
3711 enc_class aarch64_enc_rethrow() %{
3712 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
3713 %}
3714
3715 enc_class aarch64_enc_ret() %{
3716 #ifdef ASSERT
3717 if (Compile::current()->max_vector_size() > 0) {
3718 __ verify_ptrue();
3719 }
3720 #endif
3721 __ ret(lr);
3722 %}
3723
3724 enc_class aarch64_enc_tail_call(iRegP jump_target) %{
3725 Register target_reg = as_Register($jump_target$$reg);
3726 __ br(target_reg);
3727 %}
3728
3729 enc_class aarch64_enc_tail_jmp(iRegP jump_target) %{
3730 Register target_reg = as_Register($jump_target$$reg);
3731 // exception oop should be in r0
3732 // ret addr has been popped into lr
3733 // callee expects it in r3
3734 __ mov(r3, lr);
3735 __ br(target_reg);
3736 %}
3737
3738 %}
3739
3740 //----------FRAME--------------------------------------------------------------
3741 // Definition of frame structure and management information.
3742 //
3743 // S T A C K L A Y O U T Allocators stack-slot number
3744 // | (to get allocators register number
3745 // G Owned by | | v add OptoReg::stack0())
3746 // r CALLER | |
3747 // o | +--------+ pad to even-align allocators stack-slot
3748 // w V | pad0 | numbers; owned by CALLER
3749 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3750 // h ^ | in | 5
3751 // | | args | 4 Holes in incoming args owned by SELF
3752 // | | | | 3
3753 // | | +--------+
3754 // V | | old out| Empty on Intel, window on Sparc
3755 // | old |preserve| Must be even aligned.
3756 // | SP-+--------+----> Matcher::_old_SP, even aligned
3757 // | | in | 3 area for Intel ret address
3758 // Owned by |preserve| Empty on Sparc.
3759 // SELF +--------+
3760 // | | pad2 | 2 pad to align old SP
3761 // | +--------+ 1
3762 // | | locks | 0
3763 // | +--------+----> OptoReg::stack0(), even aligned
3764 // | | pad1 | 11 pad to align new SP
3765 // | +--------+
3766 // | | | 10
3767 // | | spills | 9 spills
3768 // V | | 8 (pad0 slot for callee)
3769 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3770 // ^ | out | 7
3771 // | | args | 6 Holes in outgoing args owned by CALLEE
3772 // Owned by +--------+
3773 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3774 // | new |preserve| Must be even-aligned.
3775 // | SP-+--------+----> Matcher::_new_SP, even aligned
3776 // | | |
3777 //
3778 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3779 // known from SELF's arguments and the Java calling convention.
3780 // Region 6-7 is determined per call site.
3781 // Note 2: If the calling convention leaves holes in the incoming argument
3782 // area, those holes are owned by SELF. Holes in the outgoing area
3783 // are owned by the CALLEE. Holes should not be necessary in the
3784 // incoming area, as the Java calling convention is completely under
3785 // the control of the AD file. Doubles can be sorted and packed to
3786 // avoid holes. Holes in the outgoing arguments may be necessary for
3787 // varargs C calling conventions.
3788 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3789 // even aligned with pad0 as needed.
3790 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3791 // (the latter is true on Intel but is it false on AArch64?)
3792 // region 6-11 is even aligned; it may be padded out more so that
3793 // the region from SP to FP meets the minimum stack alignment.
3794 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
3795 // alignment. Region 11, pad1, may be dynamically extended so that
3796 // SP meets the minimum alignment.
3797
3798 frame %{
3799 // These three registers define part of the calling convention
3800 // between compiled code and the interpreter.
3801
3802 // Inline Cache Register or Method for I2C.
3803 inline_cache_reg(R12);
3804
3805 // Number of stack slots consumed by locking an object
3806 sync_stack_slots(2);
3807
3808 // Compiled code's Frame Pointer
3809 frame_pointer(R31);
3810
3811 // Interpreter stores its frame pointer in a register which is
3812 // stored to the stack by I2CAdaptors.
3813 // I2CAdaptors convert from interpreted java to compiled java.
3814 interpreter_frame_pointer(R29);
3815
3816 // Stack alignment requirement
3817 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
3818
3819 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3820 // for calls to C. Supports the var-args backing area for register parms.
3821 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
3822
3823 // The after-PROLOG location of the return address. Location of
3824 // return address specifies a type (REG or STACK) and a number
3825 // representing the register number (i.e. - use a register name) or
3826 // stack slot.
3827 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3828 // Otherwise, it is above the locks and verification slot and alignment word
3829 // TODO this may well be correct but need to check why that - 2 is there
3830 // ppc port uses 0 but we definitely need to allow for fixed_slots
3831 // which folds in the space used for monitors
3832 return_addr(STACK - 2 +
3833 align_up((Compile::current()->in_preserve_stack_slots() +
3834 Compile::current()->fixed_slots()),
3835 stack_alignment_in_slots()));
3836
3837 // Location of compiled Java return values. Same as C for now.
3838 return_value
3839 %{
3840 // TODO do we allow ideal_reg == Op_RegN???
3841 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
3842 "only return normal values");
3843
3844 static const int lo[Op_RegL + 1] = { // enum name
3845 0, // Op_Node
3846 0, // Op_Set
3847 R0_num, // Op_RegN
3848 R0_num, // Op_RegI
3849 R0_num, // Op_RegP
3850 V0_num, // Op_RegF
3851 V0_num, // Op_RegD
3852 R0_num // Op_RegL
3853 };
3854
3855 static const int hi[Op_RegL + 1] = { // enum name
3856 0, // Op_Node
3857 0, // Op_Set
3858 OptoReg::Bad, // Op_RegN
3859 OptoReg::Bad, // Op_RegI
3860 R0_H_num, // Op_RegP
3861 OptoReg::Bad, // Op_RegF
3862 V0_H_num, // Op_RegD
3863 R0_H_num // Op_RegL
3864 };
3865
3866 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
3867 %}
3868 %}
3869
3870 //----------ATTRIBUTES---------------------------------------------------------
3871 //----------Operand Attributes-------------------------------------------------
3872 op_attrib op_cost(1); // Required cost attribute
3873
3874 //----------Instruction Attributes---------------------------------------------
3875 ins_attrib ins_cost(INSN_COST); // Required cost attribute
3876 ins_attrib ins_size(32); // Required size attribute (in bits)
3877 ins_attrib ins_short_branch(0); // Required flag: is this instruction
3878 // a non-matching short branch variant
3879 // of some long branch?
3880 ins_attrib ins_alignment(4); // Required alignment attribute (must
3881 // be a power of 2) specifies the
3882 // alignment that some part of the
3883 // instruction (not necessarily the
3884 // start) requires. If > 1, a
3885 // compute_padding() function must be
3886 // provided for the instruction
3887
3888 //----------OPERANDS-----------------------------------------------------------
3889 // Operand definitions must precede instruction definitions for correct parsing
3890 // in the ADLC because operands constitute user defined types which are used in
3891 // instruction definitions.
3892
3893 //----------Simple Operands----------------------------------------------------
3894
3895 // Integer operands 32 bit
3896 // 32 bit immediate
3897 operand immI()
3898 %{
3899 match(ConI);
3900
3901 op_cost(0);
3902 format %{ %}
3903 interface(CONST_INTER);
3904 %}
3905
3906 // 32 bit zero
3907 operand immI0()
3908 %{
3909 predicate(n->get_int() == 0);
3910 match(ConI);
3911
3912 op_cost(0);
3913 format %{ %}
3914 interface(CONST_INTER);
3915 %}
3916
3917 // 32 bit unit increment
3918 operand immI_1()
3919 %{
3920 predicate(n->get_int() == 1);
3921 match(ConI);
3922
3923 op_cost(0);
3924 format %{ %}
3925 interface(CONST_INTER);
3926 %}
3927
3928 // 32 bit unit decrement
3929 operand immI_M1()
3930 %{
3931 predicate(n->get_int() == -1);
3932 match(ConI);
3933
3934 op_cost(0);
3935 format %{ %}
3936 interface(CONST_INTER);
3937 %}
3938
3939 // Shift values for add/sub extension shift
3940 operand immIExt()
3941 %{
3942 predicate(0 <= n->get_int() && (n->get_int() <= 4));
3943 match(ConI);
3944
3945 op_cost(0);
3946 format %{ %}
3947 interface(CONST_INTER);
3948 %}
3949
3950 operand immI_gt_1()
3951 %{
3952 predicate(n->get_int() > 1);
3953 match(ConI);
3954
3955 op_cost(0);
3956 format %{ %}
3957 interface(CONST_INTER);
3958 %}
3959
3960 operand immI_le_4()
3961 %{
3962 predicate(n->get_int() <= 4);
3963 match(ConI);
3964
3965 op_cost(0);
3966 format %{ %}
3967 interface(CONST_INTER);
3968 %}
3969
3970 operand immI_16()
3971 %{
3972 predicate(n->get_int() == 16);
3973 match(ConI);
3974
3975 op_cost(0);
3976 format %{ %}
3977 interface(CONST_INTER);
3978 %}
3979
3980 operand immI_24()
3981 %{
3982 predicate(n->get_int() == 24);
3983 match(ConI);
3984
3985 op_cost(0);
3986 format %{ %}
3987 interface(CONST_INTER);
3988 %}
3989
3990 operand immI_32()
3991 %{
3992 predicate(n->get_int() == 32);
3993 match(ConI);
3994
3995 op_cost(0);
3996 format %{ %}
3997 interface(CONST_INTER);
3998 %}
3999
4000 operand immI_48()
4001 %{
4002 predicate(n->get_int() == 48);
4003 match(ConI);
4004
4005 op_cost(0);
4006 format %{ %}
4007 interface(CONST_INTER);
4008 %}
4009
4010 operand immI_56()
4011 %{
4012 predicate(n->get_int() == 56);
4013 match(ConI);
4014
4015 op_cost(0);
4016 format %{ %}
4017 interface(CONST_INTER);
4018 %}
4019
4020 operand immI_255()
4021 %{
4022 predicate(n->get_int() == 255);
4023 match(ConI);
4024
4025 op_cost(0);
4026 format %{ %}
4027 interface(CONST_INTER);
4028 %}
4029
4030 operand immI_65535()
4031 %{
4032 predicate(n->get_int() == 65535);
4033 match(ConI);
4034
4035 op_cost(0);
4036 format %{ %}
4037 interface(CONST_INTER);
4038 %}
4039
4040 operand immI_positive()
4041 %{
4042 predicate(n->get_int() > 0);
4043 match(ConI);
4044
4045 op_cost(0);
4046 format %{ %}
4047 interface(CONST_INTER);
4048 %}
4049
4050 // BoolTest condition for signed compare
4051 operand immI_cmp_cond()
4052 %{
4053 predicate(!Matcher::is_unsigned_booltest_pred(n->get_int()));
4054 match(ConI);
4055
4056 op_cost(0);
4057 format %{ %}
4058 interface(CONST_INTER);
4059 %}
4060
4061 // BoolTest condition for unsigned compare
4062 operand immI_cmpU_cond()
4063 %{
4064 predicate(Matcher::is_unsigned_booltest_pred(n->get_int()));
4065 match(ConI);
4066
4067 op_cost(0);
4068 format %{ %}
4069 interface(CONST_INTER);
4070 %}
4071
4072 operand immL_255()
4073 %{
4074 predicate(n->get_long() == 255L);
4075 match(ConL);
4076
4077 op_cost(0);
4078 format %{ %}
4079 interface(CONST_INTER);
4080 %}
4081
4082 operand immL_65535()
4083 %{
4084 predicate(n->get_long() == 65535L);
4085 match(ConL);
4086
4087 op_cost(0);
4088 format %{ %}
4089 interface(CONST_INTER);
4090 %}
4091
4092 operand immL_4294967295()
4093 %{
4094 predicate(n->get_long() == 4294967295L);
4095 match(ConL);
4096
4097 op_cost(0);
4098 format %{ %}
4099 interface(CONST_INTER);
4100 %}
4101
4102 operand immL_bitmask()
4103 %{
4104 predicate((n->get_long() != 0)
4105 && ((n->get_long() & 0xc000000000000000l) == 0)
4106 && is_power_of_2(n->get_long() + 1));
4107 match(ConL);
4108
4109 op_cost(0);
4110 format %{ %}
4111 interface(CONST_INTER);
4112 %}
4113
4114 operand immI_bitmask()
4115 %{
4116 predicate((n->get_int() != 0)
4117 && ((n->get_int() & 0xc0000000) == 0)
4118 && is_power_of_2(n->get_int() + 1));
4119 match(ConI);
4120
4121 op_cost(0);
4122 format %{ %}
4123 interface(CONST_INTER);
4124 %}
4125
4126 operand immL_positive_bitmaskI()
4127 %{
4128 predicate((n->get_long() != 0)
4129 && ((julong)n->get_long() < 0x80000000ULL)
4130 && is_power_of_2(n->get_long() + 1));
4131 match(ConL);
4132
4133 op_cost(0);
4134 format %{ %}
4135 interface(CONST_INTER);
4136 %}
4137
4138 // Scale values for scaled offset addressing modes (up to long but not quad)
4139 operand immIScale()
4140 %{
4141 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4142 match(ConI);
4143
4144 op_cost(0);
4145 format %{ %}
4146 interface(CONST_INTER);
4147 %}
4148
4149 // 5 bit signed integer
4150 operand immI5()
4151 %{
4152 predicate(Assembler::is_simm(n->get_int(), 5));
4153 match(ConI);
4154
4155 op_cost(0);
4156 format %{ %}
4157 interface(CONST_INTER);
4158 %}
4159
4160 // 7 bit unsigned integer
4161 operand immIU7()
4162 %{
4163 predicate(Assembler::is_uimm(n->get_int(), 7));
4164 match(ConI);
4165
4166 op_cost(0);
4167 format %{ %}
4168 interface(CONST_INTER);
4169 %}
4170
4171 // Offset for scaled or unscaled immediate loads and stores
4172 operand immIOffset()
4173 %{
4174 predicate(Address::offset_ok_for_immed(n->get_int(), 0));
4175 match(ConI);
4176
4177 op_cost(0);
4178 format %{ %}
4179 interface(CONST_INTER);
4180 %}
4181
4182 operand immIOffset1()
4183 %{
4184 predicate(Address::offset_ok_for_immed(n->get_int(), 0));
4185 match(ConI);
4186
4187 op_cost(0);
4188 format %{ %}
4189 interface(CONST_INTER);
4190 %}
4191
4192 operand immIOffset2()
4193 %{
4194 predicate(Address::offset_ok_for_immed(n->get_int(), 1));
4195 match(ConI);
4196
4197 op_cost(0);
4198 format %{ %}
4199 interface(CONST_INTER);
4200 %}
4201
4202 operand immIOffset4()
4203 %{
4204 predicate(Address::offset_ok_for_immed(n->get_int(), 2));
4205 match(ConI);
4206
4207 op_cost(0);
4208 format %{ %}
4209 interface(CONST_INTER);
4210 %}
4211
4212 operand immIOffset8()
4213 %{
4214 predicate(Address::offset_ok_for_immed(n->get_int(), 3));
4215 match(ConI);
4216
4217 op_cost(0);
4218 format %{ %}
4219 interface(CONST_INTER);
4220 %}
4221
4222 operand immIOffset16()
4223 %{
4224 predicate(Address::offset_ok_for_immed(n->get_int(), 4));
4225 match(ConI);
4226
4227 op_cost(0);
4228 format %{ %}
4229 interface(CONST_INTER);
4230 %}
4231
4232 operand immLoffset()
4233 %{
4234 predicate(Address::offset_ok_for_immed(n->get_long(), 0));
4235 match(ConL);
4236
4237 op_cost(0);
4238 format %{ %}
4239 interface(CONST_INTER);
4240 %}
4241
4242 operand immLoffset1()
4243 %{
4244 predicate(Address::offset_ok_for_immed(n->get_long(), 0));
4245 match(ConL);
4246
4247 op_cost(0);
4248 format %{ %}
4249 interface(CONST_INTER);
4250 %}
4251
4252 operand immLoffset2()
4253 %{
4254 predicate(Address::offset_ok_for_immed(n->get_long(), 1));
4255 match(ConL);
4256
4257 op_cost(0);
4258 format %{ %}
4259 interface(CONST_INTER);
4260 %}
4261
4262 operand immLoffset4()
4263 %{
4264 predicate(Address::offset_ok_for_immed(n->get_long(), 2));
4265 match(ConL);
4266
4267 op_cost(0);
4268 format %{ %}
4269 interface(CONST_INTER);
4270 %}
4271
4272 operand immLoffset8()
4273 %{
4274 predicate(Address::offset_ok_for_immed(n->get_long(), 3));
4275 match(ConL);
4276
4277 op_cost(0);
4278 format %{ %}
4279 interface(CONST_INTER);
4280 %}
4281
4282 operand immLoffset16()
4283 %{
4284 predicate(Address::offset_ok_for_immed(n->get_long(), 4));
4285 match(ConL);
4286
4287 op_cost(0);
4288 format %{ %}
4289 interface(CONST_INTER);
4290 %}
4291
4292 // 5 bit signed long integer
4293 operand immL5()
4294 %{
4295 predicate(Assembler::is_simm(n->get_long(), 5));
4296 match(ConL);
4297
4298 op_cost(0);
4299 format %{ %}
4300 interface(CONST_INTER);
4301 %}
4302
4303 // 7 bit unsigned long integer
4304 operand immLU7()
4305 %{
4306 predicate(Assembler::is_uimm(n->get_long(), 7));
4307 match(ConL);
4308
4309 op_cost(0);
4310 format %{ %}
4311 interface(CONST_INTER);
4312 %}
4313
4314 // 8 bit signed value.
4315 operand immI8()
4316 %{
4317 predicate(n->get_int() <= 127 && n->get_int() >= -128);
4318 match(ConI);
4319
4320 op_cost(0);
4321 format %{ %}
4322 interface(CONST_INTER);
4323 %}
4324
4325 // 8 bit signed value (simm8), or #simm8 LSL 8.
4326 operand immI8_shift8()
4327 %{
4328 predicate((n->get_int() <= 127 && n->get_int() >= -128) ||
4329 (n->get_int() <= 32512 && n->get_int() >= -32768 && (n->get_int() & 0xff) == 0));
4330 match(ConI);
4331
4332 op_cost(0);
4333 format %{ %}
4334 interface(CONST_INTER);
4335 %}
4336
4337 // 8 bit signed value (simm8), or #simm8 LSL 8.
4338 operand immL8_shift8()
4339 %{
4340 predicate((n->get_long() <= 127 && n->get_long() >= -128) ||
4341 (n->get_long() <= 32512 && n->get_long() >= -32768 && (n->get_long() & 0xff) == 0));
4342 match(ConL);
4343
4344 op_cost(0);
4345 format %{ %}
4346 interface(CONST_INTER);
4347 %}
4348
4349 // 8 bit integer valid for vector add sub immediate
4350 operand immBAddSubV()
4351 %{
4352 predicate(n->get_int() <= 255 && n->get_int() >= -255);
4353 match(ConI);
4354
4355 op_cost(0);
4356 format %{ %}
4357 interface(CONST_INTER);
4358 %}
4359
4360 // 32 bit integer valid for add sub immediate
4361 operand immIAddSub()
4362 %{
4363 predicate(Assembler::operand_valid_for_add_sub_immediate((int64_t)n->get_int()));
4364 match(ConI);
4365 op_cost(0);
4366 format %{ %}
4367 interface(CONST_INTER);
4368 %}
4369
4370 // 32 bit integer valid for vector add sub immediate
4371 operand immIAddSubV()
4372 %{
4373 predicate(Assembler::operand_valid_for_sve_add_sub_immediate((int64_t)n->get_int()));
4374 match(ConI);
4375
4376 op_cost(0);
4377 format %{ %}
4378 interface(CONST_INTER);
4379 %}
4380
4381 // 32 bit unsigned integer valid for logical immediate
4382
4383 operand immBLog()
4384 %{
4385 predicate(Assembler::operand_valid_for_sve_logical_immediate(BitsPerByte, (uint64_t)n->get_int()));
4386 match(ConI);
4387
4388 op_cost(0);
4389 format %{ %}
4390 interface(CONST_INTER);
4391 %}
4392
4393 operand immSLog()
4394 %{
4395 predicate(Assembler::operand_valid_for_sve_logical_immediate(BitsPerShort, (uint64_t)n->get_int()));
4396 match(ConI);
4397
4398 op_cost(0);
4399 format %{ %}
4400 interface(CONST_INTER);
4401 %}
4402
4403 operand immILog()
4404 %{
4405 predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/true, (uint64_t)n->get_int()));
4406 match(ConI);
4407
4408 op_cost(0);
4409 format %{ %}
4410 interface(CONST_INTER);
4411 %}
4412
4413 // Integer operands 64 bit
4414 // 64 bit immediate
4415 operand immL()
4416 %{
4417 match(ConL);
4418
4419 op_cost(0);
4420 format %{ %}
4421 interface(CONST_INTER);
4422 %}
4423
4424 // 64 bit zero
4425 operand immL0()
4426 %{
4427 predicate(n->get_long() == 0);
4428 match(ConL);
4429
4430 op_cost(0);
4431 format %{ %}
4432 interface(CONST_INTER);
4433 %}
4434
4435 // 64 bit unit decrement
4436 operand immL_M1()
4437 %{
4438 predicate(n->get_long() == -1);
4439 match(ConL);
4440
4441 op_cost(0);
4442 format %{ %}
4443 interface(CONST_INTER);
4444 %}
4445
4446 // 64 bit integer valid for add sub immediate
4447 operand immLAddSub()
4448 %{
4449 predicate(Assembler::operand_valid_for_add_sub_immediate(n->get_long()));
4450 match(ConL);
4451 op_cost(0);
4452 format %{ %}
4453 interface(CONST_INTER);
4454 %}
4455
4456 // 64 bit integer valid for addv subv immediate
4457 operand immLAddSubV()
4458 %{
4459 predicate(Assembler::operand_valid_for_sve_add_sub_immediate(n->get_long()));
4460 match(ConL);
4461
4462 op_cost(0);
4463 format %{ %}
4464 interface(CONST_INTER);
4465 %}
4466
4467 // 64 bit integer valid for logical immediate
4468 operand immLLog()
4469 %{
4470 predicate(Assembler::operand_valid_for_logical_immediate(/*is32*/false, (uint64_t)n->get_long()));
4471 match(ConL);
4472 op_cost(0);
4473 format %{ %}
4474 interface(CONST_INTER);
4475 %}
4476
4477 // Long Immediate: low 32-bit mask
4478 operand immL_32bits()
4479 %{
4480 predicate(n->get_long() == 0xFFFFFFFFL);
4481 match(ConL);
4482 op_cost(0);
4483 format %{ %}
4484 interface(CONST_INTER);
4485 %}
4486
4487 // Pointer operands
4488 // Pointer Immediate
4489 operand immP()
4490 %{
4491 match(ConP);
4492
4493 op_cost(0);
4494 format %{ %}
4495 interface(CONST_INTER);
4496 %}
4497
4498 // nullptr Pointer Immediate
4499 operand immP0()
4500 %{
4501 predicate(n->get_ptr() == 0);
4502 match(ConP);
4503
4504 op_cost(0);
4505 format %{ %}
4506 interface(CONST_INTER);
4507 %}
4508
4509 // Pointer Immediate One
4510 // this is used in object initialization (initial object header)
4511 operand immP_1()
4512 %{
4513 predicate(n->get_ptr() == 1);
4514 match(ConP);
4515
4516 op_cost(0);
4517 format %{ %}
4518 interface(CONST_INTER);
4519 %}
4520
4521 // Card Table Byte Map Base
4522 operand immByteMapBase()
4523 %{
4524 // Get base of card map
4525 predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
4526 (CardTable::CardValue*)n->get_ptr() == ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
4527 match(ConP);
4528
4529 op_cost(0);
4530 format %{ %}
4531 interface(CONST_INTER);
4532 %}
4533
4534 // Float and Double operands
4535 // Double Immediate
4536 operand immD()
4537 %{
4538 match(ConD);
4539 op_cost(0);
4540 format %{ %}
4541 interface(CONST_INTER);
4542 %}
4543
4544 // Double Immediate: +0.0d
4545 operand immD0()
4546 %{
4547 predicate(jlong_cast(n->getd()) == 0);
4548 match(ConD);
4549
4550 op_cost(0);
4551 format %{ %}
4552 interface(CONST_INTER);
4553 %}
4554
4555 // constant 'double +0.0'.
4556 operand immDPacked()
4557 %{
4558 predicate(Assembler::operand_valid_for_float_immediate(n->getd()));
4559 match(ConD);
4560 op_cost(0);
4561 format %{ %}
4562 interface(CONST_INTER);
4563 %}
4564
4565 // Float Immediate
4566 operand immF()
4567 %{
4568 match(ConF);
4569 op_cost(0);
4570 format %{ %}
4571 interface(CONST_INTER);
4572 %}
4573
4574 // Float Immediate: +0.0f.
4575 operand immF0()
4576 %{
4577 predicate(jint_cast(n->getf()) == 0);
4578 match(ConF);
4579
4580 op_cost(0);
4581 format %{ %}
4582 interface(CONST_INTER);
4583 %}
4584
4585 //
4586 operand immFPacked()
4587 %{
4588 predicate(Assembler::operand_valid_for_float_immediate((double)n->getf()));
4589 match(ConF);
4590 op_cost(0);
4591 format %{ %}
4592 interface(CONST_INTER);
4593 %}
4594
4595 // Narrow pointer operands
4596 // Narrow Pointer Immediate
4597 operand immN()
4598 %{
4599 match(ConN);
4600
4601 op_cost(0);
4602 format %{ %}
4603 interface(CONST_INTER);
4604 %}
4605
4606 // Narrow nullptr Pointer Immediate
4607 operand immN0()
4608 %{
4609 predicate(n->get_narrowcon() == 0);
4610 match(ConN);
4611
4612 op_cost(0);
4613 format %{ %}
4614 interface(CONST_INTER);
4615 %}
4616
4617 operand immNKlass()
4618 %{
4619 match(ConNKlass);
4620
4621 op_cost(0);
4622 format %{ %}
4623 interface(CONST_INTER);
4624 %}
4625
4626 // Integer 32 bit Register Operands
4627 // Integer 32 bitRegister (excludes SP)
4628 operand iRegI()
4629 %{
4630 constraint(ALLOC_IN_RC(any_reg32));
4631 match(RegI);
4632 match(iRegINoSp);
4633 op_cost(0);
4634 format %{ %}
4635 interface(REG_INTER);
4636 %}
4637
4638 // Integer 32 bit Register not Special
4639 operand iRegINoSp()
4640 %{
4641 constraint(ALLOC_IN_RC(no_special_reg32));
4642 match(RegI);
4643 op_cost(0);
4644 format %{ %}
4645 interface(REG_INTER);
4646 %}
4647
4648 // Integer 64 bit Register Operands
4649 // Integer 64 bit Register (includes SP)
4650 operand iRegL()
4651 %{
4652 constraint(ALLOC_IN_RC(any_reg));
4653 match(RegL);
4654 match(iRegLNoSp);
4655 op_cost(0);
4656 format %{ %}
4657 interface(REG_INTER);
4658 %}
4659
4660 // Integer 64 bit Register not Special
4661 operand iRegLNoSp()
4662 %{
4663 constraint(ALLOC_IN_RC(no_special_reg));
4664 match(RegL);
4665 match(iRegL_R0);
4666 format %{ %}
4667 interface(REG_INTER);
4668 %}
4669
4670 // Pointer Register Operands
4671 // Pointer Register
4672 operand iRegP()
4673 %{
4674 constraint(ALLOC_IN_RC(ptr_reg));
4675 match(RegP);
4676 match(iRegPNoSp);
4677 match(iRegP_R0);
4678 //match(iRegP_R2);
4679 //match(iRegP_R4);
4680 match(iRegP_R5);
4681 match(thread_RegP);
4682 op_cost(0);
4683 format %{ %}
4684 interface(REG_INTER);
4685 %}
4686
4687 // Pointer 64 bit Register not Special
4688 operand iRegPNoSp()
4689 %{
4690 constraint(ALLOC_IN_RC(no_special_ptr_reg));
4691 match(RegP);
4692 // match(iRegP);
4693 // match(iRegP_R0);
4694 // match(iRegP_R2);
4695 // match(iRegP_R4);
4696 // match(iRegP_R5);
4697 // match(thread_RegP);
4698 op_cost(0);
4699 format %{ %}
4700 interface(REG_INTER);
4701 %}
4702
4703 // This operand is not allowed to use rfp even if
4704 // rfp is not used to hold the frame pointer.
4705 operand iRegPNoSpNoRfp()
4706 %{
4707 constraint(ALLOC_IN_RC(no_special_no_rfp_ptr_reg));
4708 match(RegP);
4709 match(iRegPNoSp);
4710 op_cost(0);
4711 format %{ %}
4712 interface(REG_INTER);
4713 %}
4714
4715 // Pointer 64 bit Register R0 only
4716 operand iRegP_R0()
4717 %{
4718 constraint(ALLOC_IN_RC(r0_reg));
4719 match(RegP);
4720 // match(iRegP);
4721 match(iRegPNoSp);
4722 op_cost(0);
4723 format %{ %}
4724 interface(REG_INTER);
4725 %}
4726
4727 // Pointer 64 bit Register R1 only
4728 operand iRegP_R1()
4729 %{
4730 constraint(ALLOC_IN_RC(r1_reg));
4731 match(RegP);
4732 // match(iRegP);
4733 match(iRegPNoSp);
4734 op_cost(0);
4735 format %{ %}
4736 interface(REG_INTER);
4737 %}
4738
4739 // Pointer 64 bit Register R2 only
4740 operand iRegP_R2()
4741 %{
4742 constraint(ALLOC_IN_RC(r2_reg));
4743 match(RegP);
4744 // match(iRegP);
4745 match(iRegPNoSp);
4746 op_cost(0);
4747 format %{ %}
4748 interface(REG_INTER);
4749 %}
4750
4751 // Pointer 64 bit Register R3 only
4752 operand iRegP_R3()
4753 %{
4754 constraint(ALLOC_IN_RC(r3_reg));
4755 match(RegP);
4756 // match(iRegP);
4757 match(iRegPNoSp);
4758 op_cost(0);
4759 format %{ %}
4760 interface(REG_INTER);
4761 %}
4762
4763 // Pointer 64 bit Register R4 only
4764 operand iRegP_R4()
4765 %{
4766 constraint(ALLOC_IN_RC(r4_reg));
4767 match(RegP);
4768 // match(iRegP);
4769 match(iRegPNoSp);
4770 op_cost(0);
4771 format %{ %}
4772 interface(REG_INTER);
4773 %}
4774
4775 // Pointer 64 bit Register R5 only
4776 operand iRegP_R5()
4777 %{
4778 constraint(ALLOC_IN_RC(r5_reg));
4779 match(RegP);
4780 // match(iRegP);
4781 match(iRegPNoSp);
4782 op_cost(0);
4783 format %{ %}
4784 interface(REG_INTER);
4785 %}
4786
4787 // Pointer 64 bit Register R10 only
4788 operand iRegP_R10()
4789 %{
4790 constraint(ALLOC_IN_RC(r10_reg));
4791 match(RegP);
4792 // match(iRegP);
4793 match(iRegPNoSp);
4794 op_cost(0);
4795 format %{ %}
4796 interface(REG_INTER);
4797 %}
4798
4799 // Long 64 bit Register R0 only
4800 operand iRegL_R0()
4801 %{
4802 constraint(ALLOC_IN_RC(r0_reg));
4803 match(RegL);
4804 match(iRegLNoSp);
4805 op_cost(0);
4806 format %{ %}
4807 interface(REG_INTER);
4808 %}
4809
4810 // Long 64 bit Register R11 only
4811 operand iRegL_R11()
4812 %{
4813 constraint(ALLOC_IN_RC(r11_reg));
4814 match(RegL);
4815 match(iRegLNoSp);
4816 op_cost(0);
4817 format %{ %}
4818 interface(REG_INTER);
4819 %}
4820
4821 // Register R0 only
4822 operand iRegI_R0()
4823 %{
4824 constraint(ALLOC_IN_RC(int_r0_reg));
4825 match(RegI);
4826 match(iRegINoSp);
4827 op_cost(0);
4828 format %{ %}
4829 interface(REG_INTER);
4830 %}
4831
4832 // Register R2 only
4833 operand iRegI_R2()
4834 %{
4835 constraint(ALLOC_IN_RC(int_r2_reg));
4836 match(RegI);
4837 match(iRegINoSp);
4838 op_cost(0);
4839 format %{ %}
4840 interface(REG_INTER);
4841 %}
4842
4843 // Register R3 only
4844 operand iRegI_R3()
4845 %{
4846 constraint(ALLOC_IN_RC(int_r3_reg));
4847 match(RegI);
4848 match(iRegINoSp);
4849 op_cost(0);
4850 format %{ %}
4851 interface(REG_INTER);
4852 %}
4853
4854
4855 // Register R4 only
4856 operand iRegI_R4()
4857 %{
4858 constraint(ALLOC_IN_RC(int_r4_reg));
4859 match(RegI);
4860 match(iRegINoSp);
4861 op_cost(0);
4862 format %{ %}
4863 interface(REG_INTER);
4864 %}
4865
4866
4867 // Pointer Register Operands
4868 // Narrow Pointer Register
4869 operand iRegN()
4870 %{
4871 constraint(ALLOC_IN_RC(any_reg32));
4872 match(RegN);
4873 match(iRegNNoSp);
4874 op_cost(0);
4875 format %{ %}
4876 interface(REG_INTER);
4877 %}
4878
4879 // Integer 64 bit Register not Special
4880 operand iRegNNoSp()
4881 %{
4882 constraint(ALLOC_IN_RC(no_special_reg32));
4883 match(RegN);
4884 op_cost(0);
4885 format %{ %}
4886 interface(REG_INTER);
4887 %}
4888
4889 // Float Register
4890 // Float register operands
4891 operand vRegF()
4892 %{
4893 constraint(ALLOC_IN_RC(float_reg));
4894 match(RegF);
4895
4896 op_cost(0);
4897 format %{ %}
4898 interface(REG_INTER);
4899 %}
4900
4901 // Double Register
4902 // Double register operands
4903 operand vRegD()
4904 %{
4905 constraint(ALLOC_IN_RC(double_reg));
4906 match(RegD);
4907
4908 op_cost(0);
4909 format %{ %}
4910 interface(REG_INTER);
4911 %}
4912
4913 // Generic vector class. This will be used for
4914 // all vector operands, including NEON and SVE.
4915 operand vReg()
4916 %{
4917 constraint(ALLOC_IN_RC(dynamic));
4918 match(VecA);
4919 match(VecD);
4920 match(VecX);
4921
4922 op_cost(0);
4923 format %{ %}
4924 interface(REG_INTER);
4925 %}
4926
4927 operand vecA()
4928 %{
4929 constraint(ALLOC_IN_RC(vectora_reg));
4930 match(VecA);
4931
4932 op_cost(0);
4933 format %{ %}
4934 interface(REG_INTER);
4935 %}
4936
4937 operand vecD()
4938 %{
4939 constraint(ALLOC_IN_RC(vectord_reg));
4940 match(VecD);
4941
4942 op_cost(0);
4943 format %{ %}
4944 interface(REG_INTER);
4945 %}
4946
4947 operand vecX()
4948 %{
4949 constraint(ALLOC_IN_RC(vectorx_reg));
4950 match(VecX);
4951
4952 op_cost(0);
4953 format %{ %}
4954 interface(REG_INTER);
4955 %}
4956
4957 operand vRegD_V0()
4958 %{
4959 constraint(ALLOC_IN_RC(v0_reg));
4960 match(RegD);
4961 op_cost(0);
4962 format %{ %}
4963 interface(REG_INTER);
4964 %}
4965
4966 operand vRegD_V1()
4967 %{
4968 constraint(ALLOC_IN_RC(v1_reg));
4969 match(RegD);
4970 op_cost(0);
4971 format %{ %}
4972 interface(REG_INTER);
4973 %}
4974
4975 operand vRegD_V2()
4976 %{
4977 constraint(ALLOC_IN_RC(v2_reg));
4978 match(RegD);
4979 op_cost(0);
4980 format %{ %}
4981 interface(REG_INTER);
4982 %}
4983
4984 operand vRegD_V3()
4985 %{
4986 constraint(ALLOC_IN_RC(v3_reg));
4987 match(RegD);
4988 op_cost(0);
4989 format %{ %}
4990 interface(REG_INTER);
4991 %}
4992
4993 operand vRegD_V4()
4994 %{
4995 constraint(ALLOC_IN_RC(v4_reg));
4996 match(RegD);
4997 op_cost(0);
4998 format %{ %}
4999 interface(REG_INTER);
5000 %}
5001
5002 operand vRegD_V5()
5003 %{
5004 constraint(ALLOC_IN_RC(v5_reg));
5005 match(RegD);
5006 op_cost(0);
5007 format %{ %}
5008 interface(REG_INTER);
5009 %}
5010
5011 operand vRegD_V6()
5012 %{
5013 constraint(ALLOC_IN_RC(v6_reg));
5014 match(RegD);
5015 op_cost(0);
5016 format %{ %}
5017 interface(REG_INTER);
5018 %}
5019
5020 operand vRegD_V7()
5021 %{
5022 constraint(ALLOC_IN_RC(v7_reg));
5023 match(RegD);
5024 op_cost(0);
5025 format %{ %}
5026 interface(REG_INTER);
5027 %}
5028
5029 operand pReg()
5030 %{
5031 constraint(ALLOC_IN_RC(pr_reg));
5032 match(RegVectMask);
5033 match(pRegGov);
5034 op_cost(0);
5035 format %{ %}
5036 interface(REG_INTER);
5037 %}
5038
5039 operand pRegGov()
5040 %{
5041 constraint(ALLOC_IN_RC(gov_pr));
5042 match(RegVectMask);
5043 match(pReg);
5044 op_cost(0);
5045 format %{ %}
5046 interface(REG_INTER);
5047 %}
5048
5049 operand pRegGov_P0()
5050 %{
5051 constraint(ALLOC_IN_RC(p0_reg));
5052 match(RegVectMask);
5053 op_cost(0);
5054 format %{ %}
5055 interface(REG_INTER);
5056 %}
5057
5058 operand pRegGov_P1()
5059 %{
5060 constraint(ALLOC_IN_RC(p1_reg));
5061 match(RegVectMask);
5062 op_cost(0);
5063 format %{ %}
5064 interface(REG_INTER);
5065 %}
5066
5067 // Flags register, used as output of signed compare instructions
5068
5069 // note that on AArch64 we also use this register as the output for
5070 // for floating point compare instructions (CmpF CmpD). this ensures
5071 // that ordered inequality tests use GT, GE, LT or LE none of which
5072 // pass through cases where the result is unordered i.e. one or both
5073 // inputs to the compare is a NaN. this means that the ideal code can
5074 // replace e.g. a GT with an LE and not end up capturing the NaN case
5075 // (where the comparison should always fail). EQ and NE tests are
5076 // always generated in ideal code so that unordered folds into the NE
5077 // case, matching the behaviour of AArch64 NE.
5078 //
5079 // This differs from x86 where the outputs of FP compares use a
5080 // special FP flags registers and where compares based on this
5081 // register are distinguished into ordered inequalities (cmpOpUCF) and
5082 // EQ/NEQ tests (cmpOpUCF2). x86 has to special case the latter tests
5083 // to explicitly handle the unordered case in branches. x86 also has
5084 // to include extra CMoveX rules to accept a cmpOpUCF input.
5085
5086 operand rFlagsReg()
5087 %{
5088 constraint(ALLOC_IN_RC(int_flags));
5089 match(RegFlags);
5090
5091 op_cost(0);
5092 format %{ "RFLAGS" %}
5093 interface(REG_INTER);
5094 %}
5095
5096 // Flags register, used as output of unsigned compare instructions
5097 operand rFlagsRegU()
5098 %{
5099 constraint(ALLOC_IN_RC(int_flags));
5100 match(RegFlags);
5101
5102 op_cost(0);
5103 format %{ "RFLAGSU" %}
5104 interface(REG_INTER);
5105 %}
5106
5107 // Special Registers
5108
5109 // Method Register
5110 operand inline_cache_RegP(iRegP reg)
5111 %{
5112 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
5113 match(reg);
5114 match(iRegPNoSp);
5115 op_cost(0);
5116 format %{ %}
5117 interface(REG_INTER);
5118 %}
5119
5120 // Thread Register
5121 operand thread_RegP(iRegP reg)
5122 %{
5123 constraint(ALLOC_IN_RC(thread_reg)); // link_reg
5124 match(reg);
5125 op_cost(0);
5126 format %{ %}
5127 interface(REG_INTER);
5128 %}
5129
5130 //----------Memory Operands----------------------------------------------------
5131
5132 operand indirect(iRegP reg)
5133 %{
5134 constraint(ALLOC_IN_RC(ptr_reg));
5135 match(reg);
5136 op_cost(0);
5137 format %{ "[$reg]" %}
5138 interface(MEMORY_INTER) %{
5139 base($reg);
5140 index(0xffffffff);
5141 scale(0x0);
5142 disp(0x0);
5143 %}
5144 %}
5145
5146 operand indIndexScaledI2L(iRegP reg, iRegI ireg, immIScale scale)
5147 %{
5148 constraint(ALLOC_IN_RC(ptr_reg));
5149 predicate(size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5150 match(AddP reg (LShiftL (ConvI2L ireg) scale));
5151 op_cost(0);
5152 format %{ "$reg, $ireg sxtw($scale), 0, I2L" %}
5153 interface(MEMORY_INTER) %{
5154 base($reg);
5155 index($ireg);
5156 scale($scale);
5157 disp(0x0);
5158 %}
5159 %}
5160
5161 operand indIndexScaled(iRegP reg, iRegL lreg, immIScale scale)
5162 %{
5163 constraint(ALLOC_IN_RC(ptr_reg));
5164 predicate(size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5165 match(AddP reg (LShiftL lreg scale));
5166 op_cost(0);
5167 format %{ "$reg, $lreg lsl($scale)" %}
5168 interface(MEMORY_INTER) %{
5169 base($reg);
5170 index($lreg);
5171 scale($scale);
5172 disp(0x0);
5173 %}
5174 %}
5175
5176 operand indIndexI2L(iRegP reg, iRegI ireg)
5177 %{
5178 constraint(ALLOC_IN_RC(ptr_reg));
5179 match(AddP reg (ConvI2L ireg));
5180 op_cost(0);
5181 format %{ "$reg, $ireg, 0, I2L" %}
5182 interface(MEMORY_INTER) %{
5183 base($reg);
5184 index($ireg);
5185 scale(0x0);
5186 disp(0x0);
5187 %}
5188 %}
5189
5190 operand indIndex(iRegP reg, iRegL lreg)
5191 %{
5192 constraint(ALLOC_IN_RC(ptr_reg));
5193 match(AddP reg lreg);
5194 op_cost(0);
5195 format %{ "$reg, $lreg" %}
5196 interface(MEMORY_INTER) %{
5197 base($reg);
5198 index($lreg);
5199 scale(0x0);
5200 disp(0x0);
5201 %}
5202 %}
5203
5204 operand indOffI1(iRegP reg, immIOffset1 off)
5205 %{
5206 constraint(ALLOC_IN_RC(ptr_reg));
5207 match(AddP reg off);
5208 op_cost(0);
5209 format %{ "[$reg, $off]" %}
5210 interface(MEMORY_INTER) %{
5211 base($reg);
5212 index(0xffffffff);
5213 scale(0x0);
5214 disp($off);
5215 %}
5216 %}
5217
5218 operand indOffI2(iRegP reg, immIOffset2 off)
5219 %{
5220 constraint(ALLOC_IN_RC(ptr_reg));
5221 match(AddP reg off);
5222 op_cost(0);
5223 format %{ "[$reg, $off]" %}
5224 interface(MEMORY_INTER) %{
5225 base($reg);
5226 index(0xffffffff);
5227 scale(0x0);
5228 disp($off);
5229 %}
5230 %}
5231
5232 operand indOffI4(iRegP reg, immIOffset4 off)
5233 %{
5234 constraint(ALLOC_IN_RC(ptr_reg));
5235 match(AddP reg off);
5236 op_cost(0);
5237 format %{ "[$reg, $off]" %}
5238 interface(MEMORY_INTER) %{
5239 base($reg);
5240 index(0xffffffff);
5241 scale(0x0);
5242 disp($off);
5243 %}
5244 %}
5245
5246 operand indOffI8(iRegP reg, immIOffset8 off)
5247 %{
5248 constraint(ALLOC_IN_RC(ptr_reg));
5249 match(AddP reg off);
5250 op_cost(0);
5251 format %{ "[$reg, $off]" %}
5252 interface(MEMORY_INTER) %{
5253 base($reg);
5254 index(0xffffffff);
5255 scale(0x0);
5256 disp($off);
5257 %}
5258 %}
5259
5260 operand indOffI16(iRegP reg, immIOffset16 off)
5261 %{
5262 constraint(ALLOC_IN_RC(ptr_reg));
5263 match(AddP reg off);
5264 op_cost(0);
5265 format %{ "[$reg, $off]" %}
5266 interface(MEMORY_INTER) %{
5267 base($reg);
5268 index(0xffffffff);
5269 scale(0x0);
5270 disp($off);
5271 %}
5272 %}
5273
5274 operand indOffL1(iRegP reg, immLoffset1 off)
5275 %{
5276 constraint(ALLOC_IN_RC(ptr_reg));
5277 match(AddP reg off);
5278 op_cost(0);
5279 format %{ "[$reg, $off]" %}
5280 interface(MEMORY_INTER) %{
5281 base($reg);
5282 index(0xffffffff);
5283 scale(0x0);
5284 disp($off);
5285 %}
5286 %}
5287
5288 operand indOffL2(iRegP reg, immLoffset2 off)
5289 %{
5290 constraint(ALLOC_IN_RC(ptr_reg));
5291 match(AddP reg off);
5292 op_cost(0);
5293 format %{ "[$reg, $off]" %}
5294 interface(MEMORY_INTER) %{
5295 base($reg);
5296 index(0xffffffff);
5297 scale(0x0);
5298 disp($off);
5299 %}
5300 %}
5301
5302 operand indOffL4(iRegP reg, immLoffset4 off)
5303 %{
5304 constraint(ALLOC_IN_RC(ptr_reg));
5305 match(AddP reg off);
5306 op_cost(0);
5307 format %{ "[$reg, $off]" %}
5308 interface(MEMORY_INTER) %{
5309 base($reg);
5310 index(0xffffffff);
5311 scale(0x0);
5312 disp($off);
5313 %}
5314 %}
5315
5316 operand indOffL8(iRegP reg, immLoffset8 off)
5317 %{
5318 constraint(ALLOC_IN_RC(ptr_reg));
5319 match(AddP reg off);
5320 op_cost(0);
5321 format %{ "[$reg, $off]" %}
5322 interface(MEMORY_INTER) %{
5323 base($reg);
5324 index(0xffffffff);
5325 scale(0x0);
5326 disp($off);
5327 %}
5328 %}
5329
5330 operand indOffL16(iRegP reg, immLoffset16 off)
5331 %{
5332 constraint(ALLOC_IN_RC(ptr_reg));
5333 match(AddP reg off);
5334 op_cost(0);
5335 format %{ "[$reg, $off]" %}
5336 interface(MEMORY_INTER) %{
5337 base($reg);
5338 index(0xffffffff);
5339 scale(0x0);
5340 disp($off);
5341 %}
5342 %}
5343
5344 operand indirectN(iRegN reg)
5345 %{
5346 predicate(CompressedOops::shift() == 0);
5347 constraint(ALLOC_IN_RC(ptr_reg));
5348 match(DecodeN reg);
5349 op_cost(0);
5350 format %{ "[$reg]\t# narrow" %}
5351 interface(MEMORY_INTER) %{
5352 base($reg);
5353 index(0xffffffff);
5354 scale(0x0);
5355 disp(0x0);
5356 %}
5357 %}
5358
5359 operand indIndexScaledI2LN(iRegN reg, iRegI ireg, immIScale scale)
5360 %{
5361 predicate(CompressedOops::shift() == 0 && size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5362 constraint(ALLOC_IN_RC(ptr_reg));
5363 match(AddP (DecodeN reg) (LShiftL (ConvI2L ireg) scale));
5364 op_cost(0);
5365 format %{ "$reg, $ireg sxtw($scale), 0, I2L\t# narrow" %}
5366 interface(MEMORY_INTER) %{
5367 base($reg);
5368 index($ireg);
5369 scale($scale);
5370 disp(0x0);
5371 %}
5372 %}
5373
5374 operand indIndexScaledN(iRegN reg, iRegL lreg, immIScale scale)
5375 %{
5376 predicate(CompressedOops::shift() == 0 && size_fits_all_mem_uses(n->as_AddP(), n->in(AddPNode::Offset)->in(2)->get_int()));
5377 constraint(ALLOC_IN_RC(ptr_reg));
5378 match(AddP (DecodeN reg) (LShiftL lreg scale));
5379 op_cost(0);
5380 format %{ "$reg, $lreg lsl($scale)\t# narrow" %}
5381 interface(MEMORY_INTER) %{
5382 base($reg);
5383 index($lreg);
5384 scale($scale);
5385 disp(0x0);
5386 %}
5387 %}
5388
5389 operand indIndexI2LN(iRegN reg, iRegI ireg)
5390 %{
5391 predicate(CompressedOops::shift() == 0);
5392 constraint(ALLOC_IN_RC(ptr_reg));
5393 match(AddP (DecodeN reg) (ConvI2L ireg));
5394 op_cost(0);
5395 format %{ "$reg, $ireg, 0, I2L\t# narrow" %}
5396 interface(MEMORY_INTER) %{
5397 base($reg);
5398 index($ireg);
5399 scale(0x0);
5400 disp(0x0);
5401 %}
5402 %}
5403
5404 operand indIndexN(iRegN reg, iRegL lreg)
5405 %{
5406 predicate(CompressedOops::shift() == 0);
5407 constraint(ALLOC_IN_RC(ptr_reg));
5408 match(AddP (DecodeN reg) lreg);
5409 op_cost(0);
5410 format %{ "$reg, $lreg\t# narrow" %}
5411 interface(MEMORY_INTER) %{
5412 base($reg);
5413 index($lreg);
5414 scale(0x0);
5415 disp(0x0);
5416 %}
5417 %}
5418
5419 operand indOffIN(iRegN reg, immIOffset off)
5420 %{
5421 predicate(CompressedOops::shift() == 0);
5422 constraint(ALLOC_IN_RC(ptr_reg));
5423 match(AddP (DecodeN reg) off);
5424 op_cost(0);
5425 format %{ "[$reg, $off]\t# narrow" %}
5426 interface(MEMORY_INTER) %{
5427 base($reg);
5428 index(0xffffffff);
5429 scale(0x0);
5430 disp($off);
5431 %}
5432 %}
5433
5434 operand indOffLN(iRegN reg, immLoffset off)
5435 %{
5436 predicate(CompressedOops::shift() == 0);
5437 constraint(ALLOC_IN_RC(ptr_reg));
5438 match(AddP (DecodeN reg) off);
5439 op_cost(0);
5440 format %{ "[$reg, $off]\t# narrow" %}
5441 interface(MEMORY_INTER) %{
5442 base($reg);
5443 index(0xffffffff);
5444 scale(0x0);
5445 disp($off);
5446 %}
5447 %}
5448
5449
5450 //----------Special Memory Operands--------------------------------------------
5451 // Stack Slot Operand - This operand is used for loading and storing temporary
5452 // values on the stack where a match requires a value to
5453 // flow through memory.
5454 operand stackSlotP(sRegP reg)
5455 %{
5456 constraint(ALLOC_IN_RC(stack_slots));
5457 op_cost(100);
5458 // No match rule because this operand is only generated in matching
5459 // match(RegP);
5460 format %{ "[$reg]" %}
5461 interface(MEMORY_INTER) %{
5462 base(0x1e); // RSP
5463 index(0x0); // No Index
5464 scale(0x0); // No Scale
5465 disp($reg); // Stack Offset
5466 %}
5467 %}
5468
5469 operand stackSlotI(sRegI reg)
5470 %{
5471 constraint(ALLOC_IN_RC(stack_slots));
5472 // No match rule because this operand is only generated in matching
5473 // match(RegI);
5474 format %{ "[$reg]" %}
5475 interface(MEMORY_INTER) %{
5476 base(0x1e); // RSP
5477 index(0x0); // No Index
5478 scale(0x0); // No Scale
5479 disp($reg); // Stack Offset
5480 %}
5481 %}
5482
5483 operand stackSlotF(sRegF reg)
5484 %{
5485 constraint(ALLOC_IN_RC(stack_slots));
5486 // No match rule because this operand is only generated in matching
5487 // match(RegF);
5488 format %{ "[$reg]" %}
5489 interface(MEMORY_INTER) %{
5490 base(0x1e); // RSP
5491 index(0x0); // No Index
5492 scale(0x0); // No Scale
5493 disp($reg); // Stack Offset
5494 %}
5495 %}
5496
5497 operand stackSlotD(sRegD reg)
5498 %{
5499 constraint(ALLOC_IN_RC(stack_slots));
5500 // No match rule because this operand is only generated in matching
5501 // match(RegD);
5502 format %{ "[$reg]" %}
5503 interface(MEMORY_INTER) %{
5504 base(0x1e); // RSP
5505 index(0x0); // No Index
5506 scale(0x0); // No Scale
5507 disp($reg); // Stack Offset
5508 %}
5509 %}
5510
5511 operand stackSlotL(sRegL reg)
5512 %{
5513 constraint(ALLOC_IN_RC(stack_slots));
5514 // No match rule because this operand is only generated in matching
5515 // match(RegL);
5516 format %{ "[$reg]" %}
5517 interface(MEMORY_INTER) %{
5518 base(0x1e); // RSP
5519 index(0x0); // No Index
5520 scale(0x0); // No Scale
5521 disp($reg); // Stack Offset
5522 %}
5523 %}
5524
5525 // Operands for expressing Control Flow
5526 // NOTE: Label is a predefined operand which should not be redefined in
5527 // the AD file. It is generically handled within the ADLC.
5528
5529 //----------Conditional Branch Operands----------------------------------------
5530 // Comparison Op - This is the operation of the comparison, and is limited to
5531 // the following set of codes:
5532 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5533 //
5534 // Other attributes of the comparison, such as unsignedness, are specified
5535 // by the comparison instruction that sets a condition code flags register.
5536 // That result is represented by a flags operand whose subtype is appropriate
5537 // to the unsignedness (etc.) of the comparison.
5538 //
5539 // Later, the instruction which matches both the Comparison Op (a Bool) and
5540 // the flags (produced by the Cmp) specifies the coding of the comparison op
5541 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5542
5543 // used for signed integral comparisons and fp comparisons
5544
5545 operand cmpOp()
5546 %{
5547 match(Bool);
5548
5549 format %{ "" %}
5550 interface(COND_INTER) %{
5551 equal(0x0, "eq");
5552 not_equal(0x1, "ne");
5553 less(0xb, "lt");
5554 greater_equal(0xa, "ge");
5555 less_equal(0xd, "le");
5556 greater(0xc, "gt");
5557 overflow(0x6, "vs");
5558 no_overflow(0x7, "vc");
5559 %}
5560 %}
5561
5562 // used for unsigned integral comparisons
5563
5564 operand cmpOpU()
5565 %{
5566 match(Bool);
5567
5568 format %{ "" %}
5569 interface(COND_INTER) %{
5570 equal(0x0, "eq");
5571 not_equal(0x1, "ne");
5572 less(0x3, "lo");
5573 greater_equal(0x2, "hs");
5574 less_equal(0x9, "ls");
5575 greater(0x8, "hi");
5576 overflow(0x6, "vs");
5577 no_overflow(0x7, "vc");
5578 %}
5579 %}
5580
5581 // used for certain integral comparisons which can be
5582 // converted to cbxx or tbxx instructions
5583
5584 operand cmpOpEqNe()
5585 %{
5586 match(Bool);
5587 op_cost(0);
5588 predicate(n->as_Bool()->_test._test == BoolTest::ne
5589 || n->as_Bool()->_test._test == BoolTest::eq);
5590
5591 format %{ "" %}
5592 interface(COND_INTER) %{
5593 equal(0x0, "eq");
5594 not_equal(0x1, "ne");
5595 less(0xb, "lt");
5596 greater_equal(0xa, "ge");
5597 less_equal(0xd, "le");
5598 greater(0xc, "gt");
5599 overflow(0x6, "vs");
5600 no_overflow(0x7, "vc");
5601 %}
5602 %}
5603
5604 // used for certain integral comparisons which can be
5605 // converted to cbxx or tbxx instructions
5606
5607 operand cmpOpLtGe()
5608 %{
5609 match(Bool);
5610 op_cost(0);
5611
5612 predicate(n->as_Bool()->_test._test == BoolTest::lt
5613 || n->as_Bool()->_test._test == BoolTest::ge);
5614
5615 format %{ "" %}
5616 interface(COND_INTER) %{
5617 equal(0x0, "eq");
5618 not_equal(0x1, "ne");
5619 less(0xb, "lt");
5620 greater_equal(0xa, "ge");
5621 less_equal(0xd, "le");
5622 greater(0xc, "gt");
5623 overflow(0x6, "vs");
5624 no_overflow(0x7, "vc");
5625 %}
5626 %}
5627
5628 // used for certain unsigned integral comparisons which can be
5629 // converted to cbxx or tbxx instructions
5630
5631 operand cmpOpUEqNeLtGe()
5632 %{
5633 match(Bool);
5634 op_cost(0);
5635
5636 predicate(n->as_Bool()->_test._test == BoolTest::eq
5637 || n->as_Bool()->_test._test == BoolTest::ne
5638 || n->as_Bool()->_test._test == BoolTest::lt
5639 || n->as_Bool()->_test._test == BoolTest::ge);
5640
5641 format %{ "" %}
5642 interface(COND_INTER) %{
5643 equal(0x0, "eq");
5644 not_equal(0x1, "ne");
5645 less(0xb, "lt");
5646 greater_equal(0xa, "ge");
5647 less_equal(0xd, "le");
5648 greater(0xc, "gt");
5649 overflow(0x6, "vs");
5650 no_overflow(0x7, "vc");
5651 %}
5652 %}
5653
5654 // Special operand allowing long args to int ops to be truncated for free
5655
5656 operand iRegL2I(iRegL reg) %{
5657
5658 op_cost(0);
5659
5660 match(ConvL2I reg);
5661
5662 format %{ "l2i($reg)" %}
5663
5664 interface(REG_INTER)
5665 %}
5666
5667 opclass vmem2(indirect, indIndex, indOffI2, indOffL2);
5668 opclass vmem4(indirect, indIndex, indOffI4, indOffL4);
5669 opclass vmem8(indirect, indIndex, indOffI8, indOffL8);
5670 opclass vmem16(indirect, indIndex, indOffI16, indOffL16);
5671
5672 //----------OPERAND CLASSES----------------------------------------------------
5673 // Operand Classes are groups of operands that are used as to simplify
5674 // instruction definitions by not requiring the AD writer to specify
5675 // separate instructions for every form of operand when the
5676 // instruction accepts multiple operand types with the same basic
5677 // encoding and format. The classic case of this is memory operands.
5678
5679 // memory is used to define read/write location for load/store
5680 // instruction defs. we can turn a memory op into an Address
5681
5682 opclass memory1(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex, indOffI1, indOffL1,
5683 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN);
5684
5685 opclass memory2(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex, indOffI2, indOffL2,
5686 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN);
5687
5688 opclass memory4(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex, indOffI4, indOffL4,
5689 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN, indOffIN, indOffLN);
5690
5691 opclass memory8(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex, indOffI8, indOffL8,
5692 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN, indOffIN, indOffLN);
5693
5694 // All of the memory operands. For the pipeline description.
5695 opclass memory(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indIndex,
5696 indOffI1, indOffL1, indOffI2, indOffL2, indOffI4, indOffL4, indOffI8, indOffL8,
5697 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN, indOffIN, indOffLN);
5698
5699
5700 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
5701 // operations. it allows the src to be either an iRegI or a (ConvL2I
5702 // iRegL). in the latter case the l2i normally planted for a ConvL2I
5703 // can be elided because the 32-bit instruction will just employ the
5704 // lower 32 bits anyway.
5705 //
5706 // n.b. this does not elide all L2I conversions. if the truncated
5707 // value is consumed by more than one operation then the ConvL2I
5708 // cannot be bundled into the consuming nodes so an l2i gets planted
5709 // (actually a movw $dst $src) and the downstream instructions consume
5710 // the result of the l2i as an iRegI input. That's a shame since the
5711 // movw is actually redundant but its not too costly.
5712
5713 opclass iRegIorL2I(iRegI, iRegL2I);
5714
5715 //----------PIPELINE-----------------------------------------------------------
5716 // Rules which define the behavior of the target architectures pipeline.
5717
5718 // For specific pipelines, eg A53, define the stages of that pipeline
5719 //pipe_desc(ISS, EX1, EX2, WR);
5720 #define ISS S0
5721 #define EX1 S1
5722 #define EX2 S2
5723 #define WR S3
5724
5725 // Integer ALU reg operation
5726 pipeline %{
5727
5728 attributes %{
5729 // ARM instructions are of fixed length
5730 fixed_size_instructions; // Fixed size instructions TODO does
5731 max_instructions_per_bundle = 4; // A53 = 2, A57 = 4
5732 // ARM instructions come in 32-bit word units
5733 instruction_unit_size = 4; // An instruction is 4 bytes long
5734 instruction_fetch_unit_size = 64; // The processor fetches one line
5735 instruction_fetch_units = 1; // of 64 bytes
5736
5737 // List of nop instructions
5738 nops( MachNop );
5739 %}
5740
5741 // We don't use an actual pipeline model so don't care about resources
5742 // or description. we do use pipeline classes to introduce fixed
5743 // latencies
5744
5745 //----------RESOURCES----------------------------------------------------------
5746 // Resources are the functional units available to the machine
5747
5748 resources( INS0, INS1, INS01 = INS0 | INS1,
5749 ALU0, ALU1, ALU = ALU0 | ALU1,
5750 MAC,
5751 DIV,
5752 BRANCH,
5753 LDST,
5754 NEON_FP);
5755
5756 //----------PIPELINE DESCRIPTION-----------------------------------------------
5757 // Pipeline Description specifies the stages in the machine's pipeline
5758
5759 // Define the pipeline as a generic 6 stage pipeline
5760 pipe_desc(S0, S1, S2, S3, S4, S5);
5761
5762 //----------PIPELINE CLASSES---------------------------------------------------
5763 // Pipeline Classes describe the stages in which input and output are
5764 // referenced by the hardware pipeline.
5765
5766 pipe_class fp_dop_reg_reg_s(vRegF dst, vRegF src1, vRegF src2)
5767 %{
5768 single_instruction;
5769 src1 : S1(read);
5770 src2 : S2(read);
5771 dst : S5(write);
5772 INS01 : ISS;
5773 NEON_FP : S5;
5774 %}
5775
5776 pipe_class fp_dop_reg_reg_d(vRegD dst, vRegD src1, vRegD src2)
5777 %{
5778 single_instruction;
5779 src1 : S1(read);
5780 src2 : S2(read);
5781 dst : S5(write);
5782 INS01 : ISS;
5783 NEON_FP : S5;
5784 %}
5785
5786 pipe_class fp_uop_s(vRegF dst, vRegF src)
5787 %{
5788 single_instruction;
5789 src : S1(read);
5790 dst : S5(write);
5791 INS01 : ISS;
5792 NEON_FP : S5;
5793 %}
5794
5795 pipe_class fp_uop_d(vRegD dst, vRegD src)
5796 %{
5797 single_instruction;
5798 src : S1(read);
5799 dst : S5(write);
5800 INS01 : ISS;
5801 NEON_FP : S5;
5802 %}
5803
5804 pipe_class fp_d2f(vRegF dst, vRegD src)
5805 %{
5806 single_instruction;
5807 src : S1(read);
5808 dst : S5(write);
5809 INS01 : ISS;
5810 NEON_FP : S5;
5811 %}
5812
5813 pipe_class fp_f2d(vRegD dst, vRegF src)
5814 %{
5815 single_instruction;
5816 src : S1(read);
5817 dst : S5(write);
5818 INS01 : ISS;
5819 NEON_FP : S5;
5820 %}
5821
5822 pipe_class fp_f2i(iRegINoSp dst, vRegF src)
5823 %{
5824 single_instruction;
5825 src : S1(read);
5826 dst : S5(write);
5827 INS01 : ISS;
5828 NEON_FP : S5;
5829 %}
5830
5831 pipe_class fp_f2l(iRegLNoSp dst, vRegF src)
5832 %{
5833 single_instruction;
5834 src : S1(read);
5835 dst : S5(write);
5836 INS01 : ISS;
5837 NEON_FP : S5;
5838 %}
5839
5840 pipe_class fp_i2f(vRegF dst, iRegIorL2I src)
5841 %{
5842 single_instruction;
5843 src : S1(read);
5844 dst : S5(write);
5845 INS01 : ISS;
5846 NEON_FP : S5;
5847 %}
5848
5849 pipe_class fp_l2f(vRegF dst, iRegL src)
5850 %{
5851 single_instruction;
5852 src : S1(read);
5853 dst : S5(write);
5854 INS01 : ISS;
5855 NEON_FP : S5;
5856 %}
5857
5858 pipe_class fp_d2i(iRegINoSp dst, vRegD src)
5859 %{
5860 single_instruction;
5861 src : S1(read);
5862 dst : S5(write);
5863 INS01 : ISS;
5864 NEON_FP : S5;
5865 %}
5866
5867 pipe_class fp_d2l(iRegLNoSp dst, vRegD src)
5868 %{
5869 single_instruction;
5870 src : S1(read);
5871 dst : S5(write);
5872 INS01 : ISS;
5873 NEON_FP : S5;
5874 %}
5875
5876 pipe_class fp_i2d(vRegD dst, iRegIorL2I src)
5877 %{
5878 single_instruction;
5879 src : S1(read);
5880 dst : S5(write);
5881 INS01 : ISS;
5882 NEON_FP : S5;
5883 %}
5884
5885 pipe_class fp_l2d(vRegD dst, iRegIorL2I src)
5886 %{
5887 single_instruction;
5888 src : S1(read);
5889 dst : S5(write);
5890 INS01 : ISS;
5891 NEON_FP : S5;
5892 %}
5893
5894 pipe_class fp_div_s(vRegF dst, vRegF src1, vRegF src2)
5895 %{
5896 single_instruction;
5897 src1 : S1(read);
5898 src2 : S2(read);
5899 dst : S5(write);
5900 INS0 : ISS;
5901 NEON_FP : S5;
5902 %}
5903
5904 pipe_class fp_div_d(vRegD dst, vRegD src1, vRegD src2)
5905 %{
5906 single_instruction;
5907 src1 : S1(read);
5908 src2 : S2(read);
5909 dst : S5(write);
5910 INS0 : ISS;
5911 NEON_FP : S5;
5912 %}
5913
5914 pipe_class fp_cond_reg_reg_s(vRegF dst, vRegF src1, vRegF src2, rFlagsReg cr)
5915 %{
5916 single_instruction;
5917 cr : S1(read);
5918 src1 : S1(read);
5919 src2 : S1(read);
5920 dst : S3(write);
5921 INS01 : ISS;
5922 NEON_FP : S3;
5923 %}
5924
5925 pipe_class fp_cond_reg_reg_d(vRegD dst, vRegD src1, vRegD src2, rFlagsReg cr)
5926 %{
5927 single_instruction;
5928 cr : S1(read);
5929 src1 : S1(read);
5930 src2 : S1(read);
5931 dst : S3(write);
5932 INS01 : ISS;
5933 NEON_FP : S3;
5934 %}
5935
5936 pipe_class fp_imm_s(vRegF dst)
5937 %{
5938 single_instruction;
5939 dst : S3(write);
5940 INS01 : ISS;
5941 NEON_FP : S3;
5942 %}
5943
5944 pipe_class fp_imm_d(vRegD dst)
5945 %{
5946 single_instruction;
5947 dst : S3(write);
5948 INS01 : ISS;
5949 NEON_FP : S3;
5950 %}
5951
5952 pipe_class fp_load_constant_s(vRegF dst)
5953 %{
5954 single_instruction;
5955 dst : S4(write);
5956 INS01 : ISS;
5957 NEON_FP : S4;
5958 %}
5959
5960 pipe_class fp_load_constant_d(vRegD dst)
5961 %{
5962 single_instruction;
5963 dst : S4(write);
5964 INS01 : ISS;
5965 NEON_FP : S4;
5966 %}
5967
5968 //------- Integer ALU operations --------------------------
5969
5970 // Integer ALU reg-reg operation
5971 // Operands needed in EX1, result generated in EX2
5972 // Eg. ADD x0, x1, x2
5973 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
5974 %{
5975 single_instruction;
5976 dst : EX2(write);
5977 src1 : EX1(read);
5978 src2 : EX1(read);
5979 INS01 : ISS; // Dual issue as instruction 0 or 1
5980 ALU : EX2;
5981 %}
5982
5983 // Integer ALU reg-reg operation with constant shift
5984 // Shifted register must be available in LATE_ISS instead of EX1
5985 // Eg. ADD x0, x1, x2, LSL #2
5986 pipe_class ialu_reg_reg_shift(iRegI dst, iRegI src1, iRegI src2, immI shift)
5987 %{
5988 single_instruction;
5989 dst : EX2(write);
5990 src1 : EX1(read);
5991 src2 : ISS(read);
5992 INS01 : ISS;
5993 ALU : EX2;
5994 %}
5995
5996 // Integer ALU reg operation with constant shift
5997 // Eg. LSL x0, x1, #shift
5998 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
5999 %{
6000 single_instruction;
6001 dst : EX2(write);
6002 src1 : ISS(read);
6003 INS01 : ISS;
6004 ALU : EX2;
6005 %}
6006
6007 // Integer ALU reg-reg operation with variable shift
6008 // Both operands must be available in LATE_ISS instead of EX1
6009 // Result is available in EX1 instead of EX2
6010 // Eg. LSLV x0, x1, x2
6011 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
6012 %{
6013 single_instruction;
6014 dst : EX1(write);
6015 src1 : ISS(read);
6016 src2 : ISS(read);
6017 INS01 : ISS;
6018 ALU : EX1;
6019 %}
6020
6021 // Integer ALU reg-reg operation with extract
6022 // As for _vshift above, but result generated in EX2
6023 // Eg. EXTR x0, x1, x2, #N
6024 pipe_class ialu_reg_reg_extr(iRegI dst, iRegI src1, iRegI src2)
6025 %{
6026 single_instruction;
6027 dst : EX2(write);
6028 src1 : ISS(read);
6029 src2 : ISS(read);
6030 INS1 : ISS; // Can only dual issue as Instruction 1
6031 ALU : EX1;
6032 %}
6033
6034 // Integer ALU reg operation
6035 // Eg. NEG x0, x1
6036 pipe_class ialu_reg(iRegI dst, iRegI src)
6037 %{
6038 single_instruction;
6039 dst : EX2(write);
6040 src : EX1(read);
6041 INS01 : ISS;
6042 ALU : EX2;
6043 %}
6044
6045 // Integer ALU reg mmediate operation
6046 // Eg. ADD x0, x1, #N
6047 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
6048 %{
6049 single_instruction;
6050 dst : EX2(write);
6051 src1 : EX1(read);
6052 INS01 : ISS;
6053 ALU : EX2;
6054 %}
6055
6056 // Integer ALU immediate operation (no source operands)
6057 // Eg. MOV x0, #N
6058 pipe_class ialu_imm(iRegI dst)
6059 %{
6060 single_instruction;
6061 dst : EX1(write);
6062 INS01 : ISS;
6063 ALU : EX1;
6064 %}
6065
6066 //------- Compare operation -------------------------------
6067
6068 // Compare reg-reg
6069 // Eg. CMP x0, x1
6070 pipe_class icmp_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
6071 %{
6072 single_instruction;
6073 // fixed_latency(16);
6074 cr : EX2(write);
6075 op1 : EX1(read);
6076 op2 : EX1(read);
6077 INS01 : ISS;
6078 ALU : EX2;
6079 %}
6080
6081 // Compare reg-reg
6082 // Eg. CMP x0, #N
6083 pipe_class icmp_reg_imm(rFlagsReg cr, iRegI op1)
6084 %{
6085 single_instruction;
6086 // fixed_latency(16);
6087 cr : EX2(write);
6088 op1 : EX1(read);
6089 INS01 : ISS;
6090 ALU : EX2;
6091 %}
6092
6093 //------- Conditional instructions ------------------------
6094
6095 // Conditional no operands
6096 // Eg. CSINC x0, zr, zr, <cond>
6097 pipe_class icond_none(iRegI dst, rFlagsReg cr)
6098 %{
6099 single_instruction;
6100 cr : EX1(read);
6101 dst : EX2(write);
6102 INS01 : ISS;
6103 ALU : EX2;
6104 %}
6105
6106 // Conditional 2 operand
6107 // EG. CSEL X0, X1, X2, <cond>
6108 pipe_class icond_reg_reg(iRegI dst, iRegI src1, iRegI src2, rFlagsReg cr)
6109 %{
6110 single_instruction;
6111 cr : EX1(read);
6112 src1 : EX1(read);
6113 src2 : EX1(read);
6114 dst : EX2(write);
6115 INS01 : ISS;
6116 ALU : EX2;
6117 %}
6118
6119 // Conditional 2 operand
6120 // EG. CSEL X0, X1, X2, <cond>
6121 pipe_class icond_reg(iRegI dst, iRegI src, rFlagsReg cr)
6122 %{
6123 single_instruction;
6124 cr : EX1(read);
6125 src : EX1(read);
6126 dst : EX2(write);
6127 INS01 : ISS;
6128 ALU : EX2;
6129 %}
6130
6131 //------- Multiply pipeline operations --------------------
6132
6133 // Multiply reg-reg
6134 // Eg. MUL w0, w1, w2
6135 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
6136 %{
6137 single_instruction;
6138 dst : WR(write);
6139 src1 : ISS(read);
6140 src2 : ISS(read);
6141 INS01 : ISS;
6142 MAC : WR;
6143 %}
6144
6145 // Multiply accumulate
6146 // Eg. MADD w0, w1, w2, w3
6147 pipe_class imac_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3)
6148 %{
6149 single_instruction;
6150 dst : WR(write);
6151 src1 : ISS(read);
6152 src2 : ISS(read);
6153 src3 : ISS(read);
6154 INS01 : ISS;
6155 MAC : WR;
6156 %}
6157
6158 // Eg. MUL w0, w1, w2
6159 pipe_class lmul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
6160 %{
6161 single_instruction;
6162 fixed_latency(3); // Maximum latency for 64 bit mul
6163 dst : WR(write);
6164 src1 : ISS(read);
6165 src2 : ISS(read);
6166 INS01 : ISS;
6167 MAC : WR;
6168 %}
6169
6170 // Multiply accumulate
6171 // Eg. MADD w0, w1, w2, w3
6172 pipe_class lmac_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI src3)
6173 %{
6174 single_instruction;
6175 fixed_latency(3); // Maximum latency for 64 bit mul
6176 dst : WR(write);
6177 src1 : ISS(read);
6178 src2 : ISS(read);
6179 src3 : ISS(read);
6180 INS01 : ISS;
6181 MAC : WR;
6182 %}
6183
6184 //------- Divide pipeline operations --------------------
6185
6186 // Eg. SDIV w0, w1, w2
6187 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
6188 %{
6189 single_instruction;
6190 fixed_latency(8); // Maximum latency for 32 bit divide
6191 dst : WR(write);
6192 src1 : ISS(read);
6193 src2 : ISS(read);
6194 INS0 : ISS; // Can only dual issue as instruction 0
6195 DIV : WR;
6196 %}
6197
6198 // Eg. SDIV x0, x1, x2
6199 pipe_class ldiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
6200 %{
6201 single_instruction;
6202 fixed_latency(16); // Maximum latency for 64 bit divide
6203 dst : WR(write);
6204 src1 : ISS(read);
6205 src2 : ISS(read);
6206 INS0 : ISS; // Can only dual issue as instruction 0
6207 DIV : WR;
6208 %}
6209
6210 //------- Load pipeline operations ------------------------
6211
6212 // Load - prefetch
6213 // Eg. PFRM <mem>
6214 pipe_class iload_prefetch(memory mem)
6215 %{
6216 single_instruction;
6217 mem : ISS(read);
6218 INS01 : ISS;
6219 LDST : WR;
6220 %}
6221
6222 // Load - reg, mem
6223 // Eg. LDR x0, <mem>
6224 pipe_class iload_reg_mem(iRegI dst, memory mem)
6225 %{
6226 single_instruction;
6227 dst : WR(write);
6228 mem : ISS(read);
6229 INS01 : ISS;
6230 LDST : WR;
6231 %}
6232
6233 // Load - reg, reg
6234 // Eg. LDR x0, [sp, x1]
6235 pipe_class iload_reg_reg(iRegI dst, iRegI src)
6236 %{
6237 single_instruction;
6238 dst : WR(write);
6239 src : ISS(read);
6240 INS01 : ISS;
6241 LDST : WR;
6242 %}
6243
6244 //------- Store pipeline operations -----------------------
6245
6246 // Store - zr, mem
6247 // Eg. STR zr, <mem>
6248 pipe_class istore_mem(memory mem)
6249 %{
6250 single_instruction;
6251 mem : ISS(read);
6252 INS01 : ISS;
6253 LDST : WR;
6254 %}
6255
6256 // Store - reg, mem
6257 // Eg. STR x0, <mem>
6258 pipe_class istore_reg_mem(iRegI src, memory mem)
6259 %{
6260 single_instruction;
6261 mem : ISS(read);
6262 src : EX2(read);
6263 INS01 : ISS;
6264 LDST : WR;
6265 %}
6266
6267 // Store - reg, reg
6268 // Eg. STR x0, [sp, x1]
6269 pipe_class istore_reg_reg(iRegI dst, iRegI src)
6270 %{
6271 single_instruction;
6272 dst : ISS(read);
6273 src : EX2(read);
6274 INS01 : ISS;
6275 LDST : WR;
6276 %}
6277
6278 //------- Store pipeline operations -----------------------
6279
6280 // Branch
6281 pipe_class pipe_branch()
6282 %{
6283 single_instruction;
6284 INS01 : ISS;
6285 BRANCH : EX1;
6286 %}
6287
6288 // Conditional branch
6289 pipe_class pipe_branch_cond(rFlagsReg cr)
6290 %{
6291 single_instruction;
6292 cr : EX1(read);
6293 INS01 : ISS;
6294 BRANCH : EX1;
6295 %}
6296
6297 // Compare & Branch
6298 // EG. CBZ/CBNZ
6299 pipe_class pipe_cmp_branch(iRegI op1)
6300 %{
6301 single_instruction;
6302 op1 : EX1(read);
6303 INS01 : ISS;
6304 BRANCH : EX1;
6305 %}
6306
6307 //------- Synchronisation operations ----------------------
6308
6309 // Any operation requiring serialization.
6310 // EG. DMB/Atomic Ops/Load Acquire/Str Release
6311 pipe_class pipe_serial()
6312 %{
6313 single_instruction;
6314 force_serialization;
6315 fixed_latency(16);
6316 INS01 : ISS(2); // Cannot dual issue with any other instruction
6317 LDST : WR;
6318 %}
6319
6320 // Generic big/slow expanded idiom - also serialized
6321 pipe_class pipe_slow()
6322 %{
6323 instruction_count(10);
6324 multiple_bundles;
6325 force_serialization;
6326 fixed_latency(16);
6327 INS01 : ISS(2); // Cannot dual issue with any other instruction
6328 LDST : WR;
6329 %}
6330
6331 // Empty pipeline class
6332 pipe_class pipe_class_empty()
6333 %{
6334 single_instruction;
6335 fixed_latency(0);
6336 %}
6337
6338 // Default pipeline class.
6339 pipe_class pipe_class_default()
6340 %{
6341 single_instruction;
6342 fixed_latency(2);
6343 %}
6344
6345 // Pipeline class for compares.
6346 pipe_class pipe_class_compare()
6347 %{
6348 single_instruction;
6349 fixed_latency(16);
6350 %}
6351
6352 // Pipeline class for memory operations.
6353 pipe_class pipe_class_memory()
6354 %{
6355 single_instruction;
6356 fixed_latency(16);
6357 %}
6358
6359 // Pipeline class for call.
6360 pipe_class pipe_class_call()
6361 %{
6362 single_instruction;
6363 fixed_latency(100);
6364 %}
6365
6366 // Define the class for the Nop node.
6367 define %{
6368 MachNop = pipe_class_empty;
6369 %}
6370
6371 %}
6372 //----------INSTRUCTIONS-------------------------------------------------------
6373 //
6374 // match -- States which machine-independent subtree may be replaced
6375 // by this instruction.
6376 // ins_cost -- The estimated cost of this instruction is used by instruction
6377 // selection to identify a minimum cost tree of machine
6378 // instructions that matches a tree of machine-independent
6379 // instructions.
6380 // format -- A string providing the disassembly for this instruction.
6381 // The value of an instruction's operand may be inserted
6382 // by referring to it with a '$' prefix.
6383 // opcode -- Three instruction opcodes may be provided. These are referred
6384 // to within an encode class as $primary, $secondary, and $tertiary
6385 // rrspectively. The primary opcode is commonly used to
6386 // indicate the type of machine instruction, while secondary
6387 // and tertiary are often used for prefix options or addressing
6388 // modes.
6389 // ins_encode -- A list of encode classes with parameters. The encode class
6390 // name must have been defined in an 'enc_class' specification
6391 // in the encode section of the architecture description.
6392
6393 // ============================================================================
6394 // Memory (Load/Store) Instructions
6395
6396 // Load Instructions
6397
6398 // Load Byte (8 bit signed)
6399 instruct loadB(iRegINoSp dst, memory1 mem)
6400 %{
6401 match(Set dst (LoadB mem));
6402 predicate(!needs_acquiring_load(n));
6403
6404 ins_cost(4 * INSN_COST);
6405 format %{ "ldrsbw $dst, $mem\t# byte" %}
6406
6407 ins_encode(aarch64_enc_ldrsbw(dst, mem));
6408
6409 ins_pipe(iload_reg_mem);
6410 %}
6411
6412 // Load Byte (8 bit signed) into long
6413 instruct loadB2L(iRegLNoSp dst, memory1 mem)
6414 %{
6415 match(Set dst (ConvI2L (LoadB mem)));
6416 predicate(!needs_acquiring_load(n->in(1)));
6417
6418 ins_cost(4 * INSN_COST);
6419 format %{ "ldrsb $dst, $mem\t# byte" %}
6420
6421 ins_encode(aarch64_enc_ldrsb(dst, mem));
6422
6423 ins_pipe(iload_reg_mem);
6424 %}
6425
6426 // Load Byte (8 bit unsigned)
6427 instruct loadUB(iRegINoSp dst, memory1 mem)
6428 %{
6429 match(Set dst (LoadUB mem));
6430 predicate(!needs_acquiring_load(n));
6431
6432 ins_cost(4 * INSN_COST);
6433 format %{ "ldrbw $dst, $mem\t# byte" %}
6434
6435 ins_encode(aarch64_enc_ldrb(dst, mem));
6436
6437 ins_pipe(iload_reg_mem);
6438 %}
6439
6440 // Load Byte (8 bit unsigned) into long
6441 instruct loadUB2L(iRegLNoSp dst, memory1 mem)
6442 %{
6443 match(Set dst (ConvI2L (LoadUB mem)));
6444 predicate(!needs_acquiring_load(n->in(1)));
6445
6446 ins_cost(4 * INSN_COST);
6447 format %{ "ldrb $dst, $mem\t# byte" %}
6448
6449 ins_encode(aarch64_enc_ldrb(dst, mem));
6450
6451 ins_pipe(iload_reg_mem);
6452 %}
6453
6454 // Load Short (16 bit signed)
6455 instruct loadS(iRegINoSp dst, memory2 mem)
6456 %{
6457 match(Set dst (LoadS mem));
6458 predicate(!needs_acquiring_load(n));
6459
6460 ins_cost(4 * INSN_COST);
6461 format %{ "ldrshw $dst, $mem\t# short" %}
6462
6463 ins_encode(aarch64_enc_ldrshw(dst, mem));
6464
6465 ins_pipe(iload_reg_mem);
6466 %}
6467
6468 // Load Short (16 bit signed) into long
6469 instruct loadS2L(iRegLNoSp dst, memory2 mem)
6470 %{
6471 match(Set dst (ConvI2L (LoadS mem)));
6472 predicate(!needs_acquiring_load(n->in(1)));
6473
6474 ins_cost(4 * INSN_COST);
6475 format %{ "ldrsh $dst, $mem\t# short" %}
6476
6477 ins_encode(aarch64_enc_ldrsh(dst, mem));
6478
6479 ins_pipe(iload_reg_mem);
6480 %}
6481
6482 // Load Char (16 bit unsigned)
6483 instruct loadUS(iRegINoSp dst, memory2 mem)
6484 %{
6485 match(Set dst (LoadUS mem));
6486 predicate(!needs_acquiring_load(n));
6487
6488 ins_cost(4 * INSN_COST);
6489 format %{ "ldrh $dst, $mem\t# short" %}
6490
6491 ins_encode(aarch64_enc_ldrh(dst, mem));
6492
6493 ins_pipe(iload_reg_mem);
6494 %}
6495
6496 // Load Short/Char (16 bit unsigned) into long
6497 instruct loadUS2L(iRegLNoSp dst, memory2 mem)
6498 %{
6499 match(Set dst (ConvI2L (LoadUS mem)));
6500 predicate(!needs_acquiring_load(n->in(1)));
6501
6502 ins_cost(4 * INSN_COST);
6503 format %{ "ldrh $dst, $mem\t# short" %}
6504
6505 ins_encode(aarch64_enc_ldrh(dst, mem));
6506
6507 ins_pipe(iload_reg_mem);
6508 %}
6509
6510 // Load Integer (32 bit signed)
6511 instruct loadI(iRegINoSp dst, memory4 mem)
6512 %{
6513 match(Set dst (LoadI mem));
6514 predicate(!needs_acquiring_load(n));
6515
6516 ins_cost(4 * INSN_COST);
6517 format %{ "ldrw $dst, $mem\t# int" %}
6518
6519 ins_encode(aarch64_enc_ldrw(dst, mem));
6520
6521 ins_pipe(iload_reg_mem);
6522 %}
6523
6524 // Load Integer (32 bit signed) into long
6525 instruct loadI2L(iRegLNoSp dst, memory4 mem)
6526 %{
6527 match(Set dst (ConvI2L (LoadI mem)));
6528 predicate(!needs_acquiring_load(n->in(1)));
6529
6530 ins_cost(4 * INSN_COST);
6531 format %{ "ldrsw $dst, $mem\t# int" %}
6532
6533 ins_encode(aarch64_enc_ldrsw(dst, mem));
6534
6535 ins_pipe(iload_reg_mem);
6536 %}
6537
6538 // Load Integer (32 bit unsigned) into long
6539 instruct loadUI2L(iRegLNoSp dst, memory4 mem, immL_32bits mask)
6540 %{
6541 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6542 predicate(!needs_acquiring_load(n->in(1)->in(1)->as_Load()));
6543
6544 ins_cost(4 * INSN_COST);
6545 format %{ "ldrw $dst, $mem\t# int" %}
6546
6547 ins_encode(aarch64_enc_ldrw(dst, mem));
6548
6549 ins_pipe(iload_reg_mem);
6550 %}
6551
6552 // Load Long (64 bit signed)
6553 instruct loadL(iRegLNoSp dst, memory8 mem)
6554 %{
6555 match(Set dst (LoadL mem));
6556 predicate(!needs_acquiring_load(n));
6557
6558 ins_cost(4 * INSN_COST);
6559 format %{ "ldr $dst, $mem\t# int" %}
6560
6561 ins_encode(aarch64_enc_ldr(dst, mem));
6562
6563 ins_pipe(iload_reg_mem);
6564 %}
6565
6566 // Load Range
6567 instruct loadRange(iRegINoSp dst, memory4 mem)
6568 %{
6569 match(Set dst (LoadRange mem));
6570
6571 ins_cost(4 * INSN_COST);
6572 format %{ "ldrw $dst, $mem\t# range" %}
6573
6574 ins_encode(aarch64_enc_ldrw(dst, mem));
6575
6576 ins_pipe(iload_reg_mem);
6577 %}
6578
6579 // Load Pointer
6580 instruct loadP(iRegPNoSp dst, memory8 mem)
6581 %{
6582 match(Set dst (LoadP mem));
6583 predicate(!needs_acquiring_load(n) && (n->as_Load()->barrier_data() == 0));
6584
6585 ins_cost(4 * INSN_COST);
6586 format %{ "ldr $dst, $mem\t# ptr" %}
6587
6588 ins_encode(aarch64_enc_ldr(dst, mem));
6589
6590 ins_pipe(iload_reg_mem);
6591 %}
6592
6593 // Load Compressed Pointer
6594 instruct loadN(iRegNNoSp dst, memory4 mem)
6595 %{
6596 match(Set dst (LoadN mem));
6597 predicate(!needs_acquiring_load(n));
6598
6599 ins_cost(4 * INSN_COST);
6600 format %{ "ldrw $dst, $mem\t# compressed ptr" %}
6601
6602 ins_encode(aarch64_enc_ldrw(dst, mem));
6603
6604 ins_pipe(iload_reg_mem);
6605 %}
6606
6607 // Load Klass Pointer
6608 instruct loadKlass(iRegPNoSp dst, memory8 mem)
6609 %{
6610 match(Set dst (LoadKlass mem));
6611 predicate(!needs_acquiring_load(n));
6612
6613 ins_cost(4 * INSN_COST);
6614 format %{ "ldr $dst, $mem\t# class" %}
6615
6616 ins_encode(aarch64_enc_ldr(dst, mem));
6617
6618 ins_pipe(iload_reg_mem);
6619 %}
6620
6621 // Load Narrow Klass Pointer
6622 instruct loadNKlass(iRegNNoSp dst, memory4 mem)
6623 %{
6624 match(Set dst (LoadNKlass mem));
6625 predicate(!needs_acquiring_load(n));
6626
6627 ins_cost(4 * INSN_COST);
6628 format %{ "ldrw $dst, $mem\t# compressed class ptr" %}
6629
6630 ins_encode(aarch64_enc_ldrw(dst, mem));
6631
6632 ins_pipe(iload_reg_mem);
6633 %}
6634
6635 // Load Float
6636 instruct loadF(vRegF dst, memory4 mem)
6637 %{
6638 match(Set dst (LoadF mem));
6639 predicate(!needs_acquiring_load(n));
6640
6641 ins_cost(4 * INSN_COST);
6642 format %{ "ldrs $dst, $mem\t# float" %}
6643
6644 ins_encode( aarch64_enc_ldrs(dst, mem) );
6645
6646 ins_pipe(pipe_class_memory);
6647 %}
6648
6649 // Load Double
6650 instruct loadD(vRegD dst, memory8 mem)
6651 %{
6652 match(Set dst (LoadD mem));
6653 predicate(!needs_acquiring_load(n));
6654
6655 ins_cost(4 * INSN_COST);
6656 format %{ "ldrd $dst, $mem\t# double" %}
6657
6658 ins_encode( aarch64_enc_ldrd(dst, mem) );
6659
6660 ins_pipe(pipe_class_memory);
6661 %}
6662
6663
6664 // Load Int Constant
6665 instruct loadConI(iRegINoSp dst, immI src)
6666 %{
6667 match(Set dst src);
6668
6669 ins_cost(INSN_COST);
6670 format %{ "mov $dst, $src\t# int" %}
6671
6672 ins_encode( aarch64_enc_movw_imm(dst, src) );
6673
6674 ins_pipe(ialu_imm);
6675 %}
6676
6677 // Load Long Constant
6678 instruct loadConL(iRegLNoSp dst, immL src)
6679 %{
6680 match(Set dst src);
6681
6682 ins_cost(INSN_COST);
6683 format %{ "mov $dst, $src\t# long" %}
6684
6685 ins_encode( aarch64_enc_mov_imm(dst, src) );
6686
6687 ins_pipe(ialu_imm);
6688 %}
6689
6690 // Load Pointer Constant
6691
6692 instruct loadConP(iRegPNoSp dst, immP con)
6693 %{
6694 match(Set dst con);
6695
6696 ins_cost(INSN_COST * 4);
6697 format %{
6698 "mov $dst, $con\t# ptr\n\t"
6699 %}
6700
6701 ins_encode(aarch64_enc_mov_p(dst, con));
6702
6703 ins_pipe(ialu_imm);
6704 %}
6705
6706 // Load Null Pointer Constant
6707
6708 instruct loadConP0(iRegPNoSp dst, immP0 con)
6709 %{
6710 match(Set dst con);
6711
6712 ins_cost(INSN_COST);
6713 format %{ "mov $dst, $con\t# nullptr ptr" %}
6714
6715 ins_encode(aarch64_enc_mov_p0(dst, con));
6716
6717 ins_pipe(ialu_imm);
6718 %}
6719
6720 // Load Pointer Constant One
6721
6722 instruct loadConP1(iRegPNoSp dst, immP_1 con)
6723 %{
6724 match(Set dst con);
6725
6726 ins_cost(INSN_COST);
6727 format %{ "mov $dst, $con\t# nullptr ptr" %}
6728
6729 ins_encode(aarch64_enc_mov_p1(dst, con));
6730
6731 ins_pipe(ialu_imm);
6732 %}
6733
6734 // Load Byte Map Base Constant
6735
6736 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
6737 %{
6738 match(Set dst con);
6739
6740 ins_cost(INSN_COST);
6741 format %{ "adr $dst, $con\t# Byte Map Base" %}
6742
6743 ins_encode(aarch64_enc_mov_byte_map_base(dst, con));
6744
6745 ins_pipe(ialu_imm);
6746 %}
6747
6748 // Load Narrow Pointer Constant
6749
6750 instruct loadConN(iRegNNoSp dst, immN con)
6751 %{
6752 match(Set dst con);
6753
6754 ins_cost(INSN_COST * 4);
6755 format %{ "mov $dst, $con\t# compressed ptr" %}
6756
6757 ins_encode(aarch64_enc_mov_n(dst, con));
6758
6759 ins_pipe(ialu_imm);
6760 %}
6761
6762 // Load Narrow Null Pointer Constant
6763
6764 instruct loadConN0(iRegNNoSp dst, immN0 con)
6765 %{
6766 match(Set dst con);
6767
6768 ins_cost(INSN_COST);
6769 format %{ "mov $dst, $con\t# compressed nullptr ptr" %}
6770
6771 ins_encode(aarch64_enc_mov_n0(dst, con));
6772
6773 ins_pipe(ialu_imm);
6774 %}
6775
6776 // Load Narrow Klass Constant
6777
6778 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
6779 %{
6780 match(Set dst con);
6781
6782 ins_cost(INSN_COST);
6783 format %{ "mov $dst, $con\t# compressed klass ptr" %}
6784
6785 ins_encode(aarch64_enc_mov_nk(dst, con));
6786
6787 ins_pipe(ialu_imm);
6788 %}
6789
6790 // Load Packed Float Constant
6791
6792 instruct loadConF_packed(vRegF dst, immFPacked con) %{
6793 match(Set dst con);
6794 ins_cost(INSN_COST * 4);
6795 format %{ "fmovs $dst, $con"%}
6796 ins_encode %{
6797 __ fmovs(as_FloatRegister($dst$$reg), (double)$con$$constant);
6798 %}
6799
6800 ins_pipe(fp_imm_s);
6801 %}
6802
6803 // Load Float Constant
6804
6805 instruct loadConF(vRegF dst, immF con) %{
6806 match(Set dst con);
6807
6808 ins_cost(INSN_COST * 4);
6809
6810 format %{
6811 "ldrs $dst, [$constantaddress]\t# load from constant table: float=$con\n\t"
6812 %}
6813
6814 ins_encode %{
6815 __ ldrs(as_FloatRegister($dst$$reg), $constantaddress($con));
6816 %}
6817
6818 ins_pipe(fp_load_constant_s);
6819 %}
6820
6821 // Load Packed Double Constant
6822
6823 instruct loadConD_packed(vRegD dst, immDPacked con) %{
6824 match(Set dst con);
6825 ins_cost(INSN_COST);
6826 format %{ "fmovd $dst, $con"%}
6827 ins_encode %{
6828 __ fmovd(as_FloatRegister($dst$$reg), $con$$constant);
6829 %}
6830
6831 ins_pipe(fp_imm_d);
6832 %}
6833
6834 // Load Double Constant
6835
6836 instruct loadConD(vRegD dst, immD con) %{
6837 match(Set dst con);
6838
6839 ins_cost(INSN_COST * 5);
6840 format %{
6841 "ldrd $dst, [$constantaddress]\t# load from constant table: float=$con\n\t"
6842 %}
6843
6844 ins_encode %{
6845 __ ldrd(as_FloatRegister($dst$$reg), $constantaddress($con));
6846 %}
6847
6848 ins_pipe(fp_load_constant_d);
6849 %}
6850
6851 // Store Instructions
6852
6853 // Store CMS card-mark Immediate
6854 instruct storeimmCM0(immI0 zero, memory1 mem)
6855 %{
6856 match(Set mem (StoreCM mem zero));
6857
6858 ins_cost(INSN_COST);
6859 format %{ "storestore (elided)\n\t"
6860 "strb zr, $mem\t# byte" %}
6861
6862 ins_encode(aarch64_enc_strb0(mem));
6863
6864 ins_pipe(istore_mem);
6865 %}
6866
6867 // Store CMS card-mark Immediate with intervening StoreStore
6868 // needed when using CMS with no conditional card marking
6869 instruct storeimmCM0_ordered(immI0 zero, memory1 mem)
6870 %{
6871 match(Set mem (StoreCM mem zero));
6872
6873 ins_cost(INSN_COST * 2);
6874 format %{ "storestore\n\t"
6875 "dmb ishst"
6876 "\n\tstrb zr, $mem\t# byte" %}
6877
6878 ins_encode(aarch64_enc_strb0_ordered(mem));
6879
6880 ins_pipe(istore_mem);
6881 %}
6882
6883 // Store Byte
6884 instruct storeB(iRegIorL2I src, memory1 mem)
6885 %{
6886 match(Set mem (StoreB mem src));
6887 predicate(!needs_releasing_store(n));
6888
6889 ins_cost(INSN_COST);
6890 format %{ "strb $src, $mem\t# byte" %}
6891
6892 ins_encode(aarch64_enc_strb(src, mem));
6893
6894 ins_pipe(istore_reg_mem);
6895 %}
6896
6897
6898 instruct storeimmB0(immI0 zero, memory1 mem)
6899 %{
6900 match(Set mem (StoreB mem zero));
6901 predicate(!needs_releasing_store(n));
6902
6903 ins_cost(INSN_COST);
6904 format %{ "strb rscractch2, $mem\t# byte" %}
6905
6906 ins_encode(aarch64_enc_strb0(mem));
6907
6908 ins_pipe(istore_mem);
6909 %}
6910
6911 // Store Char/Short
6912 instruct storeC(iRegIorL2I src, memory2 mem)
6913 %{
6914 match(Set mem (StoreC mem src));
6915 predicate(!needs_releasing_store(n));
6916
6917 ins_cost(INSN_COST);
6918 format %{ "strh $src, $mem\t# short" %}
6919
6920 ins_encode(aarch64_enc_strh(src, mem));
6921
6922 ins_pipe(istore_reg_mem);
6923 %}
6924
6925 instruct storeimmC0(immI0 zero, memory2 mem)
6926 %{
6927 match(Set mem (StoreC mem zero));
6928 predicate(!needs_releasing_store(n));
6929
6930 ins_cost(INSN_COST);
6931 format %{ "strh zr, $mem\t# short" %}
6932
6933 ins_encode(aarch64_enc_strh0(mem));
6934
6935 ins_pipe(istore_mem);
6936 %}
6937
6938 // Store Integer
6939
6940 instruct storeI(iRegIorL2I src, memory4 mem)
6941 %{
6942 match(Set mem(StoreI mem src));
6943 predicate(!needs_releasing_store(n));
6944
6945 ins_cost(INSN_COST);
6946 format %{ "strw $src, $mem\t# int" %}
6947
6948 ins_encode(aarch64_enc_strw(src, mem));
6949
6950 ins_pipe(istore_reg_mem);
6951 %}
6952
6953 instruct storeimmI0(immI0 zero, memory4 mem)
6954 %{
6955 match(Set mem(StoreI mem zero));
6956 predicate(!needs_releasing_store(n));
6957
6958 ins_cost(INSN_COST);
6959 format %{ "strw zr, $mem\t# int" %}
6960
6961 ins_encode(aarch64_enc_strw0(mem));
6962
6963 ins_pipe(istore_mem);
6964 %}
6965
6966 // Store Long (64 bit signed)
6967 instruct storeL(iRegL src, memory8 mem)
6968 %{
6969 match(Set mem (StoreL mem src));
6970 predicate(!needs_releasing_store(n));
6971
6972 ins_cost(INSN_COST);
6973 format %{ "str $src, $mem\t# int" %}
6974
6975 ins_encode(aarch64_enc_str(src, mem));
6976
6977 ins_pipe(istore_reg_mem);
6978 %}
6979
6980 // Store Long (64 bit signed)
6981 instruct storeimmL0(immL0 zero, memory8 mem)
6982 %{
6983 match(Set mem (StoreL mem zero));
6984 predicate(!needs_releasing_store(n));
6985
6986 ins_cost(INSN_COST);
6987 format %{ "str zr, $mem\t# int" %}
6988
6989 ins_encode(aarch64_enc_str0(mem));
6990
6991 ins_pipe(istore_mem);
6992 %}
6993
6994 // Store Pointer
6995 instruct storeP(iRegP src, memory8 mem)
6996 %{
6997 match(Set mem (StoreP mem src));
6998 predicate(!needs_releasing_store(n) && n->as_Store()->barrier_data() == 0);
6999
7000 ins_cost(INSN_COST);
7001 format %{ "str $src, $mem\t# ptr" %}
7002
7003 ins_encode(aarch64_enc_str(src, mem));
7004
7005 ins_pipe(istore_reg_mem);
7006 %}
7007
7008 // Store Pointer
7009 instruct storeimmP0(immP0 zero, memory8 mem)
7010 %{
7011 match(Set mem (StoreP mem zero));
7012 predicate(!needs_releasing_store(n) && n->as_Store()->barrier_data() == 0);
7013
7014 ins_cost(INSN_COST);
7015 format %{ "str zr, $mem\t# ptr" %}
7016
7017 ins_encode(aarch64_enc_str0(mem));
7018
7019 ins_pipe(istore_mem);
7020 %}
7021
7022 // Store Compressed Pointer
7023 instruct storeN(iRegN src, memory4 mem)
7024 %{
7025 match(Set mem (StoreN mem src));
7026 predicate(!needs_releasing_store(n));
7027
7028 ins_cost(INSN_COST);
7029 format %{ "strw $src, $mem\t# compressed ptr" %}
7030
7031 ins_encode(aarch64_enc_strw(src, mem));
7032
7033 ins_pipe(istore_reg_mem);
7034 %}
7035
7036 instruct storeImmN0(immN0 zero, memory4 mem)
7037 %{
7038 match(Set mem (StoreN mem zero));
7039 predicate(!needs_releasing_store(n));
7040
7041 ins_cost(INSN_COST);
7042 format %{ "strw zr, $mem\t# compressed ptr" %}
7043
7044 ins_encode(aarch64_enc_strw0(mem));
7045
7046 ins_pipe(istore_mem);
7047 %}
7048
7049 // Store Float
7050 instruct storeF(vRegF src, memory4 mem)
7051 %{
7052 match(Set mem (StoreF mem src));
7053 predicate(!needs_releasing_store(n));
7054
7055 ins_cost(INSN_COST);
7056 format %{ "strs $src, $mem\t# float" %}
7057
7058 ins_encode( aarch64_enc_strs(src, mem) );
7059
7060 ins_pipe(pipe_class_memory);
7061 %}
7062
7063 // TODO
7064 // implement storeImmF0 and storeFImmPacked
7065
7066 // Store Double
7067 instruct storeD(vRegD src, memory8 mem)
7068 %{
7069 match(Set mem (StoreD mem src));
7070 predicate(!needs_releasing_store(n));
7071
7072 ins_cost(INSN_COST);
7073 format %{ "strd $src, $mem\t# double" %}
7074
7075 ins_encode( aarch64_enc_strd(src, mem) );
7076
7077 ins_pipe(pipe_class_memory);
7078 %}
7079
7080 // Store Compressed Klass Pointer
7081 instruct storeNKlass(iRegN src, memory4 mem)
7082 %{
7083 predicate(!needs_releasing_store(n));
7084 match(Set mem (StoreNKlass mem src));
7085
7086 ins_cost(INSN_COST);
7087 format %{ "strw $src, $mem\t# compressed klass ptr" %}
7088
7089 ins_encode(aarch64_enc_strw(src, mem));
7090
7091 ins_pipe(istore_reg_mem);
7092 %}
7093
7094 // TODO
7095 // implement storeImmD0 and storeDImmPacked
7096
7097 // prefetch instructions
7098 // Must be safe to execute with invalid address (cannot fault).
7099
7100 instruct prefetchalloc( memory8 mem ) %{
7101 match(PrefetchAllocation mem);
7102
7103 ins_cost(INSN_COST);
7104 format %{ "prfm $mem, PSTL1KEEP\t# Prefetch into level 1 cache write keep" %}
7105
7106 ins_encode( aarch64_enc_prefetchw(mem) );
7107
7108 ins_pipe(iload_prefetch);
7109 %}
7110
7111 // ---------------- volatile loads and stores ----------------
7112
7113 // Load Byte (8 bit signed)
7114 instruct loadB_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
7115 %{
7116 match(Set dst (LoadB mem));
7117
7118 ins_cost(VOLATILE_REF_COST);
7119 format %{ "ldarsb $dst, $mem\t# byte" %}
7120
7121 ins_encode(aarch64_enc_ldarsb(dst, mem));
7122
7123 ins_pipe(pipe_serial);
7124 %}
7125
7126 // Load Byte (8 bit signed) into long
7127 instruct loadB2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
7128 %{
7129 match(Set dst (ConvI2L (LoadB mem)));
7130
7131 ins_cost(VOLATILE_REF_COST);
7132 format %{ "ldarsb $dst, $mem\t# byte" %}
7133
7134 ins_encode(aarch64_enc_ldarsb(dst, mem));
7135
7136 ins_pipe(pipe_serial);
7137 %}
7138
7139 // Load Byte (8 bit unsigned)
7140 instruct loadUB_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
7141 %{
7142 match(Set dst (LoadUB mem));
7143
7144 ins_cost(VOLATILE_REF_COST);
7145 format %{ "ldarb $dst, $mem\t# byte" %}
7146
7147 ins_encode(aarch64_enc_ldarb(dst, mem));
7148
7149 ins_pipe(pipe_serial);
7150 %}
7151
7152 // Load Byte (8 bit unsigned) into long
7153 instruct loadUB2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
7154 %{
7155 match(Set dst (ConvI2L (LoadUB mem)));
7156
7157 ins_cost(VOLATILE_REF_COST);
7158 format %{ "ldarb $dst, $mem\t# byte" %}
7159
7160 ins_encode(aarch64_enc_ldarb(dst, mem));
7161
7162 ins_pipe(pipe_serial);
7163 %}
7164
7165 // Load Short (16 bit signed)
7166 instruct loadS_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
7167 %{
7168 match(Set dst (LoadS mem));
7169
7170 ins_cost(VOLATILE_REF_COST);
7171 format %{ "ldarshw $dst, $mem\t# short" %}
7172
7173 ins_encode(aarch64_enc_ldarshw(dst, mem));
7174
7175 ins_pipe(pipe_serial);
7176 %}
7177
7178 instruct loadUS_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
7179 %{
7180 match(Set dst (LoadUS mem));
7181
7182 ins_cost(VOLATILE_REF_COST);
7183 format %{ "ldarhw $dst, $mem\t# short" %}
7184
7185 ins_encode(aarch64_enc_ldarhw(dst, mem));
7186
7187 ins_pipe(pipe_serial);
7188 %}
7189
7190 // Load Short/Char (16 bit unsigned) into long
7191 instruct loadUS2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
7192 %{
7193 match(Set dst (ConvI2L (LoadUS mem)));
7194
7195 ins_cost(VOLATILE_REF_COST);
7196 format %{ "ldarh $dst, $mem\t# short" %}
7197
7198 ins_encode(aarch64_enc_ldarh(dst, mem));
7199
7200 ins_pipe(pipe_serial);
7201 %}
7202
7203 // Load Short/Char (16 bit signed) into long
7204 instruct loadS2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
7205 %{
7206 match(Set dst (ConvI2L (LoadS mem)));
7207
7208 ins_cost(VOLATILE_REF_COST);
7209 format %{ "ldarh $dst, $mem\t# short" %}
7210
7211 ins_encode(aarch64_enc_ldarsh(dst, mem));
7212
7213 ins_pipe(pipe_serial);
7214 %}
7215
7216 // Load Integer (32 bit signed)
7217 instruct loadI_volatile(iRegINoSp dst, /* sync_memory*/indirect mem)
7218 %{
7219 match(Set dst (LoadI mem));
7220
7221 ins_cost(VOLATILE_REF_COST);
7222 format %{ "ldarw $dst, $mem\t# int" %}
7223
7224 ins_encode(aarch64_enc_ldarw(dst, mem));
7225
7226 ins_pipe(pipe_serial);
7227 %}
7228
7229 // Load Integer (32 bit unsigned) into long
7230 instruct loadUI2L_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem, immL_32bits mask)
7231 %{
7232 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
7233
7234 ins_cost(VOLATILE_REF_COST);
7235 format %{ "ldarw $dst, $mem\t# int" %}
7236
7237 ins_encode(aarch64_enc_ldarw(dst, mem));
7238
7239 ins_pipe(pipe_serial);
7240 %}
7241
7242 // Load Long (64 bit signed)
7243 instruct loadL_volatile(iRegLNoSp dst, /* sync_memory*/indirect mem)
7244 %{
7245 match(Set dst (LoadL mem));
7246
7247 ins_cost(VOLATILE_REF_COST);
7248 format %{ "ldar $dst, $mem\t# int" %}
7249
7250 ins_encode(aarch64_enc_ldar(dst, mem));
7251
7252 ins_pipe(pipe_serial);
7253 %}
7254
7255 // Load Pointer
7256 instruct loadP_volatile(iRegPNoSp dst, /* sync_memory*/indirect mem)
7257 %{
7258 match(Set dst (LoadP mem));
7259 predicate(n->as_Load()->barrier_data() == 0);
7260
7261 ins_cost(VOLATILE_REF_COST);
7262 format %{ "ldar $dst, $mem\t# ptr" %}
7263
7264 ins_encode(aarch64_enc_ldar(dst, mem));
7265
7266 ins_pipe(pipe_serial);
7267 %}
7268
7269 // Load Compressed Pointer
7270 instruct loadN_volatile(iRegNNoSp dst, /* sync_memory*/indirect mem)
7271 %{
7272 match(Set dst (LoadN mem));
7273
7274 ins_cost(VOLATILE_REF_COST);
7275 format %{ "ldarw $dst, $mem\t# compressed ptr" %}
7276
7277 ins_encode(aarch64_enc_ldarw(dst, mem));
7278
7279 ins_pipe(pipe_serial);
7280 %}
7281
7282 // Load Float
7283 instruct loadF_volatile(vRegF dst, /* sync_memory*/indirect mem)
7284 %{
7285 match(Set dst (LoadF mem));
7286
7287 ins_cost(VOLATILE_REF_COST);
7288 format %{ "ldars $dst, $mem\t# float" %}
7289
7290 ins_encode( aarch64_enc_fldars(dst, mem) );
7291
7292 ins_pipe(pipe_serial);
7293 %}
7294
7295 // Load Double
7296 instruct loadD_volatile(vRegD dst, /* sync_memory*/indirect mem)
7297 %{
7298 match(Set dst (LoadD mem));
7299
7300 ins_cost(VOLATILE_REF_COST);
7301 format %{ "ldard $dst, $mem\t# double" %}
7302
7303 ins_encode( aarch64_enc_fldard(dst, mem) );
7304
7305 ins_pipe(pipe_serial);
7306 %}
7307
7308 // Store Byte
7309 instruct storeB_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
7310 %{
7311 match(Set mem (StoreB mem src));
7312
7313 ins_cost(VOLATILE_REF_COST);
7314 format %{ "stlrb $src, $mem\t# byte" %}
7315
7316 ins_encode(aarch64_enc_stlrb(src, mem));
7317
7318 ins_pipe(pipe_class_memory);
7319 %}
7320
7321 instruct storeimmB0_volatile(immI0 zero, /* sync_memory*/indirect mem)
7322 %{
7323 match(Set mem (StoreB mem zero));
7324
7325 ins_cost(VOLATILE_REF_COST);
7326 format %{ "stlrb zr, $mem\t# byte" %}
7327
7328 ins_encode(aarch64_enc_stlrb0(mem));
7329
7330 ins_pipe(pipe_class_memory);
7331 %}
7332
7333 // Store Char/Short
7334 instruct storeC_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
7335 %{
7336 match(Set mem (StoreC mem src));
7337
7338 ins_cost(VOLATILE_REF_COST);
7339 format %{ "stlrh $src, $mem\t# short" %}
7340
7341 ins_encode(aarch64_enc_stlrh(src, mem));
7342
7343 ins_pipe(pipe_class_memory);
7344 %}
7345
7346 instruct storeimmC0_volatile(immI0 zero, /* sync_memory*/indirect mem)
7347 %{
7348 match(Set mem (StoreC mem zero));
7349
7350 ins_cost(VOLATILE_REF_COST);
7351 format %{ "stlrh zr, $mem\t# short" %}
7352
7353 ins_encode(aarch64_enc_stlrh0(mem));
7354
7355 ins_pipe(pipe_class_memory);
7356 %}
7357
7358 // Store Integer
7359
7360 instruct storeI_volatile(iRegIorL2I src, /* sync_memory*/indirect mem)
7361 %{
7362 match(Set mem(StoreI mem src));
7363
7364 ins_cost(VOLATILE_REF_COST);
7365 format %{ "stlrw $src, $mem\t# int" %}
7366
7367 ins_encode(aarch64_enc_stlrw(src, mem));
7368
7369 ins_pipe(pipe_class_memory);
7370 %}
7371
7372 instruct storeimmI0_volatile(immI0 zero, /* sync_memory*/indirect mem)
7373 %{
7374 match(Set mem(StoreI mem zero));
7375
7376 ins_cost(VOLATILE_REF_COST);
7377 format %{ "stlrw zr, $mem\t# int" %}
7378
7379 ins_encode(aarch64_enc_stlrw0(mem));
7380
7381 ins_pipe(pipe_class_memory);
7382 %}
7383
7384 // Store Long (64 bit signed)
7385 instruct storeL_volatile(iRegL src, /* sync_memory*/indirect mem)
7386 %{
7387 match(Set mem (StoreL mem src));
7388
7389 ins_cost(VOLATILE_REF_COST);
7390 format %{ "stlr $src, $mem\t# int" %}
7391
7392 ins_encode(aarch64_enc_stlr(src, mem));
7393
7394 ins_pipe(pipe_class_memory);
7395 %}
7396
7397 instruct storeimmL0_volatile(immL0 zero, /* sync_memory*/indirect mem)
7398 %{
7399 match(Set mem (StoreL mem zero));
7400
7401 ins_cost(VOLATILE_REF_COST);
7402 format %{ "stlr zr, $mem\t# int" %}
7403
7404 ins_encode(aarch64_enc_stlr0(mem));
7405
7406 ins_pipe(pipe_class_memory);
7407 %}
7408
7409 // Store Pointer
7410 instruct storeP_volatile(iRegP src, /* sync_memory*/indirect mem)
7411 %{
7412 match(Set mem (StoreP mem src));
7413 predicate(n->as_Store()->barrier_data() == 0);
7414
7415 ins_cost(VOLATILE_REF_COST);
7416 format %{ "stlr $src, $mem\t# ptr" %}
7417
7418 ins_encode(aarch64_enc_stlr(src, mem));
7419
7420 ins_pipe(pipe_class_memory);
7421 %}
7422
7423 instruct storeimmP0_volatile(immP0 zero, /* sync_memory*/indirect mem)
7424 %{
7425 match(Set mem (StoreP mem zero));
7426 predicate(n->as_Store()->barrier_data() == 0);
7427
7428 ins_cost(VOLATILE_REF_COST);
7429 format %{ "stlr zr, $mem\t# ptr" %}
7430
7431 ins_encode(aarch64_enc_stlr0(mem));
7432
7433 ins_pipe(pipe_class_memory);
7434 %}
7435
7436 // Store Compressed Pointer
7437 instruct storeN_volatile(iRegN src, /* sync_memory*/indirect mem)
7438 %{
7439 match(Set mem (StoreN mem src));
7440
7441 ins_cost(VOLATILE_REF_COST);
7442 format %{ "stlrw $src, $mem\t# compressed ptr" %}
7443
7444 ins_encode(aarch64_enc_stlrw(src, mem));
7445
7446 ins_pipe(pipe_class_memory);
7447 %}
7448
7449 instruct storeimmN0_volatile(immN0 zero, /* sync_memory*/indirect mem)
7450 %{
7451 match(Set mem (StoreN mem zero));
7452
7453 ins_cost(VOLATILE_REF_COST);
7454 format %{ "stlrw zr, $mem\t# compressed ptr" %}
7455
7456 ins_encode(aarch64_enc_stlrw0(mem));
7457
7458 ins_pipe(pipe_class_memory);
7459 %}
7460
7461 // Store Float
7462 instruct storeF_volatile(vRegF src, /* sync_memory*/indirect mem)
7463 %{
7464 match(Set mem (StoreF mem src));
7465
7466 ins_cost(VOLATILE_REF_COST);
7467 format %{ "stlrs $src, $mem\t# float" %}
7468
7469 ins_encode( aarch64_enc_fstlrs(src, mem) );
7470
7471 ins_pipe(pipe_class_memory);
7472 %}
7473
7474 // TODO
7475 // implement storeImmF0 and storeFImmPacked
7476
7477 // Store Double
7478 instruct storeD_volatile(vRegD src, /* sync_memory*/indirect mem)
7479 %{
7480 match(Set mem (StoreD mem src));
7481
7482 ins_cost(VOLATILE_REF_COST);
7483 format %{ "stlrd $src, $mem\t# double" %}
7484
7485 ins_encode( aarch64_enc_fstlrd(src, mem) );
7486
7487 ins_pipe(pipe_class_memory);
7488 %}
7489
7490 // ---------------- end of volatile loads and stores ----------------
7491
7492 instruct cacheWB(indirect addr)
7493 %{
7494 predicate(VM_Version::supports_data_cache_line_flush());
7495 match(CacheWB addr);
7496
7497 ins_cost(100);
7498 format %{"cache wb $addr" %}
7499 ins_encode %{
7500 assert($addr->index_position() < 0, "should be");
7501 assert($addr$$disp == 0, "should be");
7502 __ cache_wb(Address($addr$$base$$Register, 0));
7503 %}
7504 ins_pipe(pipe_slow); // XXX
7505 %}
7506
7507 instruct cacheWBPreSync()
7508 %{
7509 predicate(VM_Version::supports_data_cache_line_flush());
7510 match(CacheWBPreSync);
7511
7512 ins_cost(100);
7513 format %{"cache wb presync" %}
7514 ins_encode %{
7515 __ cache_wbsync(true);
7516 %}
7517 ins_pipe(pipe_slow); // XXX
7518 %}
7519
7520 instruct cacheWBPostSync()
7521 %{
7522 predicate(VM_Version::supports_data_cache_line_flush());
7523 match(CacheWBPostSync);
7524
7525 ins_cost(100);
7526 format %{"cache wb postsync" %}
7527 ins_encode %{
7528 __ cache_wbsync(false);
7529 %}
7530 ins_pipe(pipe_slow); // XXX
7531 %}
7532
7533 // ============================================================================
7534 // BSWAP Instructions
7535
7536 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src) %{
7537 match(Set dst (ReverseBytesI src));
7538
7539 ins_cost(INSN_COST);
7540 format %{ "revw $dst, $src" %}
7541
7542 ins_encode %{
7543 __ revw(as_Register($dst$$reg), as_Register($src$$reg));
7544 %}
7545
7546 ins_pipe(ialu_reg);
7547 %}
7548
7549 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src) %{
7550 match(Set dst (ReverseBytesL src));
7551
7552 ins_cost(INSN_COST);
7553 format %{ "rev $dst, $src" %}
7554
7555 ins_encode %{
7556 __ rev(as_Register($dst$$reg), as_Register($src$$reg));
7557 %}
7558
7559 ins_pipe(ialu_reg);
7560 %}
7561
7562 instruct bytes_reverse_unsigned_short(iRegINoSp dst, iRegIorL2I src) %{
7563 match(Set dst (ReverseBytesUS src));
7564
7565 ins_cost(INSN_COST);
7566 format %{ "rev16w $dst, $src" %}
7567
7568 ins_encode %{
7569 __ rev16w(as_Register($dst$$reg), as_Register($src$$reg));
7570 %}
7571
7572 ins_pipe(ialu_reg);
7573 %}
7574
7575 instruct bytes_reverse_short(iRegINoSp dst, iRegIorL2I src) %{
7576 match(Set dst (ReverseBytesS src));
7577
7578 ins_cost(INSN_COST);
7579 format %{ "rev16w $dst, $src\n\t"
7580 "sbfmw $dst, $dst, #0, #15" %}
7581
7582 ins_encode %{
7583 __ rev16w(as_Register($dst$$reg), as_Register($src$$reg));
7584 __ sbfmw(as_Register($dst$$reg), as_Register($dst$$reg), 0U, 15U);
7585 %}
7586
7587 ins_pipe(ialu_reg);
7588 %}
7589
7590 // ============================================================================
7591 // Zero Count Instructions
7592
7593 instruct countLeadingZerosI(iRegINoSp dst, iRegIorL2I src) %{
7594 match(Set dst (CountLeadingZerosI src));
7595
7596 ins_cost(INSN_COST);
7597 format %{ "clzw $dst, $src" %}
7598 ins_encode %{
7599 __ clzw(as_Register($dst$$reg), as_Register($src$$reg));
7600 %}
7601
7602 ins_pipe(ialu_reg);
7603 %}
7604
7605 instruct countLeadingZerosL(iRegINoSp dst, iRegL src) %{
7606 match(Set dst (CountLeadingZerosL src));
7607
7608 ins_cost(INSN_COST);
7609 format %{ "clz $dst, $src" %}
7610 ins_encode %{
7611 __ clz(as_Register($dst$$reg), as_Register($src$$reg));
7612 %}
7613
7614 ins_pipe(ialu_reg);
7615 %}
7616
7617 instruct countTrailingZerosI(iRegINoSp dst, iRegIorL2I src) %{
7618 match(Set dst (CountTrailingZerosI src));
7619
7620 ins_cost(INSN_COST * 2);
7621 format %{ "rbitw $dst, $src\n\t"
7622 "clzw $dst, $dst" %}
7623 ins_encode %{
7624 __ rbitw(as_Register($dst$$reg), as_Register($src$$reg));
7625 __ clzw(as_Register($dst$$reg), as_Register($dst$$reg));
7626 %}
7627
7628 ins_pipe(ialu_reg);
7629 %}
7630
7631 instruct countTrailingZerosL(iRegINoSp dst, iRegL src) %{
7632 match(Set dst (CountTrailingZerosL src));
7633
7634 ins_cost(INSN_COST * 2);
7635 format %{ "rbit $dst, $src\n\t"
7636 "clz $dst, $dst" %}
7637 ins_encode %{
7638 __ rbit(as_Register($dst$$reg), as_Register($src$$reg));
7639 __ clz(as_Register($dst$$reg), as_Register($dst$$reg));
7640 %}
7641
7642 ins_pipe(ialu_reg);
7643 %}
7644
7645 //---------- Population Count Instructions -------------------------------------
7646 //
7647
7648 instruct popCountI(iRegINoSp dst, iRegIorL2I src, vRegF tmp) %{
7649 match(Set dst (PopCountI src));
7650 effect(TEMP tmp);
7651 ins_cost(INSN_COST * 13);
7652
7653 format %{ "movw $src, $src\n\t"
7654 "mov $tmp, $src\t# vector (1D)\n\t"
7655 "cnt $tmp, $tmp\t# vector (8B)\n\t"
7656 "addv $tmp, $tmp\t# vector (8B)\n\t"
7657 "mov $dst, $tmp\t# vector (1D)" %}
7658 ins_encode %{
7659 __ movw($src$$Register, $src$$Register); // ensure top 32 bits 0
7660 __ mov($tmp$$FloatRegister, __ D, 0, $src$$Register);
7661 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
7662 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
7663 __ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
7664 %}
7665
7666 ins_pipe(pipe_class_default);
7667 %}
7668
7669 instruct popCountI_mem(iRegINoSp dst, memory4 mem, vRegF tmp) %{
7670 match(Set dst (PopCountI (LoadI mem)));
7671 effect(TEMP tmp);
7672 ins_cost(INSN_COST * 13);
7673
7674 format %{ "ldrs $tmp, $mem\n\t"
7675 "cnt $tmp, $tmp\t# vector (8B)\n\t"
7676 "addv $tmp, $tmp\t# vector (8B)\n\t"
7677 "mov $dst, $tmp\t# vector (1D)" %}
7678 ins_encode %{
7679 FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
7680 loadStore(masm, &MacroAssembler::ldrs, tmp_reg, $mem->opcode(),
7681 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
7682 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
7683 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
7684 __ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
7685 %}
7686
7687 ins_pipe(pipe_class_default);
7688 %}
7689
7690 // Note: Long.bitCount(long) returns an int.
7691 instruct popCountL(iRegINoSp dst, iRegL src, vRegD tmp) %{
7692 match(Set dst (PopCountL src));
7693 effect(TEMP tmp);
7694 ins_cost(INSN_COST * 13);
7695
7696 format %{ "mov $tmp, $src\t# vector (1D)\n\t"
7697 "cnt $tmp, $tmp\t# vector (8B)\n\t"
7698 "addv $tmp, $tmp\t# vector (8B)\n\t"
7699 "mov $dst, $tmp\t# vector (1D)" %}
7700 ins_encode %{
7701 __ mov($tmp$$FloatRegister, __ D, 0, $src$$Register);
7702 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
7703 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
7704 __ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
7705 %}
7706
7707 ins_pipe(pipe_class_default);
7708 %}
7709
7710 instruct popCountL_mem(iRegINoSp dst, memory8 mem, vRegD tmp) %{
7711 match(Set dst (PopCountL (LoadL mem)));
7712 effect(TEMP tmp);
7713 ins_cost(INSN_COST * 13);
7714
7715 format %{ "ldrd $tmp, $mem\n\t"
7716 "cnt $tmp, $tmp\t# vector (8B)\n\t"
7717 "addv $tmp, $tmp\t# vector (8B)\n\t"
7718 "mov $dst, $tmp\t# vector (1D)" %}
7719 ins_encode %{
7720 FloatRegister tmp_reg = as_FloatRegister($tmp$$reg);
7721 loadStore(masm, &MacroAssembler::ldrd, tmp_reg, $mem->opcode(),
7722 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
7723 __ cnt($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
7724 __ addv($tmp$$FloatRegister, __ T8B, $tmp$$FloatRegister);
7725 __ mov($dst$$Register, $tmp$$FloatRegister, __ D, 0);
7726 %}
7727
7728 ins_pipe(pipe_class_default);
7729 %}
7730
7731 // ============================================================================
7732 // VerifyVectorAlignment Instruction
7733
7734 instruct verify_vector_alignment(iRegP addr, immL_positive_bitmaskI mask, rFlagsReg cr) %{
7735 match(Set addr (VerifyVectorAlignment addr mask));
7736 effect(KILL cr);
7737 format %{ "verify_vector_alignment $addr $mask \t! verify alignment" %}
7738 ins_encode %{
7739 Label Lskip;
7740 // check if masked bits of addr are zero
7741 __ tst($addr$$Register, $mask$$constant);
7742 __ br(Assembler::EQ, Lskip);
7743 __ stop("verify_vector_alignment found a misaligned vector memory access");
7744 __ bind(Lskip);
7745 %}
7746 ins_pipe(pipe_slow);
7747 %}
7748
7749 // ============================================================================
7750 // MemBar Instruction
7751
7752 instruct load_fence() %{
7753 match(LoadFence);
7754 ins_cost(VOLATILE_REF_COST);
7755
7756 format %{ "load_fence" %}
7757
7758 ins_encode %{
7759 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
7760 %}
7761 ins_pipe(pipe_serial);
7762 %}
7763
7764 instruct unnecessary_membar_acquire() %{
7765 predicate(unnecessary_acquire(n));
7766 match(MemBarAcquire);
7767 ins_cost(0);
7768
7769 format %{ "membar_acquire (elided)" %}
7770
7771 ins_encode %{
7772 __ block_comment("membar_acquire (elided)");
7773 %}
7774
7775 ins_pipe(pipe_class_empty);
7776 %}
7777
7778 instruct membar_acquire() %{
7779 match(MemBarAcquire);
7780 ins_cost(VOLATILE_REF_COST);
7781
7782 format %{ "membar_acquire\n\t"
7783 "dmb ish" %}
7784
7785 ins_encode %{
7786 __ block_comment("membar_acquire");
7787 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
7788 %}
7789
7790 ins_pipe(pipe_serial);
7791 %}
7792
7793
7794 instruct membar_acquire_lock() %{
7795 match(MemBarAcquireLock);
7796 ins_cost(VOLATILE_REF_COST);
7797
7798 format %{ "membar_acquire_lock (elided)" %}
7799
7800 ins_encode %{
7801 __ block_comment("membar_acquire_lock (elided)");
7802 %}
7803
7804 ins_pipe(pipe_serial);
7805 %}
7806
7807 instruct store_fence() %{
7808 match(StoreFence);
7809 ins_cost(VOLATILE_REF_COST);
7810
7811 format %{ "store_fence" %}
7812
7813 ins_encode %{
7814 __ membar(Assembler::LoadStore|Assembler::StoreStore);
7815 %}
7816 ins_pipe(pipe_serial);
7817 %}
7818
7819 instruct unnecessary_membar_release() %{
7820 predicate(unnecessary_release(n));
7821 match(MemBarRelease);
7822 ins_cost(0);
7823
7824 format %{ "membar_release (elided)" %}
7825
7826 ins_encode %{
7827 __ block_comment("membar_release (elided)");
7828 %}
7829 ins_pipe(pipe_serial);
7830 %}
7831
7832 instruct membar_release() %{
7833 match(MemBarRelease);
7834 ins_cost(VOLATILE_REF_COST);
7835
7836 format %{ "membar_release\n\t"
7837 "dmb ish" %}
7838
7839 ins_encode %{
7840 __ block_comment("membar_release");
7841 __ membar(Assembler::LoadStore|Assembler::StoreStore);
7842 %}
7843 ins_pipe(pipe_serial);
7844 %}
7845
7846 instruct membar_storestore() %{
7847 match(MemBarStoreStore);
7848 match(StoreStoreFence);
7849 ins_cost(VOLATILE_REF_COST);
7850
7851 format %{ "MEMBAR-store-store" %}
7852
7853 ins_encode %{
7854 __ membar(Assembler::StoreStore);
7855 %}
7856 ins_pipe(pipe_serial);
7857 %}
7858
7859 instruct membar_release_lock() %{
7860 match(MemBarReleaseLock);
7861 ins_cost(VOLATILE_REF_COST);
7862
7863 format %{ "membar_release_lock (elided)" %}
7864
7865 ins_encode %{
7866 __ block_comment("membar_release_lock (elided)");
7867 %}
7868
7869 ins_pipe(pipe_serial);
7870 %}
7871
7872 instruct unnecessary_membar_volatile() %{
7873 predicate(unnecessary_volatile(n));
7874 match(MemBarVolatile);
7875 ins_cost(0);
7876
7877 format %{ "membar_volatile (elided)" %}
7878
7879 ins_encode %{
7880 __ block_comment("membar_volatile (elided)");
7881 %}
7882
7883 ins_pipe(pipe_serial);
7884 %}
7885
7886 instruct membar_volatile() %{
7887 match(MemBarVolatile);
7888 ins_cost(VOLATILE_REF_COST*100);
7889
7890 format %{ "membar_volatile\n\t"
7891 "dmb ish"%}
7892
7893 ins_encode %{
7894 __ block_comment("membar_volatile");
7895 __ membar(Assembler::StoreLoad);
7896 %}
7897
7898 ins_pipe(pipe_serial);
7899 %}
7900
7901 // ============================================================================
7902 // Cast/Convert Instructions
7903
7904 instruct castX2P(iRegPNoSp dst, iRegL src) %{
7905 match(Set dst (CastX2P src));
7906
7907 ins_cost(INSN_COST);
7908 format %{ "mov $dst, $src\t# long -> ptr" %}
7909
7910 ins_encode %{
7911 if ($dst$$reg != $src$$reg) {
7912 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
7913 }
7914 %}
7915
7916 ins_pipe(ialu_reg);
7917 %}
7918
7919 instruct castP2X(iRegLNoSp dst, iRegP src) %{
7920 match(Set dst (CastP2X src));
7921
7922 ins_cost(INSN_COST);
7923 format %{ "mov $dst, $src\t# ptr -> long" %}
7924
7925 ins_encode %{
7926 if ($dst$$reg != $src$$reg) {
7927 __ mov(as_Register($dst$$reg), as_Register($src$$reg));
7928 }
7929 %}
7930
7931 ins_pipe(ialu_reg);
7932 %}
7933
7934 // Convert oop into int for vectors alignment masking
7935 instruct convP2I(iRegINoSp dst, iRegP src) %{
7936 match(Set dst (ConvL2I (CastP2X src)));
7937
7938 ins_cost(INSN_COST);
7939 format %{ "movw $dst, $src\t# ptr -> int" %}
7940 ins_encode %{
7941 __ movw($dst$$Register, $src$$Register);
7942 %}
7943
7944 ins_pipe(ialu_reg);
7945 %}
7946
7947 // Convert compressed oop into int for vectors alignment masking
7948 // in case of 32bit oops (heap < 4Gb).
7949 instruct convN2I(iRegINoSp dst, iRegN src)
7950 %{
7951 predicate(CompressedOops::shift() == 0);
7952 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
7953
7954 ins_cost(INSN_COST);
7955 format %{ "mov dst, $src\t# compressed ptr -> int" %}
7956 ins_encode %{
7957 __ movw($dst$$Register, $src$$Register);
7958 %}
7959
7960 ins_pipe(ialu_reg);
7961 %}
7962
7963
7964 // Convert oop pointer into compressed form
7965 instruct encodeHeapOop(iRegNNoSp dst, iRegP src, rFlagsReg cr) %{
7966 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
7967 match(Set dst (EncodeP src));
7968 effect(KILL cr);
7969 ins_cost(INSN_COST * 3);
7970 format %{ "encode_heap_oop $dst, $src" %}
7971 ins_encode %{
7972 Register s = $src$$Register;
7973 Register d = $dst$$Register;
7974 __ encode_heap_oop(d, s);
7975 %}
7976 ins_pipe(ialu_reg);
7977 %}
7978
7979 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src, rFlagsReg cr) %{
7980 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
7981 match(Set dst (EncodeP src));
7982 ins_cost(INSN_COST * 3);
7983 format %{ "encode_heap_oop_not_null $dst, $src" %}
7984 ins_encode %{
7985 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
7986 %}
7987 ins_pipe(ialu_reg);
7988 %}
7989
7990 instruct decodeHeapOop(iRegPNoSp dst, iRegN src, rFlagsReg cr) %{
7991 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
7992 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
7993 match(Set dst (DecodeN src));
7994 ins_cost(INSN_COST * 3);
7995 format %{ "decode_heap_oop $dst, $src" %}
7996 ins_encode %{
7997 Register s = $src$$Register;
7998 Register d = $dst$$Register;
7999 __ decode_heap_oop(d, s);
8000 %}
8001 ins_pipe(ialu_reg);
8002 %}
8003
8004 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src, rFlagsReg cr) %{
8005 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8006 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8007 match(Set dst (DecodeN src));
8008 ins_cost(INSN_COST * 3);
8009 format %{ "decode_heap_oop_not_null $dst, $src" %}
8010 ins_encode %{
8011 Register s = $src$$Register;
8012 Register d = $dst$$Register;
8013 __ decode_heap_oop_not_null(d, s);
8014 %}
8015 ins_pipe(ialu_reg);
8016 %}
8017
8018 // n.b. AArch64 implementations of encode_klass_not_null and
8019 // decode_klass_not_null do not modify the flags register so, unlike
8020 // Intel, we don't kill CR as a side effect here
8021
8022 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8023 match(Set dst (EncodePKlass src));
8024
8025 ins_cost(INSN_COST * 3);
8026 format %{ "encode_klass_not_null $dst,$src" %}
8027
8028 ins_encode %{
8029 Register src_reg = as_Register($src$$reg);
8030 Register dst_reg = as_Register($dst$$reg);
8031 __ encode_klass_not_null(dst_reg, src_reg);
8032 %}
8033
8034 ins_pipe(ialu_reg);
8035 %}
8036
8037 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src) %{
8038 match(Set dst (DecodeNKlass src));
8039
8040 ins_cost(INSN_COST * 3);
8041 format %{ "decode_klass_not_null $dst,$src" %}
8042
8043 ins_encode %{
8044 Register src_reg = as_Register($src$$reg);
8045 Register dst_reg = as_Register($dst$$reg);
8046 if (dst_reg != src_reg) {
8047 __ decode_klass_not_null(dst_reg, src_reg);
8048 } else {
8049 __ decode_klass_not_null(dst_reg);
8050 }
8051 %}
8052
8053 ins_pipe(ialu_reg);
8054 %}
8055
8056 instruct checkCastPP(iRegPNoSp dst)
8057 %{
8058 match(Set dst (CheckCastPP dst));
8059
8060 size(0);
8061 format %{ "# checkcastPP of $dst" %}
8062 ins_encode(/* empty encoding */);
8063 ins_pipe(pipe_class_empty);
8064 %}
8065
8066 instruct castPP(iRegPNoSp dst)
8067 %{
8068 match(Set dst (CastPP dst));
8069
8070 size(0);
8071 format %{ "# castPP of $dst" %}
8072 ins_encode(/* empty encoding */);
8073 ins_pipe(pipe_class_empty);
8074 %}
8075
8076 instruct castII(iRegI dst)
8077 %{
8078 match(Set dst (CastII dst));
8079
8080 size(0);
8081 format %{ "# castII of $dst" %}
8082 ins_encode(/* empty encoding */);
8083 ins_cost(0);
8084 ins_pipe(pipe_class_empty);
8085 %}
8086
8087 instruct castLL(iRegL dst)
8088 %{
8089 match(Set dst (CastLL dst));
8090
8091 size(0);
8092 format %{ "# castLL of $dst" %}
8093 ins_encode(/* empty encoding */);
8094 ins_cost(0);
8095 ins_pipe(pipe_class_empty);
8096 %}
8097
8098 instruct castFF(vRegF dst)
8099 %{
8100 match(Set dst (CastFF dst));
8101
8102 size(0);
8103 format %{ "# castFF of $dst" %}
8104 ins_encode(/* empty encoding */);
8105 ins_cost(0);
8106 ins_pipe(pipe_class_empty);
8107 %}
8108
8109 instruct castDD(vRegD dst)
8110 %{
8111 match(Set dst (CastDD dst));
8112
8113 size(0);
8114 format %{ "# castDD of $dst" %}
8115 ins_encode(/* empty encoding */);
8116 ins_cost(0);
8117 ins_pipe(pipe_class_empty);
8118 %}
8119
8120 instruct castVV(vReg dst)
8121 %{
8122 match(Set dst (CastVV dst));
8123
8124 size(0);
8125 format %{ "# castVV of $dst" %}
8126 ins_encode(/* empty encoding */);
8127 ins_cost(0);
8128 ins_pipe(pipe_class_empty);
8129 %}
8130
8131 instruct castVVMask(pRegGov dst)
8132 %{
8133 match(Set dst (CastVV dst));
8134
8135 size(0);
8136 format %{ "# castVV of $dst" %}
8137 ins_encode(/* empty encoding */);
8138 ins_cost(0);
8139 ins_pipe(pipe_class_empty);
8140 %}
8141
8142 // ============================================================================
8143 // Atomic operation instructions
8144 //
8145
8146 // standard CompareAndSwapX when we are using barriers
8147 // these have higher priority than the rules selected by a predicate
8148
8149 // XXX No flag versions for CompareAndSwap{I,L,P,N} because matcher
8150 // can't match them
8151
8152 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8153
8154 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
8155 ins_cost(2 * VOLATILE_REF_COST);
8156
8157 effect(KILL cr);
8158
8159 format %{
8160 "cmpxchgb $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8161 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8162 %}
8163
8164 ins_encode(aarch64_enc_cmpxchgb(mem, oldval, newval),
8165 aarch64_enc_cset_eq(res));
8166
8167 ins_pipe(pipe_slow);
8168 %}
8169
8170 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8171
8172 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
8173 ins_cost(2 * VOLATILE_REF_COST);
8174
8175 effect(KILL cr);
8176
8177 format %{
8178 "cmpxchgs $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8179 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8180 %}
8181
8182 ins_encode(aarch64_enc_cmpxchgs(mem, oldval, newval),
8183 aarch64_enc_cset_eq(res));
8184
8185 ins_pipe(pipe_slow);
8186 %}
8187
8188 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8189
8190 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
8191 ins_cost(2 * VOLATILE_REF_COST);
8192
8193 effect(KILL cr);
8194
8195 format %{
8196 "cmpxchgw $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8197 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8198 %}
8199
8200 ins_encode(aarch64_enc_cmpxchgw(mem, oldval, newval),
8201 aarch64_enc_cset_eq(res));
8202
8203 ins_pipe(pipe_slow);
8204 %}
8205
8206 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoSp newval, rFlagsReg cr) %{
8207
8208 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
8209 ins_cost(2 * VOLATILE_REF_COST);
8210
8211 effect(KILL cr);
8212
8213 format %{
8214 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval"
8215 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8216 %}
8217
8218 ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval),
8219 aarch64_enc_cset_eq(res));
8220
8221 ins_pipe(pipe_slow);
8222 %}
8223
8224 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
8225
8226 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
8227 predicate(n->as_LoadStore()->barrier_data() == 0);
8228 ins_cost(2 * VOLATILE_REF_COST);
8229
8230 effect(KILL cr);
8231
8232 format %{
8233 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval"
8234 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8235 %}
8236
8237 ins_encode(aarch64_enc_cmpxchg(mem, oldval, newval),
8238 aarch64_enc_cset_eq(res));
8239
8240 ins_pipe(pipe_slow);
8241 %}
8242
8243 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoSp newval, rFlagsReg cr) %{
8244
8245 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
8246 ins_cost(2 * VOLATILE_REF_COST);
8247
8248 effect(KILL cr);
8249
8250 format %{
8251 "cmpxchgw $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval"
8252 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8253 %}
8254
8255 ins_encode(aarch64_enc_cmpxchgw(mem, oldval, newval),
8256 aarch64_enc_cset_eq(res));
8257
8258 ins_pipe(pipe_slow);
8259 %}
8260
8261 // alternative CompareAndSwapX when we are eliding barriers
8262
8263 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8264
8265 predicate(needs_acquiring_load_exclusive(n));
8266 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
8267 ins_cost(VOLATILE_REF_COST);
8268
8269 effect(KILL cr);
8270
8271 format %{
8272 "cmpxchgb_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8273 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8274 %}
8275
8276 ins_encode(aarch64_enc_cmpxchgb_acq(mem, oldval, newval),
8277 aarch64_enc_cset_eq(res));
8278
8279 ins_pipe(pipe_slow);
8280 %}
8281
8282 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8283
8284 predicate(needs_acquiring_load_exclusive(n));
8285 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
8286 ins_cost(VOLATILE_REF_COST);
8287
8288 effect(KILL cr);
8289
8290 format %{
8291 "cmpxchgs_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8292 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8293 %}
8294
8295 ins_encode(aarch64_enc_cmpxchgs_acq(mem, oldval, newval),
8296 aarch64_enc_cset_eq(res));
8297
8298 ins_pipe(pipe_slow);
8299 %}
8300
8301 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegINoSp oldval, iRegINoSp newval, rFlagsReg cr) %{
8302
8303 predicate(needs_acquiring_load_exclusive(n));
8304 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
8305 ins_cost(VOLATILE_REF_COST);
8306
8307 effect(KILL cr);
8308
8309 format %{
8310 "cmpxchgw_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval"
8311 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8312 %}
8313
8314 ins_encode(aarch64_enc_cmpxchgw_acq(mem, oldval, newval),
8315 aarch64_enc_cset_eq(res));
8316
8317 ins_pipe(pipe_slow);
8318 %}
8319
8320 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegLNoSp oldval, iRegLNoSp newval, rFlagsReg cr) %{
8321
8322 predicate(needs_acquiring_load_exclusive(n));
8323 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
8324 ins_cost(VOLATILE_REF_COST);
8325
8326 effect(KILL cr);
8327
8328 format %{
8329 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval"
8330 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8331 %}
8332
8333 ins_encode(aarch64_enc_cmpxchg_acq(mem, oldval, newval),
8334 aarch64_enc_cset_eq(res));
8335
8336 ins_pipe(pipe_slow);
8337 %}
8338
8339 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
8340
8341 predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
8342 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
8343 ins_cost(VOLATILE_REF_COST);
8344
8345 effect(KILL cr);
8346
8347 format %{
8348 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval"
8349 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8350 %}
8351
8352 ins_encode(aarch64_enc_cmpxchg_acq(mem, oldval, newval),
8353 aarch64_enc_cset_eq(res));
8354
8355 ins_pipe(pipe_slow);
8356 %}
8357
8358 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegNNoSp oldval, iRegNNoSp newval, rFlagsReg cr) %{
8359
8360 predicate(needs_acquiring_load_exclusive(n));
8361 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
8362 ins_cost(VOLATILE_REF_COST);
8363
8364 effect(KILL cr);
8365
8366 format %{
8367 "cmpxchgw_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval"
8368 "cset $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8369 %}
8370
8371 ins_encode(aarch64_enc_cmpxchgw_acq(mem, oldval, newval),
8372 aarch64_enc_cset_eq(res));
8373
8374 ins_pipe(pipe_slow);
8375 %}
8376
8377
8378 // ---------------------------------------------------------------------
8379
8380 // BEGIN This section of the file is automatically generated. Do not edit --------------
8381
8382 // Sundry CAS operations. Note that release is always true,
8383 // regardless of the memory ordering of the CAS. This is because we
8384 // need the volatile case to be sequentially consistent but there is
8385 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
8386 // can't check the type of memory ordering here, so we always emit a
8387 // STLXR.
8388
8389 // This section is generated from cas.m4
8390
8391
8392 // This pattern is generated automatically from cas.m4.
8393 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8394 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8395 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
8396 ins_cost(2 * VOLATILE_REF_COST);
8397 effect(TEMP_DEF res, KILL cr);
8398 format %{
8399 "cmpxchgb $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
8400 %}
8401 ins_encode %{
8402 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8403 Assembler::byte, /*acquire*/ false, /*release*/ true,
8404 /*weak*/ false, $res$$Register);
8405 __ sxtbw($res$$Register, $res$$Register);
8406 %}
8407 ins_pipe(pipe_slow);
8408 %}
8409
8410 // This pattern is generated automatically from cas.m4.
8411 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8412 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8413 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
8414 ins_cost(2 * VOLATILE_REF_COST);
8415 effect(TEMP_DEF res, KILL cr);
8416 format %{
8417 "cmpxchgs $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
8418 %}
8419 ins_encode %{
8420 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8421 Assembler::halfword, /*acquire*/ false, /*release*/ true,
8422 /*weak*/ false, $res$$Register);
8423 __ sxthw($res$$Register, $res$$Register);
8424 %}
8425 ins_pipe(pipe_slow);
8426 %}
8427
8428 // This pattern is generated automatically from cas.m4.
8429 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8430 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8431 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
8432 ins_cost(2 * VOLATILE_REF_COST);
8433 effect(TEMP_DEF res, KILL cr);
8434 format %{
8435 "cmpxchgw $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
8436 %}
8437 ins_encode %{
8438 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8439 Assembler::word, /*acquire*/ false, /*release*/ true,
8440 /*weak*/ false, $res$$Register);
8441 %}
8442 ins_pipe(pipe_slow);
8443 %}
8444
8445 // This pattern is generated automatically from cas.m4.
8446 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8447 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
8448 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
8449 ins_cost(2 * VOLATILE_REF_COST);
8450 effect(TEMP_DEF res, KILL cr);
8451 format %{
8452 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
8453 %}
8454 ins_encode %{
8455 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8456 Assembler::xword, /*acquire*/ false, /*release*/ true,
8457 /*weak*/ false, $res$$Register);
8458 %}
8459 ins_pipe(pipe_slow);
8460 %}
8461
8462 // This pattern is generated automatically from cas.m4.
8463 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8464 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
8465 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
8466 ins_cost(2 * VOLATILE_REF_COST);
8467 effect(TEMP_DEF res, KILL cr);
8468 format %{
8469 "cmpxchgw $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
8470 %}
8471 ins_encode %{
8472 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8473 Assembler::word, /*acquire*/ false, /*release*/ true,
8474 /*weak*/ false, $res$$Register);
8475 %}
8476 ins_pipe(pipe_slow);
8477 %}
8478
8479 // This pattern is generated automatically from cas.m4.
8480 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8481 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
8482 predicate(n->as_LoadStore()->barrier_data() == 0);
8483 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
8484 ins_cost(2 * VOLATILE_REF_COST);
8485 effect(TEMP_DEF res, KILL cr);
8486 format %{
8487 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
8488 %}
8489 ins_encode %{
8490 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8491 Assembler::xword, /*acquire*/ false, /*release*/ true,
8492 /*weak*/ false, $res$$Register);
8493 %}
8494 ins_pipe(pipe_slow);
8495 %}
8496
8497 // This pattern is generated automatically from cas.m4.
8498 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8499 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8500 predicate(needs_acquiring_load_exclusive(n));
8501 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
8502 ins_cost(VOLATILE_REF_COST);
8503 effect(TEMP_DEF res, KILL cr);
8504 format %{
8505 "cmpxchgb_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
8506 %}
8507 ins_encode %{
8508 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8509 Assembler::byte, /*acquire*/ true, /*release*/ true,
8510 /*weak*/ false, $res$$Register);
8511 __ sxtbw($res$$Register, $res$$Register);
8512 %}
8513 ins_pipe(pipe_slow);
8514 %}
8515
8516 // This pattern is generated automatically from cas.m4.
8517 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8518 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8519 predicate(needs_acquiring_load_exclusive(n));
8520 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
8521 ins_cost(VOLATILE_REF_COST);
8522 effect(TEMP_DEF res, KILL cr);
8523 format %{
8524 "cmpxchgs_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
8525 %}
8526 ins_encode %{
8527 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8528 Assembler::halfword, /*acquire*/ true, /*release*/ true,
8529 /*weak*/ false, $res$$Register);
8530 __ sxthw($res$$Register, $res$$Register);
8531 %}
8532 ins_pipe(pipe_slow);
8533 %}
8534
8535 // This pattern is generated automatically from cas.m4.
8536 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8537 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8538 predicate(needs_acquiring_load_exclusive(n));
8539 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
8540 ins_cost(VOLATILE_REF_COST);
8541 effect(TEMP_DEF res, KILL cr);
8542 format %{
8543 "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
8544 %}
8545 ins_encode %{
8546 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8547 Assembler::word, /*acquire*/ true, /*release*/ true,
8548 /*weak*/ false, $res$$Register);
8549 %}
8550 ins_pipe(pipe_slow);
8551 %}
8552
8553 // This pattern is generated automatically from cas.m4.
8554 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8555 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
8556 predicate(needs_acquiring_load_exclusive(n));
8557 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
8558 ins_cost(VOLATILE_REF_COST);
8559 effect(TEMP_DEF res, KILL cr);
8560 format %{
8561 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
8562 %}
8563 ins_encode %{
8564 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8565 Assembler::xword, /*acquire*/ true, /*release*/ true,
8566 /*weak*/ false, $res$$Register);
8567 %}
8568 ins_pipe(pipe_slow);
8569 %}
8570
8571 // This pattern is generated automatically from cas.m4.
8572 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8573 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
8574 predicate(needs_acquiring_load_exclusive(n));
8575 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
8576 ins_cost(VOLATILE_REF_COST);
8577 effect(TEMP_DEF res, KILL cr);
8578 format %{
8579 "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
8580 %}
8581 ins_encode %{
8582 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8583 Assembler::word, /*acquire*/ true, /*release*/ true,
8584 /*weak*/ false, $res$$Register);
8585 %}
8586 ins_pipe(pipe_slow);
8587 %}
8588
8589 // This pattern is generated automatically from cas.m4.
8590 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8591 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
8592 predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
8593 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
8594 ins_cost(VOLATILE_REF_COST);
8595 effect(TEMP_DEF res, KILL cr);
8596 format %{
8597 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
8598 %}
8599 ins_encode %{
8600 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8601 Assembler::xword, /*acquire*/ true, /*release*/ true,
8602 /*weak*/ false, $res$$Register);
8603 %}
8604 ins_pipe(pipe_slow);
8605 %}
8606
8607 // This pattern is generated automatically from cas.m4.
8608 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8609 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8610 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
8611 ins_cost(2 * VOLATILE_REF_COST);
8612 effect(KILL cr);
8613 format %{
8614 "cmpxchgb $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
8615 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8616 %}
8617 ins_encode %{
8618 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8619 Assembler::byte, /*acquire*/ false, /*release*/ true,
8620 /*weak*/ true, noreg);
8621 __ csetw($res$$Register, Assembler::EQ);
8622 %}
8623 ins_pipe(pipe_slow);
8624 %}
8625
8626 // This pattern is generated automatically from cas.m4.
8627 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8628 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8629 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
8630 ins_cost(2 * VOLATILE_REF_COST);
8631 effect(KILL cr);
8632 format %{
8633 "cmpxchgs $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
8634 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8635 %}
8636 ins_encode %{
8637 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8638 Assembler::halfword, /*acquire*/ false, /*release*/ true,
8639 /*weak*/ true, noreg);
8640 __ csetw($res$$Register, Assembler::EQ);
8641 %}
8642 ins_pipe(pipe_slow);
8643 %}
8644
8645 // This pattern is generated automatically from cas.m4.
8646 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8647 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8648 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
8649 ins_cost(2 * VOLATILE_REF_COST);
8650 effect(KILL cr);
8651 format %{
8652 "cmpxchgw $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
8653 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8654 %}
8655 ins_encode %{
8656 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8657 Assembler::word, /*acquire*/ false, /*release*/ true,
8658 /*weak*/ true, noreg);
8659 __ csetw($res$$Register, Assembler::EQ);
8660 %}
8661 ins_pipe(pipe_slow);
8662 %}
8663
8664 // This pattern is generated automatically from cas.m4.
8665 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8666 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
8667 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
8668 ins_cost(2 * VOLATILE_REF_COST);
8669 effect(KILL cr);
8670 format %{
8671 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
8672 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8673 %}
8674 ins_encode %{
8675 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8676 Assembler::xword, /*acquire*/ false, /*release*/ true,
8677 /*weak*/ true, noreg);
8678 __ csetw($res$$Register, Assembler::EQ);
8679 %}
8680 ins_pipe(pipe_slow);
8681 %}
8682
8683 // This pattern is generated automatically from cas.m4.
8684 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8685 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
8686 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
8687 ins_cost(2 * VOLATILE_REF_COST);
8688 effect(KILL cr);
8689 format %{
8690 "cmpxchgw $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
8691 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8692 %}
8693 ins_encode %{
8694 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8695 Assembler::word, /*acquire*/ false, /*release*/ true,
8696 /*weak*/ true, noreg);
8697 __ csetw($res$$Register, Assembler::EQ);
8698 %}
8699 ins_pipe(pipe_slow);
8700 %}
8701
8702 // This pattern is generated automatically from cas.m4.
8703 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8704 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
8705 predicate(n->as_LoadStore()->barrier_data() == 0);
8706 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
8707 ins_cost(2 * VOLATILE_REF_COST);
8708 effect(KILL cr);
8709 format %{
8710 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
8711 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8712 %}
8713 ins_encode %{
8714 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8715 Assembler::xword, /*acquire*/ false, /*release*/ true,
8716 /*weak*/ true, noreg);
8717 __ csetw($res$$Register, Assembler::EQ);
8718 %}
8719 ins_pipe(pipe_slow);
8720 %}
8721
8722 // This pattern is generated automatically from cas.m4.
8723 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8724 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8725 predicate(needs_acquiring_load_exclusive(n));
8726 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
8727 ins_cost(VOLATILE_REF_COST);
8728 effect(KILL cr);
8729 format %{
8730 "cmpxchgb_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval"
8731 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8732 %}
8733 ins_encode %{
8734 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8735 Assembler::byte, /*acquire*/ true, /*release*/ true,
8736 /*weak*/ true, noreg);
8737 __ csetw($res$$Register, Assembler::EQ);
8738 %}
8739 ins_pipe(pipe_slow);
8740 %}
8741
8742 // This pattern is generated automatically from cas.m4.
8743 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8744 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8745 predicate(needs_acquiring_load_exclusive(n));
8746 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
8747 ins_cost(VOLATILE_REF_COST);
8748 effect(KILL cr);
8749 format %{
8750 "cmpxchgs_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval"
8751 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8752 %}
8753 ins_encode %{
8754 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8755 Assembler::halfword, /*acquire*/ true, /*release*/ true,
8756 /*weak*/ true, noreg);
8757 __ csetw($res$$Register, Assembler::EQ);
8758 %}
8759 ins_pipe(pipe_slow);
8760 %}
8761
8762 // This pattern is generated automatically from cas.m4.
8763 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8764 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval, rFlagsReg cr) %{
8765 predicate(needs_acquiring_load_exclusive(n));
8766 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
8767 ins_cost(VOLATILE_REF_COST);
8768 effect(KILL cr);
8769 format %{
8770 "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval"
8771 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8772 %}
8773 ins_encode %{
8774 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8775 Assembler::word, /*acquire*/ true, /*release*/ true,
8776 /*weak*/ true, noreg);
8777 __ csetw($res$$Register, Assembler::EQ);
8778 %}
8779 ins_pipe(pipe_slow);
8780 %}
8781
8782 // This pattern is generated automatically from cas.m4.
8783 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8784 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval, rFlagsReg cr) %{
8785 predicate(needs_acquiring_load_exclusive(n));
8786 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
8787 ins_cost(VOLATILE_REF_COST);
8788 effect(KILL cr);
8789 format %{
8790 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval"
8791 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8792 %}
8793 ins_encode %{
8794 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8795 Assembler::xword, /*acquire*/ true, /*release*/ true,
8796 /*weak*/ true, noreg);
8797 __ csetw($res$$Register, Assembler::EQ);
8798 %}
8799 ins_pipe(pipe_slow);
8800 %}
8801
8802 // This pattern is generated automatically from cas.m4.
8803 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8804 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval, rFlagsReg cr) %{
8805 predicate(needs_acquiring_load_exclusive(n));
8806 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
8807 ins_cost(VOLATILE_REF_COST);
8808 effect(KILL cr);
8809 format %{
8810 "cmpxchgw_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval"
8811 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8812 %}
8813 ins_encode %{
8814 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8815 Assembler::word, /*acquire*/ true, /*release*/ true,
8816 /*weak*/ true, noreg);
8817 __ csetw($res$$Register, Assembler::EQ);
8818 %}
8819 ins_pipe(pipe_slow);
8820 %}
8821
8822 // This pattern is generated automatically from cas.m4.
8823 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8824 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval, rFlagsReg cr) %{
8825 predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
8826 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
8827 ins_cost(VOLATILE_REF_COST);
8828 effect(KILL cr);
8829 format %{
8830 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval"
8831 "csetw $res, EQ\t# $res <-- (EQ ? 1 : 0)"
8832 %}
8833 ins_encode %{
8834 __ cmpxchg($mem$$Register, $oldval$$Register, $newval$$Register,
8835 Assembler::xword, /*acquire*/ true, /*release*/ true,
8836 /*weak*/ true, noreg);
8837 __ csetw($res$$Register, Assembler::EQ);
8838 %}
8839 ins_pipe(pipe_slow);
8840 %}
8841
8842 // END This section of the file is automatically generated. Do not edit --------------
8843 // ---------------------------------------------------------------------
8844
8845 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev) %{
8846 match(Set prev (GetAndSetI mem newv));
8847 ins_cost(2 * VOLATILE_REF_COST);
8848 format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
8849 ins_encode %{
8850 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
8851 %}
8852 ins_pipe(pipe_serial);
8853 %}
8854
8855 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev) %{
8856 match(Set prev (GetAndSetL mem newv));
8857 ins_cost(2 * VOLATILE_REF_COST);
8858 format %{ "atomic_xchg $prev, $newv, [$mem]" %}
8859 ins_encode %{
8860 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
8861 %}
8862 ins_pipe(pipe_serial);
8863 %}
8864
8865 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev) %{
8866 match(Set prev (GetAndSetN mem newv));
8867 ins_cost(2 * VOLATILE_REF_COST);
8868 format %{ "atomic_xchgw $prev, $newv, [$mem]" %}
8869 ins_encode %{
8870 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
8871 %}
8872 ins_pipe(pipe_serial);
8873 %}
8874
8875 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev) %{
8876 predicate(n->as_LoadStore()->barrier_data() == 0);
8877 match(Set prev (GetAndSetP mem newv));
8878 ins_cost(2 * VOLATILE_REF_COST);
8879 format %{ "atomic_xchg $prev, $newv, [$mem]" %}
8880 ins_encode %{
8881 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
8882 %}
8883 ins_pipe(pipe_serial);
8884 %}
8885
8886 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev) %{
8887 predicate(needs_acquiring_load_exclusive(n));
8888 match(Set prev (GetAndSetI mem newv));
8889 ins_cost(VOLATILE_REF_COST);
8890 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]" %}
8891 ins_encode %{
8892 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
8893 %}
8894 ins_pipe(pipe_serial);
8895 %}
8896
8897 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev) %{
8898 predicate(needs_acquiring_load_exclusive(n));
8899 match(Set prev (GetAndSetL mem newv));
8900 ins_cost(VOLATILE_REF_COST);
8901 format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %}
8902 ins_encode %{
8903 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
8904 %}
8905 ins_pipe(pipe_serial);
8906 %}
8907
8908 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev) %{
8909 predicate(needs_acquiring_load_exclusive(n));
8910 match(Set prev (GetAndSetN mem newv));
8911 ins_cost(VOLATILE_REF_COST);
8912 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]" %}
8913 ins_encode %{
8914 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
8915 %}
8916 ins_pipe(pipe_serial);
8917 %}
8918
8919 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev) %{
8920 predicate(needs_acquiring_load_exclusive(n) && (n->as_LoadStore()->barrier_data() == 0));
8921 match(Set prev (GetAndSetP mem newv));
8922 ins_cost(VOLATILE_REF_COST);
8923 format %{ "atomic_xchg_acq $prev, $newv, [$mem]" %}
8924 ins_encode %{
8925 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
8926 %}
8927 ins_pipe(pipe_serial);
8928 %}
8929
8930
8931 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr) %{
8932 match(Set newval (GetAndAddL mem incr));
8933 ins_cost(2 * VOLATILE_REF_COST + 1);
8934 format %{ "get_and_addL $newval, [$mem], $incr" %}
8935 ins_encode %{
8936 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
8937 %}
8938 ins_pipe(pipe_serial);
8939 %}
8940
8941 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr) %{
8942 predicate(n->as_LoadStore()->result_not_used());
8943 match(Set dummy (GetAndAddL mem incr));
8944 ins_cost(2 * VOLATILE_REF_COST);
8945 format %{ "get_and_addL [$mem], $incr" %}
8946 ins_encode %{
8947 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
8948 %}
8949 ins_pipe(pipe_serial);
8950 %}
8951
8952 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAddSub incr) %{
8953 match(Set newval (GetAndAddL mem incr));
8954 ins_cost(2 * VOLATILE_REF_COST + 1);
8955 format %{ "get_and_addL $newval, [$mem], $incr" %}
8956 ins_encode %{
8957 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
8958 %}
8959 ins_pipe(pipe_serial);
8960 %}
8961
8962 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAddSub incr) %{
8963 predicate(n->as_LoadStore()->result_not_used());
8964 match(Set dummy (GetAndAddL mem incr));
8965 ins_cost(2 * VOLATILE_REF_COST);
8966 format %{ "get_and_addL [$mem], $incr" %}
8967 ins_encode %{
8968 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
8969 %}
8970 ins_pipe(pipe_serial);
8971 %}
8972
8973 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{
8974 match(Set newval (GetAndAddI mem incr));
8975 ins_cost(2 * VOLATILE_REF_COST + 1);
8976 format %{ "get_and_addI $newval, [$mem], $incr" %}
8977 ins_encode %{
8978 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
8979 %}
8980 ins_pipe(pipe_serial);
8981 %}
8982
8983 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr) %{
8984 predicate(n->as_LoadStore()->result_not_used());
8985 match(Set dummy (GetAndAddI mem incr));
8986 ins_cost(2 * VOLATILE_REF_COST);
8987 format %{ "get_and_addI [$mem], $incr" %}
8988 ins_encode %{
8989 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
8990 %}
8991 ins_pipe(pipe_serial);
8992 %}
8993
8994 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAddSub incr) %{
8995 match(Set newval (GetAndAddI mem incr));
8996 ins_cost(2 * VOLATILE_REF_COST + 1);
8997 format %{ "get_and_addI $newval, [$mem], $incr" %}
8998 ins_encode %{
8999 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
9000 %}
9001 ins_pipe(pipe_serial);
9002 %}
9003
9004 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAddSub incr) %{
9005 predicate(n->as_LoadStore()->result_not_used());
9006 match(Set dummy (GetAndAddI mem incr));
9007 ins_cost(2 * VOLATILE_REF_COST);
9008 format %{ "get_and_addI [$mem], $incr" %}
9009 ins_encode %{
9010 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
9011 %}
9012 ins_pipe(pipe_serial);
9013 %}
9014
9015 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr) %{
9016 predicate(needs_acquiring_load_exclusive(n));
9017 match(Set newval (GetAndAddL mem incr));
9018 ins_cost(VOLATILE_REF_COST + 1);
9019 format %{ "get_and_addL_acq $newval, [$mem], $incr" %}
9020 ins_encode %{
9021 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
9022 %}
9023 ins_pipe(pipe_serial);
9024 %}
9025
9026 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
9027 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
9028 match(Set dummy (GetAndAddL mem incr));
9029 ins_cost(VOLATILE_REF_COST);
9030 format %{ "get_and_addL_acq [$mem], $incr" %}
9031 ins_encode %{
9032 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
9033 %}
9034 ins_pipe(pipe_serial);
9035 %}
9036
9037 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAddSub incr) %{
9038 predicate(needs_acquiring_load_exclusive(n));
9039 match(Set newval (GetAndAddL mem incr));
9040 ins_cost(VOLATILE_REF_COST + 1);
9041 format %{ "get_and_addL_acq $newval, [$mem], $incr" %}
9042 ins_encode %{
9043 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
9044 %}
9045 ins_pipe(pipe_serial);
9046 %}
9047
9048 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAddSub incr) %{
9049 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
9050 match(Set dummy (GetAndAddL mem incr));
9051 ins_cost(VOLATILE_REF_COST);
9052 format %{ "get_and_addL_acq [$mem], $incr" %}
9053 ins_encode %{
9054 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
9055 %}
9056 ins_pipe(pipe_serial);
9057 %}
9058
9059 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr) %{
9060 predicate(needs_acquiring_load_exclusive(n));
9061 match(Set newval (GetAndAddI mem incr));
9062 ins_cost(VOLATILE_REF_COST + 1);
9063 format %{ "get_and_addI_acq $newval, [$mem], $incr" %}
9064 ins_encode %{
9065 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
9066 %}
9067 ins_pipe(pipe_serial);
9068 %}
9069
9070 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr) %{
9071 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
9072 match(Set dummy (GetAndAddI mem incr));
9073 ins_cost(VOLATILE_REF_COST);
9074 format %{ "get_and_addI_acq [$mem], $incr" %}
9075 ins_encode %{
9076 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
9077 %}
9078 ins_pipe(pipe_serial);
9079 %}
9080
9081 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAddSub incr) %{
9082 predicate(needs_acquiring_load_exclusive(n));
9083 match(Set newval (GetAndAddI mem incr));
9084 ins_cost(VOLATILE_REF_COST + 1);
9085 format %{ "get_and_addI_acq $newval, [$mem], $incr" %}
9086 ins_encode %{
9087 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
9088 %}
9089 ins_pipe(pipe_serial);
9090 %}
9091
9092 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAddSub incr) %{
9093 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_exclusive(n));
9094 match(Set dummy (GetAndAddI mem incr));
9095 ins_cost(VOLATILE_REF_COST);
9096 format %{ "get_and_addI_acq [$mem], $incr" %}
9097 ins_encode %{
9098 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
9099 %}
9100 ins_pipe(pipe_serial);
9101 %}
9102
9103 // Manifest a CmpU result in an integer register.
9104 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
9105 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg flags)
9106 %{
9107 match(Set dst (CmpU3 src1 src2));
9108 effect(KILL flags);
9109
9110 ins_cost(INSN_COST * 3);
9111 format %{
9112 "cmpw $src1, $src2\n\t"
9113 "csetw $dst, ne\n\t"
9114 "cnegw $dst, lo\t# CmpU3(reg)"
9115 %}
9116 ins_encode %{
9117 __ cmpw($src1$$Register, $src2$$Register);
9118 __ csetw($dst$$Register, Assembler::NE);
9119 __ cnegw($dst$$Register, $dst$$Register, Assembler::LO);
9120 %}
9121
9122 ins_pipe(pipe_class_default);
9123 %}
9124
9125 instruct cmpU3_reg_imm(iRegINoSp dst, iRegI src1, immIAddSub src2, rFlagsReg flags)
9126 %{
9127 match(Set dst (CmpU3 src1 src2));
9128 effect(KILL flags);
9129
9130 ins_cost(INSN_COST * 3);
9131 format %{
9132 "subsw zr, $src1, $src2\n\t"
9133 "csetw $dst, ne\n\t"
9134 "cnegw $dst, lo\t# CmpU3(imm)"
9135 %}
9136 ins_encode %{
9137 __ subsw(zr, $src1$$Register, (int32_t)$src2$$constant);
9138 __ csetw($dst$$Register, Assembler::NE);
9139 __ cnegw($dst$$Register, $dst$$Register, Assembler::LO);
9140 %}
9141
9142 ins_pipe(pipe_class_default);
9143 %}
9144
9145 // Manifest a CmpUL result in an integer register.
9146 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
9147 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL src1, iRegL src2, rFlagsReg flags)
9148 %{
9149 match(Set dst (CmpUL3 src1 src2));
9150 effect(KILL flags);
9151
9152 ins_cost(INSN_COST * 3);
9153 format %{
9154 "cmp $src1, $src2\n\t"
9155 "csetw $dst, ne\n\t"
9156 "cnegw $dst, lo\t# CmpUL3(reg)"
9157 %}
9158 ins_encode %{
9159 __ cmp($src1$$Register, $src2$$Register);
9160 __ csetw($dst$$Register, Assembler::NE);
9161 __ cnegw($dst$$Register, $dst$$Register, Assembler::LO);
9162 %}
9163
9164 ins_pipe(pipe_class_default);
9165 %}
9166
9167 instruct cmpUL3_reg_imm(iRegINoSp dst, iRegL src1, immLAddSub src2, rFlagsReg flags)
9168 %{
9169 match(Set dst (CmpUL3 src1 src2));
9170 effect(KILL flags);
9171
9172 ins_cost(INSN_COST * 3);
9173 format %{
9174 "subs zr, $src1, $src2\n\t"
9175 "csetw $dst, ne\n\t"
9176 "cnegw $dst, lo\t# CmpUL3(imm)"
9177 %}
9178 ins_encode %{
9179 __ subs(zr, $src1$$Register, (int32_t)$src2$$constant);
9180 __ csetw($dst$$Register, Assembler::NE);
9181 __ cnegw($dst$$Register, $dst$$Register, Assembler::LO);
9182 %}
9183
9184 ins_pipe(pipe_class_default);
9185 %}
9186
9187 // Manifest a CmpL result in an integer register.
9188 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
9189 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL src1, iRegL src2, rFlagsReg flags)
9190 %{
9191 match(Set dst (CmpL3 src1 src2));
9192 effect(KILL flags);
9193
9194 ins_cost(INSN_COST * 3);
9195 format %{
9196 "cmp $src1, $src2\n\t"
9197 "csetw $dst, ne\n\t"
9198 "cnegw $dst, lt\t# CmpL3(reg)"
9199 %}
9200 ins_encode %{
9201 __ cmp($src1$$Register, $src2$$Register);
9202 __ csetw($dst$$Register, Assembler::NE);
9203 __ cnegw($dst$$Register, $dst$$Register, Assembler::LT);
9204 %}
9205
9206 ins_pipe(pipe_class_default);
9207 %}
9208
9209 instruct cmpL3_reg_imm(iRegINoSp dst, iRegL src1, immLAddSub src2, rFlagsReg flags)
9210 %{
9211 match(Set dst (CmpL3 src1 src2));
9212 effect(KILL flags);
9213
9214 ins_cost(INSN_COST * 3);
9215 format %{
9216 "subs zr, $src1, $src2\n\t"
9217 "csetw $dst, ne\n\t"
9218 "cnegw $dst, lt\t# CmpL3(imm)"
9219 %}
9220 ins_encode %{
9221 __ subs(zr, $src1$$Register, (int32_t)$src2$$constant);
9222 __ csetw($dst$$Register, Assembler::NE);
9223 __ cnegw($dst$$Register, $dst$$Register, Assembler::LT);
9224 %}
9225
9226 ins_pipe(pipe_class_default);
9227 %}
9228
9229 // ============================================================================
9230 // Conditional Move Instructions
9231
9232 // n.b. we have identical rules for both a signed compare op (cmpOp)
9233 // and an unsigned compare op (cmpOpU). it would be nice if we could
9234 // define an op class which merged both inputs and use it to type the
9235 // argument to a single rule. unfortunatelyt his fails because the
9236 // opclass does not live up to the COND_INTER interface of its
9237 // component operands. When the generic code tries to negate the
9238 // operand it ends up running the generci Machoper::negate method
9239 // which throws a ShouldNotHappen. So, we have to provide two flavours
9240 // of each rule, one for a cmpOp and a second for a cmpOpU (sigh).
9241
9242 instruct cmovI_reg_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
9243 match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
9244
9245 ins_cost(INSN_COST * 2);
9246 format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, int" %}
9247
9248 ins_encode %{
9249 __ cselw(as_Register($dst$$reg),
9250 as_Register($src2$$reg),
9251 as_Register($src1$$reg),
9252 (Assembler::Condition)$cmp$$cmpcode);
9253 %}
9254
9255 ins_pipe(icond_reg_reg);
9256 %}
9257
9258 instruct cmovUI_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
9259 match(Set dst (CMoveI (Binary cmp cr) (Binary src1 src2)));
9260
9261 ins_cost(INSN_COST * 2);
9262 format %{ "cselw $dst, $src2, $src1 $cmp\t# unsigned, int" %}
9263
9264 ins_encode %{
9265 __ cselw(as_Register($dst$$reg),
9266 as_Register($src2$$reg),
9267 as_Register($src1$$reg),
9268 (Assembler::Condition)$cmp$$cmpcode);
9269 %}
9270
9271 ins_pipe(icond_reg_reg);
9272 %}
9273
9274 // special cases where one arg is zero
9275
9276 // n.b. this is selected in preference to the rule above because it
9277 // avoids loading constant 0 into a source register
9278
9279 // TODO
9280 // we ought only to be able to cull one of these variants as the ideal
9281 // transforms ought always to order the zero consistently (to left/right?)
9282
9283 instruct cmovI_zero_reg(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, iRegIorL2I src) %{
9284 match(Set dst (CMoveI (Binary cmp cr) (Binary zero src)));
9285
9286 ins_cost(INSN_COST * 2);
9287 format %{ "cselw $dst, $src, zr $cmp\t# signed, int" %}
9288
9289 ins_encode %{
9290 __ cselw(as_Register($dst$$reg),
9291 as_Register($src$$reg),
9292 zr,
9293 (Assembler::Condition)$cmp$$cmpcode);
9294 %}
9295
9296 ins_pipe(icond_reg);
9297 %}
9298
9299 instruct cmovUI_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, iRegIorL2I src) %{
9300 match(Set dst (CMoveI (Binary cmp cr) (Binary zero src)));
9301
9302 ins_cost(INSN_COST * 2);
9303 format %{ "cselw $dst, $src, zr $cmp\t# unsigned, int" %}
9304
9305 ins_encode %{
9306 __ cselw(as_Register($dst$$reg),
9307 as_Register($src$$reg),
9308 zr,
9309 (Assembler::Condition)$cmp$$cmpcode);
9310 %}
9311
9312 ins_pipe(icond_reg);
9313 %}
9314
9315 instruct cmovI_reg_zero(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
9316 match(Set dst (CMoveI (Binary cmp cr) (Binary src zero)));
9317
9318 ins_cost(INSN_COST * 2);
9319 format %{ "cselw $dst, zr, $src $cmp\t# signed, int" %}
9320
9321 ins_encode %{
9322 __ cselw(as_Register($dst$$reg),
9323 zr,
9324 as_Register($src$$reg),
9325 (Assembler::Condition)$cmp$$cmpcode);
9326 %}
9327
9328 ins_pipe(icond_reg);
9329 %}
9330
9331 instruct cmovUI_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
9332 match(Set dst (CMoveI (Binary cmp cr) (Binary src zero)));
9333
9334 ins_cost(INSN_COST * 2);
9335 format %{ "cselw $dst, zr, $src $cmp\t# unsigned, int" %}
9336
9337 ins_encode %{
9338 __ cselw(as_Register($dst$$reg),
9339 zr,
9340 as_Register($src$$reg),
9341 (Assembler::Condition)$cmp$$cmpcode);
9342 %}
9343
9344 ins_pipe(icond_reg);
9345 %}
9346
9347 // special case for creating a boolean 0 or 1
9348
9349 // n.b. this is selected in preference to the rule above because it
9350 // avoids loading constants 0 and 1 into a source register
9351
9352 instruct cmovI_reg_zero_one(cmpOp cmp, rFlagsReg cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
9353 match(Set dst (CMoveI (Binary cmp cr) (Binary one zero)));
9354
9355 ins_cost(INSN_COST * 2);
9356 format %{ "csincw $dst, zr, zr $cmp\t# signed, int" %}
9357
9358 ins_encode %{
9359 // equivalently
9360 // cset(as_Register($dst$$reg),
9361 // negate_condition((Assembler::Condition)$cmp$$cmpcode));
9362 __ csincw(as_Register($dst$$reg),
9363 zr,
9364 zr,
9365 (Assembler::Condition)$cmp$$cmpcode);
9366 %}
9367
9368 ins_pipe(icond_none);
9369 %}
9370
9371 instruct cmovUI_reg_zero_one(cmpOpU cmp, rFlagsRegU cr, iRegINoSp dst, immI0 zero, immI_1 one) %{
9372 match(Set dst (CMoveI (Binary cmp cr) (Binary one zero)));
9373
9374 ins_cost(INSN_COST * 2);
9375 format %{ "csincw $dst, zr, zr $cmp\t# unsigned, int" %}
9376
9377 ins_encode %{
9378 // equivalently
9379 // cset(as_Register($dst$$reg),
9380 // negate_condition((Assembler::Condition)$cmp$$cmpcode));
9381 __ csincw(as_Register($dst$$reg),
9382 zr,
9383 zr,
9384 (Assembler::Condition)$cmp$$cmpcode);
9385 %}
9386
9387 ins_pipe(icond_none);
9388 %}
9389
9390 instruct cmovL_reg_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
9391 match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
9392
9393 ins_cost(INSN_COST * 2);
9394 format %{ "csel $dst, $src2, $src1 $cmp\t# signed, long" %}
9395
9396 ins_encode %{
9397 __ csel(as_Register($dst$$reg),
9398 as_Register($src2$$reg),
9399 as_Register($src1$$reg),
9400 (Assembler::Condition)$cmp$$cmpcode);
9401 %}
9402
9403 ins_pipe(icond_reg_reg);
9404 %}
9405
9406 instruct cmovUL_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src1, iRegL src2) %{
9407 match(Set dst (CMoveL (Binary cmp cr) (Binary src1 src2)));
9408
9409 ins_cost(INSN_COST * 2);
9410 format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, long" %}
9411
9412 ins_encode %{
9413 __ csel(as_Register($dst$$reg),
9414 as_Register($src2$$reg),
9415 as_Register($src1$$reg),
9416 (Assembler::Condition)$cmp$$cmpcode);
9417 %}
9418
9419 ins_pipe(icond_reg_reg);
9420 %}
9421
9422 // special cases where one arg is zero
9423
9424 instruct cmovL_reg_zero(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, iRegL src, immL0 zero) %{
9425 match(Set dst (CMoveL (Binary cmp cr) (Binary src zero)));
9426
9427 ins_cost(INSN_COST * 2);
9428 format %{ "csel $dst, zr, $src $cmp\t# signed, long" %}
9429
9430 ins_encode %{
9431 __ csel(as_Register($dst$$reg),
9432 zr,
9433 as_Register($src$$reg),
9434 (Assembler::Condition)$cmp$$cmpcode);
9435 %}
9436
9437 ins_pipe(icond_reg);
9438 %}
9439
9440 instruct cmovUL_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, iRegL src, immL0 zero) %{
9441 match(Set dst (CMoveL (Binary cmp cr) (Binary src zero)));
9442
9443 ins_cost(INSN_COST * 2);
9444 format %{ "csel $dst, zr, $src $cmp\t# unsigned, long" %}
9445
9446 ins_encode %{
9447 __ csel(as_Register($dst$$reg),
9448 zr,
9449 as_Register($src$$reg),
9450 (Assembler::Condition)$cmp$$cmpcode);
9451 %}
9452
9453 ins_pipe(icond_reg);
9454 %}
9455
9456 instruct cmovL_zero_reg(cmpOp cmp, rFlagsReg cr, iRegLNoSp dst, immL0 zero, iRegL src) %{
9457 match(Set dst (CMoveL (Binary cmp cr) (Binary zero src)));
9458
9459 ins_cost(INSN_COST * 2);
9460 format %{ "csel $dst, $src, zr $cmp\t# signed, long" %}
9461
9462 ins_encode %{
9463 __ csel(as_Register($dst$$reg),
9464 as_Register($src$$reg),
9465 zr,
9466 (Assembler::Condition)$cmp$$cmpcode);
9467 %}
9468
9469 ins_pipe(icond_reg);
9470 %}
9471
9472 instruct cmovUL_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegLNoSp dst, immL0 zero, iRegL src) %{
9473 match(Set dst (CMoveL (Binary cmp cr) (Binary zero src)));
9474
9475 ins_cost(INSN_COST * 2);
9476 format %{ "csel $dst, $src, zr $cmp\t# unsigned, long" %}
9477
9478 ins_encode %{
9479 __ csel(as_Register($dst$$reg),
9480 as_Register($src$$reg),
9481 zr,
9482 (Assembler::Condition)$cmp$$cmpcode);
9483 %}
9484
9485 ins_pipe(icond_reg);
9486 %}
9487
9488 instruct cmovP_reg_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
9489 match(Set dst (CMoveP (Binary cmp cr) (Binary src1 src2)));
9490
9491 ins_cost(INSN_COST * 2);
9492 format %{ "csel $dst, $src2, $src1 $cmp\t# signed, ptr" %}
9493
9494 ins_encode %{
9495 __ csel(as_Register($dst$$reg),
9496 as_Register($src2$$reg),
9497 as_Register($src1$$reg),
9498 (Assembler::Condition)$cmp$$cmpcode);
9499 %}
9500
9501 ins_pipe(icond_reg_reg);
9502 %}
9503
9504 instruct cmovUP_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src1, iRegP src2) %{
9505 match(Set dst (CMoveP (Binary cmp cr) (Binary src1 src2)));
9506
9507 ins_cost(INSN_COST * 2);
9508 format %{ "csel $dst, $src2, $src1 $cmp\t# unsigned, ptr" %}
9509
9510 ins_encode %{
9511 __ csel(as_Register($dst$$reg),
9512 as_Register($src2$$reg),
9513 as_Register($src1$$reg),
9514 (Assembler::Condition)$cmp$$cmpcode);
9515 %}
9516
9517 ins_pipe(icond_reg_reg);
9518 %}
9519
9520 // special cases where one arg is zero
9521
9522 instruct cmovP_reg_zero(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, iRegP src, immP0 zero) %{
9523 match(Set dst (CMoveP (Binary cmp cr) (Binary src zero)));
9524
9525 ins_cost(INSN_COST * 2);
9526 format %{ "csel $dst, zr, $src $cmp\t# signed, ptr" %}
9527
9528 ins_encode %{
9529 __ csel(as_Register($dst$$reg),
9530 zr,
9531 as_Register($src$$reg),
9532 (Assembler::Condition)$cmp$$cmpcode);
9533 %}
9534
9535 ins_pipe(icond_reg);
9536 %}
9537
9538 instruct cmovUP_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, iRegP src, immP0 zero) %{
9539 match(Set dst (CMoveP (Binary cmp cr) (Binary src zero)));
9540
9541 ins_cost(INSN_COST * 2);
9542 format %{ "csel $dst, zr, $src $cmp\t# unsigned, ptr" %}
9543
9544 ins_encode %{
9545 __ csel(as_Register($dst$$reg),
9546 zr,
9547 as_Register($src$$reg),
9548 (Assembler::Condition)$cmp$$cmpcode);
9549 %}
9550
9551 ins_pipe(icond_reg);
9552 %}
9553
9554 instruct cmovP_zero_reg(cmpOp cmp, rFlagsReg cr, iRegPNoSp dst, immP0 zero, iRegP src) %{
9555 match(Set dst (CMoveP (Binary cmp cr) (Binary zero src)));
9556
9557 ins_cost(INSN_COST * 2);
9558 format %{ "csel $dst, $src, zr $cmp\t# signed, ptr" %}
9559
9560 ins_encode %{
9561 __ csel(as_Register($dst$$reg),
9562 as_Register($src$$reg),
9563 zr,
9564 (Assembler::Condition)$cmp$$cmpcode);
9565 %}
9566
9567 ins_pipe(icond_reg);
9568 %}
9569
9570 instruct cmovUP_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegPNoSp dst, immP0 zero, iRegP src) %{
9571 match(Set dst (CMoveP (Binary cmp cr) (Binary zero src)));
9572
9573 ins_cost(INSN_COST * 2);
9574 format %{ "csel $dst, $src, zr $cmp\t# unsigned, ptr" %}
9575
9576 ins_encode %{
9577 __ csel(as_Register($dst$$reg),
9578 as_Register($src$$reg),
9579 zr,
9580 (Assembler::Condition)$cmp$$cmpcode);
9581 %}
9582
9583 ins_pipe(icond_reg);
9584 %}
9585
9586 instruct cmovN_reg_reg(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, iRegN src1, iRegN src2) %{
9587 match(Set dst (CMoveN (Binary cmp cr) (Binary src1 src2)));
9588
9589 ins_cost(INSN_COST * 2);
9590 format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, compressed ptr" %}
9591
9592 ins_encode %{
9593 __ cselw(as_Register($dst$$reg),
9594 as_Register($src2$$reg),
9595 as_Register($src1$$reg),
9596 (Assembler::Condition)$cmp$$cmpcode);
9597 %}
9598
9599 ins_pipe(icond_reg_reg);
9600 %}
9601
9602 instruct cmovUN_reg_reg(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, iRegN src1, iRegN src2) %{
9603 match(Set dst (CMoveN (Binary cmp cr) (Binary src1 src2)));
9604
9605 ins_cost(INSN_COST * 2);
9606 format %{ "cselw $dst, $src2, $src1 $cmp\t# signed, compressed ptr" %}
9607
9608 ins_encode %{
9609 __ cselw(as_Register($dst$$reg),
9610 as_Register($src2$$reg),
9611 as_Register($src1$$reg),
9612 (Assembler::Condition)$cmp$$cmpcode);
9613 %}
9614
9615 ins_pipe(icond_reg_reg);
9616 %}
9617
9618 // special cases where one arg is zero
9619
9620 instruct cmovN_reg_zero(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, iRegN src, immN0 zero) %{
9621 match(Set dst (CMoveN (Binary cmp cr) (Binary src zero)));
9622
9623 ins_cost(INSN_COST * 2);
9624 format %{ "cselw $dst, zr, $src $cmp\t# signed, compressed ptr" %}
9625
9626 ins_encode %{
9627 __ cselw(as_Register($dst$$reg),
9628 zr,
9629 as_Register($src$$reg),
9630 (Assembler::Condition)$cmp$$cmpcode);
9631 %}
9632
9633 ins_pipe(icond_reg);
9634 %}
9635
9636 instruct cmovUN_reg_zero(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, iRegN src, immN0 zero) %{
9637 match(Set dst (CMoveN (Binary cmp cr) (Binary src zero)));
9638
9639 ins_cost(INSN_COST * 2);
9640 format %{ "cselw $dst, zr, $src $cmp\t# unsigned, compressed ptr" %}
9641
9642 ins_encode %{
9643 __ cselw(as_Register($dst$$reg),
9644 zr,
9645 as_Register($src$$reg),
9646 (Assembler::Condition)$cmp$$cmpcode);
9647 %}
9648
9649 ins_pipe(icond_reg);
9650 %}
9651
9652 instruct cmovN_zero_reg(cmpOp cmp, rFlagsReg cr, iRegNNoSp dst, immN0 zero, iRegN src) %{
9653 match(Set dst (CMoveN (Binary cmp cr) (Binary zero src)));
9654
9655 ins_cost(INSN_COST * 2);
9656 format %{ "cselw $dst, $src, zr $cmp\t# signed, compressed ptr" %}
9657
9658 ins_encode %{
9659 __ cselw(as_Register($dst$$reg),
9660 as_Register($src$$reg),
9661 zr,
9662 (Assembler::Condition)$cmp$$cmpcode);
9663 %}
9664
9665 ins_pipe(icond_reg);
9666 %}
9667
9668 instruct cmovUN_zero_reg(cmpOpU cmp, rFlagsRegU cr, iRegNNoSp dst, immN0 zero, iRegN src) %{
9669 match(Set dst (CMoveN (Binary cmp cr) (Binary zero src)));
9670
9671 ins_cost(INSN_COST * 2);
9672 format %{ "cselw $dst, $src, zr $cmp\t# unsigned, compressed ptr" %}
9673
9674 ins_encode %{
9675 __ cselw(as_Register($dst$$reg),
9676 as_Register($src$$reg),
9677 zr,
9678 (Assembler::Condition)$cmp$$cmpcode);
9679 %}
9680
9681 ins_pipe(icond_reg);
9682 %}
9683
9684 instruct cmovF_reg(cmpOp cmp, rFlagsReg cr, vRegF dst, vRegF src1, vRegF src2)
9685 %{
9686 match(Set dst (CMoveF (Binary cmp cr) (Binary src1 src2)));
9687
9688 ins_cost(INSN_COST * 3);
9689
9690 format %{ "fcsels $dst, $src1, $src2, $cmp\t# signed cmove float\n\t" %}
9691 ins_encode %{
9692 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
9693 __ fcsels(as_FloatRegister($dst$$reg),
9694 as_FloatRegister($src2$$reg),
9695 as_FloatRegister($src1$$reg),
9696 cond);
9697 %}
9698
9699 ins_pipe(fp_cond_reg_reg_s);
9700 %}
9701
9702 instruct cmovUF_reg(cmpOpU cmp, rFlagsRegU cr, vRegF dst, vRegF src1, vRegF src2)
9703 %{
9704 match(Set dst (CMoveF (Binary cmp cr) (Binary src1 src2)));
9705
9706 ins_cost(INSN_COST * 3);
9707
9708 format %{ "fcsels $dst, $src1, $src2, $cmp\t# unsigned cmove float\n\t" %}
9709 ins_encode %{
9710 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
9711 __ fcsels(as_FloatRegister($dst$$reg),
9712 as_FloatRegister($src2$$reg),
9713 as_FloatRegister($src1$$reg),
9714 cond);
9715 %}
9716
9717 ins_pipe(fp_cond_reg_reg_s);
9718 %}
9719
9720 instruct cmovD_reg(cmpOp cmp, rFlagsReg cr, vRegD dst, vRegD src1, vRegD src2)
9721 %{
9722 match(Set dst (CMoveD (Binary cmp cr) (Binary src1 src2)));
9723
9724 ins_cost(INSN_COST * 3);
9725
9726 format %{ "fcseld $dst, $src1, $src2, $cmp\t# signed cmove float\n\t" %}
9727 ins_encode %{
9728 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
9729 __ fcseld(as_FloatRegister($dst$$reg),
9730 as_FloatRegister($src2$$reg),
9731 as_FloatRegister($src1$$reg),
9732 cond);
9733 %}
9734
9735 ins_pipe(fp_cond_reg_reg_d);
9736 %}
9737
9738 instruct cmovUD_reg(cmpOpU cmp, rFlagsRegU cr, vRegD dst, vRegD src1, vRegD src2)
9739 %{
9740 match(Set dst (CMoveD (Binary cmp cr) (Binary src1 src2)));
9741
9742 ins_cost(INSN_COST * 3);
9743
9744 format %{ "fcseld $dst, $src1, $src2, $cmp\t# unsigned cmove float\n\t" %}
9745 ins_encode %{
9746 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
9747 __ fcseld(as_FloatRegister($dst$$reg),
9748 as_FloatRegister($src2$$reg),
9749 as_FloatRegister($src1$$reg),
9750 cond);
9751 %}
9752
9753 ins_pipe(fp_cond_reg_reg_d);
9754 %}
9755
9756 // ============================================================================
9757 // Arithmetic Instructions
9758 //
9759
9760 // Integer Addition
9761
9762 // TODO
9763 // these currently employ operations which do not set CR and hence are
9764 // not flagged as killing CR but we would like to isolate the cases
9765 // where we want to set flags from those where we don't. need to work
9766 // out how to do that.
9767
9768 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
9769 match(Set dst (AddI src1 src2));
9770
9771 ins_cost(INSN_COST);
9772 format %{ "addw $dst, $src1, $src2" %}
9773
9774 ins_encode %{
9775 __ addw(as_Register($dst$$reg),
9776 as_Register($src1$$reg),
9777 as_Register($src2$$reg));
9778 %}
9779
9780 ins_pipe(ialu_reg_reg);
9781 %}
9782
9783 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
9784 match(Set dst (AddI src1 src2));
9785
9786 ins_cost(INSN_COST);
9787 format %{ "addw $dst, $src1, $src2" %}
9788
9789 // use opcode to indicate that this is an add not a sub
9790 opcode(0x0);
9791
9792 ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
9793
9794 ins_pipe(ialu_reg_imm);
9795 %}
9796
9797 instruct addI_reg_imm_i2l(iRegINoSp dst, iRegL src1, immIAddSub src2) %{
9798 match(Set dst (AddI (ConvL2I src1) src2));
9799
9800 ins_cost(INSN_COST);
9801 format %{ "addw $dst, $src1, $src2" %}
9802
9803 // use opcode to indicate that this is an add not a sub
9804 opcode(0x0);
9805
9806 ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
9807
9808 ins_pipe(ialu_reg_imm);
9809 %}
9810
9811 // Pointer Addition
9812 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
9813 match(Set dst (AddP src1 src2));
9814
9815 ins_cost(INSN_COST);
9816 format %{ "add $dst, $src1, $src2\t# ptr" %}
9817
9818 ins_encode %{
9819 __ add(as_Register($dst$$reg),
9820 as_Register($src1$$reg),
9821 as_Register($src2$$reg));
9822 %}
9823
9824 ins_pipe(ialu_reg_reg);
9825 %}
9826
9827 instruct addP_reg_reg_ext(iRegPNoSp dst, iRegP src1, iRegIorL2I src2) %{
9828 match(Set dst (AddP src1 (ConvI2L src2)));
9829
9830 ins_cost(1.9 * INSN_COST);
9831 format %{ "add $dst, $src1, $src2, sxtw\t# ptr" %}
9832
9833 ins_encode %{
9834 __ add(as_Register($dst$$reg),
9835 as_Register($src1$$reg),
9836 as_Register($src2$$reg), ext::sxtw);
9837 %}
9838
9839 ins_pipe(ialu_reg_reg);
9840 %}
9841
9842 instruct addP_reg_reg_lsl(iRegPNoSp dst, iRegP src1, iRegL src2, immIScale scale) %{
9843 match(Set dst (AddP src1 (LShiftL src2 scale)));
9844
9845 ins_cost(1.9 * INSN_COST);
9846 format %{ "add $dst, $src1, $src2, LShiftL $scale\t# ptr" %}
9847
9848 ins_encode %{
9849 __ lea(as_Register($dst$$reg),
9850 Address(as_Register($src1$$reg), as_Register($src2$$reg),
9851 Address::lsl($scale$$constant)));
9852 %}
9853
9854 ins_pipe(ialu_reg_reg_shift);
9855 %}
9856
9857 instruct addP_reg_reg_ext_shift(iRegPNoSp dst, iRegP src1, iRegIorL2I src2, immIScale scale) %{
9858 match(Set dst (AddP src1 (LShiftL (ConvI2L src2) scale)));
9859
9860 ins_cost(1.9 * INSN_COST);
9861 format %{ "add $dst, $src1, $src2, I2L $scale\t# ptr" %}
9862
9863 ins_encode %{
9864 __ lea(as_Register($dst$$reg),
9865 Address(as_Register($src1$$reg), as_Register($src2$$reg),
9866 Address::sxtw($scale$$constant)));
9867 %}
9868
9869 ins_pipe(ialu_reg_reg_shift);
9870 %}
9871
9872 instruct lshift_ext(iRegLNoSp dst, iRegIorL2I src, immI scale, rFlagsReg cr) %{
9873 match(Set dst (LShiftL (ConvI2L src) scale));
9874
9875 ins_cost(INSN_COST);
9876 format %{ "sbfiz $dst, $src, $scale & 63, -$scale & 63\t" %}
9877
9878 ins_encode %{
9879 __ sbfiz(as_Register($dst$$reg),
9880 as_Register($src$$reg),
9881 $scale$$constant & 63, MIN2(32, (int)((-$scale$$constant) & 63)));
9882 %}
9883
9884 ins_pipe(ialu_reg_shift);
9885 %}
9886
9887 // Pointer Immediate Addition
9888 // n.b. this needs to be more expensive than using an indirect memory
9889 // operand
9890 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAddSub src2) %{
9891 match(Set dst (AddP src1 src2));
9892
9893 ins_cost(INSN_COST);
9894 format %{ "add $dst, $src1, $src2\t# ptr" %}
9895
9896 // use opcode to indicate that this is an add not a sub
9897 opcode(0x0);
9898
9899 ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
9900
9901 ins_pipe(ialu_reg_imm);
9902 %}
9903
9904 // Long Addition
9905 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
9906
9907 match(Set dst (AddL src1 src2));
9908
9909 ins_cost(INSN_COST);
9910 format %{ "add $dst, $src1, $src2" %}
9911
9912 ins_encode %{
9913 __ add(as_Register($dst$$reg),
9914 as_Register($src1$$reg),
9915 as_Register($src2$$reg));
9916 %}
9917
9918 ins_pipe(ialu_reg_reg);
9919 %}
9920
9921 // No constant pool entries requiredLong Immediate Addition.
9922 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
9923 match(Set dst (AddL src1 src2));
9924
9925 ins_cost(INSN_COST);
9926 format %{ "add $dst, $src1, $src2" %}
9927
9928 // use opcode to indicate that this is an add not a sub
9929 opcode(0x0);
9930
9931 ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
9932
9933 ins_pipe(ialu_reg_imm);
9934 %}
9935
9936 // Integer Subtraction
9937 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
9938 match(Set dst (SubI src1 src2));
9939
9940 ins_cost(INSN_COST);
9941 format %{ "subw $dst, $src1, $src2" %}
9942
9943 ins_encode %{
9944 __ subw(as_Register($dst$$reg),
9945 as_Register($src1$$reg),
9946 as_Register($src2$$reg));
9947 %}
9948
9949 ins_pipe(ialu_reg_reg);
9950 %}
9951
9952 // Immediate Subtraction
9953 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
9954 match(Set dst (SubI src1 src2));
9955
9956 ins_cost(INSN_COST);
9957 format %{ "subw $dst, $src1, $src2" %}
9958
9959 // use opcode to indicate that this is a sub not an add
9960 opcode(0x1);
9961
9962 ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
9963
9964 ins_pipe(ialu_reg_imm);
9965 %}
9966
9967 // Long Subtraction
9968 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
9969
9970 match(Set dst (SubL src1 src2));
9971
9972 ins_cost(INSN_COST);
9973 format %{ "sub $dst, $src1, $src2" %}
9974
9975 ins_encode %{
9976 __ sub(as_Register($dst$$reg),
9977 as_Register($src1$$reg),
9978 as_Register($src2$$reg));
9979 %}
9980
9981 ins_pipe(ialu_reg_reg);
9982 %}
9983
9984 // No constant pool entries requiredLong Immediate Subtraction.
9985 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
9986 match(Set dst (SubL src1 src2));
9987
9988 ins_cost(INSN_COST);
9989 format %{ "sub$dst, $src1, $src2" %}
9990
9991 // use opcode to indicate that this is a sub not an add
9992 opcode(0x1);
9993
9994 ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
9995
9996 ins_pipe(ialu_reg_imm);
9997 %}
9998
9999 // Integer Negation (special case for sub)
10000
10001 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr) %{
10002 match(Set dst (SubI zero src));
10003
10004 ins_cost(INSN_COST);
10005 format %{ "negw $dst, $src\t# int" %}
10006
10007 ins_encode %{
10008 __ negw(as_Register($dst$$reg),
10009 as_Register($src$$reg));
10010 %}
10011
10012 ins_pipe(ialu_reg);
10013 %}
10014
10015 // Long Negation
10016
10017 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero, rFlagsReg cr) %{
10018 match(Set dst (SubL zero src));
10019
10020 ins_cost(INSN_COST);
10021 format %{ "neg $dst, $src\t# long" %}
10022
10023 ins_encode %{
10024 __ neg(as_Register($dst$$reg),
10025 as_Register($src$$reg));
10026 %}
10027
10028 ins_pipe(ialu_reg);
10029 %}
10030
10031 // Integer Multiply
10032
10033 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10034 match(Set dst (MulI src1 src2));
10035
10036 ins_cost(INSN_COST * 3);
10037 format %{ "mulw $dst, $src1, $src2" %}
10038
10039 ins_encode %{
10040 __ mulw(as_Register($dst$$reg),
10041 as_Register($src1$$reg),
10042 as_Register($src2$$reg));
10043 %}
10044
10045 ins_pipe(imul_reg_reg);
10046 %}
10047
10048 instruct smulI(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10049 match(Set dst (MulL (ConvI2L src1) (ConvI2L src2)));
10050
10051 ins_cost(INSN_COST * 3);
10052 format %{ "smull $dst, $src1, $src2" %}
10053
10054 ins_encode %{
10055 __ smull(as_Register($dst$$reg),
10056 as_Register($src1$$reg),
10057 as_Register($src2$$reg));
10058 %}
10059
10060 ins_pipe(imul_reg_reg);
10061 %}
10062
10063 // Long Multiply
10064
10065 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10066 match(Set dst (MulL src1 src2));
10067
10068 ins_cost(INSN_COST * 5);
10069 format %{ "mul $dst, $src1, $src2" %}
10070
10071 ins_encode %{
10072 __ mul(as_Register($dst$$reg),
10073 as_Register($src1$$reg),
10074 as_Register($src2$$reg));
10075 %}
10076
10077 ins_pipe(lmul_reg_reg);
10078 %}
10079
10080 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr)
10081 %{
10082 match(Set dst (MulHiL src1 src2));
10083
10084 ins_cost(INSN_COST * 7);
10085 format %{ "smulh $dst, $src1, $src2\t# mulhi" %}
10086
10087 ins_encode %{
10088 __ smulh(as_Register($dst$$reg),
10089 as_Register($src1$$reg),
10090 as_Register($src2$$reg));
10091 %}
10092
10093 ins_pipe(lmul_reg_reg);
10094 %}
10095
10096 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr)
10097 %{
10098 match(Set dst (UMulHiL src1 src2));
10099
10100 ins_cost(INSN_COST * 7);
10101 format %{ "umulh $dst, $src1, $src2\t# umulhi" %}
10102
10103 ins_encode %{
10104 __ umulh(as_Register($dst$$reg),
10105 as_Register($src1$$reg),
10106 as_Register($src2$$reg));
10107 %}
10108
10109 ins_pipe(lmul_reg_reg);
10110 %}
10111
10112 // Combined Integer Multiply & Add/Sub
10113
10114 instruct maddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
10115 match(Set dst (AddI src3 (MulI src1 src2)));
10116
10117 ins_cost(INSN_COST * 3);
10118 format %{ "madd $dst, $src1, $src2, $src3" %}
10119
10120 ins_encode %{
10121 __ maddw(as_Register($dst$$reg),
10122 as_Register($src1$$reg),
10123 as_Register($src2$$reg),
10124 as_Register($src3$$reg));
10125 %}
10126
10127 ins_pipe(imac_reg_reg);
10128 %}
10129
10130 instruct msubI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3) %{
10131 match(Set dst (SubI src3 (MulI src1 src2)));
10132
10133 ins_cost(INSN_COST * 3);
10134 format %{ "msub $dst, $src1, $src2, $src3" %}
10135
10136 ins_encode %{
10137 __ msubw(as_Register($dst$$reg),
10138 as_Register($src1$$reg),
10139 as_Register($src2$$reg),
10140 as_Register($src3$$reg));
10141 %}
10142
10143 ins_pipe(imac_reg_reg);
10144 %}
10145
10146 // Combined Integer Multiply & Neg
10147
10148 instruct mnegI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI0 zero) %{
10149 match(Set dst (MulI (SubI zero src1) src2));
10150
10151 ins_cost(INSN_COST * 3);
10152 format %{ "mneg $dst, $src1, $src2" %}
10153
10154 ins_encode %{
10155 __ mnegw(as_Register($dst$$reg),
10156 as_Register($src1$$reg),
10157 as_Register($src2$$reg));
10158 %}
10159
10160 ins_pipe(imac_reg_reg);
10161 %}
10162
10163 // Combined Long Multiply & Add/Sub
10164
10165 instruct maddL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
10166 match(Set dst (AddL src3 (MulL src1 src2)));
10167
10168 ins_cost(INSN_COST * 5);
10169 format %{ "madd $dst, $src1, $src2, $src3" %}
10170
10171 ins_encode %{
10172 __ madd(as_Register($dst$$reg),
10173 as_Register($src1$$reg),
10174 as_Register($src2$$reg),
10175 as_Register($src3$$reg));
10176 %}
10177
10178 ins_pipe(lmac_reg_reg);
10179 %}
10180
10181 instruct msubL(iRegLNoSp dst, iRegL src1, iRegL src2, iRegL src3) %{
10182 match(Set dst (SubL src3 (MulL src1 src2)));
10183
10184 ins_cost(INSN_COST * 5);
10185 format %{ "msub $dst, $src1, $src2, $src3" %}
10186
10187 ins_encode %{
10188 __ msub(as_Register($dst$$reg),
10189 as_Register($src1$$reg),
10190 as_Register($src2$$reg),
10191 as_Register($src3$$reg));
10192 %}
10193
10194 ins_pipe(lmac_reg_reg);
10195 %}
10196
10197 // Combined Long Multiply & Neg
10198
10199 instruct mnegL(iRegLNoSp dst, iRegL src1, iRegL src2, immL0 zero) %{
10200 match(Set dst (MulL (SubL zero src1) src2));
10201
10202 ins_cost(INSN_COST * 5);
10203 format %{ "mneg $dst, $src1, $src2" %}
10204
10205 ins_encode %{
10206 __ mneg(as_Register($dst$$reg),
10207 as_Register($src1$$reg),
10208 as_Register($src2$$reg));
10209 %}
10210
10211 ins_pipe(lmac_reg_reg);
10212 %}
10213
10214 // Combine Integer Signed Multiply & Add/Sub/Neg Long
10215
10216 instruct smaddL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegLNoSp src3) %{
10217 match(Set dst (AddL src3 (MulL (ConvI2L src1) (ConvI2L src2))));
10218
10219 ins_cost(INSN_COST * 3);
10220 format %{ "smaddl $dst, $src1, $src2, $src3" %}
10221
10222 ins_encode %{
10223 __ smaddl(as_Register($dst$$reg),
10224 as_Register($src1$$reg),
10225 as_Register($src2$$reg),
10226 as_Register($src3$$reg));
10227 %}
10228
10229 ins_pipe(imac_reg_reg);
10230 %}
10231
10232 instruct smsubL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegLNoSp src3) %{
10233 match(Set dst (SubL src3 (MulL (ConvI2L src1) (ConvI2L src2))));
10234
10235 ins_cost(INSN_COST * 3);
10236 format %{ "smsubl $dst, $src1, $src2, $src3" %}
10237
10238 ins_encode %{
10239 __ smsubl(as_Register($dst$$reg),
10240 as_Register($src1$$reg),
10241 as_Register($src2$$reg),
10242 as_Register($src3$$reg));
10243 %}
10244
10245 ins_pipe(imac_reg_reg);
10246 %}
10247
10248 instruct smnegL(iRegLNoSp dst, iRegIorL2I src1, iRegIorL2I src2, immL0 zero) %{
10249 match(Set dst (MulL (SubL zero (ConvI2L src1)) (ConvI2L src2)));
10250
10251 ins_cost(INSN_COST * 3);
10252 format %{ "smnegl $dst, $src1, $src2" %}
10253
10254 ins_encode %{
10255 __ smnegl(as_Register($dst$$reg),
10256 as_Register($src1$$reg),
10257 as_Register($src2$$reg));
10258 %}
10259
10260 ins_pipe(imac_reg_reg);
10261 %}
10262
10263 // Combined Multiply-Add Shorts into Integer (dst = src1 * src2 + src3 * src4)
10264
10265 instruct muladdS2I(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, iRegIorL2I src3, iRegIorL2I src4) %{
10266 match(Set dst (MulAddS2I (Binary src1 src2) (Binary src3 src4)));
10267
10268 ins_cost(INSN_COST * 5);
10269 format %{ "mulw rscratch1, $src1, $src2\n\t"
10270 "maddw $dst, $src3, $src4, rscratch1" %}
10271
10272 ins_encode %{
10273 __ mulw(rscratch1, as_Register($src1$$reg), as_Register($src2$$reg));
10274 __ maddw(as_Register($dst$$reg), as_Register($src3$$reg), as_Register($src4$$reg), rscratch1); %}
10275
10276 ins_pipe(imac_reg_reg);
10277 %}
10278
10279 // Integer Divide
10280
10281 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10282 match(Set dst (DivI src1 src2));
10283
10284 ins_cost(INSN_COST * 19);
10285 format %{ "sdivw $dst, $src1, $src2" %}
10286
10287 ins_encode(aarch64_enc_divw(dst, src1, src2));
10288 ins_pipe(idiv_reg_reg);
10289 %}
10290
10291 // Long Divide
10292
10293 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10294 match(Set dst (DivL src1 src2));
10295
10296 ins_cost(INSN_COST * 35);
10297 format %{ "sdiv $dst, $src1, $src2" %}
10298
10299 ins_encode(aarch64_enc_div(dst, src1, src2));
10300 ins_pipe(ldiv_reg_reg);
10301 %}
10302
10303 // Integer Remainder
10304
10305 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10306 match(Set dst (ModI src1 src2));
10307
10308 ins_cost(INSN_COST * 22);
10309 format %{ "sdivw rscratch1, $src1, $src2\n\t"
10310 "msubw $dst, rscratch1, $src2, $src1" %}
10311
10312 ins_encode(aarch64_enc_modw(dst, src1, src2));
10313 ins_pipe(idiv_reg_reg);
10314 %}
10315
10316 // Long Remainder
10317
10318 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10319 match(Set dst (ModL src1 src2));
10320
10321 ins_cost(INSN_COST * 38);
10322 format %{ "sdiv rscratch1, $src1, $src2\n"
10323 "msub $dst, rscratch1, $src2, $src1" %}
10324
10325 ins_encode(aarch64_enc_mod(dst, src1, src2));
10326 ins_pipe(ldiv_reg_reg);
10327 %}
10328
10329 // Unsigned Integer Divide
10330
10331 instruct UdivI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10332 match(Set dst (UDivI src1 src2));
10333
10334 ins_cost(INSN_COST * 19);
10335 format %{ "udivw $dst, $src1, $src2" %}
10336
10337 ins_encode %{
10338 __ udivw($dst$$Register, $src1$$Register, $src2$$Register);
10339 %}
10340
10341 ins_pipe(idiv_reg_reg);
10342 %}
10343
10344 // Unsigned Long Divide
10345
10346 instruct UdivL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10347 match(Set dst (UDivL src1 src2));
10348
10349 ins_cost(INSN_COST * 35);
10350 format %{ "udiv $dst, $src1, $src2" %}
10351
10352 ins_encode %{
10353 __ udiv($dst$$Register, $src1$$Register, $src2$$Register);
10354 %}
10355
10356 ins_pipe(ldiv_reg_reg);
10357 %}
10358
10359 // Unsigned Integer Remainder
10360
10361 instruct UmodI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10362 match(Set dst (UModI src1 src2));
10363
10364 ins_cost(INSN_COST * 22);
10365 format %{ "udivw rscratch1, $src1, $src2\n\t"
10366 "msubw $dst, rscratch1, $src2, $src1" %}
10367
10368 ins_encode %{
10369 __ udivw(rscratch1, $src1$$Register, $src2$$Register);
10370 __ msubw($dst$$Register, rscratch1, $src2$$Register, $src1$$Register);
10371 %}
10372
10373 ins_pipe(idiv_reg_reg);
10374 %}
10375
10376 // Unsigned Long Remainder
10377
10378 instruct UModL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
10379 match(Set dst (UModL src1 src2));
10380
10381 ins_cost(INSN_COST * 38);
10382 format %{ "udiv rscratch1, $src1, $src2\n"
10383 "msub $dst, rscratch1, $src2, $src1" %}
10384
10385 ins_encode %{
10386 __ udiv(rscratch1, $src1$$Register, $src2$$Register);
10387 __ msub($dst$$Register, rscratch1, $src2$$Register, $src1$$Register);
10388 %}
10389
10390 ins_pipe(ldiv_reg_reg);
10391 %}
10392
10393 // Integer Shifts
10394
10395 // Shift Left Register
10396 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10397 match(Set dst (LShiftI src1 src2));
10398
10399 ins_cost(INSN_COST * 2);
10400 format %{ "lslvw $dst, $src1, $src2" %}
10401
10402 ins_encode %{
10403 __ lslvw(as_Register($dst$$reg),
10404 as_Register($src1$$reg),
10405 as_Register($src2$$reg));
10406 %}
10407
10408 ins_pipe(ialu_reg_reg_vshift);
10409 %}
10410
10411 // Shift Left Immediate
10412 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
10413 match(Set dst (LShiftI src1 src2));
10414
10415 ins_cost(INSN_COST);
10416 format %{ "lslw $dst, $src1, ($src2 & 0x1f)" %}
10417
10418 ins_encode %{
10419 __ lslw(as_Register($dst$$reg),
10420 as_Register($src1$$reg),
10421 $src2$$constant & 0x1f);
10422 %}
10423
10424 ins_pipe(ialu_reg_shift);
10425 %}
10426
10427 // Shift Right Logical Register
10428 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10429 match(Set dst (URShiftI src1 src2));
10430
10431 ins_cost(INSN_COST * 2);
10432 format %{ "lsrvw $dst, $src1, $src2" %}
10433
10434 ins_encode %{
10435 __ lsrvw(as_Register($dst$$reg),
10436 as_Register($src1$$reg),
10437 as_Register($src2$$reg));
10438 %}
10439
10440 ins_pipe(ialu_reg_reg_vshift);
10441 %}
10442
10443 // Shift Right Logical Immediate
10444 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
10445 match(Set dst (URShiftI src1 src2));
10446
10447 ins_cost(INSN_COST);
10448 format %{ "lsrw $dst, $src1, ($src2 & 0x1f)" %}
10449
10450 ins_encode %{
10451 __ lsrw(as_Register($dst$$reg),
10452 as_Register($src1$$reg),
10453 $src2$$constant & 0x1f);
10454 %}
10455
10456 ins_pipe(ialu_reg_shift);
10457 %}
10458
10459 // Shift Right Arithmetic Register
10460 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
10461 match(Set dst (RShiftI src1 src2));
10462
10463 ins_cost(INSN_COST * 2);
10464 format %{ "asrvw $dst, $src1, $src2" %}
10465
10466 ins_encode %{
10467 __ asrvw(as_Register($dst$$reg),
10468 as_Register($src1$$reg),
10469 as_Register($src2$$reg));
10470 %}
10471
10472 ins_pipe(ialu_reg_reg_vshift);
10473 %}
10474
10475 // Shift Right Arithmetic Immediate
10476 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
10477 match(Set dst (RShiftI src1 src2));
10478
10479 ins_cost(INSN_COST);
10480 format %{ "asrw $dst, $src1, ($src2 & 0x1f)" %}
10481
10482 ins_encode %{
10483 __ asrw(as_Register($dst$$reg),
10484 as_Register($src1$$reg),
10485 $src2$$constant & 0x1f);
10486 %}
10487
10488 ins_pipe(ialu_reg_shift);
10489 %}
10490
10491 // Combined Int Mask and Right Shift (using UBFM)
10492 // TODO
10493
10494 // Long Shifts
10495
10496 // Shift Left Register
10497 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
10498 match(Set dst (LShiftL src1 src2));
10499
10500 ins_cost(INSN_COST * 2);
10501 format %{ "lslv $dst, $src1, $src2" %}
10502
10503 ins_encode %{
10504 __ lslv(as_Register($dst$$reg),
10505 as_Register($src1$$reg),
10506 as_Register($src2$$reg));
10507 %}
10508
10509 ins_pipe(ialu_reg_reg_vshift);
10510 %}
10511
10512 // Shift Left Immediate
10513 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
10514 match(Set dst (LShiftL src1 src2));
10515
10516 ins_cost(INSN_COST);
10517 format %{ "lsl $dst, $src1, ($src2 & 0x3f)" %}
10518
10519 ins_encode %{
10520 __ lsl(as_Register($dst$$reg),
10521 as_Register($src1$$reg),
10522 $src2$$constant & 0x3f);
10523 %}
10524
10525 ins_pipe(ialu_reg_shift);
10526 %}
10527
10528 // Shift Right Logical Register
10529 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
10530 match(Set dst (URShiftL src1 src2));
10531
10532 ins_cost(INSN_COST * 2);
10533 format %{ "lsrv $dst, $src1, $src2" %}
10534
10535 ins_encode %{
10536 __ lsrv(as_Register($dst$$reg),
10537 as_Register($src1$$reg),
10538 as_Register($src2$$reg));
10539 %}
10540
10541 ins_pipe(ialu_reg_reg_vshift);
10542 %}
10543
10544 // Shift Right Logical Immediate
10545 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
10546 match(Set dst (URShiftL src1 src2));
10547
10548 ins_cost(INSN_COST);
10549 format %{ "lsr $dst, $src1, ($src2 & 0x3f)" %}
10550
10551 ins_encode %{
10552 __ lsr(as_Register($dst$$reg),
10553 as_Register($src1$$reg),
10554 $src2$$constant & 0x3f);
10555 %}
10556
10557 ins_pipe(ialu_reg_shift);
10558 %}
10559
10560 // A special-case pattern for card table stores.
10561 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
10562 match(Set dst (URShiftL (CastP2X src1) src2));
10563
10564 ins_cost(INSN_COST);
10565 format %{ "lsr $dst, p2x($src1), ($src2 & 0x3f)" %}
10566
10567 ins_encode %{
10568 __ lsr(as_Register($dst$$reg),
10569 as_Register($src1$$reg),
10570 $src2$$constant & 0x3f);
10571 %}
10572
10573 ins_pipe(ialu_reg_shift);
10574 %}
10575
10576 // Shift Right Arithmetic Register
10577 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
10578 match(Set dst (RShiftL src1 src2));
10579
10580 ins_cost(INSN_COST * 2);
10581 format %{ "asrv $dst, $src1, $src2" %}
10582
10583 ins_encode %{
10584 __ asrv(as_Register($dst$$reg),
10585 as_Register($src1$$reg),
10586 as_Register($src2$$reg));
10587 %}
10588
10589 ins_pipe(ialu_reg_reg_vshift);
10590 %}
10591
10592 // Shift Right Arithmetic Immediate
10593 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
10594 match(Set dst (RShiftL src1 src2));
10595
10596 ins_cost(INSN_COST);
10597 format %{ "asr $dst, $src1, ($src2 & 0x3f)" %}
10598
10599 ins_encode %{
10600 __ asr(as_Register($dst$$reg),
10601 as_Register($src1$$reg),
10602 $src2$$constant & 0x3f);
10603 %}
10604
10605 ins_pipe(ialu_reg_shift);
10606 %}
10607
10608 // BEGIN This section of the file is automatically generated. Do not edit --------------
10609 // This section is generated from aarch64_ad.m4
10610
10611 // This pattern is automatically generated from aarch64_ad.m4
10612 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10613 instruct regL_not_reg(iRegLNoSp dst,
10614 iRegL src1, immL_M1 m1,
10615 rFlagsReg cr) %{
10616 match(Set dst (XorL src1 m1));
10617 ins_cost(INSN_COST);
10618 format %{ "eon $dst, $src1, zr" %}
10619
10620 ins_encode %{
10621 __ eon(as_Register($dst$$reg),
10622 as_Register($src1$$reg),
10623 zr,
10624 Assembler::LSL, 0);
10625 %}
10626
10627 ins_pipe(ialu_reg);
10628 %}
10629
10630 // This pattern is automatically generated from aarch64_ad.m4
10631 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10632 instruct regI_not_reg(iRegINoSp dst,
10633 iRegIorL2I src1, immI_M1 m1,
10634 rFlagsReg cr) %{
10635 match(Set dst (XorI src1 m1));
10636 ins_cost(INSN_COST);
10637 format %{ "eonw $dst, $src1, zr" %}
10638
10639 ins_encode %{
10640 __ eonw(as_Register($dst$$reg),
10641 as_Register($src1$$reg),
10642 zr,
10643 Assembler::LSL, 0);
10644 %}
10645
10646 ins_pipe(ialu_reg);
10647 %}
10648
10649 // This pattern is automatically generated from aarch64_ad.m4
10650 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10651 instruct NegI_reg_URShift_reg(iRegINoSp dst,
10652 immI0 zero, iRegIorL2I src1, immI src2) %{
10653 match(Set dst (SubI zero (URShiftI src1 src2)));
10654
10655 ins_cost(1.9 * INSN_COST);
10656 format %{ "negw $dst, $src1, LSR $src2" %}
10657
10658 ins_encode %{
10659 __ negw(as_Register($dst$$reg), as_Register($src1$$reg),
10660 Assembler::LSR, $src2$$constant & 0x1f);
10661 %}
10662
10663 ins_pipe(ialu_reg_shift);
10664 %}
10665
10666 // This pattern is automatically generated from aarch64_ad.m4
10667 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10668 instruct NegI_reg_RShift_reg(iRegINoSp dst,
10669 immI0 zero, iRegIorL2I src1, immI src2) %{
10670 match(Set dst (SubI zero (RShiftI src1 src2)));
10671
10672 ins_cost(1.9 * INSN_COST);
10673 format %{ "negw $dst, $src1, ASR $src2" %}
10674
10675 ins_encode %{
10676 __ negw(as_Register($dst$$reg), as_Register($src1$$reg),
10677 Assembler::ASR, $src2$$constant & 0x1f);
10678 %}
10679
10680 ins_pipe(ialu_reg_shift);
10681 %}
10682
10683 // This pattern is automatically generated from aarch64_ad.m4
10684 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10685 instruct NegI_reg_LShift_reg(iRegINoSp dst,
10686 immI0 zero, iRegIorL2I src1, immI src2) %{
10687 match(Set dst (SubI zero (LShiftI src1 src2)));
10688
10689 ins_cost(1.9 * INSN_COST);
10690 format %{ "negw $dst, $src1, LSL $src2" %}
10691
10692 ins_encode %{
10693 __ negw(as_Register($dst$$reg), as_Register($src1$$reg),
10694 Assembler::LSL, $src2$$constant & 0x1f);
10695 %}
10696
10697 ins_pipe(ialu_reg_shift);
10698 %}
10699
10700 // This pattern is automatically generated from aarch64_ad.m4
10701 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10702 instruct NegL_reg_URShift_reg(iRegLNoSp dst,
10703 immL0 zero, iRegL src1, immI src2) %{
10704 match(Set dst (SubL zero (URShiftL src1 src2)));
10705
10706 ins_cost(1.9 * INSN_COST);
10707 format %{ "neg $dst, $src1, LSR $src2" %}
10708
10709 ins_encode %{
10710 __ neg(as_Register($dst$$reg), as_Register($src1$$reg),
10711 Assembler::LSR, $src2$$constant & 0x3f);
10712 %}
10713
10714 ins_pipe(ialu_reg_shift);
10715 %}
10716
10717 // This pattern is automatically generated from aarch64_ad.m4
10718 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10719 instruct NegL_reg_RShift_reg(iRegLNoSp dst,
10720 immL0 zero, iRegL src1, immI src2) %{
10721 match(Set dst (SubL zero (RShiftL src1 src2)));
10722
10723 ins_cost(1.9 * INSN_COST);
10724 format %{ "neg $dst, $src1, ASR $src2" %}
10725
10726 ins_encode %{
10727 __ neg(as_Register($dst$$reg), as_Register($src1$$reg),
10728 Assembler::ASR, $src2$$constant & 0x3f);
10729 %}
10730
10731 ins_pipe(ialu_reg_shift);
10732 %}
10733
10734 // This pattern is automatically generated from aarch64_ad.m4
10735 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10736 instruct NegL_reg_LShift_reg(iRegLNoSp dst,
10737 immL0 zero, iRegL src1, immI src2) %{
10738 match(Set dst (SubL zero (LShiftL src1 src2)));
10739
10740 ins_cost(1.9 * INSN_COST);
10741 format %{ "neg $dst, $src1, LSL $src2" %}
10742
10743 ins_encode %{
10744 __ neg(as_Register($dst$$reg), as_Register($src1$$reg),
10745 Assembler::LSL, $src2$$constant & 0x3f);
10746 %}
10747
10748 ins_pipe(ialu_reg_shift);
10749 %}
10750
10751 // This pattern is automatically generated from aarch64_ad.m4
10752 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10753 instruct AndI_reg_not_reg(iRegINoSp dst,
10754 iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1) %{
10755 match(Set dst (AndI src1 (XorI src2 m1)));
10756 ins_cost(INSN_COST);
10757 format %{ "bicw $dst, $src1, $src2" %}
10758
10759 ins_encode %{
10760 __ bicw(as_Register($dst$$reg),
10761 as_Register($src1$$reg),
10762 as_Register($src2$$reg),
10763 Assembler::LSL, 0);
10764 %}
10765
10766 ins_pipe(ialu_reg_reg);
10767 %}
10768
10769 // This pattern is automatically generated from aarch64_ad.m4
10770 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10771 instruct AndL_reg_not_reg(iRegLNoSp dst,
10772 iRegL src1, iRegL src2, immL_M1 m1) %{
10773 match(Set dst (AndL src1 (XorL src2 m1)));
10774 ins_cost(INSN_COST);
10775 format %{ "bic $dst, $src1, $src2" %}
10776
10777 ins_encode %{
10778 __ bic(as_Register($dst$$reg),
10779 as_Register($src1$$reg),
10780 as_Register($src2$$reg),
10781 Assembler::LSL, 0);
10782 %}
10783
10784 ins_pipe(ialu_reg_reg);
10785 %}
10786
10787 // This pattern is automatically generated from aarch64_ad.m4
10788 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10789 instruct OrI_reg_not_reg(iRegINoSp dst,
10790 iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1) %{
10791 match(Set dst (OrI src1 (XorI src2 m1)));
10792 ins_cost(INSN_COST);
10793 format %{ "ornw $dst, $src1, $src2" %}
10794
10795 ins_encode %{
10796 __ ornw(as_Register($dst$$reg),
10797 as_Register($src1$$reg),
10798 as_Register($src2$$reg),
10799 Assembler::LSL, 0);
10800 %}
10801
10802 ins_pipe(ialu_reg_reg);
10803 %}
10804
10805 // This pattern is automatically generated from aarch64_ad.m4
10806 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10807 instruct OrL_reg_not_reg(iRegLNoSp dst,
10808 iRegL src1, iRegL src2, immL_M1 m1) %{
10809 match(Set dst (OrL src1 (XorL src2 m1)));
10810 ins_cost(INSN_COST);
10811 format %{ "orn $dst, $src1, $src2" %}
10812
10813 ins_encode %{
10814 __ orn(as_Register($dst$$reg),
10815 as_Register($src1$$reg),
10816 as_Register($src2$$reg),
10817 Assembler::LSL, 0);
10818 %}
10819
10820 ins_pipe(ialu_reg_reg);
10821 %}
10822
10823 // This pattern is automatically generated from aarch64_ad.m4
10824 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10825 instruct XorI_reg_not_reg(iRegINoSp dst,
10826 iRegIorL2I src1, iRegIorL2I src2, immI_M1 m1) %{
10827 match(Set dst (XorI m1 (XorI src2 src1)));
10828 ins_cost(INSN_COST);
10829 format %{ "eonw $dst, $src1, $src2" %}
10830
10831 ins_encode %{
10832 __ eonw(as_Register($dst$$reg),
10833 as_Register($src1$$reg),
10834 as_Register($src2$$reg),
10835 Assembler::LSL, 0);
10836 %}
10837
10838 ins_pipe(ialu_reg_reg);
10839 %}
10840
10841 // This pattern is automatically generated from aarch64_ad.m4
10842 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10843 instruct XorL_reg_not_reg(iRegLNoSp dst,
10844 iRegL src1, iRegL src2, immL_M1 m1) %{
10845 match(Set dst (XorL m1 (XorL src2 src1)));
10846 ins_cost(INSN_COST);
10847 format %{ "eon $dst, $src1, $src2" %}
10848
10849 ins_encode %{
10850 __ eon(as_Register($dst$$reg),
10851 as_Register($src1$$reg),
10852 as_Register($src2$$reg),
10853 Assembler::LSL, 0);
10854 %}
10855
10856 ins_pipe(ialu_reg_reg);
10857 %}
10858
10859 // This pattern is automatically generated from aarch64_ad.m4
10860 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10861 // val & (-1 ^ (val >>> shift)) ==> bicw
10862 instruct AndI_reg_URShift_not_reg(iRegINoSp dst,
10863 iRegIorL2I src1, iRegIorL2I src2,
10864 immI src3, immI_M1 src4) %{
10865 match(Set dst (AndI src1 (XorI(URShiftI src2 src3) src4)));
10866 ins_cost(1.9 * INSN_COST);
10867 format %{ "bicw $dst, $src1, $src2, LSR $src3" %}
10868
10869 ins_encode %{
10870 __ bicw(as_Register($dst$$reg),
10871 as_Register($src1$$reg),
10872 as_Register($src2$$reg),
10873 Assembler::LSR,
10874 $src3$$constant & 0x1f);
10875 %}
10876
10877 ins_pipe(ialu_reg_reg_shift);
10878 %}
10879
10880 // This pattern is automatically generated from aarch64_ad.m4
10881 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10882 // val & (-1 ^ (val >>> shift)) ==> bic
10883 instruct AndL_reg_URShift_not_reg(iRegLNoSp dst,
10884 iRegL src1, iRegL src2,
10885 immI src3, immL_M1 src4) %{
10886 match(Set dst (AndL src1 (XorL(URShiftL src2 src3) src4)));
10887 ins_cost(1.9 * INSN_COST);
10888 format %{ "bic $dst, $src1, $src2, LSR $src3" %}
10889
10890 ins_encode %{
10891 __ bic(as_Register($dst$$reg),
10892 as_Register($src1$$reg),
10893 as_Register($src2$$reg),
10894 Assembler::LSR,
10895 $src3$$constant & 0x3f);
10896 %}
10897
10898 ins_pipe(ialu_reg_reg_shift);
10899 %}
10900
10901 // This pattern is automatically generated from aarch64_ad.m4
10902 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10903 // val & (-1 ^ (val >> shift)) ==> bicw
10904 instruct AndI_reg_RShift_not_reg(iRegINoSp dst,
10905 iRegIorL2I src1, iRegIorL2I src2,
10906 immI src3, immI_M1 src4) %{
10907 match(Set dst (AndI src1 (XorI(RShiftI src2 src3) src4)));
10908 ins_cost(1.9 * INSN_COST);
10909 format %{ "bicw $dst, $src1, $src2, ASR $src3" %}
10910
10911 ins_encode %{
10912 __ bicw(as_Register($dst$$reg),
10913 as_Register($src1$$reg),
10914 as_Register($src2$$reg),
10915 Assembler::ASR,
10916 $src3$$constant & 0x1f);
10917 %}
10918
10919 ins_pipe(ialu_reg_reg_shift);
10920 %}
10921
10922 // This pattern is automatically generated from aarch64_ad.m4
10923 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10924 // val & (-1 ^ (val >> shift)) ==> bic
10925 instruct AndL_reg_RShift_not_reg(iRegLNoSp dst,
10926 iRegL src1, iRegL src2,
10927 immI src3, immL_M1 src4) %{
10928 match(Set dst (AndL src1 (XorL(RShiftL src2 src3) src4)));
10929 ins_cost(1.9 * INSN_COST);
10930 format %{ "bic $dst, $src1, $src2, ASR $src3" %}
10931
10932 ins_encode %{
10933 __ bic(as_Register($dst$$reg),
10934 as_Register($src1$$reg),
10935 as_Register($src2$$reg),
10936 Assembler::ASR,
10937 $src3$$constant & 0x3f);
10938 %}
10939
10940 ins_pipe(ialu_reg_reg_shift);
10941 %}
10942
10943 // This pattern is automatically generated from aarch64_ad.m4
10944 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10945 // val & (-1 ^ (val ror shift)) ==> bicw
10946 instruct AndI_reg_RotateRight_not_reg(iRegINoSp dst,
10947 iRegIorL2I src1, iRegIorL2I src2,
10948 immI src3, immI_M1 src4) %{
10949 match(Set dst (AndI src1 (XorI(RotateRight src2 src3) src4)));
10950 ins_cost(1.9 * INSN_COST);
10951 format %{ "bicw $dst, $src1, $src2, ROR $src3" %}
10952
10953 ins_encode %{
10954 __ bicw(as_Register($dst$$reg),
10955 as_Register($src1$$reg),
10956 as_Register($src2$$reg),
10957 Assembler::ROR,
10958 $src3$$constant & 0x1f);
10959 %}
10960
10961 ins_pipe(ialu_reg_reg_shift);
10962 %}
10963
10964 // This pattern is automatically generated from aarch64_ad.m4
10965 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10966 // val & (-1 ^ (val ror shift)) ==> bic
10967 instruct AndL_reg_RotateRight_not_reg(iRegLNoSp dst,
10968 iRegL src1, iRegL src2,
10969 immI src3, immL_M1 src4) %{
10970 match(Set dst (AndL src1 (XorL(RotateRight src2 src3) src4)));
10971 ins_cost(1.9 * INSN_COST);
10972 format %{ "bic $dst, $src1, $src2, ROR $src3" %}
10973
10974 ins_encode %{
10975 __ bic(as_Register($dst$$reg),
10976 as_Register($src1$$reg),
10977 as_Register($src2$$reg),
10978 Assembler::ROR,
10979 $src3$$constant & 0x3f);
10980 %}
10981
10982 ins_pipe(ialu_reg_reg_shift);
10983 %}
10984
10985 // This pattern is automatically generated from aarch64_ad.m4
10986 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
10987 // val & (-1 ^ (val << shift)) ==> bicw
10988 instruct AndI_reg_LShift_not_reg(iRegINoSp dst,
10989 iRegIorL2I src1, iRegIorL2I src2,
10990 immI src3, immI_M1 src4) %{
10991 match(Set dst (AndI src1 (XorI(LShiftI src2 src3) src4)));
10992 ins_cost(1.9 * INSN_COST);
10993 format %{ "bicw $dst, $src1, $src2, LSL $src3" %}
10994
10995 ins_encode %{
10996 __ bicw(as_Register($dst$$reg),
10997 as_Register($src1$$reg),
10998 as_Register($src2$$reg),
10999 Assembler::LSL,
11000 $src3$$constant & 0x1f);
11001 %}
11002
11003 ins_pipe(ialu_reg_reg_shift);
11004 %}
11005
11006 // This pattern is automatically generated from aarch64_ad.m4
11007 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11008 // val & (-1 ^ (val << shift)) ==> bic
11009 instruct AndL_reg_LShift_not_reg(iRegLNoSp dst,
11010 iRegL src1, iRegL src2,
11011 immI src3, immL_M1 src4) %{
11012 match(Set dst (AndL src1 (XorL(LShiftL src2 src3) src4)));
11013 ins_cost(1.9 * INSN_COST);
11014 format %{ "bic $dst, $src1, $src2, LSL $src3" %}
11015
11016 ins_encode %{
11017 __ bic(as_Register($dst$$reg),
11018 as_Register($src1$$reg),
11019 as_Register($src2$$reg),
11020 Assembler::LSL,
11021 $src3$$constant & 0x3f);
11022 %}
11023
11024 ins_pipe(ialu_reg_reg_shift);
11025 %}
11026
11027 // This pattern is automatically generated from aarch64_ad.m4
11028 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11029 // val ^ (-1 ^ (val >>> shift)) ==> eonw
11030 instruct XorI_reg_URShift_not_reg(iRegINoSp dst,
11031 iRegIorL2I src1, iRegIorL2I src2,
11032 immI src3, immI_M1 src4) %{
11033 match(Set dst (XorI src4 (XorI(URShiftI src2 src3) src1)));
11034 ins_cost(1.9 * INSN_COST);
11035 format %{ "eonw $dst, $src1, $src2, LSR $src3" %}
11036
11037 ins_encode %{
11038 __ eonw(as_Register($dst$$reg),
11039 as_Register($src1$$reg),
11040 as_Register($src2$$reg),
11041 Assembler::LSR,
11042 $src3$$constant & 0x1f);
11043 %}
11044
11045 ins_pipe(ialu_reg_reg_shift);
11046 %}
11047
11048 // This pattern is automatically generated from aarch64_ad.m4
11049 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11050 // val ^ (-1 ^ (val >>> shift)) ==> eon
11051 instruct XorL_reg_URShift_not_reg(iRegLNoSp dst,
11052 iRegL src1, iRegL src2,
11053 immI src3, immL_M1 src4) %{
11054 match(Set dst (XorL src4 (XorL(URShiftL src2 src3) src1)));
11055 ins_cost(1.9 * INSN_COST);
11056 format %{ "eon $dst, $src1, $src2, LSR $src3" %}
11057
11058 ins_encode %{
11059 __ eon(as_Register($dst$$reg),
11060 as_Register($src1$$reg),
11061 as_Register($src2$$reg),
11062 Assembler::LSR,
11063 $src3$$constant & 0x3f);
11064 %}
11065
11066 ins_pipe(ialu_reg_reg_shift);
11067 %}
11068
11069 // This pattern is automatically generated from aarch64_ad.m4
11070 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11071 // val ^ (-1 ^ (val >> shift)) ==> eonw
11072 instruct XorI_reg_RShift_not_reg(iRegINoSp dst,
11073 iRegIorL2I src1, iRegIorL2I src2,
11074 immI src3, immI_M1 src4) %{
11075 match(Set dst (XorI src4 (XorI(RShiftI src2 src3) src1)));
11076 ins_cost(1.9 * INSN_COST);
11077 format %{ "eonw $dst, $src1, $src2, ASR $src3" %}
11078
11079 ins_encode %{
11080 __ eonw(as_Register($dst$$reg),
11081 as_Register($src1$$reg),
11082 as_Register($src2$$reg),
11083 Assembler::ASR,
11084 $src3$$constant & 0x1f);
11085 %}
11086
11087 ins_pipe(ialu_reg_reg_shift);
11088 %}
11089
11090 // This pattern is automatically generated from aarch64_ad.m4
11091 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11092 // val ^ (-1 ^ (val >> shift)) ==> eon
11093 instruct XorL_reg_RShift_not_reg(iRegLNoSp dst,
11094 iRegL src1, iRegL src2,
11095 immI src3, immL_M1 src4) %{
11096 match(Set dst (XorL src4 (XorL(RShiftL src2 src3) src1)));
11097 ins_cost(1.9 * INSN_COST);
11098 format %{ "eon $dst, $src1, $src2, ASR $src3" %}
11099
11100 ins_encode %{
11101 __ eon(as_Register($dst$$reg),
11102 as_Register($src1$$reg),
11103 as_Register($src2$$reg),
11104 Assembler::ASR,
11105 $src3$$constant & 0x3f);
11106 %}
11107
11108 ins_pipe(ialu_reg_reg_shift);
11109 %}
11110
11111 // This pattern is automatically generated from aarch64_ad.m4
11112 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11113 // val ^ (-1 ^ (val ror shift)) ==> eonw
11114 instruct XorI_reg_RotateRight_not_reg(iRegINoSp dst,
11115 iRegIorL2I src1, iRegIorL2I src2,
11116 immI src3, immI_M1 src4) %{
11117 match(Set dst (XorI src4 (XorI(RotateRight src2 src3) src1)));
11118 ins_cost(1.9 * INSN_COST);
11119 format %{ "eonw $dst, $src1, $src2, ROR $src3" %}
11120
11121 ins_encode %{
11122 __ eonw(as_Register($dst$$reg),
11123 as_Register($src1$$reg),
11124 as_Register($src2$$reg),
11125 Assembler::ROR,
11126 $src3$$constant & 0x1f);
11127 %}
11128
11129 ins_pipe(ialu_reg_reg_shift);
11130 %}
11131
11132 // This pattern is automatically generated from aarch64_ad.m4
11133 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11134 // val ^ (-1 ^ (val ror shift)) ==> eon
11135 instruct XorL_reg_RotateRight_not_reg(iRegLNoSp dst,
11136 iRegL src1, iRegL src2,
11137 immI src3, immL_M1 src4) %{
11138 match(Set dst (XorL src4 (XorL(RotateRight src2 src3) src1)));
11139 ins_cost(1.9 * INSN_COST);
11140 format %{ "eon $dst, $src1, $src2, ROR $src3" %}
11141
11142 ins_encode %{
11143 __ eon(as_Register($dst$$reg),
11144 as_Register($src1$$reg),
11145 as_Register($src2$$reg),
11146 Assembler::ROR,
11147 $src3$$constant & 0x3f);
11148 %}
11149
11150 ins_pipe(ialu_reg_reg_shift);
11151 %}
11152
11153 // This pattern is automatically generated from aarch64_ad.m4
11154 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11155 // val ^ (-1 ^ (val << shift)) ==> eonw
11156 instruct XorI_reg_LShift_not_reg(iRegINoSp dst,
11157 iRegIorL2I src1, iRegIorL2I src2,
11158 immI src3, immI_M1 src4) %{
11159 match(Set dst (XorI src4 (XorI(LShiftI src2 src3) src1)));
11160 ins_cost(1.9 * INSN_COST);
11161 format %{ "eonw $dst, $src1, $src2, LSL $src3" %}
11162
11163 ins_encode %{
11164 __ eonw(as_Register($dst$$reg),
11165 as_Register($src1$$reg),
11166 as_Register($src2$$reg),
11167 Assembler::LSL,
11168 $src3$$constant & 0x1f);
11169 %}
11170
11171 ins_pipe(ialu_reg_reg_shift);
11172 %}
11173
11174 // This pattern is automatically generated from aarch64_ad.m4
11175 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11176 // val ^ (-1 ^ (val << shift)) ==> eon
11177 instruct XorL_reg_LShift_not_reg(iRegLNoSp dst,
11178 iRegL src1, iRegL src2,
11179 immI src3, immL_M1 src4) %{
11180 match(Set dst (XorL src4 (XorL(LShiftL src2 src3) src1)));
11181 ins_cost(1.9 * INSN_COST);
11182 format %{ "eon $dst, $src1, $src2, LSL $src3" %}
11183
11184 ins_encode %{
11185 __ eon(as_Register($dst$$reg),
11186 as_Register($src1$$reg),
11187 as_Register($src2$$reg),
11188 Assembler::LSL,
11189 $src3$$constant & 0x3f);
11190 %}
11191
11192 ins_pipe(ialu_reg_reg_shift);
11193 %}
11194
11195 // This pattern is automatically generated from aarch64_ad.m4
11196 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11197 // val | (-1 ^ (val >>> shift)) ==> ornw
11198 instruct OrI_reg_URShift_not_reg(iRegINoSp dst,
11199 iRegIorL2I src1, iRegIorL2I src2,
11200 immI src3, immI_M1 src4) %{
11201 match(Set dst (OrI src1 (XorI(URShiftI src2 src3) src4)));
11202 ins_cost(1.9 * INSN_COST);
11203 format %{ "ornw $dst, $src1, $src2, LSR $src3" %}
11204
11205 ins_encode %{
11206 __ ornw(as_Register($dst$$reg),
11207 as_Register($src1$$reg),
11208 as_Register($src2$$reg),
11209 Assembler::LSR,
11210 $src3$$constant & 0x1f);
11211 %}
11212
11213 ins_pipe(ialu_reg_reg_shift);
11214 %}
11215
11216 // This pattern is automatically generated from aarch64_ad.m4
11217 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11218 // val | (-1 ^ (val >>> shift)) ==> orn
11219 instruct OrL_reg_URShift_not_reg(iRegLNoSp dst,
11220 iRegL src1, iRegL src2,
11221 immI src3, immL_M1 src4) %{
11222 match(Set dst (OrL src1 (XorL(URShiftL src2 src3) src4)));
11223 ins_cost(1.9 * INSN_COST);
11224 format %{ "orn $dst, $src1, $src2, LSR $src3" %}
11225
11226 ins_encode %{
11227 __ orn(as_Register($dst$$reg),
11228 as_Register($src1$$reg),
11229 as_Register($src2$$reg),
11230 Assembler::LSR,
11231 $src3$$constant & 0x3f);
11232 %}
11233
11234 ins_pipe(ialu_reg_reg_shift);
11235 %}
11236
11237 // This pattern is automatically generated from aarch64_ad.m4
11238 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11239 // val | (-1 ^ (val >> shift)) ==> ornw
11240 instruct OrI_reg_RShift_not_reg(iRegINoSp dst,
11241 iRegIorL2I src1, iRegIorL2I src2,
11242 immI src3, immI_M1 src4) %{
11243 match(Set dst (OrI src1 (XorI(RShiftI src2 src3) src4)));
11244 ins_cost(1.9 * INSN_COST);
11245 format %{ "ornw $dst, $src1, $src2, ASR $src3" %}
11246
11247 ins_encode %{
11248 __ ornw(as_Register($dst$$reg),
11249 as_Register($src1$$reg),
11250 as_Register($src2$$reg),
11251 Assembler::ASR,
11252 $src3$$constant & 0x1f);
11253 %}
11254
11255 ins_pipe(ialu_reg_reg_shift);
11256 %}
11257
11258 // This pattern is automatically generated from aarch64_ad.m4
11259 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11260 // val | (-1 ^ (val >> shift)) ==> orn
11261 instruct OrL_reg_RShift_not_reg(iRegLNoSp dst,
11262 iRegL src1, iRegL src2,
11263 immI src3, immL_M1 src4) %{
11264 match(Set dst (OrL src1 (XorL(RShiftL src2 src3) src4)));
11265 ins_cost(1.9 * INSN_COST);
11266 format %{ "orn $dst, $src1, $src2, ASR $src3" %}
11267
11268 ins_encode %{
11269 __ orn(as_Register($dst$$reg),
11270 as_Register($src1$$reg),
11271 as_Register($src2$$reg),
11272 Assembler::ASR,
11273 $src3$$constant & 0x3f);
11274 %}
11275
11276 ins_pipe(ialu_reg_reg_shift);
11277 %}
11278
11279 // This pattern is automatically generated from aarch64_ad.m4
11280 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11281 // val | (-1 ^ (val ror shift)) ==> ornw
11282 instruct OrI_reg_RotateRight_not_reg(iRegINoSp dst,
11283 iRegIorL2I src1, iRegIorL2I src2,
11284 immI src3, immI_M1 src4) %{
11285 match(Set dst (OrI src1 (XorI(RotateRight src2 src3) src4)));
11286 ins_cost(1.9 * INSN_COST);
11287 format %{ "ornw $dst, $src1, $src2, ROR $src3" %}
11288
11289 ins_encode %{
11290 __ ornw(as_Register($dst$$reg),
11291 as_Register($src1$$reg),
11292 as_Register($src2$$reg),
11293 Assembler::ROR,
11294 $src3$$constant & 0x1f);
11295 %}
11296
11297 ins_pipe(ialu_reg_reg_shift);
11298 %}
11299
11300 // This pattern is automatically generated from aarch64_ad.m4
11301 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11302 // val | (-1 ^ (val ror shift)) ==> orn
11303 instruct OrL_reg_RotateRight_not_reg(iRegLNoSp dst,
11304 iRegL src1, iRegL src2,
11305 immI src3, immL_M1 src4) %{
11306 match(Set dst (OrL src1 (XorL(RotateRight src2 src3) src4)));
11307 ins_cost(1.9 * INSN_COST);
11308 format %{ "orn $dst, $src1, $src2, ROR $src3" %}
11309
11310 ins_encode %{
11311 __ orn(as_Register($dst$$reg),
11312 as_Register($src1$$reg),
11313 as_Register($src2$$reg),
11314 Assembler::ROR,
11315 $src3$$constant & 0x3f);
11316 %}
11317
11318 ins_pipe(ialu_reg_reg_shift);
11319 %}
11320
11321 // This pattern is automatically generated from aarch64_ad.m4
11322 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11323 // val | (-1 ^ (val << shift)) ==> ornw
11324 instruct OrI_reg_LShift_not_reg(iRegINoSp dst,
11325 iRegIorL2I src1, iRegIorL2I src2,
11326 immI src3, immI_M1 src4) %{
11327 match(Set dst (OrI src1 (XorI(LShiftI src2 src3) src4)));
11328 ins_cost(1.9 * INSN_COST);
11329 format %{ "ornw $dst, $src1, $src2, LSL $src3" %}
11330
11331 ins_encode %{
11332 __ ornw(as_Register($dst$$reg),
11333 as_Register($src1$$reg),
11334 as_Register($src2$$reg),
11335 Assembler::LSL,
11336 $src3$$constant & 0x1f);
11337 %}
11338
11339 ins_pipe(ialu_reg_reg_shift);
11340 %}
11341
11342 // This pattern is automatically generated from aarch64_ad.m4
11343 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11344 // val | (-1 ^ (val << shift)) ==> orn
11345 instruct OrL_reg_LShift_not_reg(iRegLNoSp dst,
11346 iRegL src1, iRegL src2,
11347 immI src3, immL_M1 src4) %{
11348 match(Set dst (OrL src1 (XorL(LShiftL src2 src3) src4)));
11349 ins_cost(1.9 * INSN_COST);
11350 format %{ "orn $dst, $src1, $src2, LSL $src3" %}
11351
11352 ins_encode %{
11353 __ orn(as_Register($dst$$reg),
11354 as_Register($src1$$reg),
11355 as_Register($src2$$reg),
11356 Assembler::LSL,
11357 $src3$$constant & 0x3f);
11358 %}
11359
11360 ins_pipe(ialu_reg_reg_shift);
11361 %}
11362
11363 // This pattern is automatically generated from aarch64_ad.m4
11364 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11365 instruct AndI_reg_URShift_reg(iRegINoSp dst,
11366 iRegIorL2I src1, iRegIorL2I src2,
11367 immI src3) %{
11368 match(Set dst (AndI src1 (URShiftI src2 src3)));
11369
11370 ins_cost(1.9 * INSN_COST);
11371 format %{ "andw $dst, $src1, $src2, LSR $src3" %}
11372
11373 ins_encode %{
11374 __ andw(as_Register($dst$$reg),
11375 as_Register($src1$$reg),
11376 as_Register($src2$$reg),
11377 Assembler::LSR,
11378 $src3$$constant & 0x1f);
11379 %}
11380
11381 ins_pipe(ialu_reg_reg_shift);
11382 %}
11383
11384 // This pattern is automatically generated from aarch64_ad.m4
11385 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11386 instruct AndL_reg_URShift_reg(iRegLNoSp dst,
11387 iRegL src1, iRegL src2,
11388 immI src3) %{
11389 match(Set dst (AndL src1 (URShiftL src2 src3)));
11390
11391 ins_cost(1.9 * INSN_COST);
11392 format %{ "andr $dst, $src1, $src2, LSR $src3" %}
11393
11394 ins_encode %{
11395 __ andr(as_Register($dst$$reg),
11396 as_Register($src1$$reg),
11397 as_Register($src2$$reg),
11398 Assembler::LSR,
11399 $src3$$constant & 0x3f);
11400 %}
11401
11402 ins_pipe(ialu_reg_reg_shift);
11403 %}
11404
11405 // This pattern is automatically generated from aarch64_ad.m4
11406 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11407 instruct AndI_reg_RShift_reg(iRegINoSp dst,
11408 iRegIorL2I src1, iRegIorL2I src2,
11409 immI src3) %{
11410 match(Set dst (AndI src1 (RShiftI src2 src3)));
11411
11412 ins_cost(1.9 * INSN_COST);
11413 format %{ "andw $dst, $src1, $src2, ASR $src3" %}
11414
11415 ins_encode %{
11416 __ andw(as_Register($dst$$reg),
11417 as_Register($src1$$reg),
11418 as_Register($src2$$reg),
11419 Assembler::ASR,
11420 $src3$$constant & 0x1f);
11421 %}
11422
11423 ins_pipe(ialu_reg_reg_shift);
11424 %}
11425
11426 // This pattern is automatically generated from aarch64_ad.m4
11427 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11428 instruct AndL_reg_RShift_reg(iRegLNoSp dst,
11429 iRegL src1, iRegL src2,
11430 immI src3) %{
11431 match(Set dst (AndL src1 (RShiftL src2 src3)));
11432
11433 ins_cost(1.9 * INSN_COST);
11434 format %{ "andr $dst, $src1, $src2, ASR $src3" %}
11435
11436 ins_encode %{
11437 __ andr(as_Register($dst$$reg),
11438 as_Register($src1$$reg),
11439 as_Register($src2$$reg),
11440 Assembler::ASR,
11441 $src3$$constant & 0x3f);
11442 %}
11443
11444 ins_pipe(ialu_reg_reg_shift);
11445 %}
11446
11447 // This pattern is automatically generated from aarch64_ad.m4
11448 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11449 instruct AndI_reg_LShift_reg(iRegINoSp dst,
11450 iRegIorL2I src1, iRegIorL2I src2,
11451 immI src3) %{
11452 match(Set dst (AndI src1 (LShiftI src2 src3)));
11453
11454 ins_cost(1.9 * INSN_COST);
11455 format %{ "andw $dst, $src1, $src2, LSL $src3" %}
11456
11457 ins_encode %{
11458 __ andw(as_Register($dst$$reg),
11459 as_Register($src1$$reg),
11460 as_Register($src2$$reg),
11461 Assembler::LSL,
11462 $src3$$constant & 0x1f);
11463 %}
11464
11465 ins_pipe(ialu_reg_reg_shift);
11466 %}
11467
11468 // This pattern is automatically generated from aarch64_ad.m4
11469 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11470 instruct AndL_reg_LShift_reg(iRegLNoSp dst,
11471 iRegL src1, iRegL src2,
11472 immI src3) %{
11473 match(Set dst (AndL src1 (LShiftL src2 src3)));
11474
11475 ins_cost(1.9 * INSN_COST);
11476 format %{ "andr $dst, $src1, $src2, LSL $src3" %}
11477
11478 ins_encode %{
11479 __ andr(as_Register($dst$$reg),
11480 as_Register($src1$$reg),
11481 as_Register($src2$$reg),
11482 Assembler::LSL,
11483 $src3$$constant & 0x3f);
11484 %}
11485
11486 ins_pipe(ialu_reg_reg_shift);
11487 %}
11488
11489 // This pattern is automatically generated from aarch64_ad.m4
11490 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11491 instruct AndI_reg_RotateRight_reg(iRegINoSp dst,
11492 iRegIorL2I src1, iRegIorL2I src2,
11493 immI src3) %{
11494 match(Set dst (AndI src1 (RotateRight src2 src3)));
11495
11496 ins_cost(1.9 * INSN_COST);
11497 format %{ "andw $dst, $src1, $src2, ROR $src3" %}
11498
11499 ins_encode %{
11500 __ andw(as_Register($dst$$reg),
11501 as_Register($src1$$reg),
11502 as_Register($src2$$reg),
11503 Assembler::ROR,
11504 $src3$$constant & 0x1f);
11505 %}
11506
11507 ins_pipe(ialu_reg_reg_shift);
11508 %}
11509
11510 // This pattern is automatically generated from aarch64_ad.m4
11511 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11512 instruct AndL_reg_RotateRight_reg(iRegLNoSp dst,
11513 iRegL src1, iRegL src2,
11514 immI src3) %{
11515 match(Set dst (AndL src1 (RotateRight src2 src3)));
11516
11517 ins_cost(1.9 * INSN_COST);
11518 format %{ "andr $dst, $src1, $src2, ROR $src3" %}
11519
11520 ins_encode %{
11521 __ andr(as_Register($dst$$reg),
11522 as_Register($src1$$reg),
11523 as_Register($src2$$reg),
11524 Assembler::ROR,
11525 $src3$$constant & 0x3f);
11526 %}
11527
11528 ins_pipe(ialu_reg_reg_shift);
11529 %}
11530
11531 // This pattern is automatically generated from aarch64_ad.m4
11532 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11533 instruct XorI_reg_URShift_reg(iRegINoSp dst,
11534 iRegIorL2I src1, iRegIorL2I src2,
11535 immI src3) %{
11536 match(Set dst (XorI src1 (URShiftI src2 src3)));
11537
11538 ins_cost(1.9 * INSN_COST);
11539 format %{ "eorw $dst, $src1, $src2, LSR $src3" %}
11540
11541 ins_encode %{
11542 __ eorw(as_Register($dst$$reg),
11543 as_Register($src1$$reg),
11544 as_Register($src2$$reg),
11545 Assembler::LSR,
11546 $src3$$constant & 0x1f);
11547 %}
11548
11549 ins_pipe(ialu_reg_reg_shift);
11550 %}
11551
11552 // This pattern is automatically generated from aarch64_ad.m4
11553 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11554 instruct XorL_reg_URShift_reg(iRegLNoSp dst,
11555 iRegL src1, iRegL src2,
11556 immI src3) %{
11557 match(Set dst (XorL src1 (URShiftL src2 src3)));
11558
11559 ins_cost(1.9 * INSN_COST);
11560 format %{ "eor $dst, $src1, $src2, LSR $src3" %}
11561
11562 ins_encode %{
11563 __ eor(as_Register($dst$$reg),
11564 as_Register($src1$$reg),
11565 as_Register($src2$$reg),
11566 Assembler::LSR,
11567 $src3$$constant & 0x3f);
11568 %}
11569
11570 ins_pipe(ialu_reg_reg_shift);
11571 %}
11572
11573 // This pattern is automatically generated from aarch64_ad.m4
11574 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11575 instruct XorI_reg_RShift_reg(iRegINoSp dst,
11576 iRegIorL2I src1, iRegIorL2I src2,
11577 immI src3) %{
11578 match(Set dst (XorI src1 (RShiftI src2 src3)));
11579
11580 ins_cost(1.9 * INSN_COST);
11581 format %{ "eorw $dst, $src1, $src2, ASR $src3" %}
11582
11583 ins_encode %{
11584 __ eorw(as_Register($dst$$reg),
11585 as_Register($src1$$reg),
11586 as_Register($src2$$reg),
11587 Assembler::ASR,
11588 $src3$$constant & 0x1f);
11589 %}
11590
11591 ins_pipe(ialu_reg_reg_shift);
11592 %}
11593
11594 // This pattern is automatically generated from aarch64_ad.m4
11595 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11596 instruct XorL_reg_RShift_reg(iRegLNoSp dst,
11597 iRegL src1, iRegL src2,
11598 immI src3) %{
11599 match(Set dst (XorL src1 (RShiftL src2 src3)));
11600
11601 ins_cost(1.9 * INSN_COST);
11602 format %{ "eor $dst, $src1, $src2, ASR $src3" %}
11603
11604 ins_encode %{
11605 __ eor(as_Register($dst$$reg),
11606 as_Register($src1$$reg),
11607 as_Register($src2$$reg),
11608 Assembler::ASR,
11609 $src3$$constant & 0x3f);
11610 %}
11611
11612 ins_pipe(ialu_reg_reg_shift);
11613 %}
11614
11615 // This pattern is automatically generated from aarch64_ad.m4
11616 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11617 instruct XorI_reg_LShift_reg(iRegINoSp dst,
11618 iRegIorL2I src1, iRegIorL2I src2,
11619 immI src3) %{
11620 match(Set dst (XorI src1 (LShiftI src2 src3)));
11621
11622 ins_cost(1.9 * INSN_COST);
11623 format %{ "eorw $dst, $src1, $src2, LSL $src3" %}
11624
11625 ins_encode %{
11626 __ eorw(as_Register($dst$$reg),
11627 as_Register($src1$$reg),
11628 as_Register($src2$$reg),
11629 Assembler::LSL,
11630 $src3$$constant & 0x1f);
11631 %}
11632
11633 ins_pipe(ialu_reg_reg_shift);
11634 %}
11635
11636 // This pattern is automatically generated from aarch64_ad.m4
11637 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11638 instruct XorL_reg_LShift_reg(iRegLNoSp dst,
11639 iRegL src1, iRegL src2,
11640 immI src3) %{
11641 match(Set dst (XorL src1 (LShiftL src2 src3)));
11642
11643 ins_cost(1.9 * INSN_COST);
11644 format %{ "eor $dst, $src1, $src2, LSL $src3" %}
11645
11646 ins_encode %{
11647 __ eor(as_Register($dst$$reg),
11648 as_Register($src1$$reg),
11649 as_Register($src2$$reg),
11650 Assembler::LSL,
11651 $src3$$constant & 0x3f);
11652 %}
11653
11654 ins_pipe(ialu_reg_reg_shift);
11655 %}
11656
11657 // This pattern is automatically generated from aarch64_ad.m4
11658 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11659 instruct XorI_reg_RotateRight_reg(iRegINoSp dst,
11660 iRegIorL2I src1, iRegIorL2I src2,
11661 immI src3) %{
11662 match(Set dst (XorI src1 (RotateRight src2 src3)));
11663
11664 ins_cost(1.9 * INSN_COST);
11665 format %{ "eorw $dst, $src1, $src2, ROR $src3" %}
11666
11667 ins_encode %{
11668 __ eorw(as_Register($dst$$reg),
11669 as_Register($src1$$reg),
11670 as_Register($src2$$reg),
11671 Assembler::ROR,
11672 $src3$$constant & 0x1f);
11673 %}
11674
11675 ins_pipe(ialu_reg_reg_shift);
11676 %}
11677
11678 // This pattern is automatically generated from aarch64_ad.m4
11679 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11680 instruct XorL_reg_RotateRight_reg(iRegLNoSp dst,
11681 iRegL src1, iRegL src2,
11682 immI src3) %{
11683 match(Set dst (XorL src1 (RotateRight src2 src3)));
11684
11685 ins_cost(1.9 * INSN_COST);
11686 format %{ "eor $dst, $src1, $src2, ROR $src3" %}
11687
11688 ins_encode %{
11689 __ eor(as_Register($dst$$reg),
11690 as_Register($src1$$reg),
11691 as_Register($src2$$reg),
11692 Assembler::ROR,
11693 $src3$$constant & 0x3f);
11694 %}
11695
11696 ins_pipe(ialu_reg_reg_shift);
11697 %}
11698
11699 // This pattern is automatically generated from aarch64_ad.m4
11700 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11701 instruct OrI_reg_URShift_reg(iRegINoSp dst,
11702 iRegIorL2I src1, iRegIorL2I src2,
11703 immI src3) %{
11704 match(Set dst (OrI src1 (URShiftI src2 src3)));
11705
11706 ins_cost(1.9 * INSN_COST);
11707 format %{ "orrw $dst, $src1, $src2, LSR $src3" %}
11708
11709 ins_encode %{
11710 __ orrw(as_Register($dst$$reg),
11711 as_Register($src1$$reg),
11712 as_Register($src2$$reg),
11713 Assembler::LSR,
11714 $src3$$constant & 0x1f);
11715 %}
11716
11717 ins_pipe(ialu_reg_reg_shift);
11718 %}
11719
11720 // This pattern is automatically generated from aarch64_ad.m4
11721 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11722 instruct OrL_reg_URShift_reg(iRegLNoSp dst,
11723 iRegL src1, iRegL src2,
11724 immI src3) %{
11725 match(Set dst (OrL src1 (URShiftL src2 src3)));
11726
11727 ins_cost(1.9 * INSN_COST);
11728 format %{ "orr $dst, $src1, $src2, LSR $src3" %}
11729
11730 ins_encode %{
11731 __ orr(as_Register($dst$$reg),
11732 as_Register($src1$$reg),
11733 as_Register($src2$$reg),
11734 Assembler::LSR,
11735 $src3$$constant & 0x3f);
11736 %}
11737
11738 ins_pipe(ialu_reg_reg_shift);
11739 %}
11740
11741 // This pattern is automatically generated from aarch64_ad.m4
11742 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11743 instruct OrI_reg_RShift_reg(iRegINoSp dst,
11744 iRegIorL2I src1, iRegIorL2I src2,
11745 immI src3) %{
11746 match(Set dst (OrI src1 (RShiftI src2 src3)));
11747
11748 ins_cost(1.9 * INSN_COST);
11749 format %{ "orrw $dst, $src1, $src2, ASR $src3" %}
11750
11751 ins_encode %{
11752 __ orrw(as_Register($dst$$reg),
11753 as_Register($src1$$reg),
11754 as_Register($src2$$reg),
11755 Assembler::ASR,
11756 $src3$$constant & 0x1f);
11757 %}
11758
11759 ins_pipe(ialu_reg_reg_shift);
11760 %}
11761
11762 // This pattern is automatically generated from aarch64_ad.m4
11763 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11764 instruct OrL_reg_RShift_reg(iRegLNoSp dst,
11765 iRegL src1, iRegL src2,
11766 immI src3) %{
11767 match(Set dst (OrL src1 (RShiftL src2 src3)));
11768
11769 ins_cost(1.9 * INSN_COST);
11770 format %{ "orr $dst, $src1, $src2, ASR $src3" %}
11771
11772 ins_encode %{
11773 __ orr(as_Register($dst$$reg),
11774 as_Register($src1$$reg),
11775 as_Register($src2$$reg),
11776 Assembler::ASR,
11777 $src3$$constant & 0x3f);
11778 %}
11779
11780 ins_pipe(ialu_reg_reg_shift);
11781 %}
11782
11783 // This pattern is automatically generated from aarch64_ad.m4
11784 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11785 instruct OrI_reg_LShift_reg(iRegINoSp dst,
11786 iRegIorL2I src1, iRegIorL2I src2,
11787 immI src3) %{
11788 match(Set dst (OrI src1 (LShiftI src2 src3)));
11789
11790 ins_cost(1.9 * INSN_COST);
11791 format %{ "orrw $dst, $src1, $src2, LSL $src3" %}
11792
11793 ins_encode %{
11794 __ orrw(as_Register($dst$$reg),
11795 as_Register($src1$$reg),
11796 as_Register($src2$$reg),
11797 Assembler::LSL,
11798 $src3$$constant & 0x1f);
11799 %}
11800
11801 ins_pipe(ialu_reg_reg_shift);
11802 %}
11803
11804 // This pattern is automatically generated from aarch64_ad.m4
11805 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11806 instruct OrL_reg_LShift_reg(iRegLNoSp dst,
11807 iRegL src1, iRegL src2,
11808 immI src3) %{
11809 match(Set dst (OrL src1 (LShiftL src2 src3)));
11810
11811 ins_cost(1.9 * INSN_COST);
11812 format %{ "orr $dst, $src1, $src2, LSL $src3" %}
11813
11814 ins_encode %{
11815 __ orr(as_Register($dst$$reg),
11816 as_Register($src1$$reg),
11817 as_Register($src2$$reg),
11818 Assembler::LSL,
11819 $src3$$constant & 0x3f);
11820 %}
11821
11822 ins_pipe(ialu_reg_reg_shift);
11823 %}
11824
11825 // This pattern is automatically generated from aarch64_ad.m4
11826 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11827 instruct OrI_reg_RotateRight_reg(iRegINoSp dst,
11828 iRegIorL2I src1, iRegIorL2I src2,
11829 immI src3) %{
11830 match(Set dst (OrI src1 (RotateRight src2 src3)));
11831
11832 ins_cost(1.9 * INSN_COST);
11833 format %{ "orrw $dst, $src1, $src2, ROR $src3" %}
11834
11835 ins_encode %{
11836 __ orrw(as_Register($dst$$reg),
11837 as_Register($src1$$reg),
11838 as_Register($src2$$reg),
11839 Assembler::ROR,
11840 $src3$$constant & 0x1f);
11841 %}
11842
11843 ins_pipe(ialu_reg_reg_shift);
11844 %}
11845
11846 // This pattern is automatically generated from aarch64_ad.m4
11847 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11848 instruct OrL_reg_RotateRight_reg(iRegLNoSp dst,
11849 iRegL src1, iRegL src2,
11850 immI src3) %{
11851 match(Set dst (OrL src1 (RotateRight src2 src3)));
11852
11853 ins_cost(1.9 * INSN_COST);
11854 format %{ "orr $dst, $src1, $src2, ROR $src3" %}
11855
11856 ins_encode %{
11857 __ orr(as_Register($dst$$reg),
11858 as_Register($src1$$reg),
11859 as_Register($src2$$reg),
11860 Assembler::ROR,
11861 $src3$$constant & 0x3f);
11862 %}
11863
11864 ins_pipe(ialu_reg_reg_shift);
11865 %}
11866
11867 // This pattern is automatically generated from aarch64_ad.m4
11868 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11869 instruct AddI_reg_URShift_reg(iRegINoSp dst,
11870 iRegIorL2I src1, iRegIorL2I src2,
11871 immI src3) %{
11872 match(Set dst (AddI src1 (URShiftI src2 src3)));
11873
11874 ins_cost(1.9 * INSN_COST);
11875 format %{ "addw $dst, $src1, $src2, LSR $src3" %}
11876
11877 ins_encode %{
11878 __ addw(as_Register($dst$$reg),
11879 as_Register($src1$$reg),
11880 as_Register($src2$$reg),
11881 Assembler::LSR,
11882 $src3$$constant & 0x1f);
11883 %}
11884
11885 ins_pipe(ialu_reg_reg_shift);
11886 %}
11887
11888 // This pattern is automatically generated from aarch64_ad.m4
11889 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11890 instruct AddL_reg_URShift_reg(iRegLNoSp dst,
11891 iRegL src1, iRegL src2,
11892 immI src3) %{
11893 match(Set dst (AddL src1 (URShiftL src2 src3)));
11894
11895 ins_cost(1.9 * INSN_COST);
11896 format %{ "add $dst, $src1, $src2, LSR $src3" %}
11897
11898 ins_encode %{
11899 __ add(as_Register($dst$$reg),
11900 as_Register($src1$$reg),
11901 as_Register($src2$$reg),
11902 Assembler::LSR,
11903 $src3$$constant & 0x3f);
11904 %}
11905
11906 ins_pipe(ialu_reg_reg_shift);
11907 %}
11908
11909 // This pattern is automatically generated from aarch64_ad.m4
11910 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11911 instruct AddI_reg_RShift_reg(iRegINoSp dst,
11912 iRegIorL2I src1, iRegIorL2I src2,
11913 immI src3) %{
11914 match(Set dst (AddI src1 (RShiftI src2 src3)));
11915
11916 ins_cost(1.9 * INSN_COST);
11917 format %{ "addw $dst, $src1, $src2, ASR $src3" %}
11918
11919 ins_encode %{
11920 __ addw(as_Register($dst$$reg),
11921 as_Register($src1$$reg),
11922 as_Register($src2$$reg),
11923 Assembler::ASR,
11924 $src3$$constant & 0x1f);
11925 %}
11926
11927 ins_pipe(ialu_reg_reg_shift);
11928 %}
11929
11930 // This pattern is automatically generated from aarch64_ad.m4
11931 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11932 instruct AddL_reg_RShift_reg(iRegLNoSp dst,
11933 iRegL src1, iRegL src2,
11934 immI src3) %{
11935 match(Set dst (AddL src1 (RShiftL src2 src3)));
11936
11937 ins_cost(1.9 * INSN_COST);
11938 format %{ "add $dst, $src1, $src2, ASR $src3" %}
11939
11940 ins_encode %{
11941 __ add(as_Register($dst$$reg),
11942 as_Register($src1$$reg),
11943 as_Register($src2$$reg),
11944 Assembler::ASR,
11945 $src3$$constant & 0x3f);
11946 %}
11947
11948 ins_pipe(ialu_reg_reg_shift);
11949 %}
11950
11951 // This pattern is automatically generated from aarch64_ad.m4
11952 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11953 instruct AddI_reg_LShift_reg(iRegINoSp dst,
11954 iRegIorL2I src1, iRegIorL2I src2,
11955 immI src3) %{
11956 match(Set dst (AddI src1 (LShiftI src2 src3)));
11957
11958 ins_cost(1.9 * INSN_COST);
11959 format %{ "addw $dst, $src1, $src2, LSL $src3" %}
11960
11961 ins_encode %{
11962 __ addw(as_Register($dst$$reg),
11963 as_Register($src1$$reg),
11964 as_Register($src2$$reg),
11965 Assembler::LSL,
11966 $src3$$constant & 0x1f);
11967 %}
11968
11969 ins_pipe(ialu_reg_reg_shift);
11970 %}
11971
11972 // This pattern is automatically generated from aarch64_ad.m4
11973 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11974 instruct AddL_reg_LShift_reg(iRegLNoSp dst,
11975 iRegL src1, iRegL src2,
11976 immI src3) %{
11977 match(Set dst (AddL src1 (LShiftL src2 src3)));
11978
11979 ins_cost(1.9 * INSN_COST);
11980 format %{ "add $dst, $src1, $src2, LSL $src3" %}
11981
11982 ins_encode %{
11983 __ add(as_Register($dst$$reg),
11984 as_Register($src1$$reg),
11985 as_Register($src2$$reg),
11986 Assembler::LSL,
11987 $src3$$constant & 0x3f);
11988 %}
11989
11990 ins_pipe(ialu_reg_reg_shift);
11991 %}
11992
11993 // This pattern is automatically generated from aarch64_ad.m4
11994 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
11995 instruct SubI_reg_URShift_reg(iRegINoSp dst,
11996 iRegIorL2I src1, iRegIorL2I src2,
11997 immI src3) %{
11998 match(Set dst (SubI src1 (URShiftI src2 src3)));
11999
12000 ins_cost(1.9 * INSN_COST);
12001 format %{ "subw $dst, $src1, $src2, LSR $src3" %}
12002
12003 ins_encode %{
12004 __ subw(as_Register($dst$$reg),
12005 as_Register($src1$$reg),
12006 as_Register($src2$$reg),
12007 Assembler::LSR,
12008 $src3$$constant & 0x1f);
12009 %}
12010
12011 ins_pipe(ialu_reg_reg_shift);
12012 %}
12013
12014 // This pattern is automatically generated from aarch64_ad.m4
12015 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12016 instruct SubL_reg_URShift_reg(iRegLNoSp dst,
12017 iRegL src1, iRegL src2,
12018 immI src3) %{
12019 match(Set dst (SubL src1 (URShiftL src2 src3)));
12020
12021 ins_cost(1.9 * INSN_COST);
12022 format %{ "sub $dst, $src1, $src2, LSR $src3" %}
12023
12024 ins_encode %{
12025 __ sub(as_Register($dst$$reg),
12026 as_Register($src1$$reg),
12027 as_Register($src2$$reg),
12028 Assembler::LSR,
12029 $src3$$constant & 0x3f);
12030 %}
12031
12032 ins_pipe(ialu_reg_reg_shift);
12033 %}
12034
12035 // This pattern is automatically generated from aarch64_ad.m4
12036 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12037 instruct SubI_reg_RShift_reg(iRegINoSp dst,
12038 iRegIorL2I src1, iRegIorL2I src2,
12039 immI src3) %{
12040 match(Set dst (SubI src1 (RShiftI src2 src3)));
12041
12042 ins_cost(1.9 * INSN_COST);
12043 format %{ "subw $dst, $src1, $src2, ASR $src3" %}
12044
12045 ins_encode %{
12046 __ subw(as_Register($dst$$reg),
12047 as_Register($src1$$reg),
12048 as_Register($src2$$reg),
12049 Assembler::ASR,
12050 $src3$$constant & 0x1f);
12051 %}
12052
12053 ins_pipe(ialu_reg_reg_shift);
12054 %}
12055
12056 // This pattern is automatically generated from aarch64_ad.m4
12057 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12058 instruct SubL_reg_RShift_reg(iRegLNoSp dst,
12059 iRegL src1, iRegL src2,
12060 immI src3) %{
12061 match(Set dst (SubL src1 (RShiftL src2 src3)));
12062
12063 ins_cost(1.9 * INSN_COST);
12064 format %{ "sub $dst, $src1, $src2, ASR $src3" %}
12065
12066 ins_encode %{
12067 __ sub(as_Register($dst$$reg),
12068 as_Register($src1$$reg),
12069 as_Register($src2$$reg),
12070 Assembler::ASR,
12071 $src3$$constant & 0x3f);
12072 %}
12073
12074 ins_pipe(ialu_reg_reg_shift);
12075 %}
12076
12077 // This pattern is automatically generated from aarch64_ad.m4
12078 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12079 instruct SubI_reg_LShift_reg(iRegINoSp dst,
12080 iRegIorL2I src1, iRegIorL2I src2,
12081 immI src3) %{
12082 match(Set dst (SubI src1 (LShiftI src2 src3)));
12083
12084 ins_cost(1.9 * INSN_COST);
12085 format %{ "subw $dst, $src1, $src2, LSL $src3" %}
12086
12087 ins_encode %{
12088 __ subw(as_Register($dst$$reg),
12089 as_Register($src1$$reg),
12090 as_Register($src2$$reg),
12091 Assembler::LSL,
12092 $src3$$constant & 0x1f);
12093 %}
12094
12095 ins_pipe(ialu_reg_reg_shift);
12096 %}
12097
12098 // This pattern is automatically generated from aarch64_ad.m4
12099 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12100 instruct SubL_reg_LShift_reg(iRegLNoSp dst,
12101 iRegL src1, iRegL src2,
12102 immI src3) %{
12103 match(Set dst (SubL src1 (LShiftL src2 src3)));
12104
12105 ins_cost(1.9 * INSN_COST);
12106 format %{ "sub $dst, $src1, $src2, LSL $src3" %}
12107
12108 ins_encode %{
12109 __ sub(as_Register($dst$$reg),
12110 as_Register($src1$$reg),
12111 as_Register($src2$$reg),
12112 Assembler::LSL,
12113 $src3$$constant & 0x3f);
12114 %}
12115
12116 ins_pipe(ialu_reg_reg_shift);
12117 %}
12118
12119 // This pattern is automatically generated from aarch64_ad.m4
12120 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12121
12122 // Shift Left followed by Shift Right.
12123 // This idiom is used by the compiler for the i2b bytecode etc.
12124 instruct sbfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
12125 %{
12126 match(Set dst (RShiftL (LShiftL src lshift_count) rshift_count));
12127 ins_cost(INSN_COST * 2);
12128 format %{ "sbfm $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
12129 ins_encode %{
12130 int lshift = $lshift_count$$constant & 63;
12131 int rshift = $rshift_count$$constant & 63;
12132 int s = 63 - lshift;
12133 int r = (rshift - lshift) & 63;
12134 __ sbfm(as_Register($dst$$reg),
12135 as_Register($src$$reg),
12136 r, s);
12137 %}
12138
12139 ins_pipe(ialu_reg_shift);
12140 %}
12141
12142 // This pattern is automatically generated from aarch64_ad.m4
12143 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12144
12145 // Shift Left followed by Shift Right.
12146 // This idiom is used by the compiler for the i2b bytecode etc.
12147 instruct sbfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
12148 %{
12149 match(Set dst (RShiftI (LShiftI src lshift_count) rshift_count));
12150 ins_cost(INSN_COST * 2);
12151 format %{ "sbfmw $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
12152 ins_encode %{
12153 int lshift = $lshift_count$$constant & 31;
12154 int rshift = $rshift_count$$constant & 31;
12155 int s = 31 - lshift;
12156 int r = (rshift - lshift) & 31;
12157 __ sbfmw(as_Register($dst$$reg),
12158 as_Register($src$$reg),
12159 r, s);
12160 %}
12161
12162 ins_pipe(ialu_reg_shift);
12163 %}
12164
12165 // This pattern is automatically generated from aarch64_ad.m4
12166 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12167
12168 // Shift Left followed by Shift Right.
12169 // This idiom is used by the compiler for the i2b bytecode etc.
12170 instruct ubfmL(iRegLNoSp dst, iRegL src, immI lshift_count, immI rshift_count)
12171 %{
12172 match(Set dst (URShiftL (LShiftL src lshift_count) rshift_count));
12173 ins_cost(INSN_COST * 2);
12174 format %{ "ubfm $dst, $src, $rshift_count - $lshift_count, #63 - $lshift_count" %}
12175 ins_encode %{
12176 int lshift = $lshift_count$$constant & 63;
12177 int rshift = $rshift_count$$constant & 63;
12178 int s = 63 - lshift;
12179 int r = (rshift - lshift) & 63;
12180 __ ubfm(as_Register($dst$$reg),
12181 as_Register($src$$reg),
12182 r, s);
12183 %}
12184
12185 ins_pipe(ialu_reg_shift);
12186 %}
12187
12188 // This pattern is automatically generated from aarch64_ad.m4
12189 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12190
12191 // Shift Left followed by Shift Right.
12192 // This idiom is used by the compiler for the i2b bytecode etc.
12193 instruct ubfmwI(iRegINoSp dst, iRegIorL2I src, immI lshift_count, immI rshift_count)
12194 %{
12195 match(Set dst (URShiftI (LShiftI src lshift_count) rshift_count));
12196 ins_cost(INSN_COST * 2);
12197 format %{ "ubfmw $dst, $src, $rshift_count - $lshift_count, #31 - $lshift_count" %}
12198 ins_encode %{
12199 int lshift = $lshift_count$$constant & 31;
12200 int rshift = $rshift_count$$constant & 31;
12201 int s = 31 - lshift;
12202 int r = (rshift - lshift) & 31;
12203 __ ubfmw(as_Register($dst$$reg),
12204 as_Register($src$$reg),
12205 r, s);
12206 %}
12207
12208 ins_pipe(ialu_reg_shift);
12209 %}
12210
12211 // Bitfield extract with shift & mask
12212
12213 // This pattern is automatically generated from aarch64_ad.m4
12214 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12215 instruct ubfxwI(iRegINoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
12216 %{
12217 match(Set dst (AndI (URShiftI src rshift) mask));
12218 // Make sure we are not going to exceed what ubfxw can do.
12219 predicate((exact_log2(n->in(2)->get_int() + 1) + (n->in(1)->in(2)->get_int() & 31)) <= (31 + 1));
12220
12221 ins_cost(INSN_COST);
12222 format %{ "ubfxw $dst, $src, $rshift, $mask" %}
12223 ins_encode %{
12224 int rshift = $rshift$$constant & 31;
12225 intptr_t mask = $mask$$constant;
12226 int width = exact_log2(mask+1);
12227 __ ubfxw(as_Register($dst$$reg),
12228 as_Register($src$$reg), rshift, width);
12229 %}
12230 ins_pipe(ialu_reg_shift);
12231 %}
12232
12233 // This pattern is automatically generated from aarch64_ad.m4
12234 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12235 instruct ubfxL(iRegLNoSp dst, iRegL src, immI rshift, immL_bitmask mask)
12236 %{
12237 match(Set dst (AndL (URShiftL src rshift) mask));
12238 // Make sure we are not going to exceed what ubfx can do.
12239 predicate((exact_log2_long(n->in(2)->get_long() + 1) + (n->in(1)->in(2)->get_int() & 63)) <= (63 + 1));
12240
12241 ins_cost(INSN_COST);
12242 format %{ "ubfx $dst, $src, $rshift, $mask" %}
12243 ins_encode %{
12244 int rshift = $rshift$$constant & 63;
12245 intptr_t mask = $mask$$constant;
12246 int width = exact_log2_long(mask+1);
12247 __ ubfx(as_Register($dst$$reg),
12248 as_Register($src$$reg), rshift, width);
12249 %}
12250 ins_pipe(ialu_reg_shift);
12251 %}
12252
12253
12254 // This pattern is automatically generated from aarch64_ad.m4
12255 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12256
12257 // We can use ubfx when extending an And with a mask when we know mask
12258 // is positive. We know that because immI_bitmask guarantees it.
12259 instruct ubfxIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI rshift, immI_bitmask mask)
12260 %{
12261 match(Set dst (ConvI2L (AndI (URShiftI src rshift) mask)));
12262 // Make sure we are not going to exceed what ubfxw can do.
12263 predicate((exact_log2(n->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(1)->in(2)->get_int() & 31)) <= (31 + 1));
12264
12265 ins_cost(INSN_COST * 2);
12266 format %{ "ubfx $dst, $src, $rshift, $mask" %}
12267 ins_encode %{
12268 int rshift = $rshift$$constant & 31;
12269 intptr_t mask = $mask$$constant;
12270 int width = exact_log2(mask+1);
12271 __ ubfx(as_Register($dst$$reg),
12272 as_Register($src$$reg), rshift, width);
12273 %}
12274 ins_pipe(ialu_reg_shift);
12275 %}
12276
12277
12278 // This pattern is automatically generated from aarch64_ad.m4
12279 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12280
12281 // We can use ubfiz when masking by a positive number and then left shifting the result.
12282 // We know that the mask is positive because immI_bitmask guarantees it.
12283 instruct ubfizwI(iRegINoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
12284 %{
12285 match(Set dst (LShiftI (AndI src mask) lshift));
12286 predicate((exact_log2(n->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 31)) <= (31 + 1));
12287
12288 ins_cost(INSN_COST);
12289 format %{ "ubfizw $dst, $src, $lshift, $mask" %}
12290 ins_encode %{
12291 int lshift = $lshift$$constant & 31;
12292 intptr_t mask = $mask$$constant;
12293 int width = exact_log2(mask+1);
12294 __ ubfizw(as_Register($dst$$reg),
12295 as_Register($src$$reg), lshift, width);
12296 %}
12297 ins_pipe(ialu_reg_shift);
12298 %}
12299
12300 // This pattern is automatically generated from aarch64_ad.m4
12301 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12302
12303 // We can use ubfiz when masking by a positive number and then left shifting the result.
12304 // We know that the mask is positive because immL_bitmask guarantees it.
12305 instruct ubfizL(iRegLNoSp dst, iRegL src, immI lshift, immL_bitmask mask)
12306 %{
12307 match(Set dst (LShiftL (AndL src mask) lshift));
12308 predicate((exact_log2_long(n->in(1)->in(2)->get_long() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1));
12309
12310 ins_cost(INSN_COST);
12311 format %{ "ubfiz $dst, $src, $lshift, $mask" %}
12312 ins_encode %{
12313 int lshift = $lshift$$constant & 63;
12314 intptr_t mask = $mask$$constant;
12315 int width = exact_log2_long(mask+1);
12316 __ ubfiz(as_Register($dst$$reg),
12317 as_Register($src$$reg), lshift, width);
12318 %}
12319 ins_pipe(ialu_reg_shift);
12320 %}
12321
12322 // This pattern is automatically generated from aarch64_ad.m4
12323 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12324
12325 // We can use ubfiz when masking by a positive number and then left shifting the result.
12326 // We know that the mask is positive because immI_bitmask guarantees it.
12327 instruct ubfizwIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
12328 %{
12329 match(Set dst (ConvI2L (LShiftI (AndI src mask) lshift)));
12330 predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(1)->in(2)->get_int() & 31)) <= 31);
12331
12332 ins_cost(INSN_COST);
12333 format %{ "ubfizw $dst, $src, $lshift, $mask" %}
12334 ins_encode %{
12335 int lshift = $lshift$$constant & 31;
12336 intptr_t mask = $mask$$constant;
12337 int width = exact_log2(mask+1);
12338 __ ubfizw(as_Register($dst$$reg),
12339 as_Register($src$$reg), lshift, width);
12340 %}
12341 ins_pipe(ialu_reg_shift);
12342 %}
12343
12344 // This pattern is automatically generated from aarch64_ad.m4
12345 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12346
12347 // We can use ubfiz when masking by a positive number and then left shifting the result.
12348 // We know that the mask is positive because immL_bitmask guarantees it.
12349 instruct ubfizLConvL2I(iRegINoSp dst, iRegL src, immI lshift, immL_positive_bitmaskI mask)
12350 %{
12351 match(Set dst (ConvL2I (LShiftL (AndL src mask) lshift)));
12352 predicate((exact_log2_long(n->in(1)->in(1)->in(2)->get_long() + 1) + (n->in(1)->in(2)->get_int() & 63)) <= 31);
12353
12354 ins_cost(INSN_COST);
12355 format %{ "ubfiz $dst, $src, $lshift, $mask" %}
12356 ins_encode %{
12357 int lshift = $lshift$$constant & 63;
12358 intptr_t mask = $mask$$constant;
12359 int width = exact_log2_long(mask+1);
12360 __ ubfiz(as_Register($dst$$reg),
12361 as_Register($src$$reg), lshift, width);
12362 %}
12363 ins_pipe(ialu_reg_shift);
12364 %}
12365
12366
12367 // This pattern is automatically generated from aarch64_ad.m4
12368 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12369
12370 // If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz
12371 instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
12372 %{
12373 match(Set dst (LShiftL (ConvI2L (AndI src mask)) lshift));
12374 predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1));
12375
12376 ins_cost(INSN_COST);
12377 format %{ "ubfiz $dst, $src, $lshift, $mask" %}
12378 ins_encode %{
12379 int lshift = $lshift$$constant & 63;
12380 intptr_t mask = $mask$$constant;
12381 int width = exact_log2(mask+1);
12382 __ ubfiz(as_Register($dst$$reg),
12383 as_Register($src$$reg), lshift, width);
12384 %}
12385 ins_pipe(ialu_reg_shift);
12386 %}
12387
12388 // This pattern is automatically generated from aarch64_ad.m4
12389 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12390
12391 // If there is a convert L to I block between and AndL and a LShiftI, we can also match ubfiz
12392 instruct ubfizLConvL2Ix(iRegINoSp dst, iRegL src, immI lshift, immL_positive_bitmaskI mask)
12393 %{
12394 match(Set dst (LShiftI (ConvL2I (AndL src mask)) lshift));
12395 predicate((exact_log2_long(n->in(1)->in(1)->in(2)->get_long() + 1) + (n->in(2)->get_int() & 31)) <= 31);
12396
12397 ins_cost(INSN_COST);
12398 format %{ "ubfiz $dst, $src, $lshift, $mask" %}
12399 ins_encode %{
12400 int lshift = $lshift$$constant & 31;
12401 intptr_t mask = $mask$$constant;
12402 int width = exact_log2(mask+1);
12403 __ ubfiz(as_Register($dst$$reg),
12404 as_Register($src$$reg), lshift, width);
12405 %}
12406 ins_pipe(ialu_reg_shift);
12407 %}
12408
12409 // This pattern is automatically generated from aarch64_ad.m4
12410 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12411
12412 // Can skip int2long conversions after AND with small bitmask
12413 instruct ubfizIConvI2LAndI(iRegLNoSp dst, iRegI src, immI_bitmask msk)
12414 %{
12415 match(Set dst (ConvI2L (AndI src msk)));
12416 ins_cost(INSN_COST);
12417 format %{ "ubfiz $dst, $src, 0, exact_log2($msk + 1) " %}
12418 ins_encode %{
12419 __ ubfiz(as_Register($dst$$reg), as_Register($src$$reg), 0, exact_log2($msk$$constant + 1));
12420 %}
12421 ins_pipe(ialu_reg_shift);
12422 %}
12423
12424
12425 // Rotations
12426
12427 // This pattern is automatically generated from aarch64_ad.m4
12428 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12429 instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
12430 %{
12431 match(Set dst (OrL (LShiftL src1 lshift) (URShiftL src2 rshift)));
12432 predicate(0 == (((n->in(1)->in(2)->get_int() & 63) + (n->in(2)->in(2)->get_int() & 63)) & 63));
12433
12434 ins_cost(INSN_COST);
12435 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12436
12437 ins_encode %{
12438 __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12439 $rshift$$constant & 63);
12440 %}
12441 ins_pipe(ialu_reg_reg_extr);
12442 %}
12443
12444
12445 // This pattern is automatically generated from aarch64_ad.m4
12446 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12447 instruct extrOrI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
12448 %{
12449 match(Set dst (OrI (LShiftI src1 lshift) (URShiftI src2 rshift)));
12450 predicate(0 == (((n->in(1)->in(2)->get_int() & 31) + (n->in(2)->in(2)->get_int() & 31)) & 31));
12451
12452 ins_cost(INSN_COST);
12453 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12454
12455 ins_encode %{
12456 __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12457 $rshift$$constant & 31);
12458 %}
12459 ins_pipe(ialu_reg_reg_extr);
12460 %}
12461
12462
12463 // This pattern is automatically generated from aarch64_ad.m4
12464 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12465 instruct extrAddL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
12466 %{
12467 match(Set dst (AddL (LShiftL src1 lshift) (URShiftL src2 rshift)));
12468 predicate(0 == (((n->in(1)->in(2)->get_int() & 63) + (n->in(2)->in(2)->get_int() & 63)) & 63));
12469
12470 ins_cost(INSN_COST);
12471 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12472
12473 ins_encode %{
12474 __ extr(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12475 $rshift$$constant & 63);
12476 %}
12477 ins_pipe(ialu_reg_reg_extr);
12478 %}
12479
12480
12481 // This pattern is automatically generated from aarch64_ad.m4
12482 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12483 instruct extrAddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift, immI rshift, rFlagsReg cr)
12484 %{
12485 match(Set dst (AddI (LShiftI src1 lshift) (URShiftI src2 rshift)));
12486 predicate(0 == (((n->in(1)->in(2)->get_int() & 31) + (n->in(2)->in(2)->get_int() & 31)) & 31));
12487
12488 ins_cost(INSN_COST);
12489 format %{ "extr $dst, $src1, $src2, #$rshift" %}
12490
12491 ins_encode %{
12492 __ extrw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg),
12493 $rshift$$constant & 31);
12494 %}
12495 ins_pipe(ialu_reg_reg_extr);
12496 %}
12497
12498 // This pattern is automatically generated from aarch64_ad.m4
12499 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12500 instruct rorI_imm(iRegINoSp dst, iRegI src, immI shift)
12501 %{
12502 match(Set dst (RotateRight src shift));
12503
12504 ins_cost(INSN_COST);
12505 format %{ "ror $dst, $src, $shift" %}
12506
12507 ins_encode %{
12508 __ extrw(as_Register($dst$$reg), as_Register($src$$reg), as_Register($src$$reg),
12509 $shift$$constant & 0x1f);
12510 %}
12511 ins_pipe(ialu_reg_reg_vshift);
12512 %}
12513
12514 // This pattern is automatically generated from aarch64_ad.m4
12515 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12516 instruct rorL_imm(iRegLNoSp dst, iRegL src, immI shift)
12517 %{
12518 match(Set dst (RotateRight src shift));
12519
12520 ins_cost(INSN_COST);
12521 format %{ "ror $dst, $src, $shift" %}
12522
12523 ins_encode %{
12524 __ extr(as_Register($dst$$reg), as_Register($src$$reg), as_Register($src$$reg),
12525 $shift$$constant & 0x3f);
12526 %}
12527 ins_pipe(ialu_reg_reg_vshift);
12528 %}
12529
12530 // This pattern is automatically generated from aarch64_ad.m4
12531 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12532 instruct rorI_reg(iRegINoSp dst, iRegI src, iRegI shift)
12533 %{
12534 match(Set dst (RotateRight src shift));
12535
12536 ins_cost(INSN_COST);
12537 format %{ "ror $dst, $src, $shift" %}
12538
12539 ins_encode %{
12540 __ rorvw(as_Register($dst$$reg), as_Register($src$$reg), as_Register($shift$$reg));
12541 %}
12542 ins_pipe(ialu_reg_reg_vshift);
12543 %}
12544
12545 // This pattern is automatically generated from aarch64_ad.m4
12546 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12547 instruct rorL_reg(iRegLNoSp dst, iRegL src, iRegI shift)
12548 %{
12549 match(Set dst (RotateRight src shift));
12550
12551 ins_cost(INSN_COST);
12552 format %{ "ror $dst, $src, $shift" %}
12553
12554 ins_encode %{
12555 __ rorv(as_Register($dst$$reg), as_Register($src$$reg), as_Register($shift$$reg));
12556 %}
12557 ins_pipe(ialu_reg_reg_vshift);
12558 %}
12559
12560 // This pattern is automatically generated from aarch64_ad.m4
12561 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12562 instruct rolI_reg(iRegINoSp dst, iRegI src, iRegI shift)
12563 %{
12564 match(Set dst (RotateLeft src shift));
12565
12566 ins_cost(INSN_COST);
12567 format %{ "rol $dst, $src, $shift" %}
12568
12569 ins_encode %{
12570 __ subw(rscratch1, zr, as_Register($shift$$reg));
12571 __ rorvw(as_Register($dst$$reg), as_Register($src$$reg), rscratch1);
12572 %}
12573 ins_pipe(ialu_reg_reg_vshift);
12574 %}
12575
12576 // This pattern is automatically generated from aarch64_ad.m4
12577 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12578 instruct rolL_reg(iRegLNoSp dst, iRegL src, iRegI shift)
12579 %{
12580 match(Set dst (RotateLeft src shift));
12581
12582 ins_cost(INSN_COST);
12583 format %{ "rol $dst, $src, $shift" %}
12584
12585 ins_encode %{
12586 __ subw(rscratch1, zr, as_Register($shift$$reg));
12587 __ rorv(as_Register($dst$$reg), as_Register($src$$reg), rscratch1);
12588 %}
12589 ins_pipe(ialu_reg_reg_vshift);
12590 %}
12591
12592
12593 // Add/subtract (extended)
12594
12595 // This pattern is automatically generated from aarch64_ad.m4
12596 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12597 instruct AddExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr)
12598 %{
12599 match(Set dst (AddL src1 (ConvI2L src2)));
12600 ins_cost(INSN_COST);
12601 format %{ "add $dst, $src1, $src2, sxtw" %}
12602
12603 ins_encode %{
12604 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12605 as_Register($src2$$reg), ext::sxtw);
12606 %}
12607 ins_pipe(ialu_reg_reg);
12608 %}
12609
12610 // This pattern is automatically generated from aarch64_ad.m4
12611 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12612 instruct SubExtI(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, rFlagsReg cr)
12613 %{
12614 match(Set dst (SubL src1 (ConvI2L src2)));
12615 ins_cost(INSN_COST);
12616 format %{ "sub $dst, $src1, $src2, sxtw" %}
12617
12618 ins_encode %{
12619 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12620 as_Register($src2$$reg), ext::sxtw);
12621 %}
12622 ins_pipe(ialu_reg_reg);
12623 %}
12624
12625 // This pattern is automatically generated from aarch64_ad.m4
12626 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12627 instruct AddExtI_sxth(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_16 lshift, immI_16 rshift, rFlagsReg cr)
12628 %{
12629 match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
12630 ins_cost(INSN_COST);
12631 format %{ "add $dst, $src1, $src2, sxth" %}
12632
12633 ins_encode %{
12634 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12635 as_Register($src2$$reg), ext::sxth);
12636 %}
12637 ins_pipe(ialu_reg_reg);
12638 %}
12639
12640 // This pattern is automatically generated from aarch64_ad.m4
12641 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12642 instruct AddExtI_sxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
12643 %{
12644 match(Set dst (AddI src1 (RShiftI (LShiftI src2 lshift) rshift)));
12645 ins_cost(INSN_COST);
12646 format %{ "add $dst, $src1, $src2, sxtb" %}
12647
12648 ins_encode %{
12649 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12650 as_Register($src2$$reg), ext::sxtb);
12651 %}
12652 ins_pipe(ialu_reg_reg);
12653 %}
12654
12655 // This pattern is automatically generated from aarch64_ad.m4
12656 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12657 instruct AddExtI_uxtb(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_24 lshift, immI_24 rshift, rFlagsReg cr)
12658 %{
12659 match(Set dst (AddI src1 (URShiftI (LShiftI src2 lshift) rshift)));
12660 ins_cost(INSN_COST);
12661 format %{ "add $dst, $src1, $src2, uxtb" %}
12662
12663 ins_encode %{
12664 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12665 as_Register($src2$$reg), ext::uxtb);
12666 %}
12667 ins_pipe(ialu_reg_reg);
12668 %}
12669
12670 // This pattern is automatically generated from aarch64_ad.m4
12671 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12672 instruct AddExtL_sxth(iRegLNoSp dst, iRegL src1, iRegL src2, immI_48 lshift, immI_48 rshift, rFlagsReg cr)
12673 %{
12674 match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
12675 ins_cost(INSN_COST);
12676 format %{ "add $dst, $src1, $src2, sxth" %}
12677
12678 ins_encode %{
12679 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12680 as_Register($src2$$reg), ext::sxth);
12681 %}
12682 ins_pipe(ialu_reg_reg);
12683 %}
12684
12685 // This pattern is automatically generated from aarch64_ad.m4
12686 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12687 instruct AddExtL_sxtw(iRegLNoSp dst, iRegL src1, iRegL src2, immI_32 lshift, immI_32 rshift, rFlagsReg cr)
12688 %{
12689 match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
12690 ins_cost(INSN_COST);
12691 format %{ "add $dst, $src1, $src2, sxtw" %}
12692
12693 ins_encode %{
12694 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12695 as_Register($src2$$reg), ext::sxtw);
12696 %}
12697 ins_pipe(ialu_reg_reg);
12698 %}
12699
12700 // This pattern is automatically generated from aarch64_ad.m4
12701 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12702 instruct AddExtL_sxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
12703 %{
12704 match(Set dst (AddL src1 (RShiftL (LShiftL src2 lshift) rshift)));
12705 ins_cost(INSN_COST);
12706 format %{ "add $dst, $src1, $src2, sxtb" %}
12707
12708 ins_encode %{
12709 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12710 as_Register($src2$$reg), ext::sxtb);
12711 %}
12712 ins_pipe(ialu_reg_reg);
12713 %}
12714
12715 // This pattern is automatically generated from aarch64_ad.m4
12716 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12717 instruct AddExtL_uxtb(iRegLNoSp dst, iRegL src1, iRegL src2, immI_56 lshift, immI_56 rshift, rFlagsReg cr)
12718 %{
12719 match(Set dst (AddL src1 (URShiftL (LShiftL src2 lshift) rshift)));
12720 ins_cost(INSN_COST);
12721 format %{ "add $dst, $src1, $src2, uxtb" %}
12722
12723 ins_encode %{
12724 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12725 as_Register($src2$$reg), ext::uxtb);
12726 %}
12727 ins_pipe(ialu_reg_reg);
12728 %}
12729
12730 // This pattern is automatically generated from aarch64_ad.m4
12731 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12732 instruct AddExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr)
12733 %{
12734 match(Set dst (AddI src1 (AndI src2 mask)));
12735 ins_cost(INSN_COST);
12736 format %{ "addw $dst, $src1, $src2, uxtb" %}
12737
12738 ins_encode %{
12739 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
12740 as_Register($src2$$reg), ext::uxtb);
12741 %}
12742 ins_pipe(ialu_reg_reg);
12743 %}
12744
12745 // This pattern is automatically generated from aarch64_ad.m4
12746 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12747 instruct AddExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr)
12748 %{
12749 match(Set dst (AddI src1 (AndI src2 mask)));
12750 ins_cost(INSN_COST);
12751 format %{ "addw $dst, $src1, $src2, uxth" %}
12752
12753 ins_encode %{
12754 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
12755 as_Register($src2$$reg), ext::uxth);
12756 %}
12757 ins_pipe(ialu_reg_reg);
12758 %}
12759
12760 // This pattern is automatically generated from aarch64_ad.m4
12761 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12762 instruct AddExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
12763 %{
12764 match(Set dst (AddL src1 (AndL src2 mask)));
12765 ins_cost(INSN_COST);
12766 format %{ "add $dst, $src1, $src2, uxtb" %}
12767
12768 ins_encode %{
12769 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12770 as_Register($src2$$reg), ext::uxtb);
12771 %}
12772 ins_pipe(ialu_reg_reg);
12773 %}
12774
12775 // This pattern is automatically generated from aarch64_ad.m4
12776 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12777 instruct AddExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
12778 %{
12779 match(Set dst (AddL src1 (AndL src2 mask)));
12780 ins_cost(INSN_COST);
12781 format %{ "add $dst, $src1, $src2, uxth" %}
12782
12783 ins_encode %{
12784 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12785 as_Register($src2$$reg), ext::uxth);
12786 %}
12787 ins_pipe(ialu_reg_reg);
12788 %}
12789
12790 // This pattern is automatically generated from aarch64_ad.m4
12791 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12792 instruct AddExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
12793 %{
12794 match(Set dst (AddL src1 (AndL src2 mask)));
12795 ins_cost(INSN_COST);
12796 format %{ "add $dst, $src1, $src2, uxtw" %}
12797
12798 ins_encode %{
12799 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12800 as_Register($src2$$reg), ext::uxtw);
12801 %}
12802 ins_pipe(ialu_reg_reg);
12803 %}
12804
12805 // This pattern is automatically generated from aarch64_ad.m4
12806 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12807 instruct SubExtI_uxtb_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, rFlagsReg cr)
12808 %{
12809 match(Set dst (SubI src1 (AndI src2 mask)));
12810 ins_cost(INSN_COST);
12811 format %{ "subw $dst, $src1, $src2, uxtb" %}
12812
12813 ins_encode %{
12814 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
12815 as_Register($src2$$reg), ext::uxtb);
12816 %}
12817 ins_pipe(ialu_reg_reg);
12818 %}
12819
12820 // This pattern is automatically generated from aarch64_ad.m4
12821 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12822 instruct SubExtI_uxth_and(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, rFlagsReg cr)
12823 %{
12824 match(Set dst (SubI src1 (AndI src2 mask)));
12825 ins_cost(INSN_COST);
12826 format %{ "subw $dst, $src1, $src2, uxth" %}
12827
12828 ins_encode %{
12829 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
12830 as_Register($src2$$reg), ext::uxth);
12831 %}
12832 ins_pipe(ialu_reg_reg);
12833 %}
12834
12835 // This pattern is automatically generated from aarch64_ad.m4
12836 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12837 instruct SubExtL_uxtb_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, rFlagsReg cr)
12838 %{
12839 match(Set dst (SubL src1 (AndL src2 mask)));
12840 ins_cost(INSN_COST);
12841 format %{ "sub $dst, $src1, $src2, uxtb" %}
12842
12843 ins_encode %{
12844 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12845 as_Register($src2$$reg), ext::uxtb);
12846 %}
12847 ins_pipe(ialu_reg_reg);
12848 %}
12849
12850 // This pattern is automatically generated from aarch64_ad.m4
12851 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12852 instruct SubExtL_uxth_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, rFlagsReg cr)
12853 %{
12854 match(Set dst (SubL src1 (AndL src2 mask)));
12855 ins_cost(INSN_COST);
12856 format %{ "sub $dst, $src1, $src2, uxth" %}
12857
12858 ins_encode %{
12859 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12860 as_Register($src2$$reg), ext::uxth);
12861 %}
12862 ins_pipe(ialu_reg_reg);
12863 %}
12864
12865 // This pattern is automatically generated from aarch64_ad.m4
12866 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12867 instruct SubExtL_uxtw_and(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, rFlagsReg cr)
12868 %{
12869 match(Set dst (SubL src1 (AndL src2 mask)));
12870 ins_cost(INSN_COST);
12871 format %{ "sub $dst, $src1, $src2, uxtw" %}
12872
12873 ins_encode %{
12874 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12875 as_Register($src2$$reg), ext::uxtw);
12876 %}
12877 ins_pipe(ialu_reg_reg);
12878 %}
12879
12880
12881 // This pattern is automatically generated from aarch64_ad.m4
12882 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12883 instruct AddExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)
12884 %{
12885 match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
12886 ins_cost(1.9 * INSN_COST);
12887 format %{ "add $dst, $src1, $src2, sxtb #lshift2" %}
12888
12889 ins_encode %{
12890 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12891 as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
12892 %}
12893 ins_pipe(ialu_reg_reg_shift);
12894 %}
12895
12896 // This pattern is automatically generated from aarch64_ad.m4
12897 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12898 instruct AddExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)
12899 %{
12900 match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
12901 ins_cost(1.9 * INSN_COST);
12902 format %{ "add $dst, $src1, $src2, sxth #lshift2" %}
12903
12904 ins_encode %{
12905 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12906 as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
12907 %}
12908 ins_pipe(ialu_reg_reg_shift);
12909 %}
12910
12911 // This pattern is automatically generated from aarch64_ad.m4
12912 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12913 instruct AddExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)
12914 %{
12915 match(Set dst (AddL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
12916 ins_cost(1.9 * INSN_COST);
12917 format %{ "add $dst, $src1, $src2, sxtw #lshift2" %}
12918
12919 ins_encode %{
12920 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
12921 as_Register($src2$$reg), ext::sxtw, ($lshift2$$constant));
12922 %}
12923 ins_pipe(ialu_reg_reg_shift);
12924 %}
12925
12926 // This pattern is automatically generated from aarch64_ad.m4
12927 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12928 instruct SubExtL_sxtb_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_56 lshift1, immI_56 rshift1, rFlagsReg cr)
12929 %{
12930 match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
12931 ins_cost(1.9 * INSN_COST);
12932 format %{ "sub $dst, $src1, $src2, sxtb #lshift2" %}
12933
12934 ins_encode %{
12935 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12936 as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
12937 %}
12938 ins_pipe(ialu_reg_reg_shift);
12939 %}
12940
12941 // This pattern is automatically generated from aarch64_ad.m4
12942 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12943 instruct SubExtL_sxth_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_48 lshift1, immI_48 rshift1, rFlagsReg cr)
12944 %{
12945 match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
12946 ins_cost(1.9 * INSN_COST);
12947 format %{ "sub $dst, $src1, $src2, sxth #lshift2" %}
12948
12949 ins_encode %{
12950 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12951 as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
12952 %}
12953 ins_pipe(ialu_reg_reg_shift);
12954 %}
12955
12956 // This pattern is automatically generated from aarch64_ad.m4
12957 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12958 instruct SubExtL_sxtw_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immIExt lshift2, immI_32 lshift1, immI_32 rshift1, rFlagsReg cr)
12959 %{
12960 match(Set dst (SubL src1 (LShiftL (RShiftL (LShiftL src2 lshift1) rshift1) lshift2)));
12961 ins_cost(1.9 * INSN_COST);
12962 format %{ "sub $dst, $src1, $src2, sxtw #lshift2" %}
12963
12964 ins_encode %{
12965 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
12966 as_Register($src2$$reg), ext::sxtw, ($lshift2$$constant));
12967 %}
12968 ins_pipe(ialu_reg_reg_shift);
12969 %}
12970
12971 // This pattern is automatically generated from aarch64_ad.m4
12972 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12973 instruct AddExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)
12974 %{
12975 match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
12976 ins_cost(1.9 * INSN_COST);
12977 format %{ "addw $dst, $src1, $src2, sxtb #lshift2" %}
12978
12979 ins_encode %{
12980 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
12981 as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
12982 %}
12983 ins_pipe(ialu_reg_reg_shift);
12984 %}
12985
12986 // This pattern is automatically generated from aarch64_ad.m4
12987 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
12988 instruct AddExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)
12989 %{
12990 match(Set dst (AddI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
12991 ins_cost(1.9 * INSN_COST);
12992 format %{ "addw $dst, $src1, $src2, sxth #lshift2" %}
12993
12994 ins_encode %{
12995 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
12996 as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
12997 %}
12998 ins_pipe(ialu_reg_reg_shift);
12999 %}
13000
13001 // This pattern is automatically generated from aarch64_ad.m4
13002 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13003 instruct SubExtI_sxtb_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_24 lshift1, immI_24 rshift1, rFlagsReg cr)
13004 %{
13005 match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
13006 ins_cost(1.9 * INSN_COST);
13007 format %{ "subw $dst, $src1, $src2, sxtb #lshift2" %}
13008
13009 ins_encode %{
13010 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
13011 as_Register($src2$$reg), ext::sxtb, ($lshift2$$constant));
13012 %}
13013 ins_pipe(ialu_reg_reg_shift);
13014 %}
13015
13016 // This pattern is automatically generated from aarch64_ad.m4
13017 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13018 instruct SubExtI_sxth_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immIExt lshift2, immI_16 lshift1, immI_16 rshift1, rFlagsReg cr)
13019 %{
13020 match(Set dst (SubI src1 (LShiftI (RShiftI (LShiftI src2 lshift1) rshift1) lshift2)));
13021 ins_cost(1.9 * INSN_COST);
13022 format %{ "subw $dst, $src1, $src2, sxth #lshift2" %}
13023
13024 ins_encode %{
13025 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
13026 as_Register($src2$$reg), ext::sxth, ($lshift2$$constant));
13027 %}
13028 ins_pipe(ialu_reg_reg_shift);
13029 %}
13030
13031 // This pattern is automatically generated from aarch64_ad.m4
13032 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13033 instruct AddExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
13034 %{
13035 match(Set dst (AddL src1 (LShiftL (ConvI2L src2) lshift)));
13036 ins_cost(1.9 * INSN_COST);
13037 format %{ "add $dst, $src1, $src2, sxtw #lshift" %}
13038
13039 ins_encode %{
13040 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13041 as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));
13042 %}
13043 ins_pipe(ialu_reg_reg_shift);
13044 %}
13045
13046 // This pattern is automatically generated from aarch64_ad.m4
13047 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13048 instruct SubExtI_shift(iRegLNoSp dst, iRegL src1, iRegIorL2I src2, immIExt lshift, rFlagsReg cr)
13049 %{
13050 match(Set dst (SubL src1 (LShiftL (ConvI2L src2) lshift)));
13051 ins_cost(1.9 * INSN_COST);
13052 format %{ "sub $dst, $src1, $src2, sxtw #lshift" %}
13053
13054 ins_encode %{
13055 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13056 as_Register($src2$$reg), ext::sxtw, ($lshift$$constant));
13057 %}
13058 ins_pipe(ialu_reg_reg_shift);
13059 %}
13060
13061 // This pattern is automatically generated from aarch64_ad.m4
13062 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13063 instruct AddExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)
13064 %{
13065 match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
13066 ins_cost(1.9 * INSN_COST);
13067 format %{ "add $dst, $src1, $src2, uxtb #lshift" %}
13068
13069 ins_encode %{
13070 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13071 as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
13072 %}
13073 ins_pipe(ialu_reg_reg_shift);
13074 %}
13075
13076 // This pattern is automatically generated from aarch64_ad.m4
13077 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13078 instruct AddExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)
13079 %{
13080 match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
13081 ins_cost(1.9 * INSN_COST);
13082 format %{ "add $dst, $src1, $src2, uxth #lshift" %}
13083
13084 ins_encode %{
13085 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13086 as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
13087 %}
13088 ins_pipe(ialu_reg_reg_shift);
13089 %}
13090
13091 // This pattern is automatically generated from aarch64_ad.m4
13092 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13093 instruct AddExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)
13094 %{
13095 match(Set dst (AddL src1 (LShiftL (AndL src2 mask) lshift)));
13096 ins_cost(1.9 * INSN_COST);
13097 format %{ "add $dst, $src1, $src2, uxtw #lshift" %}
13098
13099 ins_encode %{
13100 __ add(as_Register($dst$$reg), as_Register($src1$$reg),
13101 as_Register($src2$$reg), ext::uxtw, ($lshift$$constant));
13102 %}
13103 ins_pipe(ialu_reg_reg_shift);
13104 %}
13105
13106 // This pattern is automatically generated from aarch64_ad.m4
13107 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13108 instruct SubExtL_uxtb_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_255 mask, immIExt lshift, rFlagsReg cr)
13109 %{
13110 match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
13111 ins_cost(1.9 * INSN_COST);
13112 format %{ "sub $dst, $src1, $src2, uxtb #lshift" %}
13113
13114 ins_encode %{
13115 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13116 as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
13117 %}
13118 ins_pipe(ialu_reg_reg_shift);
13119 %}
13120
13121 // This pattern is automatically generated from aarch64_ad.m4
13122 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13123 instruct SubExtL_uxth_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_65535 mask, immIExt lshift, rFlagsReg cr)
13124 %{
13125 match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
13126 ins_cost(1.9 * INSN_COST);
13127 format %{ "sub $dst, $src1, $src2, uxth #lshift" %}
13128
13129 ins_encode %{
13130 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13131 as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
13132 %}
13133 ins_pipe(ialu_reg_reg_shift);
13134 %}
13135
13136 // This pattern is automatically generated from aarch64_ad.m4
13137 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13138 instruct SubExtL_uxtw_and_shift(iRegLNoSp dst, iRegL src1, iRegL src2, immL_4294967295 mask, immIExt lshift, rFlagsReg cr)
13139 %{
13140 match(Set dst (SubL src1 (LShiftL (AndL src2 mask) lshift)));
13141 ins_cost(1.9 * INSN_COST);
13142 format %{ "sub $dst, $src1, $src2, uxtw #lshift" %}
13143
13144 ins_encode %{
13145 __ sub(as_Register($dst$$reg), as_Register($src1$$reg),
13146 as_Register($src2$$reg), ext::uxtw, ($lshift$$constant));
13147 %}
13148 ins_pipe(ialu_reg_reg_shift);
13149 %}
13150
13151 // This pattern is automatically generated from aarch64_ad.m4
13152 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13153 instruct AddExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)
13154 %{
13155 match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));
13156 ins_cost(1.9 * INSN_COST);
13157 format %{ "addw $dst, $src1, $src2, uxtb #lshift" %}
13158
13159 ins_encode %{
13160 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
13161 as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
13162 %}
13163 ins_pipe(ialu_reg_reg_shift);
13164 %}
13165
13166 // This pattern is automatically generated from aarch64_ad.m4
13167 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13168 instruct AddExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)
13169 %{
13170 match(Set dst (AddI src1 (LShiftI (AndI src2 mask) lshift)));
13171 ins_cost(1.9 * INSN_COST);
13172 format %{ "addw $dst, $src1, $src2, uxth #lshift" %}
13173
13174 ins_encode %{
13175 __ addw(as_Register($dst$$reg), as_Register($src1$$reg),
13176 as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
13177 %}
13178 ins_pipe(ialu_reg_reg_shift);
13179 %}
13180
13181 // This pattern is automatically generated from aarch64_ad.m4
13182 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13183 instruct SubExtI_uxtb_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_255 mask, immIExt lshift, rFlagsReg cr)
13184 %{
13185 match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));
13186 ins_cost(1.9 * INSN_COST);
13187 format %{ "subw $dst, $src1, $src2, uxtb #lshift" %}
13188
13189 ins_encode %{
13190 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
13191 as_Register($src2$$reg), ext::uxtb, ($lshift$$constant));
13192 %}
13193 ins_pipe(ialu_reg_reg_shift);
13194 %}
13195
13196 // This pattern is automatically generated from aarch64_ad.m4
13197 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13198 instruct SubExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI_65535 mask, immIExt lshift, rFlagsReg cr)
13199 %{
13200 match(Set dst (SubI src1 (LShiftI (AndI src2 mask) lshift)));
13201 ins_cost(1.9 * INSN_COST);
13202 format %{ "subw $dst, $src1, $src2, uxth #lshift" %}
13203
13204 ins_encode %{
13205 __ subw(as_Register($dst$$reg), as_Register($src1$$reg),
13206 as_Register($src2$$reg), ext::uxth, ($lshift$$constant));
13207 %}
13208 ins_pipe(ialu_reg_reg_shift);
13209 %}
13210
13211 // This pattern is automatically generated from aarch64_ad.m4
13212 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13213 instruct cmovI_reg_reg_lt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
13214 %{
13215 effect(DEF dst, USE src1, USE src2, USE cr);
13216 ins_cost(INSN_COST * 2);
13217 format %{ "cselw $dst, $src1, $src2 lt\t" %}
13218
13219 ins_encode %{
13220 __ cselw($dst$$Register,
13221 $src1$$Register,
13222 $src2$$Register,
13223 Assembler::LT);
13224 %}
13225 ins_pipe(icond_reg_reg);
13226 %}
13227
13228 // This pattern is automatically generated from aarch64_ad.m4
13229 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13230 instruct cmovI_reg_reg_gt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
13231 %{
13232 effect(DEF dst, USE src1, USE src2, USE cr);
13233 ins_cost(INSN_COST * 2);
13234 format %{ "cselw $dst, $src1, $src2 gt\t" %}
13235
13236 ins_encode %{
13237 __ cselw($dst$$Register,
13238 $src1$$Register,
13239 $src2$$Register,
13240 Assembler::GT);
13241 %}
13242 ins_pipe(icond_reg_reg);
13243 %}
13244
13245 // This pattern is automatically generated from aarch64_ad.m4
13246 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13247 instruct cmovI_reg_imm0_lt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13248 %{
13249 effect(DEF dst, USE src1, USE cr);
13250 ins_cost(INSN_COST * 2);
13251 format %{ "cselw $dst, $src1, zr lt\t" %}
13252
13253 ins_encode %{
13254 __ cselw($dst$$Register,
13255 $src1$$Register,
13256 zr,
13257 Assembler::LT);
13258 %}
13259 ins_pipe(icond_reg);
13260 %}
13261
13262 // This pattern is automatically generated from aarch64_ad.m4
13263 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13264 instruct cmovI_reg_imm0_gt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13265 %{
13266 effect(DEF dst, USE src1, USE cr);
13267 ins_cost(INSN_COST * 2);
13268 format %{ "cselw $dst, $src1, zr gt\t" %}
13269
13270 ins_encode %{
13271 __ cselw($dst$$Register,
13272 $src1$$Register,
13273 zr,
13274 Assembler::GT);
13275 %}
13276 ins_pipe(icond_reg);
13277 %}
13278
13279 // This pattern is automatically generated from aarch64_ad.m4
13280 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13281 instruct cmovI_reg_imm1_le(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13282 %{
13283 effect(DEF dst, USE src1, USE cr);
13284 ins_cost(INSN_COST * 2);
13285 format %{ "csincw $dst, $src1, zr le\t" %}
13286
13287 ins_encode %{
13288 __ csincw($dst$$Register,
13289 $src1$$Register,
13290 zr,
13291 Assembler::LE);
13292 %}
13293 ins_pipe(icond_reg);
13294 %}
13295
13296 // This pattern is automatically generated from aarch64_ad.m4
13297 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13298 instruct cmovI_reg_imm1_gt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13299 %{
13300 effect(DEF dst, USE src1, USE cr);
13301 ins_cost(INSN_COST * 2);
13302 format %{ "csincw $dst, $src1, zr gt\t" %}
13303
13304 ins_encode %{
13305 __ csincw($dst$$Register,
13306 $src1$$Register,
13307 zr,
13308 Assembler::GT);
13309 %}
13310 ins_pipe(icond_reg);
13311 %}
13312
13313 // This pattern is automatically generated from aarch64_ad.m4
13314 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13315 instruct cmovI_reg_immM1_lt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13316 %{
13317 effect(DEF dst, USE src1, USE cr);
13318 ins_cost(INSN_COST * 2);
13319 format %{ "csinvw $dst, $src1, zr lt\t" %}
13320
13321 ins_encode %{
13322 __ csinvw($dst$$Register,
13323 $src1$$Register,
13324 zr,
13325 Assembler::LT);
13326 %}
13327 ins_pipe(icond_reg);
13328 %}
13329
13330 // This pattern is automatically generated from aarch64_ad.m4
13331 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13332 instruct cmovI_reg_immM1_ge(iRegINoSp dst, iRegI src1, rFlagsReg cr)
13333 %{
13334 effect(DEF dst, USE src1, USE cr);
13335 ins_cost(INSN_COST * 2);
13336 format %{ "csinvw $dst, $src1, zr ge\t" %}
13337
13338 ins_encode %{
13339 __ csinvw($dst$$Register,
13340 $src1$$Register,
13341 zr,
13342 Assembler::GE);
13343 %}
13344 ins_pipe(icond_reg);
13345 %}
13346
13347 // This pattern is automatically generated from aarch64_ad.m4
13348 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13349 instruct minI_reg_imm0(iRegINoSp dst, iRegIorL2I src, immI0 imm)
13350 %{
13351 match(Set dst (MinI src imm));
13352 ins_cost(INSN_COST * 3);
13353 expand %{
13354 rFlagsReg cr;
13355 compI_reg_imm0(cr, src);
13356 cmovI_reg_imm0_lt(dst, src, cr);
13357 %}
13358 %}
13359
13360 // This pattern is automatically generated from aarch64_ad.m4
13361 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13362 instruct minI_imm0_reg(iRegINoSp dst, immI0 imm, iRegIorL2I src)
13363 %{
13364 match(Set dst (MinI imm src));
13365 ins_cost(INSN_COST * 3);
13366 expand %{
13367 rFlagsReg cr;
13368 compI_reg_imm0(cr, src);
13369 cmovI_reg_imm0_lt(dst, src, cr);
13370 %}
13371 %}
13372
13373 // This pattern is automatically generated from aarch64_ad.m4
13374 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13375 instruct minI_reg_imm1(iRegINoSp dst, iRegIorL2I src, immI_1 imm)
13376 %{
13377 match(Set dst (MinI src imm));
13378 ins_cost(INSN_COST * 3);
13379 expand %{
13380 rFlagsReg cr;
13381 compI_reg_imm0(cr, src);
13382 cmovI_reg_imm1_le(dst, src, cr);
13383 %}
13384 %}
13385
13386 // This pattern is automatically generated from aarch64_ad.m4
13387 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13388 instruct minI_imm1_reg(iRegINoSp dst, immI_1 imm, iRegIorL2I src)
13389 %{
13390 match(Set dst (MinI imm src));
13391 ins_cost(INSN_COST * 3);
13392 expand %{
13393 rFlagsReg cr;
13394 compI_reg_imm0(cr, src);
13395 cmovI_reg_imm1_le(dst, src, cr);
13396 %}
13397 %}
13398
13399 // This pattern is automatically generated from aarch64_ad.m4
13400 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13401 instruct minI_reg_immM1(iRegINoSp dst, iRegIorL2I src, immI_M1 imm)
13402 %{
13403 match(Set dst (MinI src imm));
13404 ins_cost(INSN_COST * 3);
13405 expand %{
13406 rFlagsReg cr;
13407 compI_reg_imm0(cr, src);
13408 cmovI_reg_immM1_lt(dst, src, cr);
13409 %}
13410 %}
13411
13412 // This pattern is automatically generated from aarch64_ad.m4
13413 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13414 instruct minI_immM1_reg(iRegINoSp dst, immI_M1 imm, iRegIorL2I src)
13415 %{
13416 match(Set dst (MinI imm src));
13417 ins_cost(INSN_COST * 3);
13418 expand %{
13419 rFlagsReg cr;
13420 compI_reg_imm0(cr, src);
13421 cmovI_reg_immM1_lt(dst, src, cr);
13422 %}
13423 %}
13424
13425 // This pattern is automatically generated from aarch64_ad.m4
13426 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13427 instruct maxI_reg_imm0(iRegINoSp dst, iRegIorL2I src, immI0 imm)
13428 %{
13429 match(Set dst (MaxI src imm));
13430 ins_cost(INSN_COST * 3);
13431 expand %{
13432 rFlagsReg cr;
13433 compI_reg_imm0(cr, src);
13434 cmovI_reg_imm0_gt(dst, src, cr);
13435 %}
13436 %}
13437
13438 // This pattern is automatically generated from aarch64_ad.m4
13439 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13440 instruct maxI_imm0_reg(iRegINoSp dst, immI0 imm, iRegIorL2I src)
13441 %{
13442 match(Set dst (MaxI imm src));
13443 ins_cost(INSN_COST * 3);
13444 expand %{
13445 rFlagsReg cr;
13446 compI_reg_imm0(cr, src);
13447 cmovI_reg_imm0_gt(dst, src, cr);
13448 %}
13449 %}
13450
13451 // This pattern is automatically generated from aarch64_ad.m4
13452 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13453 instruct maxI_reg_imm1(iRegINoSp dst, iRegIorL2I src, immI_1 imm)
13454 %{
13455 match(Set dst (MaxI src imm));
13456 ins_cost(INSN_COST * 3);
13457 expand %{
13458 rFlagsReg cr;
13459 compI_reg_imm0(cr, src);
13460 cmovI_reg_imm1_gt(dst, src, cr);
13461 %}
13462 %}
13463
13464 // This pattern is automatically generated from aarch64_ad.m4
13465 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13466 instruct maxI_imm1_reg(iRegINoSp dst, immI_1 imm, iRegIorL2I src)
13467 %{
13468 match(Set dst (MaxI imm src));
13469 ins_cost(INSN_COST * 3);
13470 expand %{
13471 rFlagsReg cr;
13472 compI_reg_imm0(cr, src);
13473 cmovI_reg_imm1_gt(dst, src, cr);
13474 %}
13475 %}
13476
13477 // This pattern is automatically generated from aarch64_ad.m4
13478 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13479 instruct maxI_reg_immM1(iRegINoSp dst, iRegIorL2I src, immI_M1 imm)
13480 %{
13481 match(Set dst (MaxI src imm));
13482 ins_cost(INSN_COST * 3);
13483 expand %{
13484 rFlagsReg cr;
13485 compI_reg_imm0(cr, src);
13486 cmovI_reg_immM1_ge(dst, src, cr);
13487 %}
13488 %}
13489
13490 // This pattern is automatically generated from aarch64_ad.m4
13491 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13492 instruct maxI_immM1_reg(iRegINoSp dst, immI_M1 imm, iRegIorL2I src)
13493 %{
13494 match(Set dst (MaxI imm src));
13495 ins_cost(INSN_COST * 3);
13496 expand %{
13497 rFlagsReg cr;
13498 compI_reg_imm0(cr, src);
13499 cmovI_reg_immM1_ge(dst, src, cr);
13500 %}
13501 %}
13502
13503 // This pattern is automatically generated from aarch64_ad.m4
13504 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13505 instruct bits_reverse_I(iRegINoSp dst, iRegIorL2I src)
13506 %{
13507 match(Set dst (ReverseI src));
13508 ins_cost(INSN_COST);
13509 format %{ "rbitw $dst, $src" %}
13510 ins_encode %{
13511 __ rbitw($dst$$Register, $src$$Register);
13512 %}
13513 ins_pipe(ialu_reg);
13514 %}
13515
13516 // This pattern is automatically generated from aarch64_ad.m4
13517 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
13518 instruct bits_reverse_L(iRegLNoSp dst, iRegL src)
13519 %{
13520 match(Set dst (ReverseL src));
13521 ins_cost(INSN_COST);
13522 format %{ "rbit $dst, $src" %}
13523 ins_encode %{
13524 __ rbit($dst$$Register, $src$$Register);
13525 %}
13526 ins_pipe(ialu_reg);
13527 %}
13528
13529
13530 // END This section of the file is automatically generated. Do not edit --------------
13531
13532
13533 // ============================================================================
13534 // Floating Point Arithmetic Instructions
13535
13536 instruct addF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
13537 match(Set dst (AddF src1 src2));
13538
13539 ins_cost(INSN_COST * 5);
13540 format %{ "fadds $dst, $src1, $src2" %}
13541
13542 ins_encode %{
13543 __ fadds(as_FloatRegister($dst$$reg),
13544 as_FloatRegister($src1$$reg),
13545 as_FloatRegister($src2$$reg));
13546 %}
13547
13548 ins_pipe(fp_dop_reg_reg_s);
13549 %}
13550
13551 instruct addD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
13552 match(Set dst (AddD src1 src2));
13553
13554 ins_cost(INSN_COST * 5);
13555 format %{ "faddd $dst, $src1, $src2" %}
13556
13557 ins_encode %{
13558 __ faddd(as_FloatRegister($dst$$reg),
13559 as_FloatRegister($src1$$reg),
13560 as_FloatRegister($src2$$reg));
13561 %}
13562
13563 ins_pipe(fp_dop_reg_reg_d);
13564 %}
13565
13566 instruct subF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
13567 match(Set dst (SubF src1 src2));
13568
13569 ins_cost(INSN_COST * 5);
13570 format %{ "fsubs $dst, $src1, $src2" %}
13571
13572 ins_encode %{
13573 __ fsubs(as_FloatRegister($dst$$reg),
13574 as_FloatRegister($src1$$reg),
13575 as_FloatRegister($src2$$reg));
13576 %}
13577
13578 ins_pipe(fp_dop_reg_reg_s);
13579 %}
13580
13581 instruct subD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
13582 match(Set dst (SubD src1 src2));
13583
13584 ins_cost(INSN_COST * 5);
13585 format %{ "fsubd $dst, $src1, $src2" %}
13586
13587 ins_encode %{
13588 __ fsubd(as_FloatRegister($dst$$reg),
13589 as_FloatRegister($src1$$reg),
13590 as_FloatRegister($src2$$reg));
13591 %}
13592
13593 ins_pipe(fp_dop_reg_reg_d);
13594 %}
13595
13596 instruct mulF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
13597 match(Set dst (MulF src1 src2));
13598
13599 ins_cost(INSN_COST * 6);
13600 format %{ "fmuls $dst, $src1, $src2" %}
13601
13602 ins_encode %{
13603 __ fmuls(as_FloatRegister($dst$$reg),
13604 as_FloatRegister($src1$$reg),
13605 as_FloatRegister($src2$$reg));
13606 %}
13607
13608 ins_pipe(fp_dop_reg_reg_s);
13609 %}
13610
13611 instruct mulD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
13612 match(Set dst (MulD src1 src2));
13613
13614 ins_cost(INSN_COST * 6);
13615 format %{ "fmuld $dst, $src1, $src2" %}
13616
13617 ins_encode %{
13618 __ fmuld(as_FloatRegister($dst$$reg),
13619 as_FloatRegister($src1$$reg),
13620 as_FloatRegister($src2$$reg));
13621 %}
13622
13623 ins_pipe(fp_dop_reg_reg_d);
13624 %}
13625
13626 // src1 * src2 + src3
13627 instruct maddF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3) %{
13628 match(Set dst (FmaF src3 (Binary src1 src2)));
13629
13630 format %{ "fmadds $dst, $src1, $src2, $src3" %}
13631
13632 ins_encode %{
13633 assert(UseFMA, "Needs FMA instructions support.");
13634 __ fmadds(as_FloatRegister($dst$$reg),
13635 as_FloatRegister($src1$$reg),
13636 as_FloatRegister($src2$$reg),
13637 as_FloatRegister($src3$$reg));
13638 %}
13639
13640 ins_pipe(pipe_class_default);
13641 %}
13642
13643 // src1 * src2 + src3
13644 instruct maddD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3) %{
13645 match(Set dst (FmaD src3 (Binary src1 src2)));
13646
13647 format %{ "fmaddd $dst, $src1, $src2, $src3" %}
13648
13649 ins_encode %{
13650 assert(UseFMA, "Needs FMA instructions support.");
13651 __ fmaddd(as_FloatRegister($dst$$reg),
13652 as_FloatRegister($src1$$reg),
13653 as_FloatRegister($src2$$reg),
13654 as_FloatRegister($src3$$reg));
13655 %}
13656
13657 ins_pipe(pipe_class_default);
13658 %}
13659
13660 // src1 * (-src2) + src3
13661 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
13662 instruct msubF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3) %{
13663 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
13664
13665 format %{ "fmsubs $dst, $src1, $src2, $src3" %}
13666
13667 ins_encode %{
13668 assert(UseFMA, "Needs FMA instructions support.");
13669 __ fmsubs(as_FloatRegister($dst$$reg),
13670 as_FloatRegister($src1$$reg),
13671 as_FloatRegister($src2$$reg),
13672 as_FloatRegister($src3$$reg));
13673 %}
13674
13675 ins_pipe(pipe_class_default);
13676 %}
13677
13678 // src1 * (-src2) + src3
13679 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
13680 instruct msubD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3) %{
13681 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
13682
13683 format %{ "fmsubd $dst, $src1, $src2, $src3" %}
13684
13685 ins_encode %{
13686 assert(UseFMA, "Needs FMA instructions support.");
13687 __ fmsubd(as_FloatRegister($dst$$reg),
13688 as_FloatRegister($src1$$reg),
13689 as_FloatRegister($src2$$reg),
13690 as_FloatRegister($src3$$reg));
13691 %}
13692
13693 ins_pipe(pipe_class_default);
13694 %}
13695
13696 // src1 * (-src2) - src3
13697 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
13698 instruct mnaddF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3) %{
13699 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
13700
13701 format %{ "fnmadds $dst, $src1, $src2, $src3" %}
13702
13703 ins_encode %{
13704 assert(UseFMA, "Needs FMA instructions support.");
13705 __ fnmadds(as_FloatRegister($dst$$reg),
13706 as_FloatRegister($src1$$reg),
13707 as_FloatRegister($src2$$reg),
13708 as_FloatRegister($src3$$reg));
13709 %}
13710
13711 ins_pipe(pipe_class_default);
13712 %}
13713
13714 // src1 * (-src2) - src3
13715 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
13716 instruct mnaddD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3) %{
13717 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
13718
13719 format %{ "fnmaddd $dst, $src1, $src2, $src3" %}
13720
13721 ins_encode %{
13722 assert(UseFMA, "Needs FMA instructions support.");
13723 __ fnmaddd(as_FloatRegister($dst$$reg),
13724 as_FloatRegister($src1$$reg),
13725 as_FloatRegister($src2$$reg),
13726 as_FloatRegister($src3$$reg));
13727 %}
13728
13729 ins_pipe(pipe_class_default);
13730 %}
13731
13732 // src1 * src2 - src3
13733 instruct mnsubF_reg_reg(vRegF dst, vRegF src1, vRegF src2, vRegF src3, immF0 zero) %{
13734 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
13735
13736 format %{ "fnmsubs $dst, $src1, $src2, $src3" %}
13737
13738 ins_encode %{
13739 assert(UseFMA, "Needs FMA instructions support.");
13740 __ fnmsubs(as_FloatRegister($dst$$reg),
13741 as_FloatRegister($src1$$reg),
13742 as_FloatRegister($src2$$reg),
13743 as_FloatRegister($src3$$reg));
13744 %}
13745
13746 ins_pipe(pipe_class_default);
13747 %}
13748
13749 // src1 * src2 - src3
13750 instruct mnsubD_reg_reg(vRegD dst, vRegD src1, vRegD src2, vRegD src3, immD0 zero) %{
13751 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
13752
13753 format %{ "fnmsubd $dst, $src1, $src2, $src3" %}
13754
13755 ins_encode %{
13756 assert(UseFMA, "Needs FMA instructions support.");
13757 // n.b. insn name should be fnmsubd
13758 __ fnmsub(as_FloatRegister($dst$$reg),
13759 as_FloatRegister($src1$$reg),
13760 as_FloatRegister($src2$$reg),
13761 as_FloatRegister($src3$$reg));
13762 %}
13763
13764 ins_pipe(pipe_class_default);
13765 %}
13766
13767
13768 // Math.max(FF)F
13769 instruct maxF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
13770 match(Set dst (MaxF src1 src2));
13771
13772 format %{ "fmaxs $dst, $src1, $src2" %}
13773 ins_encode %{
13774 __ fmaxs(as_FloatRegister($dst$$reg),
13775 as_FloatRegister($src1$$reg),
13776 as_FloatRegister($src2$$reg));
13777 %}
13778
13779 ins_pipe(fp_dop_reg_reg_s);
13780 %}
13781
13782 // Math.min(FF)F
13783 instruct minF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
13784 match(Set dst (MinF src1 src2));
13785
13786 format %{ "fmins $dst, $src1, $src2" %}
13787 ins_encode %{
13788 __ fmins(as_FloatRegister($dst$$reg),
13789 as_FloatRegister($src1$$reg),
13790 as_FloatRegister($src2$$reg));
13791 %}
13792
13793 ins_pipe(fp_dop_reg_reg_s);
13794 %}
13795
13796 // Math.max(DD)D
13797 instruct maxD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
13798 match(Set dst (MaxD src1 src2));
13799
13800 format %{ "fmaxd $dst, $src1, $src2" %}
13801 ins_encode %{
13802 __ fmaxd(as_FloatRegister($dst$$reg),
13803 as_FloatRegister($src1$$reg),
13804 as_FloatRegister($src2$$reg));
13805 %}
13806
13807 ins_pipe(fp_dop_reg_reg_d);
13808 %}
13809
13810 // Math.min(DD)D
13811 instruct minD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
13812 match(Set dst (MinD src1 src2));
13813
13814 format %{ "fmind $dst, $src1, $src2" %}
13815 ins_encode %{
13816 __ fmind(as_FloatRegister($dst$$reg),
13817 as_FloatRegister($src1$$reg),
13818 as_FloatRegister($src2$$reg));
13819 %}
13820
13821 ins_pipe(fp_dop_reg_reg_d);
13822 %}
13823
13824
13825 instruct divF_reg_reg(vRegF dst, vRegF src1, vRegF src2) %{
13826 match(Set dst (DivF src1 src2));
13827
13828 ins_cost(INSN_COST * 18);
13829 format %{ "fdivs $dst, $src1, $src2" %}
13830
13831 ins_encode %{
13832 __ fdivs(as_FloatRegister($dst$$reg),
13833 as_FloatRegister($src1$$reg),
13834 as_FloatRegister($src2$$reg));
13835 %}
13836
13837 ins_pipe(fp_div_s);
13838 %}
13839
13840 instruct divD_reg_reg(vRegD dst, vRegD src1, vRegD src2) %{
13841 match(Set dst (DivD src1 src2));
13842
13843 ins_cost(INSN_COST * 32);
13844 format %{ "fdivd $dst, $src1, $src2" %}
13845
13846 ins_encode %{
13847 __ fdivd(as_FloatRegister($dst$$reg),
13848 as_FloatRegister($src1$$reg),
13849 as_FloatRegister($src2$$reg));
13850 %}
13851
13852 ins_pipe(fp_div_d);
13853 %}
13854
13855 instruct negF_reg_reg(vRegF dst, vRegF src) %{
13856 match(Set dst (NegF src));
13857
13858 ins_cost(INSN_COST * 3);
13859 format %{ "fneg $dst, $src" %}
13860
13861 ins_encode %{
13862 __ fnegs(as_FloatRegister($dst$$reg),
13863 as_FloatRegister($src$$reg));
13864 %}
13865
13866 ins_pipe(fp_uop_s);
13867 %}
13868
13869 instruct negD_reg_reg(vRegD dst, vRegD src) %{
13870 match(Set dst (NegD src));
13871
13872 ins_cost(INSN_COST * 3);
13873 format %{ "fnegd $dst, $src" %}
13874
13875 ins_encode %{
13876 __ fnegd(as_FloatRegister($dst$$reg),
13877 as_FloatRegister($src$$reg));
13878 %}
13879
13880 ins_pipe(fp_uop_d);
13881 %}
13882
13883 instruct absI_reg(iRegINoSp dst, iRegIorL2I src, rFlagsReg cr)
13884 %{
13885 match(Set dst (AbsI src));
13886
13887 effect(KILL cr);
13888 ins_cost(INSN_COST * 2);
13889 format %{ "cmpw $src, zr\n\t"
13890 "cnegw $dst, $src, Assembler::LT\t# int abs"
13891 %}
13892
13893 ins_encode %{
13894 __ cmpw(as_Register($src$$reg), zr);
13895 __ cnegw(as_Register($dst$$reg), as_Register($src$$reg), Assembler::LT);
13896 %}
13897 ins_pipe(pipe_class_default);
13898 %}
13899
13900 instruct absL_reg(iRegLNoSp dst, iRegL src, rFlagsReg cr)
13901 %{
13902 match(Set dst (AbsL src));
13903
13904 effect(KILL cr);
13905 ins_cost(INSN_COST * 2);
13906 format %{ "cmp $src, zr\n\t"
13907 "cneg $dst, $src, Assembler::LT\t# long abs"
13908 %}
13909
13910 ins_encode %{
13911 __ cmp(as_Register($src$$reg), zr);
13912 __ cneg(as_Register($dst$$reg), as_Register($src$$reg), Assembler::LT);
13913 %}
13914 ins_pipe(pipe_class_default);
13915 %}
13916
13917 instruct absF_reg(vRegF dst, vRegF src) %{
13918 match(Set dst (AbsF src));
13919
13920 ins_cost(INSN_COST * 3);
13921 format %{ "fabss $dst, $src" %}
13922 ins_encode %{
13923 __ fabss(as_FloatRegister($dst$$reg),
13924 as_FloatRegister($src$$reg));
13925 %}
13926
13927 ins_pipe(fp_uop_s);
13928 %}
13929
13930 instruct absD_reg(vRegD dst, vRegD src) %{
13931 match(Set dst (AbsD src));
13932
13933 ins_cost(INSN_COST * 3);
13934 format %{ "fabsd $dst, $src" %}
13935 ins_encode %{
13936 __ fabsd(as_FloatRegister($dst$$reg),
13937 as_FloatRegister($src$$reg));
13938 %}
13939
13940 ins_pipe(fp_uop_d);
13941 %}
13942
13943 instruct absdF_reg(vRegF dst, vRegF src1, vRegF src2) %{
13944 match(Set dst (AbsF (SubF src1 src2)));
13945
13946 ins_cost(INSN_COST * 3);
13947 format %{ "fabds $dst, $src1, $src2" %}
13948 ins_encode %{
13949 __ fabds(as_FloatRegister($dst$$reg),
13950 as_FloatRegister($src1$$reg),
13951 as_FloatRegister($src2$$reg));
13952 %}
13953
13954 ins_pipe(fp_uop_s);
13955 %}
13956
13957 instruct absdD_reg(vRegD dst, vRegD src1, vRegD src2) %{
13958 match(Set dst (AbsD (SubD src1 src2)));
13959
13960 ins_cost(INSN_COST * 3);
13961 format %{ "fabdd $dst, $src1, $src2" %}
13962 ins_encode %{
13963 __ fabdd(as_FloatRegister($dst$$reg),
13964 as_FloatRegister($src1$$reg),
13965 as_FloatRegister($src2$$reg));
13966 %}
13967
13968 ins_pipe(fp_uop_d);
13969 %}
13970
13971 instruct sqrtD_reg(vRegD dst, vRegD src) %{
13972 match(Set dst (SqrtD src));
13973
13974 ins_cost(INSN_COST * 50);
13975 format %{ "fsqrtd $dst, $src" %}
13976 ins_encode %{
13977 __ fsqrtd(as_FloatRegister($dst$$reg),
13978 as_FloatRegister($src$$reg));
13979 %}
13980
13981 ins_pipe(fp_div_s);
13982 %}
13983
13984 instruct sqrtF_reg(vRegF dst, vRegF src) %{
13985 match(Set dst (SqrtF src));
13986
13987 ins_cost(INSN_COST * 50);
13988 format %{ "fsqrts $dst, $src" %}
13989 ins_encode %{
13990 __ fsqrts(as_FloatRegister($dst$$reg),
13991 as_FloatRegister($src$$reg));
13992 %}
13993
13994 ins_pipe(fp_div_d);
13995 %}
13996
13997 // Math.rint, floor, ceil
13998 instruct roundD_reg(vRegD dst, vRegD src, immI rmode) %{
13999 match(Set dst (RoundDoubleMode src rmode));
14000 format %{ "frint $dst, $src, $rmode" %}
14001 ins_encode %{
14002 switch ($rmode$$constant) {
14003 case RoundDoubleModeNode::rmode_rint:
14004 __ frintnd(as_FloatRegister($dst$$reg),
14005 as_FloatRegister($src$$reg));
14006 break;
14007 case RoundDoubleModeNode::rmode_floor:
14008 __ frintmd(as_FloatRegister($dst$$reg),
14009 as_FloatRegister($src$$reg));
14010 break;
14011 case RoundDoubleModeNode::rmode_ceil:
14012 __ frintpd(as_FloatRegister($dst$$reg),
14013 as_FloatRegister($src$$reg));
14014 break;
14015 }
14016 %}
14017 ins_pipe(fp_uop_d);
14018 %}
14019
14020 instruct copySignD_reg(vRegD dst, vRegD src1, vRegD src2, vRegD zero) %{
14021 match(Set dst (CopySignD src1 (Binary src2 zero)));
14022 effect(TEMP_DEF dst, USE src1, USE src2, USE zero);
14023 format %{ "CopySignD $dst $src1 $src2" %}
14024 ins_encode %{
14025 FloatRegister dst = as_FloatRegister($dst$$reg),
14026 src1 = as_FloatRegister($src1$$reg),
14027 src2 = as_FloatRegister($src2$$reg),
14028 zero = as_FloatRegister($zero$$reg);
14029 __ fnegd(dst, zero);
14030 __ bsl(dst, __ T8B, src2, src1);
14031 %}
14032 ins_pipe(fp_uop_d);
14033 %}
14034
14035 instruct copySignF_reg(vRegF dst, vRegF src1, vRegF src2) %{
14036 match(Set dst (CopySignF src1 src2));
14037 effect(TEMP_DEF dst, USE src1, USE src2);
14038 format %{ "CopySignF $dst $src1 $src2" %}
14039 ins_encode %{
14040 FloatRegister dst = as_FloatRegister($dst$$reg),
14041 src1 = as_FloatRegister($src1$$reg),
14042 src2 = as_FloatRegister($src2$$reg);
14043 __ movi(dst, __ T2S, 0x80, 24);
14044 __ bsl(dst, __ T8B, src2, src1);
14045 %}
14046 ins_pipe(fp_uop_d);
14047 %}
14048
14049 instruct signumD_reg(vRegD dst, vRegD src, vRegD zero, vRegD one) %{
14050 match(Set dst (SignumD src (Binary zero one)));
14051 effect(TEMP_DEF dst, USE src, USE zero, USE one);
14052 format %{ "signumD $dst, $src" %}
14053 ins_encode %{
14054 FloatRegister src = as_FloatRegister($src$$reg),
14055 dst = as_FloatRegister($dst$$reg),
14056 zero = as_FloatRegister($zero$$reg),
14057 one = as_FloatRegister($one$$reg);
14058 __ facgtd(dst, src, zero); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
14059 __ ushrd(dst, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
14060 // Bit selection instruction gets bit from "one" for each enabled bit in
14061 // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
14062 // NaN the whole "src" will be copied because "dst" is zero. For all other
14063 // "src" values dst is 0x7FF..F, which means only the sign bit is copied
14064 // from "src", and all other bits are copied from 1.0.
14065 __ bsl(dst, __ T8B, one, src);
14066 %}
14067 ins_pipe(fp_uop_d);
14068 %}
14069
14070 instruct signumF_reg(vRegF dst, vRegF src, vRegF zero, vRegF one) %{
14071 match(Set dst (SignumF src (Binary zero one)));
14072 effect(TEMP_DEF dst, USE src, USE zero, USE one);
14073 format %{ "signumF $dst, $src" %}
14074 ins_encode %{
14075 FloatRegister src = as_FloatRegister($src$$reg),
14076 dst = as_FloatRegister($dst$$reg),
14077 zero = as_FloatRegister($zero$$reg),
14078 one = as_FloatRegister($one$$reg);
14079 __ facgts(dst, src, zero); // dst=0 for +-0.0 and NaN. 0xFFF..F otherwise
14080 __ ushr(dst, __ T2S, dst, 1); // dst=0 for +-0.0 and NaN. 0x7FF..F otherwise
14081 // Bit selection instruction gets bit from "one" for each enabled bit in
14082 // "dst", otherwise gets a bit from "src". For "src" that contains +-0.0 or
14083 // NaN the whole "src" will be copied because "dst" is zero. For all other
14084 // "src" values dst is 0x7FF..F, which means only the sign bit is copied
14085 // from "src", and all other bits are copied from 1.0.
14086 __ bsl(dst, __ T8B, one, src);
14087 %}
14088 ins_pipe(fp_uop_d);
14089 %}
14090
14091 instruct onspinwait() %{
14092 match(OnSpinWait);
14093 ins_cost(INSN_COST);
14094
14095 format %{ "onspinwait" %}
14096
14097 ins_encode %{
14098 __ spin_wait();
14099 %}
14100 ins_pipe(pipe_class_empty);
14101 %}
14102
14103 // ============================================================================
14104 // Logical Instructions
14105
14106 // Integer Logical Instructions
14107
14108 // And Instructions
14109
14110
14111 instruct andI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, rFlagsReg cr) %{
14112 match(Set dst (AndI src1 src2));
14113
14114 format %{ "andw $dst, $src1, $src2\t# int" %}
14115
14116 ins_cost(INSN_COST);
14117 ins_encode %{
14118 __ andw(as_Register($dst$$reg),
14119 as_Register($src1$$reg),
14120 as_Register($src2$$reg));
14121 %}
14122
14123 ins_pipe(ialu_reg_reg);
14124 %}
14125
14126 instruct andI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2, rFlagsReg cr) %{
14127 match(Set dst (AndI src1 src2));
14128
14129 format %{ "andsw $dst, $src1, $src2\t# int" %}
14130
14131 ins_cost(INSN_COST);
14132 ins_encode %{
14133 __ andw(as_Register($dst$$reg),
14134 as_Register($src1$$reg),
14135 (uint64_t)($src2$$constant));
14136 %}
14137
14138 ins_pipe(ialu_reg_imm);
14139 %}
14140
14141 // Or Instructions
14142
14143 instruct orI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
14144 match(Set dst (OrI src1 src2));
14145
14146 format %{ "orrw $dst, $src1, $src2\t# int" %}
14147
14148 ins_cost(INSN_COST);
14149 ins_encode %{
14150 __ orrw(as_Register($dst$$reg),
14151 as_Register($src1$$reg),
14152 as_Register($src2$$reg));
14153 %}
14154
14155 ins_pipe(ialu_reg_reg);
14156 %}
14157
14158 instruct orI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2) %{
14159 match(Set dst (OrI src1 src2));
14160
14161 format %{ "orrw $dst, $src1, $src2\t# int" %}
14162
14163 ins_cost(INSN_COST);
14164 ins_encode %{
14165 __ orrw(as_Register($dst$$reg),
14166 as_Register($src1$$reg),
14167 (uint64_t)($src2$$constant));
14168 %}
14169
14170 ins_pipe(ialu_reg_imm);
14171 %}
14172
14173 // Xor Instructions
14174
14175 instruct xorI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
14176 match(Set dst (XorI src1 src2));
14177
14178 format %{ "eorw $dst, $src1, $src2\t# int" %}
14179
14180 ins_cost(INSN_COST);
14181 ins_encode %{
14182 __ eorw(as_Register($dst$$reg),
14183 as_Register($src1$$reg),
14184 as_Register($src2$$reg));
14185 %}
14186
14187 ins_pipe(ialu_reg_reg);
14188 %}
14189
14190 instruct xorI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immILog src2) %{
14191 match(Set dst (XorI src1 src2));
14192
14193 format %{ "eorw $dst, $src1, $src2\t# int" %}
14194
14195 ins_cost(INSN_COST);
14196 ins_encode %{
14197 __ eorw(as_Register($dst$$reg),
14198 as_Register($src1$$reg),
14199 (uint64_t)($src2$$constant));
14200 %}
14201
14202 ins_pipe(ialu_reg_imm);
14203 %}
14204
14205 // Long Logical Instructions
14206 // TODO
14207
14208 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2, rFlagsReg cr) %{
14209 match(Set dst (AndL src1 src2));
14210
14211 format %{ "and $dst, $src1, $src2\t# int" %}
14212
14213 ins_cost(INSN_COST);
14214 ins_encode %{
14215 __ andr(as_Register($dst$$reg),
14216 as_Register($src1$$reg),
14217 as_Register($src2$$reg));
14218 %}
14219
14220 ins_pipe(ialu_reg_reg);
14221 %}
14222
14223 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2, rFlagsReg cr) %{
14224 match(Set dst (AndL src1 src2));
14225
14226 format %{ "and $dst, $src1, $src2\t# int" %}
14227
14228 ins_cost(INSN_COST);
14229 ins_encode %{
14230 __ andr(as_Register($dst$$reg),
14231 as_Register($src1$$reg),
14232 (uint64_t)($src2$$constant));
14233 %}
14234
14235 ins_pipe(ialu_reg_imm);
14236 %}
14237
14238 // Or Instructions
14239
14240 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
14241 match(Set dst (OrL src1 src2));
14242
14243 format %{ "orr $dst, $src1, $src2\t# int" %}
14244
14245 ins_cost(INSN_COST);
14246 ins_encode %{
14247 __ orr(as_Register($dst$$reg),
14248 as_Register($src1$$reg),
14249 as_Register($src2$$reg));
14250 %}
14251
14252 ins_pipe(ialu_reg_reg);
14253 %}
14254
14255 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2) %{
14256 match(Set dst (OrL src1 src2));
14257
14258 format %{ "orr $dst, $src1, $src2\t# int" %}
14259
14260 ins_cost(INSN_COST);
14261 ins_encode %{
14262 __ orr(as_Register($dst$$reg),
14263 as_Register($src1$$reg),
14264 (uint64_t)($src2$$constant));
14265 %}
14266
14267 ins_pipe(ialu_reg_imm);
14268 %}
14269
14270 // Xor Instructions
14271
14272 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
14273 match(Set dst (XorL src1 src2));
14274
14275 format %{ "eor $dst, $src1, $src2\t# int" %}
14276
14277 ins_cost(INSN_COST);
14278 ins_encode %{
14279 __ eor(as_Register($dst$$reg),
14280 as_Register($src1$$reg),
14281 as_Register($src2$$reg));
14282 %}
14283
14284 ins_pipe(ialu_reg_reg);
14285 %}
14286
14287 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLLog src2) %{
14288 match(Set dst (XorL src1 src2));
14289
14290 ins_cost(INSN_COST);
14291 format %{ "eor $dst, $src1, $src2\t# int" %}
14292
14293 ins_encode %{
14294 __ eor(as_Register($dst$$reg),
14295 as_Register($src1$$reg),
14296 (uint64_t)($src2$$constant));
14297 %}
14298
14299 ins_pipe(ialu_reg_imm);
14300 %}
14301
14302 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
14303 %{
14304 match(Set dst (ConvI2L src));
14305
14306 ins_cost(INSN_COST);
14307 format %{ "sxtw $dst, $src\t# i2l" %}
14308 ins_encode %{
14309 __ sbfm($dst$$Register, $src$$Register, 0, 31);
14310 %}
14311 ins_pipe(ialu_reg_shift);
14312 %}
14313
14314 // this pattern occurs in bigmath arithmetic
14315 instruct convUI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
14316 %{
14317 match(Set dst (AndL (ConvI2L src) mask));
14318
14319 ins_cost(INSN_COST);
14320 format %{ "ubfm $dst, $src, 0, 31\t# ui2l" %}
14321 ins_encode %{
14322 __ ubfm($dst$$Register, $src$$Register, 0, 31);
14323 %}
14324
14325 ins_pipe(ialu_reg_shift);
14326 %}
14327
14328 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
14329 match(Set dst (ConvL2I src));
14330
14331 ins_cost(INSN_COST);
14332 format %{ "movw $dst, $src \t// l2i" %}
14333
14334 ins_encode %{
14335 __ movw(as_Register($dst$$reg), as_Register($src$$reg));
14336 %}
14337
14338 ins_pipe(ialu_reg);
14339 %}
14340
14341 instruct convD2F_reg(vRegF dst, vRegD src) %{
14342 match(Set dst (ConvD2F src));
14343
14344 ins_cost(INSN_COST * 5);
14345 format %{ "fcvtd $dst, $src \t// d2f" %}
14346
14347 ins_encode %{
14348 __ fcvtd(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
14349 %}
14350
14351 ins_pipe(fp_d2f);
14352 %}
14353
14354 instruct convF2D_reg(vRegD dst, vRegF src) %{
14355 match(Set dst (ConvF2D src));
14356
14357 ins_cost(INSN_COST * 5);
14358 format %{ "fcvts $dst, $src \t// f2d" %}
14359
14360 ins_encode %{
14361 __ fcvts(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
14362 %}
14363
14364 ins_pipe(fp_f2d);
14365 %}
14366
14367 instruct convF2I_reg_reg(iRegINoSp dst, vRegF src) %{
14368 match(Set dst (ConvF2I src));
14369
14370 ins_cost(INSN_COST * 5);
14371 format %{ "fcvtzsw $dst, $src \t// f2i" %}
14372
14373 ins_encode %{
14374 __ fcvtzsw(as_Register($dst$$reg), as_FloatRegister($src$$reg));
14375 %}
14376
14377 ins_pipe(fp_f2i);
14378 %}
14379
14380 instruct convF2L_reg_reg(iRegLNoSp dst, vRegF src) %{
14381 match(Set dst (ConvF2L src));
14382
14383 ins_cost(INSN_COST * 5);
14384 format %{ "fcvtzs $dst, $src \t// f2l" %}
14385
14386 ins_encode %{
14387 __ fcvtzs(as_Register($dst$$reg), as_FloatRegister($src$$reg));
14388 %}
14389
14390 ins_pipe(fp_f2l);
14391 %}
14392
14393 instruct convF2HF_reg_reg(iRegINoSp dst, vRegF src, vRegF tmp) %{
14394 match(Set dst (ConvF2HF src));
14395 format %{ "fcvt $tmp, $src\t# convert single to half precision\n\t"
14396 "smov $dst, $tmp\t# move result from $tmp to $dst"
14397 %}
14398 effect(TEMP tmp);
14399 ins_encode %{
14400 __ flt_to_flt16($dst$$Register, $src$$FloatRegister, $tmp$$FloatRegister);
14401 %}
14402 ins_pipe(pipe_slow);
14403 %}
14404
14405 instruct convHF2F_reg_reg(vRegF dst, iRegINoSp src, vRegF tmp) %{
14406 match(Set dst (ConvHF2F src));
14407 format %{ "mov $tmp, $src\t# move source from $src to $tmp\n\t"
14408 "fcvt $dst, $tmp\t# convert half to single precision"
14409 %}
14410 effect(TEMP tmp);
14411 ins_encode %{
14412 __ flt16_to_flt($dst$$FloatRegister, $src$$Register, $tmp$$FloatRegister);
14413 %}
14414 ins_pipe(pipe_slow);
14415 %}
14416
14417 instruct convI2F_reg_reg(vRegF dst, iRegIorL2I src) %{
14418 match(Set dst (ConvI2F src));
14419
14420 ins_cost(INSN_COST * 5);
14421 format %{ "scvtfws $dst, $src \t// i2f" %}
14422
14423 ins_encode %{
14424 __ scvtfws(as_FloatRegister($dst$$reg), as_Register($src$$reg));
14425 %}
14426
14427 ins_pipe(fp_i2f);
14428 %}
14429
14430 instruct convL2F_reg_reg(vRegF dst, iRegL src) %{
14431 match(Set dst (ConvL2F src));
14432
14433 ins_cost(INSN_COST * 5);
14434 format %{ "scvtfs $dst, $src \t// l2f" %}
14435
14436 ins_encode %{
14437 __ scvtfs(as_FloatRegister($dst$$reg), as_Register($src$$reg));
14438 %}
14439
14440 ins_pipe(fp_l2f);
14441 %}
14442
14443 instruct convD2I_reg_reg(iRegINoSp dst, vRegD src) %{
14444 match(Set dst (ConvD2I src));
14445
14446 ins_cost(INSN_COST * 5);
14447 format %{ "fcvtzdw $dst, $src \t// d2i" %}
14448
14449 ins_encode %{
14450 __ fcvtzdw(as_Register($dst$$reg), as_FloatRegister($src$$reg));
14451 %}
14452
14453 ins_pipe(fp_d2i);
14454 %}
14455
14456 instruct convD2L_reg_reg(iRegLNoSp dst, vRegD src) %{
14457 match(Set dst (ConvD2L src));
14458
14459 ins_cost(INSN_COST * 5);
14460 format %{ "fcvtzd $dst, $src \t// d2l" %}
14461
14462 ins_encode %{
14463 __ fcvtzd(as_Register($dst$$reg), as_FloatRegister($src$$reg));
14464 %}
14465
14466 ins_pipe(fp_d2l);
14467 %}
14468
14469 instruct convI2D_reg_reg(vRegD dst, iRegIorL2I src) %{
14470 match(Set dst (ConvI2D src));
14471
14472 ins_cost(INSN_COST * 5);
14473 format %{ "scvtfwd $dst, $src \t// i2d" %}
14474
14475 ins_encode %{
14476 __ scvtfwd(as_FloatRegister($dst$$reg), as_Register($src$$reg));
14477 %}
14478
14479 ins_pipe(fp_i2d);
14480 %}
14481
14482 instruct convL2D_reg_reg(vRegD dst, iRegL src) %{
14483 match(Set dst (ConvL2D src));
14484
14485 ins_cost(INSN_COST * 5);
14486 format %{ "scvtfd $dst, $src \t// l2d" %}
14487
14488 ins_encode %{
14489 __ scvtfd(as_FloatRegister($dst$$reg), as_Register($src$$reg));
14490 %}
14491
14492 ins_pipe(fp_l2d);
14493 %}
14494
14495 instruct round_double_reg(iRegLNoSp dst, vRegD src, vRegD ftmp, rFlagsReg cr)
14496 %{
14497 match(Set dst (RoundD src));
14498 effect(TEMP_DEF dst, TEMP ftmp, KILL cr);
14499 format %{ "java_round_double $dst,$src"%}
14500 ins_encode %{
14501 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg),
14502 as_FloatRegister($ftmp$$reg));
14503 %}
14504 ins_pipe(pipe_slow);
14505 %}
14506
14507 instruct round_float_reg(iRegINoSp dst, vRegF src, vRegF ftmp, rFlagsReg cr)
14508 %{
14509 match(Set dst (RoundF src));
14510 effect(TEMP_DEF dst, TEMP ftmp, KILL cr);
14511 format %{ "java_round_float $dst,$src"%}
14512 ins_encode %{
14513 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg),
14514 as_FloatRegister($ftmp$$reg));
14515 %}
14516 ins_pipe(pipe_slow);
14517 %}
14518
14519 // stack <-> reg and reg <-> reg shuffles with no conversion
14520
14521 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
14522
14523 match(Set dst (MoveF2I src));
14524
14525 effect(DEF dst, USE src);
14526
14527 ins_cost(4 * INSN_COST);
14528
14529 format %{ "ldrw $dst, $src\t# MoveF2I_stack_reg" %}
14530
14531 ins_encode %{
14532 __ ldrw($dst$$Register, Address(sp, $src$$disp));
14533 %}
14534
14535 ins_pipe(iload_reg_reg);
14536
14537 %}
14538
14539 instruct MoveI2F_stack_reg(vRegF dst, stackSlotI src) %{
14540
14541 match(Set dst (MoveI2F src));
14542
14543 effect(DEF dst, USE src);
14544
14545 ins_cost(4 * INSN_COST);
14546
14547 format %{ "ldrs $dst, $src\t# MoveI2F_stack_reg" %}
14548
14549 ins_encode %{
14550 __ ldrs(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
14551 %}
14552
14553 ins_pipe(pipe_class_memory);
14554
14555 %}
14556
14557 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
14558
14559 match(Set dst (MoveD2L src));
14560
14561 effect(DEF dst, USE src);
14562
14563 ins_cost(4 * INSN_COST);
14564
14565 format %{ "ldr $dst, $src\t# MoveD2L_stack_reg" %}
14566
14567 ins_encode %{
14568 __ ldr($dst$$Register, Address(sp, $src$$disp));
14569 %}
14570
14571 ins_pipe(iload_reg_reg);
14572
14573 %}
14574
14575 instruct MoveL2D_stack_reg(vRegD dst, stackSlotL src) %{
14576
14577 match(Set dst (MoveL2D src));
14578
14579 effect(DEF dst, USE src);
14580
14581 ins_cost(4 * INSN_COST);
14582
14583 format %{ "ldrd $dst, $src\t# MoveL2D_stack_reg" %}
14584
14585 ins_encode %{
14586 __ ldrd(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
14587 %}
14588
14589 ins_pipe(pipe_class_memory);
14590
14591 %}
14592
14593 instruct MoveF2I_reg_stack(stackSlotI dst, vRegF src) %{
14594
14595 match(Set dst (MoveF2I src));
14596
14597 effect(DEF dst, USE src);
14598
14599 ins_cost(INSN_COST);
14600
14601 format %{ "strs $src, $dst\t# MoveF2I_reg_stack" %}
14602
14603 ins_encode %{
14604 __ strs(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
14605 %}
14606
14607 ins_pipe(pipe_class_memory);
14608
14609 %}
14610
14611 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
14612
14613 match(Set dst (MoveI2F src));
14614
14615 effect(DEF dst, USE src);
14616
14617 ins_cost(INSN_COST);
14618
14619 format %{ "strw $src, $dst\t# MoveI2F_reg_stack" %}
14620
14621 ins_encode %{
14622 __ strw($src$$Register, Address(sp, $dst$$disp));
14623 %}
14624
14625 ins_pipe(istore_reg_reg);
14626
14627 %}
14628
14629 instruct MoveD2L_reg_stack(stackSlotL dst, vRegD src) %{
14630
14631 match(Set dst (MoveD2L src));
14632
14633 effect(DEF dst, USE src);
14634
14635 ins_cost(INSN_COST);
14636
14637 format %{ "strd $dst, $src\t# MoveD2L_reg_stack" %}
14638
14639 ins_encode %{
14640 __ strd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
14641 %}
14642
14643 ins_pipe(pipe_class_memory);
14644
14645 %}
14646
14647 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
14648
14649 match(Set dst (MoveL2D src));
14650
14651 effect(DEF dst, USE src);
14652
14653 ins_cost(INSN_COST);
14654
14655 format %{ "str $src, $dst\t# MoveL2D_reg_stack" %}
14656
14657 ins_encode %{
14658 __ str($src$$Register, Address(sp, $dst$$disp));
14659 %}
14660
14661 ins_pipe(istore_reg_reg);
14662
14663 %}
14664
14665 instruct MoveF2I_reg_reg(iRegINoSp dst, vRegF src) %{
14666
14667 match(Set dst (MoveF2I src));
14668
14669 effect(DEF dst, USE src);
14670
14671 ins_cost(INSN_COST);
14672
14673 format %{ "fmovs $dst, $src\t# MoveF2I_reg_reg" %}
14674
14675 ins_encode %{
14676 __ fmovs($dst$$Register, as_FloatRegister($src$$reg));
14677 %}
14678
14679 ins_pipe(fp_f2i);
14680
14681 %}
14682
14683 instruct MoveI2F_reg_reg(vRegF dst, iRegI src) %{
14684
14685 match(Set dst (MoveI2F src));
14686
14687 effect(DEF dst, USE src);
14688
14689 ins_cost(INSN_COST);
14690
14691 format %{ "fmovs $dst, $src\t# MoveI2F_reg_reg" %}
14692
14693 ins_encode %{
14694 __ fmovs(as_FloatRegister($dst$$reg), $src$$Register);
14695 %}
14696
14697 ins_pipe(fp_i2f);
14698
14699 %}
14700
14701 instruct MoveD2L_reg_reg(iRegLNoSp dst, vRegD src) %{
14702
14703 match(Set dst (MoveD2L src));
14704
14705 effect(DEF dst, USE src);
14706
14707 ins_cost(INSN_COST);
14708
14709 format %{ "fmovd $dst, $src\t# MoveD2L_reg_reg" %}
14710
14711 ins_encode %{
14712 __ fmovd($dst$$Register, as_FloatRegister($src$$reg));
14713 %}
14714
14715 ins_pipe(fp_d2l);
14716
14717 %}
14718
14719 instruct MoveL2D_reg_reg(vRegD dst, iRegL src) %{
14720
14721 match(Set dst (MoveL2D src));
14722
14723 effect(DEF dst, USE src);
14724
14725 ins_cost(INSN_COST);
14726
14727 format %{ "fmovd $dst, $src\t# MoveL2D_reg_reg" %}
14728
14729 ins_encode %{
14730 __ fmovd(as_FloatRegister($dst$$reg), $src$$Register);
14731 %}
14732
14733 ins_pipe(fp_l2d);
14734
14735 %}
14736
14737 // ============================================================================
14738 // clearing of an array
14739
14740 instruct clearArray_reg_reg(iRegL_R11 cnt, iRegP_R10 base, Universe dummy, rFlagsReg cr)
14741 %{
14742 match(Set dummy (ClearArray cnt base));
14743 effect(USE_KILL cnt, USE_KILL base, KILL cr);
14744
14745 ins_cost(4 * INSN_COST);
14746 format %{ "ClearArray $cnt, $base" %}
14747
14748 ins_encode %{
14749 address tpc = __ zero_words($base$$Register, $cnt$$Register);
14750 if (tpc == nullptr) {
14751 ciEnv::current()->record_failure("CodeCache is full");
14752 return;
14753 }
14754 %}
14755
14756 ins_pipe(pipe_class_memory);
14757 %}
14758
14759 instruct clearArray_imm_reg(immL cnt, iRegP_R10 base, iRegL_R11 temp, Universe dummy, rFlagsReg cr)
14760 %{
14761 predicate((uint64_t)n->in(2)->get_long()
14762 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
14763 match(Set dummy (ClearArray cnt base));
14764 effect(TEMP temp, USE_KILL base, KILL cr);
14765
14766 ins_cost(4 * INSN_COST);
14767 format %{ "ClearArray $cnt, $base" %}
14768
14769 ins_encode %{
14770 address tpc = __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
14771 if (tpc == nullptr) {
14772 ciEnv::current()->record_failure("CodeCache is full");
14773 return;
14774 }
14775 %}
14776
14777 ins_pipe(pipe_class_memory);
14778 %}
14779
14780 // ============================================================================
14781 // Overflow Math Instructions
14782
14783 instruct overflowAddI_reg_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
14784 %{
14785 match(Set cr (OverflowAddI op1 op2));
14786
14787 format %{ "cmnw $op1, $op2\t# overflow check int" %}
14788 ins_cost(INSN_COST);
14789 ins_encode %{
14790 __ cmnw($op1$$Register, $op2$$Register);
14791 %}
14792
14793 ins_pipe(icmp_reg_reg);
14794 %}
14795
14796 instruct overflowAddI_reg_imm(rFlagsReg cr, iRegIorL2I op1, immIAddSub op2)
14797 %{
14798 match(Set cr (OverflowAddI op1 op2));
14799
14800 format %{ "cmnw $op1, $op2\t# overflow check int" %}
14801 ins_cost(INSN_COST);
14802 ins_encode %{
14803 __ cmnw($op1$$Register, $op2$$constant);
14804 %}
14805
14806 ins_pipe(icmp_reg_imm);
14807 %}
14808
14809 instruct overflowAddL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
14810 %{
14811 match(Set cr (OverflowAddL op1 op2));
14812
14813 format %{ "cmn $op1, $op2\t# overflow check long" %}
14814 ins_cost(INSN_COST);
14815 ins_encode %{
14816 __ cmn($op1$$Register, $op2$$Register);
14817 %}
14818
14819 ins_pipe(icmp_reg_reg);
14820 %}
14821
14822 instruct overflowAddL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
14823 %{
14824 match(Set cr (OverflowAddL op1 op2));
14825
14826 format %{ "adds zr, $op1, $op2\t# overflow check long" %}
14827 ins_cost(INSN_COST);
14828 ins_encode %{
14829 __ adds(zr, $op1$$Register, $op2$$constant);
14830 %}
14831
14832 ins_pipe(icmp_reg_imm);
14833 %}
14834
14835 instruct overflowSubI_reg_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
14836 %{
14837 match(Set cr (OverflowSubI op1 op2));
14838
14839 format %{ "cmpw $op1, $op2\t# overflow check int" %}
14840 ins_cost(INSN_COST);
14841 ins_encode %{
14842 __ cmpw($op1$$Register, $op2$$Register);
14843 %}
14844
14845 ins_pipe(icmp_reg_reg);
14846 %}
14847
14848 instruct overflowSubI_reg_imm(rFlagsReg cr, iRegIorL2I op1, immIAddSub op2)
14849 %{
14850 match(Set cr (OverflowSubI op1 op2));
14851
14852 format %{ "cmpw $op1, $op2\t# overflow check int" %}
14853 ins_cost(INSN_COST);
14854 ins_encode %{
14855 __ cmpw($op1$$Register, $op2$$constant);
14856 %}
14857
14858 ins_pipe(icmp_reg_imm);
14859 %}
14860
14861 instruct overflowSubL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
14862 %{
14863 match(Set cr (OverflowSubL op1 op2));
14864
14865 format %{ "cmp $op1, $op2\t# overflow check long" %}
14866 ins_cost(INSN_COST);
14867 ins_encode %{
14868 __ cmp($op1$$Register, $op2$$Register);
14869 %}
14870
14871 ins_pipe(icmp_reg_reg);
14872 %}
14873
14874 instruct overflowSubL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
14875 %{
14876 match(Set cr (OverflowSubL op1 op2));
14877
14878 format %{ "cmp $op1, $op2\t# overflow check long" %}
14879 ins_cost(INSN_COST);
14880 ins_encode %{
14881 __ subs(zr, $op1$$Register, $op2$$constant);
14882 %}
14883
14884 ins_pipe(icmp_reg_imm);
14885 %}
14886
14887 instruct overflowNegI_reg(rFlagsReg cr, immI0 zero, iRegIorL2I op1)
14888 %{
14889 match(Set cr (OverflowSubI zero op1));
14890
14891 format %{ "cmpw zr, $op1\t# overflow check int" %}
14892 ins_cost(INSN_COST);
14893 ins_encode %{
14894 __ cmpw(zr, $op1$$Register);
14895 %}
14896
14897 ins_pipe(icmp_reg_imm);
14898 %}
14899
14900 instruct overflowNegL_reg(rFlagsReg cr, immI0 zero, iRegL op1)
14901 %{
14902 match(Set cr (OverflowSubL zero op1));
14903
14904 format %{ "cmp zr, $op1\t# overflow check long" %}
14905 ins_cost(INSN_COST);
14906 ins_encode %{
14907 __ cmp(zr, $op1$$Register);
14908 %}
14909
14910 ins_pipe(icmp_reg_imm);
14911 %}
14912
14913 instruct overflowMulI_reg(rFlagsReg cr, iRegIorL2I op1, iRegIorL2I op2)
14914 %{
14915 match(Set cr (OverflowMulI op1 op2));
14916
14917 format %{ "smull rscratch1, $op1, $op2\t# overflow check int\n\t"
14918 "cmp rscratch1, rscratch1, sxtw\n\t"
14919 "movw rscratch1, #0x80000000\n\t"
14920 "cselw rscratch1, rscratch1, zr, NE\n\t"
14921 "cmpw rscratch1, #1" %}
14922 ins_cost(5 * INSN_COST);
14923 ins_encode %{
14924 __ smull(rscratch1, $op1$$Register, $op2$$Register);
14925 __ subs(zr, rscratch1, rscratch1, ext::sxtw); // NE => overflow
14926 __ movw(rscratch1, 0x80000000); // Develop 0 (EQ),
14927 __ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE)
14928 __ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS
14929 %}
14930
14931 ins_pipe(pipe_slow);
14932 %}
14933
14934 instruct overflowMulI_reg_branch(cmpOp cmp, iRegIorL2I op1, iRegIorL2I op2, label labl, rFlagsReg cr)
14935 %{
14936 match(If cmp (OverflowMulI op1 op2));
14937 predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow
14938 || n->in(1)->as_Bool()->_test._test == BoolTest::no_overflow);
14939 effect(USE labl, KILL cr);
14940
14941 format %{ "smull rscratch1, $op1, $op2\t# overflow check int\n\t"
14942 "cmp rscratch1, rscratch1, sxtw\n\t"
14943 "b$cmp $labl" %}
14944 ins_cost(3 * INSN_COST); // Branch is rare so treat as INSN_COST
14945 ins_encode %{
14946 Label* L = $labl$$label;
14947 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14948 __ smull(rscratch1, $op1$$Register, $op2$$Register);
14949 __ subs(zr, rscratch1, rscratch1, ext::sxtw); // NE => overflow
14950 __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L);
14951 %}
14952
14953 ins_pipe(pipe_serial);
14954 %}
14955
14956 instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2)
14957 %{
14958 match(Set cr (OverflowMulL op1 op2));
14959
14960 format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
14961 "smulh rscratch2, $op1, $op2\n\t"
14962 "cmp rscratch2, rscratch1, ASR #63\n\t"
14963 "movw rscratch1, #0x80000000\n\t"
14964 "cselw rscratch1, rscratch1, zr, NE\n\t"
14965 "cmpw rscratch1, #1" %}
14966 ins_cost(6 * INSN_COST);
14967 ins_encode %{
14968 __ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63
14969 __ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127
14970 __ cmp(rscratch2, rscratch1, Assembler::ASR, 63); // Top is pure sign ext
14971 __ movw(rscratch1, 0x80000000); // Develop 0 (EQ),
14972 __ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE)
14973 __ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS
14974 %}
14975
14976 ins_pipe(pipe_slow);
14977 %}
14978
14979 instruct overflowMulL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, rFlagsReg cr)
14980 %{
14981 match(If cmp (OverflowMulL op1 op2));
14982 predicate(n->in(1)->as_Bool()->_test._test == BoolTest::overflow
14983 || n->in(1)->as_Bool()->_test._test == BoolTest::no_overflow);
14984 effect(USE labl, KILL cr);
14985
14986 format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
14987 "smulh rscratch2, $op1, $op2\n\t"
14988 "cmp rscratch2, rscratch1, ASR #63\n\t"
14989 "b$cmp $labl" %}
14990 ins_cost(4 * INSN_COST); // Branch is rare so treat as INSN_COST
14991 ins_encode %{
14992 Label* L = $labl$$label;
14993 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
14994 __ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63
14995 __ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127
14996 __ cmp(rscratch2, rscratch1, Assembler::ASR, 63); // Top is pure sign ext
14997 __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L);
14998 %}
14999
15000 ins_pipe(pipe_serial);
15001 %}
15002
15003 // ============================================================================
15004 // Compare Instructions
15005
15006 instruct compI_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
15007 %{
15008 match(Set cr (CmpI op1 op2));
15009
15010 effect(DEF cr, USE op1, USE op2);
15011
15012 ins_cost(INSN_COST);
15013 format %{ "cmpw $op1, $op2" %}
15014
15015 ins_encode(aarch64_enc_cmpw(op1, op2));
15016
15017 ins_pipe(icmp_reg_reg);
15018 %}
15019
15020 instruct compI_reg_immI0(rFlagsReg cr, iRegI op1, immI0 zero)
15021 %{
15022 match(Set cr (CmpI op1 zero));
15023
15024 effect(DEF cr, USE op1);
15025
15026 ins_cost(INSN_COST);
15027 format %{ "cmpw $op1, 0" %}
15028
15029 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, zero));
15030
15031 ins_pipe(icmp_reg_imm);
15032 %}
15033
15034 instruct compI_reg_immIAddSub(rFlagsReg cr, iRegI op1, immIAddSub op2)
15035 %{
15036 match(Set cr (CmpI op1 op2));
15037
15038 effect(DEF cr, USE op1);
15039
15040 ins_cost(INSN_COST);
15041 format %{ "cmpw $op1, $op2" %}
15042
15043 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, op2));
15044
15045 ins_pipe(icmp_reg_imm);
15046 %}
15047
15048 instruct compI_reg_immI(rFlagsReg cr, iRegI op1, immI op2)
15049 %{
15050 match(Set cr (CmpI op1 op2));
15051
15052 effect(DEF cr, USE op1);
15053
15054 ins_cost(INSN_COST * 2);
15055 format %{ "cmpw $op1, $op2" %}
15056
15057 ins_encode(aarch64_enc_cmpw_imm(op1, op2));
15058
15059 ins_pipe(icmp_reg_imm);
15060 %}
15061
15062 // Unsigned compare Instructions; really, same as signed compare
15063 // except it should only be used to feed an If or a CMovI which takes a
15064 // cmpOpU.
15065
15066 instruct compU_reg_reg(rFlagsRegU cr, iRegI op1, iRegI op2)
15067 %{
15068 match(Set cr (CmpU op1 op2));
15069
15070 effect(DEF cr, USE op1, USE op2);
15071
15072 ins_cost(INSN_COST);
15073 format %{ "cmpw $op1, $op2\t# unsigned" %}
15074
15075 ins_encode(aarch64_enc_cmpw(op1, op2));
15076
15077 ins_pipe(icmp_reg_reg);
15078 %}
15079
15080 instruct compU_reg_immI0(rFlagsRegU cr, iRegI op1, immI0 zero)
15081 %{
15082 match(Set cr (CmpU op1 zero));
15083
15084 effect(DEF cr, USE op1);
15085
15086 ins_cost(INSN_COST);
15087 format %{ "cmpw $op1, #0\t# unsigned" %}
15088
15089 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, zero));
15090
15091 ins_pipe(icmp_reg_imm);
15092 %}
15093
15094 instruct compU_reg_immIAddSub(rFlagsRegU cr, iRegI op1, immIAddSub op2)
15095 %{
15096 match(Set cr (CmpU op1 op2));
15097
15098 effect(DEF cr, USE op1);
15099
15100 ins_cost(INSN_COST);
15101 format %{ "cmpw $op1, $op2\t# unsigned" %}
15102
15103 ins_encode(aarch64_enc_cmpw_imm_addsub(op1, op2));
15104
15105 ins_pipe(icmp_reg_imm);
15106 %}
15107
15108 instruct compU_reg_immI(rFlagsRegU cr, iRegI op1, immI op2)
15109 %{
15110 match(Set cr (CmpU op1 op2));
15111
15112 effect(DEF cr, USE op1);
15113
15114 ins_cost(INSN_COST * 2);
15115 format %{ "cmpw $op1, $op2\t# unsigned" %}
15116
15117 ins_encode(aarch64_enc_cmpw_imm(op1, op2));
15118
15119 ins_pipe(icmp_reg_imm);
15120 %}
15121
15122 instruct compL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
15123 %{
15124 match(Set cr (CmpL op1 op2));
15125
15126 effect(DEF cr, USE op1, USE op2);
15127
15128 ins_cost(INSN_COST);
15129 format %{ "cmp $op1, $op2" %}
15130
15131 ins_encode(aarch64_enc_cmp(op1, op2));
15132
15133 ins_pipe(icmp_reg_reg);
15134 %}
15135
15136 instruct compL_reg_immL0(rFlagsReg cr, iRegL op1, immL0 zero)
15137 %{
15138 match(Set cr (CmpL op1 zero));
15139
15140 effect(DEF cr, USE op1);
15141
15142 ins_cost(INSN_COST);
15143 format %{ "tst $op1" %}
15144
15145 ins_encode(aarch64_enc_cmp_imm_addsub(op1, zero));
15146
15147 ins_pipe(icmp_reg_imm);
15148 %}
15149
15150 instruct compL_reg_immLAddSub(rFlagsReg cr, iRegL op1, immLAddSub op2)
15151 %{
15152 match(Set cr (CmpL op1 op2));
15153
15154 effect(DEF cr, USE op1);
15155
15156 ins_cost(INSN_COST);
15157 format %{ "cmp $op1, $op2" %}
15158
15159 ins_encode(aarch64_enc_cmp_imm_addsub(op1, op2));
15160
15161 ins_pipe(icmp_reg_imm);
15162 %}
15163
15164 instruct compL_reg_immL(rFlagsReg cr, iRegL op1, immL op2)
15165 %{
15166 match(Set cr (CmpL op1 op2));
15167
15168 effect(DEF cr, USE op1);
15169
15170 ins_cost(INSN_COST * 2);
15171 format %{ "cmp $op1, $op2" %}
15172
15173 ins_encode(aarch64_enc_cmp_imm(op1, op2));
15174
15175 ins_pipe(icmp_reg_imm);
15176 %}
15177
15178 instruct compUL_reg_reg(rFlagsRegU cr, iRegL op1, iRegL op2)
15179 %{
15180 match(Set cr (CmpUL op1 op2));
15181
15182 effect(DEF cr, USE op1, USE op2);
15183
15184 ins_cost(INSN_COST);
15185 format %{ "cmp $op1, $op2" %}
15186
15187 ins_encode(aarch64_enc_cmp(op1, op2));
15188
15189 ins_pipe(icmp_reg_reg);
15190 %}
15191
15192 instruct compUL_reg_immL0(rFlagsRegU cr, iRegL op1, immL0 zero)
15193 %{
15194 match(Set cr (CmpUL op1 zero));
15195
15196 effect(DEF cr, USE op1);
15197
15198 ins_cost(INSN_COST);
15199 format %{ "tst $op1" %}
15200
15201 ins_encode(aarch64_enc_cmp_imm_addsub(op1, zero));
15202
15203 ins_pipe(icmp_reg_imm);
15204 %}
15205
15206 instruct compUL_reg_immLAddSub(rFlagsRegU cr, iRegL op1, immLAddSub op2)
15207 %{
15208 match(Set cr (CmpUL op1 op2));
15209
15210 effect(DEF cr, USE op1);
15211
15212 ins_cost(INSN_COST);
15213 format %{ "cmp $op1, $op2" %}
15214
15215 ins_encode(aarch64_enc_cmp_imm_addsub(op1, op2));
15216
15217 ins_pipe(icmp_reg_imm);
15218 %}
15219
15220 instruct compUL_reg_immL(rFlagsRegU cr, iRegL op1, immL op2)
15221 %{
15222 match(Set cr (CmpUL op1 op2));
15223
15224 effect(DEF cr, USE op1);
15225
15226 ins_cost(INSN_COST * 2);
15227 format %{ "cmp $op1, $op2" %}
15228
15229 ins_encode(aarch64_enc_cmp_imm(op1, op2));
15230
15231 ins_pipe(icmp_reg_imm);
15232 %}
15233
15234 instruct compP_reg_reg(rFlagsRegU cr, iRegP op1, iRegP op2)
15235 %{
15236 match(Set cr (CmpP op1 op2));
15237
15238 effect(DEF cr, USE op1, USE op2);
15239
15240 ins_cost(INSN_COST);
15241 format %{ "cmp $op1, $op2\t // ptr" %}
15242
15243 ins_encode(aarch64_enc_cmpp(op1, op2));
15244
15245 ins_pipe(icmp_reg_reg);
15246 %}
15247
15248 instruct compN_reg_reg(rFlagsRegU cr, iRegN op1, iRegN op2)
15249 %{
15250 match(Set cr (CmpN op1 op2));
15251
15252 effect(DEF cr, USE op1, USE op2);
15253
15254 ins_cost(INSN_COST);
15255 format %{ "cmp $op1, $op2\t // compressed ptr" %}
15256
15257 ins_encode(aarch64_enc_cmpn(op1, op2));
15258
15259 ins_pipe(icmp_reg_reg);
15260 %}
15261
15262 instruct testP_reg(rFlagsRegU cr, iRegP op1, immP0 zero)
15263 %{
15264 match(Set cr (CmpP op1 zero));
15265
15266 effect(DEF cr, USE op1, USE zero);
15267
15268 ins_cost(INSN_COST);
15269 format %{ "cmp $op1, 0\t // ptr" %}
15270
15271 ins_encode(aarch64_enc_testp(op1));
15272
15273 ins_pipe(icmp_reg_imm);
15274 %}
15275
15276 instruct testN_reg(rFlagsRegU cr, iRegN op1, immN0 zero)
15277 %{
15278 match(Set cr (CmpN op1 zero));
15279
15280 effect(DEF cr, USE op1, USE zero);
15281
15282 ins_cost(INSN_COST);
15283 format %{ "cmp $op1, 0\t // compressed ptr" %}
15284
15285 ins_encode(aarch64_enc_testn(op1));
15286
15287 ins_pipe(icmp_reg_imm);
15288 %}
15289
15290 // FP comparisons
15291 //
15292 // n.b. CmpF/CmpD set a normal flags reg which then gets compared
15293 // using normal cmpOp. See declaration of rFlagsReg for details.
15294
15295 instruct compF_reg_reg(rFlagsReg cr, vRegF src1, vRegF src2)
15296 %{
15297 match(Set cr (CmpF src1 src2));
15298
15299 ins_cost(3 * INSN_COST);
15300 format %{ "fcmps $src1, $src2" %}
15301
15302 ins_encode %{
15303 __ fcmps(as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15304 %}
15305
15306 ins_pipe(pipe_class_compare);
15307 %}
15308
15309 instruct compF_reg_zero(rFlagsReg cr, vRegF src1, immF0 src2)
15310 %{
15311 match(Set cr (CmpF src1 src2));
15312
15313 ins_cost(3 * INSN_COST);
15314 format %{ "fcmps $src1, 0.0" %}
15315
15316 ins_encode %{
15317 __ fcmps(as_FloatRegister($src1$$reg), 0.0);
15318 %}
15319
15320 ins_pipe(pipe_class_compare);
15321 %}
15322 // FROM HERE
15323
15324 instruct compD_reg_reg(rFlagsReg cr, vRegD src1, vRegD src2)
15325 %{
15326 match(Set cr (CmpD src1 src2));
15327
15328 ins_cost(3 * INSN_COST);
15329 format %{ "fcmpd $src1, $src2" %}
15330
15331 ins_encode %{
15332 __ fcmpd(as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
15333 %}
15334
15335 ins_pipe(pipe_class_compare);
15336 %}
15337
15338 instruct compD_reg_zero(rFlagsReg cr, vRegD src1, immD0 src2)
15339 %{
15340 match(Set cr (CmpD src1 src2));
15341
15342 ins_cost(3 * INSN_COST);
15343 format %{ "fcmpd $src1, 0.0" %}
15344
15345 ins_encode %{
15346 __ fcmpd(as_FloatRegister($src1$$reg), 0.0);
15347 %}
15348
15349 ins_pipe(pipe_class_compare);
15350 %}
15351
15352 instruct compF3_reg_reg(iRegINoSp dst, vRegF src1, vRegF src2, rFlagsReg cr)
15353 %{
15354 match(Set dst (CmpF3 src1 src2));
15355 effect(KILL cr);
15356
15357 ins_cost(5 * INSN_COST);
15358 format %{ "fcmps $src1, $src2\n\t"
15359 "csinvw($dst, zr, zr, eq\n\t"
15360 "csnegw($dst, $dst, $dst, lt)"
15361 %}
15362
15363 ins_encode %{
15364 Label done;
15365 FloatRegister s1 = as_FloatRegister($src1$$reg);
15366 FloatRegister s2 = as_FloatRegister($src2$$reg);
15367 Register d = as_Register($dst$$reg);
15368 __ fcmps(s1, s2);
15369 // installs 0 if EQ else -1
15370 __ csinvw(d, zr, zr, Assembler::EQ);
15371 // keeps -1 if less or unordered else installs 1
15372 __ csnegw(d, d, d, Assembler::LT);
15373 __ bind(done);
15374 %}
15375
15376 ins_pipe(pipe_class_default);
15377
15378 %}
15379
15380 instruct compD3_reg_reg(iRegINoSp dst, vRegD src1, vRegD src2, rFlagsReg cr)
15381 %{
15382 match(Set dst (CmpD3 src1 src2));
15383 effect(KILL cr);
15384
15385 ins_cost(5 * INSN_COST);
15386 format %{ "fcmpd $src1, $src2\n\t"
15387 "csinvw($dst, zr, zr, eq\n\t"
15388 "csnegw($dst, $dst, $dst, lt)"
15389 %}
15390
15391 ins_encode %{
15392 Label done;
15393 FloatRegister s1 = as_FloatRegister($src1$$reg);
15394 FloatRegister s2 = as_FloatRegister($src2$$reg);
15395 Register d = as_Register($dst$$reg);
15396 __ fcmpd(s1, s2);
15397 // installs 0 if EQ else -1
15398 __ csinvw(d, zr, zr, Assembler::EQ);
15399 // keeps -1 if less or unordered else installs 1
15400 __ csnegw(d, d, d, Assembler::LT);
15401 __ bind(done);
15402 %}
15403 ins_pipe(pipe_class_default);
15404
15405 %}
15406
15407 instruct compF3_reg_immF0(iRegINoSp dst, vRegF src1, immF0 zero, rFlagsReg cr)
15408 %{
15409 match(Set dst (CmpF3 src1 zero));
15410 effect(KILL cr);
15411
15412 ins_cost(5 * INSN_COST);
15413 format %{ "fcmps $src1, 0.0\n\t"
15414 "csinvw($dst, zr, zr, eq\n\t"
15415 "csnegw($dst, $dst, $dst, lt)"
15416 %}
15417
15418 ins_encode %{
15419 Label done;
15420 FloatRegister s1 = as_FloatRegister($src1$$reg);
15421 Register d = as_Register($dst$$reg);
15422 __ fcmps(s1, 0.0);
15423 // installs 0 if EQ else -1
15424 __ csinvw(d, zr, zr, Assembler::EQ);
15425 // keeps -1 if less or unordered else installs 1
15426 __ csnegw(d, d, d, Assembler::LT);
15427 __ bind(done);
15428 %}
15429
15430 ins_pipe(pipe_class_default);
15431
15432 %}
15433
15434 instruct compD3_reg_immD0(iRegINoSp dst, vRegD src1, immD0 zero, rFlagsReg cr)
15435 %{
15436 match(Set dst (CmpD3 src1 zero));
15437 effect(KILL cr);
15438
15439 ins_cost(5 * INSN_COST);
15440 format %{ "fcmpd $src1, 0.0\n\t"
15441 "csinvw($dst, zr, zr, eq\n\t"
15442 "csnegw($dst, $dst, $dst, lt)"
15443 %}
15444
15445 ins_encode %{
15446 Label done;
15447 FloatRegister s1 = as_FloatRegister($src1$$reg);
15448 Register d = as_Register($dst$$reg);
15449 __ fcmpd(s1, 0.0);
15450 // installs 0 if EQ else -1
15451 __ csinvw(d, zr, zr, Assembler::EQ);
15452 // keeps -1 if less or unordered else installs 1
15453 __ csnegw(d, d, d, Assembler::LT);
15454 __ bind(done);
15455 %}
15456 ins_pipe(pipe_class_default);
15457
15458 %}
15459
15460 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegIorL2I p, iRegIorL2I q, rFlagsReg cr)
15461 %{
15462 match(Set dst (CmpLTMask p q));
15463 effect(KILL cr);
15464
15465 ins_cost(3 * INSN_COST);
15466
15467 format %{ "cmpw $p, $q\t# cmpLTMask\n\t"
15468 "csetw $dst, lt\n\t"
15469 "subw $dst, zr, $dst"
15470 %}
15471
15472 ins_encode %{
15473 __ cmpw(as_Register($p$$reg), as_Register($q$$reg));
15474 __ csetw(as_Register($dst$$reg), Assembler::LT);
15475 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
15476 %}
15477
15478 ins_pipe(ialu_reg_reg);
15479 %}
15480
15481 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr)
15482 %{
15483 match(Set dst (CmpLTMask src zero));
15484 effect(KILL cr);
15485
15486 ins_cost(INSN_COST);
15487
15488 format %{ "asrw $dst, $src, #31\t# cmpLTMask0" %}
15489
15490 ins_encode %{
15491 __ asrw(as_Register($dst$$reg), as_Register($src$$reg), 31);
15492 %}
15493
15494 ins_pipe(ialu_reg_shift);
15495 %}
15496
15497 // ============================================================================
15498 // Max and Min
15499
15500 // Like compI_reg_reg or compI_reg_immI0 but without match rule and second zero parameter.
15501
15502 instruct compI_reg_imm0(rFlagsReg cr, iRegI src)
15503 %{
15504 effect(DEF cr, USE src);
15505 ins_cost(INSN_COST);
15506 format %{ "cmpw $src, 0" %}
15507
15508 ins_encode %{
15509 __ cmpw($src$$Register, 0);
15510 %}
15511 ins_pipe(icmp_reg_imm);
15512 %}
15513
15514 instruct minI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2)
15515 %{
15516 match(Set dst (MinI src1 src2));
15517 ins_cost(INSN_COST * 3);
15518
15519 expand %{
15520 rFlagsReg cr;
15521 compI_reg_reg(cr, src1, src2);
15522 cmovI_reg_reg_lt(dst, src1, src2, cr);
15523 %}
15524 %}
15525
15526 instruct maxI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2)
15527 %{
15528 match(Set dst (MaxI src1 src2));
15529 ins_cost(INSN_COST * 3);
15530
15531 expand %{
15532 rFlagsReg cr;
15533 compI_reg_reg(cr, src1, src2);
15534 cmovI_reg_reg_gt(dst, src1, src2, cr);
15535 %}
15536 %}
15537
15538
15539 // ============================================================================
15540 // Branch Instructions
15541
15542 // Direct Branch.
15543 instruct branch(label lbl)
15544 %{
15545 match(Goto);
15546
15547 effect(USE lbl);
15548
15549 ins_cost(BRANCH_COST);
15550 format %{ "b $lbl" %}
15551
15552 ins_encode(aarch64_enc_b(lbl));
15553
15554 ins_pipe(pipe_branch);
15555 %}
15556
15557 // Conditional Near Branch
15558 instruct branchCon(cmpOp cmp, rFlagsReg cr, label lbl)
15559 %{
15560 // Same match rule as `branchConFar'.
15561 match(If cmp cr);
15562
15563 effect(USE lbl);
15564
15565 ins_cost(BRANCH_COST);
15566 // If set to 1 this indicates that the current instruction is a
15567 // short variant of a long branch. This avoids using this
15568 // instruction in first-pass matching. It will then only be used in
15569 // the `Shorten_branches' pass.
15570 // ins_short_branch(1);
15571 format %{ "b$cmp $lbl" %}
15572
15573 ins_encode(aarch64_enc_br_con(cmp, lbl));
15574
15575 ins_pipe(pipe_branch_cond);
15576 %}
15577
15578 // Conditional Near Branch Unsigned
15579 instruct branchConU(cmpOpU cmp, rFlagsRegU cr, label lbl)
15580 %{
15581 // Same match rule as `branchConFar'.
15582 match(If cmp cr);
15583
15584 effect(USE lbl);
15585
15586 ins_cost(BRANCH_COST);
15587 // If set to 1 this indicates that the current instruction is a
15588 // short variant of a long branch. This avoids using this
15589 // instruction in first-pass matching. It will then only be used in
15590 // the `Shorten_branches' pass.
15591 // ins_short_branch(1);
15592 format %{ "b$cmp $lbl\t# unsigned" %}
15593
15594 ins_encode(aarch64_enc_br_conU(cmp, lbl));
15595
15596 ins_pipe(pipe_branch_cond);
15597 %}
15598
15599 // Make use of CBZ and CBNZ. These instructions, as well as being
15600 // shorter than (cmp; branch), have the additional benefit of not
15601 // killing the flags.
15602
15603 instruct cmpI_imm0_branch(cmpOpEqNe cmp, iRegIorL2I op1, immI0 op2, label labl, rFlagsReg cr) %{
15604 match(If cmp (CmpI op1 op2));
15605 effect(USE labl);
15606
15607 ins_cost(BRANCH_COST);
15608 format %{ "cbw$cmp $op1, $labl" %}
15609 ins_encode %{
15610 Label* L = $labl$$label;
15611 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15612 if (cond == Assembler::EQ)
15613 __ cbzw($op1$$Register, *L);
15614 else
15615 __ cbnzw($op1$$Register, *L);
15616 %}
15617 ins_pipe(pipe_cmp_branch);
15618 %}
15619
15620 instruct cmpL_imm0_branch(cmpOpEqNe cmp, iRegL op1, immL0 op2, label labl, rFlagsReg cr) %{
15621 match(If cmp (CmpL op1 op2));
15622 effect(USE labl);
15623
15624 ins_cost(BRANCH_COST);
15625 format %{ "cb$cmp $op1, $labl" %}
15626 ins_encode %{
15627 Label* L = $labl$$label;
15628 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15629 if (cond == Assembler::EQ)
15630 __ cbz($op1$$Register, *L);
15631 else
15632 __ cbnz($op1$$Register, *L);
15633 %}
15634 ins_pipe(pipe_cmp_branch);
15635 %}
15636
15637 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 op2, label labl, rFlagsReg cr) %{
15638 match(If cmp (CmpP op1 op2));
15639 effect(USE labl);
15640
15641 ins_cost(BRANCH_COST);
15642 format %{ "cb$cmp $op1, $labl" %}
15643 ins_encode %{
15644 Label* L = $labl$$label;
15645 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15646 if (cond == Assembler::EQ)
15647 __ cbz($op1$$Register, *L);
15648 else
15649 __ cbnz($op1$$Register, *L);
15650 %}
15651 ins_pipe(pipe_cmp_branch);
15652 %}
15653
15654 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 op2, label labl, rFlagsReg cr) %{
15655 match(If cmp (CmpN op1 op2));
15656 effect(USE labl);
15657
15658 ins_cost(BRANCH_COST);
15659 format %{ "cbw$cmp $op1, $labl" %}
15660 ins_encode %{
15661 Label* L = $labl$$label;
15662 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15663 if (cond == Assembler::EQ)
15664 __ cbzw($op1$$Register, *L);
15665 else
15666 __ cbnzw($op1$$Register, *L);
15667 %}
15668 ins_pipe(pipe_cmp_branch);
15669 %}
15670
15671 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN oop, immP0 zero, label labl, rFlagsReg cr) %{
15672 match(If cmp (CmpP (DecodeN oop) zero));
15673 effect(USE labl);
15674
15675 ins_cost(BRANCH_COST);
15676 format %{ "cb$cmp $oop, $labl" %}
15677 ins_encode %{
15678 Label* L = $labl$$label;
15679 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15680 if (cond == Assembler::EQ)
15681 __ cbzw($oop$$Register, *L);
15682 else
15683 __ cbnzw($oop$$Register, *L);
15684 %}
15685 ins_pipe(pipe_cmp_branch);
15686 %}
15687
15688 instruct cmpUI_imm0_branch(cmpOpUEqNeLtGe cmp, iRegIorL2I op1, immI0 op2, label labl, rFlagsRegU cr) %{
15689 match(If cmp (CmpU op1 op2));
15690 effect(USE labl);
15691
15692 ins_cost(BRANCH_COST);
15693 format %{ "cbw$cmp $op1, $labl" %}
15694 ins_encode %{
15695 Label* L = $labl$$label;
15696 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15697 if (cond == Assembler::EQ || cond == Assembler::LS)
15698 __ cbzw($op1$$Register, *L);
15699 else
15700 __ cbnzw($op1$$Register, *L);
15701 %}
15702 ins_pipe(pipe_cmp_branch);
15703 %}
15704
15705 instruct cmpUL_imm0_branch(cmpOpUEqNeLtGe cmp, iRegL op1, immL0 op2, label labl, rFlagsRegU cr) %{
15706 match(If cmp (CmpUL op1 op2));
15707 effect(USE labl);
15708
15709 ins_cost(BRANCH_COST);
15710 format %{ "cb$cmp $op1, $labl" %}
15711 ins_encode %{
15712 Label* L = $labl$$label;
15713 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15714 if (cond == Assembler::EQ || cond == Assembler::LS)
15715 __ cbz($op1$$Register, *L);
15716 else
15717 __ cbnz($op1$$Register, *L);
15718 %}
15719 ins_pipe(pipe_cmp_branch);
15720 %}
15721
15722 // Test bit and Branch
15723
15724 // Patterns for short (< 32KiB) variants
15725 instruct cmpL_branch_sign(cmpOpLtGe cmp, iRegL op1, immL0 op2, label labl) %{
15726 match(If cmp (CmpL op1 op2));
15727 effect(USE labl);
15728
15729 ins_cost(BRANCH_COST);
15730 format %{ "cb$cmp $op1, $labl # long" %}
15731 ins_encode %{
15732 Label* L = $labl$$label;
15733 Assembler::Condition cond =
15734 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
15735 __ tbr(cond, $op1$$Register, 63, *L);
15736 %}
15737 ins_pipe(pipe_cmp_branch);
15738 ins_short_branch(1);
15739 %}
15740
15741 instruct cmpI_branch_sign(cmpOpLtGe cmp, iRegIorL2I op1, immI0 op2, label labl) %{
15742 match(If cmp (CmpI op1 op2));
15743 effect(USE labl);
15744
15745 ins_cost(BRANCH_COST);
15746 format %{ "cb$cmp $op1, $labl # int" %}
15747 ins_encode %{
15748 Label* L = $labl$$label;
15749 Assembler::Condition cond =
15750 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
15751 __ tbr(cond, $op1$$Register, 31, *L);
15752 %}
15753 ins_pipe(pipe_cmp_branch);
15754 ins_short_branch(1);
15755 %}
15756
15757 instruct cmpL_branch_bit(cmpOpEqNe cmp, iRegL op1, immL op2, immL0 op3, label labl) %{
15758 match(If cmp (CmpL (AndL op1 op2) op3));
15759 predicate(is_power_of_2((julong)n->in(2)->in(1)->in(2)->get_long()));
15760 effect(USE labl);
15761
15762 ins_cost(BRANCH_COST);
15763 format %{ "tb$cmp $op1, $op2, $labl" %}
15764 ins_encode %{
15765 Label* L = $labl$$label;
15766 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15767 int bit = exact_log2_long($op2$$constant);
15768 __ tbr(cond, $op1$$Register, bit, *L);
15769 %}
15770 ins_pipe(pipe_cmp_branch);
15771 ins_short_branch(1);
15772 %}
15773
15774 instruct cmpI_branch_bit(cmpOpEqNe cmp, iRegIorL2I op1, immI op2, immI0 op3, label labl) %{
15775 match(If cmp (CmpI (AndI op1 op2) op3));
15776 predicate(is_power_of_2((juint)n->in(2)->in(1)->in(2)->get_int()));
15777 effect(USE labl);
15778
15779 ins_cost(BRANCH_COST);
15780 format %{ "tb$cmp $op1, $op2, $labl" %}
15781 ins_encode %{
15782 Label* L = $labl$$label;
15783 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15784 int bit = exact_log2((juint)$op2$$constant);
15785 __ tbr(cond, $op1$$Register, bit, *L);
15786 %}
15787 ins_pipe(pipe_cmp_branch);
15788 ins_short_branch(1);
15789 %}
15790
15791 // And far variants
15792 instruct far_cmpL_branch_sign(cmpOpLtGe cmp, iRegL op1, immL0 op2, label labl) %{
15793 match(If cmp (CmpL op1 op2));
15794 effect(USE labl);
15795
15796 ins_cost(BRANCH_COST);
15797 format %{ "cb$cmp $op1, $labl # long" %}
15798 ins_encode %{
15799 Label* L = $labl$$label;
15800 Assembler::Condition cond =
15801 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
15802 __ tbr(cond, $op1$$Register, 63, *L, /*far*/true);
15803 %}
15804 ins_pipe(pipe_cmp_branch);
15805 %}
15806
15807 instruct far_cmpI_branch_sign(cmpOpLtGe cmp, iRegIorL2I op1, immI0 op2, label labl) %{
15808 match(If cmp (CmpI op1 op2));
15809 effect(USE labl);
15810
15811 ins_cost(BRANCH_COST);
15812 format %{ "cb$cmp $op1, $labl # int" %}
15813 ins_encode %{
15814 Label* L = $labl$$label;
15815 Assembler::Condition cond =
15816 ((Assembler::Condition)$cmp$$cmpcode == Assembler::LT) ? Assembler::NE : Assembler::EQ;
15817 __ tbr(cond, $op1$$Register, 31, *L, /*far*/true);
15818 %}
15819 ins_pipe(pipe_cmp_branch);
15820 %}
15821
15822 instruct far_cmpL_branch_bit(cmpOpEqNe cmp, iRegL op1, immL op2, immL0 op3, label labl) %{
15823 match(If cmp (CmpL (AndL op1 op2) op3));
15824 predicate(is_power_of_2((julong)n->in(2)->in(1)->in(2)->get_long()));
15825 effect(USE labl);
15826
15827 ins_cost(BRANCH_COST);
15828 format %{ "tb$cmp $op1, $op2, $labl" %}
15829 ins_encode %{
15830 Label* L = $labl$$label;
15831 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15832 int bit = exact_log2_long($op2$$constant);
15833 __ tbr(cond, $op1$$Register, bit, *L, /*far*/true);
15834 %}
15835 ins_pipe(pipe_cmp_branch);
15836 %}
15837
15838 instruct far_cmpI_branch_bit(cmpOpEqNe cmp, iRegIorL2I op1, immI op2, immI0 op3, label labl) %{
15839 match(If cmp (CmpI (AndI op1 op2) op3));
15840 predicate(is_power_of_2((juint)n->in(2)->in(1)->in(2)->get_int()));
15841 effect(USE labl);
15842
15843 ins_cost(BRANCH_COST);
15844 format %{ "tb$cmp $op1, $op2, $labl" %}
15845 ins_encode %{
15846 Label* L = $labl$$label;
15847 Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
15848 int bit = exact_log2((juint)$op2$$constant);
15849 __ tbr(cond, $op1$$Register, bit, *L, /*far*/true);
15850 %}
15851 ins_pipe(pipe_cmp_branch);
15852 %}
15853
15854 // Test bits
15855
15856 instruct cmpL_and(cmpOp cmp, iRegL op1, immL op2, immL0 op3, rFlagsReg cr) %{
15857 match(Set cr (CmpL (AndL op1 op2) op3));
15858 predicate(Assembler::operand_valid_for_logical_immediate
15859 (/*is_32*/false, n->in(1)->in(2)->get_long()));
15860
15861 ins_cost(INSN_COST);
15862 format %{ "tst $op1, $op2 # long" %}
15863 ins_encode %{
15864 __ tst($op1$$Register, $op2$$constant);
15865 %}
15866 ins_pipe(ialu_reg_reg);
15867 %}
15868
15869 instruct cmpI_and(cmpOp cmp, iRegIorL2I op1, immI op2, immI0 op3, rFlagsReg cr) %{
15870 match(Set cr (CmpI (AndI op1 op2) op3));
15871 predicate(Assembler::operand_valid_for_logical_immediate
15872 (/*is_32*/true, n->in(1)->in(2)->get_int()));
15873
15874 ins_cost(INSN_COST);
15875 format %{ "tst $op1, $op2 # int" %}
15876 ins_encode %{
15877 __ tstw($op1$$Register, $op2$$constant);
15878 %}
15879 ins_pipe(ialu_reg_reg);
15880 %}
15881
15882 instruct cmpL_and_reg(cmpOp cmp, iRegL op1, iRegL op2, immL0 op3, rFlagsReg cr) %{
15883 match(Set cr (CmpL (AndL op1 op2) op3));
15884
15885 ins_cost(INSN_COST);
15886 format %{ "tst $op1, $op2 # long" %}
15887 ins_encode %{
15888 __ tst($op1$$Register, $op2$$Register);
15889 %}
15890 ins_pipe(ialu_reg_reg);
15891 %}
15892
15893 instruct cmpI_and_reg(cmpOp cmp, iRegIorL2I op1, iRegIorL2I op2, immI0 op3, rFlagsReg cr) %{
15894 match(Set cr (CmpI (AndI op1 op2) op3));
15895
15896 ins_cost(INSN_COST);
15897 format %{ "tstw $op1, $op2 # int" %}
15898 ins_encode %{
15899 __ tstw($op1$$Register, $op2$$Register);
15900 %}
15901 ins_pipe(ialu_reg_reg);
15902 %}
15903
15904
15905 // Conditional Far Branch
15906 // Conditional Far Branch Unsigned
15907 // TODO: fixme
15908
15909 // counted loop end branch near
15910 instruct branchLoopEnd(cmpOp cmp, rFlagsReg cr, label lbl)
15911 %{
15912 match(CountedLoopEnd cmp cr);
15913
15914 effect(USE lbl);
15915
15916 ins_cost(BRANCH_COST);
15917 // short variant.
15918 // ins_short_branch(1);
15919 format %{ "b$cmp $lbl \t// counted loop end" %}
15920
15921 ins_encode(aarch64_enc_br_con(cmp, lbl));
15922
15923 ins_pipe(pipe_branch);
15924 %}
15925
15926 // counted loop end branch far
15927 // TODO: fixme
15928
15929 // ============================================================================
15930 // inlined locking and unlocking
15931
15932 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2, iRegPNoSp tmp3)
15933 %{
15934 predicate(LockingMode != LM_LIGHTWEIGHT);
15935 match(Set cr (FastLock object box));
15936 effect(TEMP tmp, TEMP tmp2, TEMP tmp3);
15937
15938 ins_cost(5 * INSN_COST);
15939 format %{ "fastlock $object,$box\t! kills $tmp,$tmp2,$tmp3" %}
15940
15941 ins_encode %{
15942 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $tmp2$$Register, $tmp3$$Register);
15943 %}
15944
15945 ins_pipe(pipe_serial);
15946 %}
15947
15948 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2)
15949 %{
15950 predicate(LockingMode != LM_LIGHTWEIGHT);
15951 match(Set cr (FastUnlock object box));
15952 effect(TEMP tmp, TEMP tmp2);
15953
15954 ins_cost(5 * INSN_COST);
15955 format %{ "fastunlock $object,$box\t! kills $tmp, $tmp2" %}
15956
15957 ins_encode %{
15958 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, $tmp2$$Register);
15959 %}
15960
15961 ins_pipe(pipe_serial);
15962 %}
15963
15964 instruct cmpFastLockLightweight(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2, iRegPNoSp tmp3)
15965 %{
15966 predicate(LockingMode == LM_LIGHTWEIGHT);
15967 match(Set cr (FastLock object box));
15968 effect(TEMP tmp, TEMP tmp2, TEMP tmp3);
15969
15970 ins_cost(5 * INSN_COST);
15971 format %{ "fastlock $object,$box\t! kills $tmp,$tmp2,$tmp3" %}
15972
15973 ins_encode %{
15974 __ fast_lock_lightweight($object$$Register, $tmp$$Register, $tmp2$$Register, $tmp3$$Register);
15975 %}
15976
15977 ins_pipe(pipe_serial);
15978 %}
15979
15980 instruct cmpFastUnlockLightweight(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2, iRegPNoSp tmp3)
15981 %{
15982 predicate(LockingMode == LM_LIGHTWEIGHT);
15983 match(Set cr (FastUnlock object box));
15984 effect(TEMP tmp, TEMP tmp2, TEMP tmp3);
15985
15986 ins_cost(5 * INSN_COST);
15987 format %{ "fastunlock $object,$box\t! kills $tmp, $tmp2, $tmp3" %}
15988
15989 ins_encode %{
15990 __ fast_unlock_lightweight($object$$Register, $tmp$$Register, $tmp2$$Register, $tmp3$$Register);
15991 %}
15992
15993 ins_pipe(pipe_serial);
15994 %}
15995
15996 // ============================================================================
15997 // Safepoint Instructions
15998
15999 // TODO
16000 // provide a near and far version of this code
16001
16002 instruct safePoint(rFlagsReg cr, iRegP poll)
16003 %{
16004 match(SafePoint poll);
16005 effect(KILL cr);
16006
16007 format %{
16008 "ldrw zr, [$poll]\t# Safepoint: poll for GC"
16009 %}
16010 ins_encode %{
16011 __ read_polling_page(as_Register($poll$$reg), relocInfo::poll_type);
16012 %}
16013 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
16014 %}
16015
16016
16017 // ============================================================================
16018 // Procedure Call/Return Instructions
16019
16020 // Call Java Static Instruction
16021
16022 instruct CallStaticJavaDirect(method meth)
16023 %{
16024 match(CallStaticJava);
16025
16026 effect(USE meth);
16027
16028 ins_cost(CALL_COST);
16029
16030 format %{ "call,static $meth \t// ==> " %}
16031
16032 ins_encode(aarch64_enc_java_static_call(meth),
16033 aarch64_enc_call_epilog);
16034
16035 ins_pipe(pipe_class_call);
16036 %}
16037
16038 // TO HERE
16039
16040 // Call Java Dynamic Instruction
16041 instruct CallDynamicJavaDirect(method meth)
16042 %{
16043 match(CallDynamicJava);
16044
16045 effect(USE meth);
16046
16047 ins_cost(CALL_COST);
16048
16049 format %{ "CALL,dynamic $meth \t// ==> " %}
16050
16051 ins_encode(aarch64_enc_java_dynamic_call(meth),
16052 aarch64_enc_call_epilog);
16053
16054 ins_pipe(pipe_class_call);
16055 %}
16056
16057 // Call Runtime Instruction
16058
16059 instruct CallRuntimeDirect(method meth)
16060 %{
16061 match(CallRuntime);
16062
16063 effect(USE meth);
16064
16065 ins_cost(CALL_COST);
16066
16067 format %{ "CALL, runtime $meth" %}
16068
16069 ins_encode( aarch64_enc_java_to_runtime(meth) );
16070
16071 ins_pipe(pipe_class_call);
16072 %}
16073
16074 // Call Runtime Instruction
16075
16076 instruct CallLeafDirect(method meth)
16077 %{
16078 match(CallLeaf);
16079
16080 effect(USE meth);
16081
16082 ins_cost(CALL_COST);
16083
16084 format %{ "CALL, runtime leaf $meth" %}
16085
16086 ins_encode( aarch64_enc_java_to_runtime(meth) );
16087
16088 ins_pipe(pipe_class_call);
16089 %}
16090
16091 // Call Runtime Instruction
16092
16093 instruct CallLeafNoFPDirect(method meth)
16094 %{
16095 match(CallLeafNoFP);
16096
16097 effect(USE meth);
16098
16099 ins_cost(CALL_COST);
16100
16101 format %{ "CALL, runtime leaf nofp $meth" %}
16102
16103 ins_encode( aarch64_enc_java_to_runtime(meth) );
16104
16105 ins_pipe(pipe_class_call);
16106 %}
16107
16108 // Tail Call; Jump from runtime stub to Java code.
16109 // Also known as an 'interprocedural jump'.
16110 // Target of jump will eventually return to caller.
16111 // TailJump below removes the return address.
16112 // Don't use rfp for 'jump_target' because a MachEpilogNode has already been
16113 // emitted just above the TailCall which has reset rfp to the caller state.
16114 instruct TailCalljmpInd(iRegPNoSpNoRfp jump_target, inline_cache_RegP method_ptr)
16115 %{
16116 match(TailCall jump_target method_ptr);
16117
16118 ins_cost(CALL_COST);
16119
16120 format %{ "br $jump_target\t# $method_ptr holds method" %}
16121
16122 ins_encode(aarch64_enc_tail_call(jump_target));
16123
16124 ins_pipe(pipe_class_call);
16125 %}
16126
16127 instruct TailjmpInd(iRegPNoSpNoRfp jump_target, iRegP_R0 ex_oop)
16128 %{
16129 match(TailJump jump_target ex_oop);
16130
16131 ins_cost(CALL_COST);
16132
16133 format %{ "br $jump_target\t# $ex_oop holds exception oop" %}
16134
16135 ins_encode(aarch64_enc_tail_jmp(jump_target));
16136
16137 ins_pipe(pipe_class_call);
16138 %}
16139
16140 // Create exception oop: created by stack-crawling runtime code.
16141 // Created exception is now available to this handler, and is setup
16142 // just prior to jumping to this handler. No code emitted.
16143 // TODO check
16144 // should ex_oop be in r0? intel uses rax, ppc cannot use r0 so uses rarg1
16145 instruct CreateException(iRegP_R0 ex_oop)
16146 %{
16147 match(Set ex_oop (CreateEx));
16148
16149 format %{ " -- \t// exception oop; no code emitted" %}
16150
16151 size(0);
16152
16153 ins_encode( /*empty*/ );
16154
16155 ins_pipe(pipe_class_empty);
16156 %}
16157
16158 // Rethrow exception: The exception oop will come in the first
16159 // argument position. Then JUMP (not call) to the rethrow stub code.
16160 instruct RethrowException() %{
16161 match(Rethrow);
16162 ins_cost(CALL_COST);
16163
16164 format %{ "b rethrow_stub" %}
16165
16166 ins_encode( aarch64_enc_rethrow() );
16167
16168 ins_pipe(pipe_class_call);
16169 %}
16170
16171
16172 // Return Instruction
16173 // epilog node loads ret address into lr as part of frame pop
16174 instruct Ret()
16175 %{
16176 match(Return);
16177
16178 format %{ "ret\t// return register" %}
16179
16180 ins_encode( aarch64_enc_ret() );
16181
16182 ins_pipe(pipe_branch);
16183 %}
16184
16185 // Die now.
16186 instruct ShouldNotReachHere() %{
16187 match(Halt);
16188
16189 ins_cost(CALL_COST);
16190 format %{ "ShouldNotReachHere" %}
16191
16192 ins_encode %{
16193 if (is_reachable()) {
16194 __ stop(_halt_reason);
16195 }
16196 %}
16197
16198 ins_pipe(pipe_class_default);
16199 %}
16200
16201 // ============================================================================
16202 // Partial Subtype Check
16203 //
16204 // superklass array for an instance of the superklass. Set a hidden
16205 // internal cache on a hit (cache is checked with exposed code in
16206 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
16207 // encoding ALSO sets flags.
16208
16209 instruct partialSubtypeCheck(iRegP_R4 sub, iRegP_R0 super, iRegP_R2 temp, iRegP_R5 result, rFlagsReg cr)
16210 %{
16211 match(Set result (PartialSubtypeCheck sub super));
16212 effect(KILL cr, KILL temp);
16213
16214 ins_cost(1100); // slightly larger than the next version
16215 format %{ "partialSubtypeCheck $result, $sub, $super" %}
16216
16217 ins_encode(aarch64_enc_partial_subtype_check(sub, super, temp, result));
16218
16219 opcode(0x1); // Force zero of result reg on hit
16220
16221 ins_pipe(pipe_class_memory);
16222 %}
16223
16224 instruct partialSubtypeCheckConstSuper(iRegP_R4 sub, iRegP_R0 super_reg, immP super_con, vRegD_V0 vtemp, iRegP_R5 result,
16225 iRegP_R1 tempR1, iRegP_R2 tempR2, iRegP_R3 tempR3,
16226 rFlagsReg cr)
16227 %{
16228 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
16229 predicate(UseSecondarySupersTable);
16230 effect(KILL cr, TEMP tempR1, TEMP tempR2, TEMP tempR3, TEMP vtemp);
16231
16232 ins_cost(700); // smaller than the next version
16233 format %{ "partialSubtypeCheck $result, $sub, super" %}
16234
16235 ins_encode %{
16236 bool success = false;
16237 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
16238 if (InlineSecondarySupersTest) {
16239 success = __ lookup_secondary_supers_table($sub$$Register, $super_reg$$Register,
16240 $tempR1$$Register, $tempR2$$Register, $tempR3$$Register,
16241 $vtemp$$FloatRegister,
16242 $result$$Register,
16243 super_klass_slot);
16244 } else {
16245 address call = __ trampoline_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
16246 success = (call != nullptr);
16247 }
16248 if (!success) {
16249 ciEnv::current()->record_failure("CodeCache is full");
16250 return;
16251 }
16252 %}
16253
16254 ins_pipe(pipe_class_memory);
16255 %}
16256
16257 instruct partialSubtypeCheckVsZero(iRegP_R4 sub, iRegP_R0 super, iRegP_R2 temp, iRegP_R5 result, immP0 zero, rFlagsReg cr)
16258 %{
16259 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
16260 effect(KILL temp, KILL result);
16261
16262 ins_cost(1100); // slightly larger than the next version
16263 format %{ "partialSubtypeCheck $result, $sub, $super == 0" %}
16264
16265 ins_encode(aarch64_enc_partial_subtype_check(sub, super, temp, result));
16266
16267 opcode(0x0); // Don't zero result reg on hit
16268
16269 ins_pipe(pipe_class_memory);
16270 %}
16271
16272 // Intrisics for String.compareTo()
16273
16274 instruct string_compareU(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16275 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2, rFlagsReg cr)
16276 %{
16277 predicate((UseSVE == 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU));
16278 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16279 effect(KILL tmp1, KILL tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16280
16281 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1" %}
16282 ins_encode %{
16283 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16284 __ string_compare($str1$$Register, $str2$$Register,
16285 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16286 $tmp1$$Register, $tmp2$$Register,
16287 fnoreg, fnoreg, fnoreg, pnoreg, pnoreg, StrIntrinsicNode::UU);
16288 %}
16289 ins_pipe(pipe_class_memory);
16290 %}
16291
16292 instruct string_compareL(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16293 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2, rFlagsReg cr)
16294 %{
16295 predicate((UseSVE == 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL));
16296 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16297 effect(KILL tmp1, KILL tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16298
16299 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1" %}
16300 ins_encode %{
16301 __ string_compare($str1$$Register, $str2$$Register,
16302 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16303 $tmp1$$Register, $tmp2$$Register,
16304 fnoreg, fnoreg, fnoreg, pnoreg, pnoreg, StrIntrinsicNode::LL);
16305 %}
16306 ins_pipe(pipe_class_memory);
16307 %}
16308
16309 instruct string_compareUL(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16310 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16311 vRegD_V0 vtmp1, vRegD_V1 vtmp2, vRegD_V2 vtmp3, rFlagsReg cr)
16312 %{
16313 predicate((UseSVE == 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL));
16314 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16315 effect(KILL tmp1, KILL tmp2, KILL vtmp1, KILL vtmp2, KILL vtmp3,
16316 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16317
16318 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1, $tmp2, $vtmp1, $vtmp2, $vtmp3" %}
16319 ins_encode %{
16320 __ string_compare($str1$$Register, $str2$$Register,
16321 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16322 $tmp1$$Register, $tmp2$$Register,
16323 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister,
16324 $vtmp3$$FloatRegister, pnoreg, pnoreg, StrIntrinsicNode::UL);
16325 %}
16326 ins_pipe(pipe_class_memory);
16327 %}
16328
16329 instruct string_compareLU(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16330 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16331 vRegD_V0 vtmp1, vRegD_V1 vtmp2, vRegD_V2 vtmp3, rFlagsReg cr)
16332 %{
16333 predicate((UseSVE == 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU));
16334 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16335 effect(KILL tmp1, KILL tmp2, KILL vtmp1, KILL vtmp2, KILL vtmp3,
16336 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16337
16338 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # KILL $tmp1, $tmp2, $vtmp1, $vtmp2, $vtmp3" %}
16339 ins_encode %{
16340 __ string_compare($str1$$Register, $str2$$Register,
16341 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16342 $tmp1$$Register, $tmp2$$Register,
16343 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister,
16344 $vtmp3$$FloatRegister, pnoreg, pnoreg, StrIntrinsicNode::LU);
16345 %}
16346 ins_pipe(pipe_class_memory);
16347 %}
16348
16349 // Note that Z registers alias the corresponding NEON registers, we declare the vector operands of
16350 // these string_compare variants as NEON register type for convenience so that the prototype of
16351 // string_compare can be shared with all variants.
16352
16353 instruct string_compareLL_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16354 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16355 vRegD_V0 vtmp1, vRegD_V1 vtmp2, pRegGov_P0 pgtmp1,
16356 pRegGov_P1 pgtmp2, rFlagsReg cr)
16357 %{
16358 predicate((UseSVE > 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL));
16359 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16360 effect(TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, TEMP pgtmp1, TEMP pgtmp2,
16361 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16362
16363 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # USE sve" %}
16364 ins_encode %{
16365 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16366 __ string_compare($str1$$Register, $str2$$Register,
16367 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16368 $tmp1$$Register, $tmp2$$Register,
16369 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister, fnoreg,
16370 as_PRegister($pgtmp1$$reg), as_PRegister($pgtmp2$$reg),
16371 StrIntrinsicNode::LL);
16372 %}
16373 ins_pipe(pipe_class_memory);
16374 %}
16375
16376 instruct string_compareLU_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16377 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16378 vRegD_V0 vtmp1, vRegD_V1 vtmp2, pRegGov_P0 pgtmp1,
16379 pRegGov_P1 pgtmp2, rFlagsReg cr)
16380 %{
16381 predicate((UseSVE > 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU));
16382 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16383 effect(TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, TEMP pgtmp1, TEMP pgtmp2,
16384 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16385
16386 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # USE sve" %}
16387 ins_encode %{
16388 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16389 __ string_compare($str1$$Register, $str2$$Register,
16390 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16391 $tmp1$$Register, $tmp2$$Register,
16392 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister, fnoreg,
16393 as_PRegister($pgtmp1$$reg), as_PRegister($pgtmp2$$reg),
16394 StrIntrinsicNode::LU);
16395 %}
16396 ins_pipe(pipe_class_memory);
16397 %}
16398
16399 instruct string_compareUL_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16400 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16401 vRegD_V0 vtmp1, vRegD_V1 vtmp2, pRegGov_P0 pgtmp1,
16402 pRegGov_P1 pgtmp2, rFlagsReg cr)
16403 %{
16404 predicate((UseSVE > 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL));
16405 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16406 effect(TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, TEMP pgtmp1, TEMP pgtmp2,
16407 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16408
16409 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # USE sve" %}
16410 ins_encode %{
16411 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16412 __ string_compare($str1$$Register, $str2$$Register,
16413 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16414 $tmp1$$Register, $tmp2$$Register,
16415 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister, fnoreg,
16416 as_PRegister($pgtmp1$$reg), as_PRegister($pgtmp2$$reg),
16417 StrIntrinsicNode::UL);
16418 %}
16419 ins_pipe(pipe_class_memory);
16420 %}
16421
16422 instruct string_compareUU_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4 cnt2,
16423 iRegI_R0 result, iRegP_R10 tmp1, iRegL_R11 tmp2,
16424 vRegD_V0 vtmp1, vRegD_V1 vtmp2, pRegGov_P0 pgtmp1,
16425 pRegGov_P1 pgtmp2, rFlagsReg cr)
16426 %{
16427 predicate((UseSVE > 0) && (((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU));
16428 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
16429 effect(TEMP tmp1, TEMP tmp2, TEMP vtmp1, TEMP vtmp2, TEMP pgtmp1, TEMP pgtmp2,
16430 USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
16431
16432 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result # USE sve" %}
16433 ins_encode %{
16434 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16435 __ string_compare($str1$$Register, $str2$$Register,
16436 $cnt1$$Register, $cnt2$$Register, $result$$Register,
16437 $tmp1$$Register, $tmp2$$Register,
16438 $vtmp1$$FloatRegister, $vtmp2$$FloatRegister, fnoreg,
16439 as_PRegister($pgtmp1$$reg), as_PRegister($pgtmp2$$reg),
16440 StrIntrinsicNode::UU);
16441 %}
16442 ins_pipe(pipe_class_memory);
16443 %}
16444
16445 instruct string_indexofUU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
16446 iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
16447 iRegINoSp tmp3, iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6,
16448 vRegD_V0 vtmp0, vRegD_V1 vtmp1, rFlagsReg cr)
16449 %{
16450 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
16451 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
16452 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
16453 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
16454 TEMP vtmp0, TEMP vtmp1, KILL cr);
16455 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU) "
16456 "# KILL $str1 $cnt1 $str2 $cnt2 $tmp1 $tmp2 $tmp3 $tmp4 $tmp5 $tmp6 V0-V1 cr" %}
16457
16458 ins_encode %{
16459 __ string_indexof($str1$$Register, $str2$$Register,
16460 $cnt1$$Register, $cnt2$$Register,
16461 $tmp1$$Register, $tmp2$$Register,
16462 $tmp3$$Register, $tmp4$$Register,
16463 $tmp5$$Register, $tmp6$$Register,
16464 -1, $result$$Register, StrIntrinsicNode::UU);
16465 %}
16466 ins_pipe(pipe_class_memory);
16467 %}
16468
16469 instruct string_indexofLL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
16470 iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
16471 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6,
16472 vRegD_V0 vtmp0, vRegD_V1 vtmp1, rFlagsReg cr)
16473 %{
16474 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
16475 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
16476 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
16477 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
16478 TEMP vtmp0, TEMP vtmp1, KILL cr);
16479 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL) "
16480 "# KILL $str1 $cnt1 $str2 $cnt2 $tmp1 $tmp2 $tmp3 $tmp4 $tmp5 $tmp6 V0-V1 cr" %}
16481
16482 ins_encode %{
16483 __ string_indexof($str1$$Register, $str2$$Register,
16484 $cnt1$$Register, $cnt2$$Register,
16485 $tmp1$$Register, $tmp2$$Register,
16486 $tmp3$$Register, $tmp4$$Register,
16487 $tmp5$$Register, $tmp6$$Register,
16488 -1, $result$$Register, StrIntrinsicNode::LL);
16489 %}
16490 ins_pipe(pipe_class_memory);
16491 %}
16492
16493 instruct string_indexofUL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
16494 iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,iRegINoSp tmp3,
16495 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6,
16496 vRegD_V0 vtmp0, vRegD_V1 vtmp1, rFlagsReg cr)
16497 %{
16498 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
16499 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
16500 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2,
16501 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
16502 TEMP tmp6, TEMP vtmp0, TEMP vtmp1, KILL cr);
16503 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL) "
16504 "# KILL $str1 cnt1 $str2 $cnt2 $tmp1 $tmp2 $tmp3 $tmp4 $tmp5 $tmp6 V0-V1 cr" %}
16505
16506 ins_encode %{
16507 __ string_indexof($str1$$Register, $str2$$Register,
16508 $cnt1$$Register, $cnt2$$Register,
16509 $tmp1$$Register, $tmp2$$Register,
16510 $tmp3$$Register, $tmp4$$Register,
16511 $tmp5$$Register, $tmp6$$Register,
16512 -1, $result$$Register, StrIntrinsicNode::UL);
16513 %}
16514 ins_pipe(pipe_class_memory);
16515 %}
16516
16517 instruct string_indexof_conUU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
16518 immI_le_4 int_cnt2, iRegI_R0 result, iRegINoSp tmp1,
16519 iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
16520 %{
16521 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
16522 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
16523 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
16524 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
16525 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU) "
16526 "# KILL $str1 $cnt1 $str2 $tmp1 $tmp2 $tmp3 $tmp4 cr" %}
16527
16528 ins_encode %{
16529 int icnt2 = (int)$int_cnt2$$constant;
16530 __ string_indexof($str1$$Register, $str2$$Register,
16531 $cnt1$$Register, zr,
16532 $tmp1$$Register, $tmp2$$Register,
16533 $tmp3$$Register, $tmp4$$Register, zr, zr,
16534 icnt2, $result$$Register, StrIntrinsicNode::UU);
16535 %}
16536 ins_pipe(pipe_class_memory);
16537 %}
16538
16539 instruct string_indexof_conLL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
16540 immI_le_4 int_cnt2, iRegI_R0 result, iRegINoSp tmp1,
16541 iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
16542 %{
16543 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
16544 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
16545 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
16546 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
16547 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL) "
16548 "# KILL $str1 $cnt1 $str2 $tmp1 $tmp2 $tmp3 $tmp4 cr" %}
16549
16550 ins_encode %{
16551 int icnt2 = (int)$int_cnt2$$constant;
16552 __ string_indexof($str1$$Register, $str2$$Register,
16553 $cnt1$$Register, zr,
16554 $tmp1$$Register, $tmp2$$Register,
16555 $tmp3$$Register, $tmp4$$Register, zr, zr,
16556 icnt2, $result$$Register, StrIntrinsicNode::LL);
16557 %}
16558 ins_pipe(pipe_class_memory);
16559 %}
16560
16561 instruct string_indexof_conUL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
16562 immI_1 int_cnt2, iRegI_R0 result, iRegINoSp tmp1,
16563 iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
16564 %{
16565 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
16566 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
16567 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1,
16568 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
16569 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL) "
16570 "# KILL $str1 $cnt1 $str2 $tmp1 $tmp2 $tmp3 $tmp4 cr" %}
16571
16572 ins_encode %{
16573 int icnt2 = (int)$int_cnt2$$constant;
16574 __ string_indexof($str1$$Register, $str2$$Register,
16575 $cnt1$$Register, zr,
16576 $tmp1$$Register, $tmp2$$Register,
16577 $tmp3$$Register, $tmp4$$Register, zr, zr,
16578 icnt2, $result$$Register, StrIntrinsicNode::UL);
16579 %}
16580 ins_pipe(pipe_class_memory);
16581 %}
16582
16583 instruct string_indexof_char(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
16584 iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
16585 iRegINoSp tmp3, rFlagsReg cr)
16586 %{
16587 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
16588 predicate((UseSVE == 0) && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
16589 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch,
16590 TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
16591
16592 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
16593
16594 ins_encode %{
16595 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
16596 $result$$Register, $tmp1$$Register, $tmp2$$Register,
16597 $tmp3$$Register);
16598 %}
16599 ins_pipe(pipe_class_memory);
16600 %}
16601
16602 instruct stringL_indexof_char(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
16603 iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
16604 iRegINoSp tmp3, rFlagsReg cr)
16605 %{
16606 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
16607 predicate((UseSVE == 0) && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
16608 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch,
16609 TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
16610
16611 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result" %}
16612
16613 ins_encode %{
16614 __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
16615 $result$$Register, $tmp1$$Register, $tmp2$$Register,
16616 $tmp3$$Register);
16617 %}
16618 ins_pipe(pipe_class_memory);
16619 %}
16620
16621 instruct stringL_indexof_char_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
16622 iRegI_R0 result, vecA ztmp1, vecA ztmp2,
16623 pRegGov pgtmp, pReg ptmp, rFlagsReg cr) %{
16624 predicate(UseSVE > 0 && ((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L);
16625 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
16626 effect(TEMP ztmp1, TEMP ztmp2, TEMP pgtmp, TEMP ptmp, KILL cr);
16627 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result # use sve" %}
16628 ins_encode %{
16629 __ string_indexof_char_sve($str1$$Register, $cnt1$$Register, $ch$$Register,
16630 $result$$Register, $ztmp1$$FloatRegister,
16631 $ztmp2$$FloatRegister, $pgtmp$$PRegister,
16632 $ptmp$$PRegister, true /* isL */);
16633 %}
16634 ins_pipe(pipe_class_memory);
16635 %}
16636
16637 instruct stringU_indexof_char_sve(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
16638 iRegI_R0 result, vecA ztmp1, vecA ztmp2,
16639 pRegGov pgtmp, pReg ptmp, rFlagsReg cr) %{
16640 predicate(UseSVE > 0 && ((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U);
16641 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
16642 effect(TEMP ztmp1, TEMP ztmp2, TEMP pgtmp, TEMP ptmp, KILL cr);
16643 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result # use sve" %}
16644 ins_encode %{
16645 __ string_indexof_char_sve($str1$$Register, $cnt1$$Register, $ch$$Register,
16646 $result$$Register, $ztmp1$$FloatRegister,
16647 $ztmp2$$FloatRegister, $pgtmp$$PRegister,
16648 $ptmp$$PRegister, false /* isL */);
16649 %}
16650 ins_pipe(pipe_class_memory);
16651 %}
16652
16653 instruct string_equalsL(iRegP_R1 str1, iRegP_R3 str2, iRegI_R4 cnt,
16654 iRegI_R0 result, rFlagsReg cr)
16655 %{
16656 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
16657 match(Set result (StrEquals (Binary str1 str2) cnt));
16658 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
16659
16660 format %{ "String Equals $str1,$str2,$cnt -> $result" %}
16661 ins_encode %{
16662 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
16663 __ string_equals($str1$$Register, $str2$$Register,
16664 $result$$Register, $cnt$$Register);
16665 %}
16666 ins_pipe(pipe_class_memory);
16667 %}
16668
16669 instruct array_equalsB(iRegP_R1 ary1, iRegP_R2 ary2, iRegI_R0 result,
16670 iRegP_R3 tmp1, iRegP_R4 tmp2, iRegP_R5 tmp3,
16671 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2, vRegD_V3 vtmp3,
16672 vRegD_V4 vtmp4, vRegD_V5 vtmp5, vRegD_V6 vtmp6, vRegD_V7 vtmp7,
16673 iRegP_R10 tmp, rFlagsReg cr)
16674 %{
16675 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
16676 match(Set result (AryEq ary1 ary2));
16677 effect(KILL tmp, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3,
16678 TEMP vtmp0, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3, TEMP vtmp4, TEMP vtmp5,
16679 TEMP vtmp6, TEMP vtmp7, KILL cr);
16680
16681 format %{ "Array Equals $ary1,ary2 -> $result # KILL $ary1 $ary2 $tmp $tmp1 $tmp2 $tmp3 V0-V7 cr" %}
16682 ins_encode %{
16683 address tpc = __ arrays_equals($ary1$$Register, $ary2$$Register,
16684 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
16685 $result$$Register, $tmp$$Register, 1);
16686 if (tpc == nullptr) {
16687 ciEnv::current()->record_failure("CodeCache is full");
16688 return;
16689 }
16690 %}
16691 ins_pipe(pipe_class_memory);
16692 %}
16693
16694 instruct array_equalsC(iRegP_R1 ary1, iRegP_R2 ary2, iRegI_R0 result,
16695 iRegP_R3 tmp1, iRegP_R4 tmp2, iRegP_R5 tmp3,
16696 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2, vRegD_V3 vtmp3,
16697 vRegD_V4 vtmp4, vRegD_V5 vtmp5, vRegD_V6 vtmp6, vRegD_V7 vtmp7,
16698 iRegP_R10 tmp, rFlagsReg cr)
16699 %{
16700 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
16701 match(Set result (AryEq ary1 ary2));
16702 effect(KILL tmp, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3,
16703 TEMP vtmp0, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3, TEMP vtmp4, TEMP vtmp5,
16704 TEMP vtmp6, TEMP vtmp7, KILL cr);
16705
16706 format %{ "Array Equals $ary1,ary2 -> $result # KILL $ary1 $ary2 $tmp $tmp1 $tmp2 $tmp3 V0-V7 cr" %}
16707 ins_encode %{
16708 address tpc = __ arrays_equals($ary1$$Register, $ary2$$Register,
16709 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
16710 $result$$Register, $tmp$$Register, 2);
16711 if (tpc == nullptr) {
16712 ciEnv::current()->record_failure("CodeCache is full");
16713 return;
16714 }
16715 %}
16716 ins_pipe(pipe_class_memory);
16717 %}
16718
16719 instruct count_positives(iRegP_R1 ary1, iRegI_R2 len, iRegI_R0 result, rFlagsReg cr)
16720 %{
16721 match(Set result (CountPositives ary1 len));
16722 effect(USE_KILL ary1, USE_KILL len, KILL cr);
16723 format %{ "count positives byte[] $ary1,$len -> $result" %}
16724 ins_encode %{
16725 address tpc = __ count_positives($ary1$$Register, $len$$Register, $result$$Register);
16726 if (tpc == nullptr) {
16727 ciEnv::current()->record_failure("CodeCache is full");
16728 return;
16729 }
16730 %}
16731 ins_pipe( pipe_slow );
16732 %}
16733
16734 // fast char[] to byte[] compression
16735 instruct string_compress(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
16736 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2,
16737 vRegD_V3 vtmp3, vRegD_V4 vtmp4, vRegD_V5 vtmp5,
16738 iRegI_R0 result, rFlagsReg cr)
16739 %{
16740 match(Set result (StrCompressedCopy src (Binary dst len)));
16741 effect(TEMP vtmp0, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3, TEMP vtmp4, TEMP vtmp5,
16742 USE_KILL src, USE_KILL dst, USE len, KILL cr);
16743
16744 format %{ "String Compress $src,$dst,$len -> $result # KILL $src $dst V0-V5 cr" %}
16745 ins_encode %{
16746 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
16747 $result$$Register, $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
16748 $vtmp2$$FloatRegister, $vtmp3$$FloatRegister,
16749 $vtmp4$$FloatRegister, $vtmp5$$FloatRegister);
16750 %}
16751 ins_pipe(pipe_slow);
16752 %}
16753
16754 // fast byte[] to char[] inflation
16755 instruct string_inflate(Universe dummy, iRegP_R0 src, iRegP_R1 dst, iRegI_R2 len, iRegP_R3 tmp,
16756 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2, vRegD_V3 vtmp3,
16757 vRegD_V4 vtmp4, vRegD_V5 vtmp5, vRegD_V6 vtmp6, rFlagsReg cr)
16758 %{
16759 match(Set dummy (StrInflatedCopy src (Binary dst len)));
16760 effect(TEMP vtmp0, TEMP vtmp1, TEMP vtmp2, TEMP vtmp3,
16761 TEMP vtmp4, TEMP vtmp5, TEMP vtmp6, TEMP tmp,
16762 USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
16763
16764 format %{ "String Inflate $src,$dst # KILL $tmp $src $dst $len V0-V6 cr" %}
16765 ins_encode %{
16766 address tpc = __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
16767 $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
16768 $vtmp2$$FloatRegister, $tmp$$Register);
16769 if (tpc == nullptr) {
16770 ciEnv::current()->record_failure("CodeCache is full");
16771 return;
16772 }
16773 %}
16774 ins_pipe(pipe_class_memory);
16775 %}
16776
16777 // encode char[] to byte[] in ISO_8859_1
16778 instruct encode_iso_array(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
16779 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2,
16780 vRegD_V3 vtmp3, vRegD_V4 vtmp4, vRegD_V5 vtmp5,
16781 iRegI_R0 result, rFlagsReg cr)
16782 %{
16783 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
16784 match(Set result (EncodeISOArray src (Binary dst len)));
16785 effect(USE_KILL src, USE_KILL dst, USE len, KILL vtmp0, KILL vtmp1,
16786 KILL vtmp2, KILL vtmp3, KILL vtmp4, KILL vtmp5, KILL cr);
16787
16788 format %{ "Encode ISO array $src,$dst,$len -> $result # KILL $src $dst V0-V5 cr" %}
16789 ins_encode %{
16790 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
16791 $result$$Register, false,
16792 $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
16793 $vtmp2$$FloatRegister, $vtmp3$$FloatRegister,
16794 $vtmp4$$FloatRegister, $vtmp5$$FloatRegister);
16795 %}
16796 ins_pipe(pipe_class_memory);
16797 %}
16798
16799 instruct encode_ascii_array(iRegP_R2 src, iRegP_R1 dst, iRegI_R3 len,
16800 vRegD_V0 vtmp0, vRegD_V1 vtmp1, vRegD_V2 vtmp2,
16801 vRegD_V3 vtmp3, vRegD_V4 vtmp4, vRegD_V5 vtmp5,
16802 iRegI_R0 result, rFlagsReg cr)
16803 %{
16804 predicate(((EncodeISOArrayNode*)n)->is_ascii());
16805 match(Set result (EncodeISOArray src (Binary dst len)));
16806 effect(USE_KILL src, USE_KILL dst, USE len, KILL vtmp0, KILL vtmp1,
16807 KILL vtmp2, KILL vtmp3, KILL vtmp4, KILL vtmp5, KILL cr);
16808
16809 format %{ "Encode ASCII array $src,$dst,$len -> $result # KILL $src $dst V0-V5 cr" %}
16810 ins_encode %{
16811 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
16812 $result$$Register, true,
16813 $vtmp0$$FloatRegister, $vtmp1$$FloatRegister,
16814 $vtmp2$$FloatRegister, $vtmp3$$FloatRegister,
16815 $vtmp4$$FloatRegister, $vtmp5$$FloatRegister);
16816 %}
16817 ins_pipe(pipe_class_memory);
16818 %}
16819
16820 //----------------------------- CompressBits/ExpandBits ------------------------
16821
16822 instruct compressBitsI_reg(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask,
16823 vRegF tdst, vRegF tsrc, vRegF tmask) %{
16824 match(Set dst (CompressBits src mask));
16825 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
16826 format %{ "mov $tsrc, $src\n\t"
16827 "mov $tmask, $mask\n\t"
16828 "bext $tdst, $tsrc, $tmask\n\t"
16829 "mov $dst, $tdst"
16830 %}
16831 ins_encode %{
16832 __ mov($tsrc$$FloatRegister, __ S, 0, $src$$Register);
16833 __ mov($tmask$$FloatRegister, __ S, 0, $mask$$Register);
16834 __ sve_bext($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
16835 __ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
16836 %}
16837 ins_pipe(pipe_slow);
16838 %}
16839
16840 instruct compressBitsI_memcon(iRegINoSp dst, memory4 mem, immI mask,
16841 vRegF tdst, vRegF tsrc, vRegF tmask) %{
16842 match(Set dst (CompressBits (LoadI mem) mask));
16843 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
16844 format %{ "ldrs $tsrc, $mem\n\t"
16845 "ldrs $tmask, $mask\n\t"
16846 "bext $tdst, $tsrc, $tmask\n\t"
16847 "mov $dst, $tdst"
16848 %}
16849 ins_encode %{
16850 loadStore(masm, &MacroAssembler::ldrs, $tsrc$$FloatRegister, $mem->opcode(),
16851 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
16852 __ ldrs($tmask$$FloatRegister, $constantaddress($mask));
16853 __ sve_bext($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
16854 __ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
16855 %}
16856 ins_pipe(pipe_slow);
16857 %}
16858
16859 instruct compressBitsL_reg(iRegLNoSp dst, iRegL src, iRegL mask,
16860 vRegD tdst, vRegD tsrc, vRegD tmask) %{
16861 match(Set dst (CompressBits src mask));
16862 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
16863 format %{ "mov $tsrc, $src\n\t"
16864 "mov $tmask, $mask\n\t"
16865 "bext $tdst, $tsrc, $tmask\n\t"
16866 "mov $dst, $tdst"
16867 %}
16868 ins_encode %{
16869 __ mov($tsrc$$FloatRegister, __ D, 0, $src$$Register);
16870 __ mov($tmask$$FloatRegister, __ D, 0, $mask$$Register);
16871 __ sve_bext($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
16872 __ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
16873 %}
16874 ins_pipe(pipe_slow);
16875 %}
16876
16877 instruct compressBitsL_memcon(iRegLNoSp dst, memory8 mem, immL mask,
16878 vRegF tdst, vRegF tsrc, vRegF tmask) %{
16879 match(Set dst (CompressBits (LoadL mem) mask));
16880 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
16881 format %{ "ldrd $tsrc, $mem\n\t"
16882 "ldrd $tmask, $mask\n\t"
16883 "bext $tdst, $tsrc, $tmask\n\t"
16884 "mov $dst, $tdst"
16885 %}
16886 ins_encode %{
16887 loadStore(masm, &MacroAssembler::ldrd, $tsrc$$FloatRegister, $mem->opcode(),
16888 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
16889 __ ldrd($tmask$$FloatRegister, $constantaddress($mask));
16890 __ sve_bext($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
16891 __ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
16892 %}
16893 ins_pipe(pipe_slow);
16894 %}
16895
16896 instruct expandBitsI_reg(iRegINoSp dst, iRegIorL2I src, iRegIorL2I mask,
16897 vRegF tdst, vRegF tsrc, vRegF tmask) %{
16898 match(Set dst (ExpandBits src mask));
16899 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
16900 format %{ "mov $tsrc, $src\n\t"
16901 "mov $tmask, $mask\n\t"
16902 "bdep $tdst, $tsrc, $tmask\n\t"
16903 "mov $dst, $tdst"
16904 %}
16905 ins_encode %{
16906 __ mov($tsrc$$FloatRegister, __ S, 0, $src$$Register);
16907 __ mov($tmask$$FloatRegister, __ S, 0, $mask$$Register);
16908 __ sve_bdep($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
16909 __ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
16910 %}
16911 ins_pipe(pipe_slow);
16912 %}
16913
16914 instruct expandBitsI_memcon(iRegINoSp dst, memory4 mem, immI mask,
16915 vRegF tdst, vRegF tsrc, vRegF tmask) %{
16916 match(Set dst (ExpandBits (LoadI mem) mask));
16917 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
16918 format %{ "ldrs $tsrc, $mem\n\t"
16919 "ldrs $tmask, $mask\n\t"
16920 "bdep $tdst, $tsrc, $tmask\n\t"
16921 "mov $dst, $tdst"
16922 %}
16923 ins_encode %{
16924 loadStore(masm, &MacroAssembler::ldrs, $tsrc$$FloatRegister, $mem->opcode(),
16925 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
16926 __ ldrs($tmask$$FloatRegister, $constantaddress($mask));
16927 __ sve_bdep($tdst$$FloatRegister, __ S, $tsrc$$FloatRegister, $tmask$$FloatRegister);
16928 __ mov($dst$$Register, $tdst$$FloatRegister, __ S, 0);
16929 %}
16930 ins_pipe(pipe_slow);
16931 %}
16932
16933 instruct expandBitsL_reg(iRegLNoSp dst, iRegL src, iRegL mask,
16934 vRegD tdst, vRegD tsrc, vRegD tmask) %{
16935 match(Set dst (ExpandBits src mask));
16936 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
16937 format %{ "mov $tsrc, $src\n\t"
16938 "mov $tmask, $mask\n\t"
16939 "bdep $tdst, $tsrc, $tmask\n\t"
16940 "mov $dst, $tdst"
16941 %}
16942 ins_encode %{
16943 __ mov($tsrc$$FloatRegister, __ D, 0, $src$$Register);
16944 __ mov($tmask$$FloatRegister, __ D, 0, $mask$$Register);
16945 __ sve_bdep($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
16946 __ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
16947 %}
16948 ins_pipe(pipe_slow);
16949 %}
16950
16951
16952 instruct expandBitsL_memcon(iRegINoSp dst, memory8 mem, immL mask,
16953 vRegF tdst, vRegF tsrc, vRegF tmask) %{
16954 match(Set dst (ExpandBits (LoadL mem) mask));
16955 effect(TEMP tdst, TEMP tsrc, TEMP tmask);
16956 format %{ "ldrd $tsrc, $mem\n\t"
16957 "ldrd $tmask, $mask\n\t"
16958 "bdep $tdst, $tsrc, $tmask\n\t"
16959 "mov $dst, $tdst"
16960 %}
16961 ins_encode %{
16962 loadStore(masm, &MacroAssembler::ldrd, $tsrc$$FloatRegister, $mem->opcode(),
16963 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 8);
16964 __ ldrd($tmask$$FloatRegister, $constantaddress($mask));
16965 __ sve_bdep($tdst$$FloatRegister, __ D, $tsrc$$FloatRegister, $tmask$$FloatRegister);
16966 __ mov($dst$$Register, $tdst$$FloatRegister, __ D, 0);
16967 %}
16968 ins_pipe(pipe_slow);
16969 %}
16970
16971 // ============================================================================
16972 // This name is KNOWN by the ADLC and cannot be changed.
16973 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
16974 // for this guy.
16975 instruct tlsLoadP(thread_RegP dst)
16976 %{
16977 match(Set dst (ThreadLocal));
16978
16979 ins_cost(0);
16980
16981 format %{ " -- \t// $dst=Thread::current(), empty" %}
16982
16983 size(0);
16984
16985 ins_encode( /*empty*/ );
16986
16987 ins_pipe(pipe_class_empty);
16988 %}
16989
16990 //----------PEEPHOLE RULES-----------------------------------------------------
16991 // These must follow all instruction definitions as they use the names
16992 // defined in the instructions definitions.
16993 //
16994 // peepmatch ( root_instr_name [preceding_instruction]* );
16995 //
16996 // peepconstraint %{
16997 // (instruction_number.operand_name relational_op instruction_number.operand_name
16998 // [, ...] );
16999 // // instruction numbers are zero-based using left to right order in peepmatch
17000 //
17001 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
17002 // // provide an instruction_number.operand_name for each operand that appears
17003 // // in the replacement instruction's match rule
17004 //
17005 // ---------VM FLAGS---------------------------------------------------------
17006 //
17007 // All peephole optimizations can be turned off using -XX:-OptoPeephole
17008 //
17009 // Each peephole rule is given an identifying number starting with zero and
17010 // increasing by one in the order seen by the parser. An individual peephole
17011 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
17012 // on the command-line.
17013 //
17014 // ---------CURRENT LIMITATIONS----------------------------------------------
17015 //
17016 // Only match adjacent instructions in same basic block
17017 // Only equality constraints
17018 // Only constraints between operands, not (0.dest_reg == RAX_enc)
17019 // Only one replacement instruction
17020 //
17021 // ---------EXAMPLE----------------------------------------------------------
17022 //
17023 // // pertinent parts of existing instructions in architecture description
17024 // instruct movI(iRegINoSp dst, iRegI src)
17025 // %{
17026 // match(Set dst (CopyI src));
17027 // %}
17028 //
17029 // instruct incI_iReg(iRegINoSp dst, immI1 src, rFlagsReg cr)
17030 // %{
17031 // match(Set dst (AddI dst src));
17032 // effect(KILL cr);
17033 // %}
17034 //
17035 // // Change (inc mov) to lea
17036 // peephole %{
17037 // // increment preceded by register-register move
17038 // peepmatch ( incI_iReg movI );
17039 // // require that the destination register of the increment
17040 // // match the destination register of the move
17041 // peepconstraint ( 0.dst == 1.dst );
17042 // // construct a replacement instruction that sets
17043 // // the destination to ( move's source register + one )
17044 // peepreplace ( leaI_iReg_immI( 0.dst 1.src 0.src ) );
17045 // %}
17046 //
17047
17048 // Implementation no longer uses movX instructions since
17049 // machine-independent system no longer uses CopyX nodes.
17050 //
17051 // peephole
17052 // %{
17053 // peepmatch (incI_iReg movI);
17054 // peepconstraint (0.dst == 1.dst);
17055 // peepreplace (leaI_iReg_immI(0.dst 1.src 0.src));
17056 // %}
17057
17058 // peephole
17059 // %{
17060 // peepmatch (decI_iReg movI);
17061 // peepconstraint (0.dst == 1.dst);
17062 // peepreplace (leaI_iReg_immI(0.dst 1.src 0.src));
17063 // %}
17064
17065 // peephole
17066 // %{
17067 // peepmatch (addI_iReg_imm movI);
17068 // peepconstraint (0.dst == 1.dst);
17069 // peepreplace (leaI_iReg_immI(0.dst 1.src 0.src));
17070 // %}
17071
17072 // peephole
17073 // %{
17074 // peepmatch (incL_iReg movL);
17075 // peepconstraint (0.dst == 1.dst);
17076 // peepreplace (leaL_iReg_immL(0.dst 1.src 0.src));
17077 // %}
17078
17079 // peephole
17080 // %{
17081 // peepmatch (decL_iReg movL);
17082 // peepconstraint (0.dst == 1.dst);
17083 // peepreplace (leaL_iReg_immL(0.dst 1.src 0.src));
17084 // %}
17085
17086 // peephole
17087 // %{
17088 // peepmatch (addL_iReg_imm movL);
17089 // peepconstraint (0.dst == 1.dst);
17090 // peepreplace (leaL_iReg_immL(0.dst 1.src 0.src));
17091 // %}
17092
17093 // peephole
17094 // %{
17095 // peepmatch (addP_iReg_imm movP);
17096 // peepconstraint (0.dst == 1.dst);
17097 // peepreplace (leaP_iReg_imm(0.dst 1.src 0.src));
17098 // %}
17099
17100 // // Change load of spilled value to only a spill
17101 // instruct storeI(memory mem, iRegI src)
17102 // %{
17103 // match(Set mem (StoreI mem src));
17104 // %}
17105 //
17106 // instruct loadI(iRegINoSp dst, memory mem)
17107 // %{
17108 // match(Set dst (LoadI mem));
17109 // %}
17110 //
17111
17112 //----------SMARTSPILL RULES---------------------------------------------------
17113 // These must follow all instruction definitions as they use the names
17114 // defined in the instructions definitions.
17115
17116 // Local Variables:
17117 // mode: c++
17118 // End: